From bc60901a3dff5b58ecf9285d810f9c8d6583ddaa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Jun 2019 10:01:26 +0100 Subject: [PATCH] add address and output mode from LDSTCUs --- src/experiment/compldst.py | 8 +++++++- src/experiment/score6600.py | 11 +++++++---- src/regfile/regfile.py | 12 ++++++------ 3 files changed, 20 insertions(+), 11 deletions(-) diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py index 0a0a4c2e..e2fccf87 100644 --- a/src/experiment/compldst.py +++ b/src/experiment/compldst.py @@ -78,6 +78,7 @@ class LDSTCompUnit(Elaboratable): self.sto_rel_o = Signal(reset_less=True) # request store (to mem) self.req_rel_o = Signal(reset_less=True) # request write (result) self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU) + self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST) # hmm... TODO... move these to outside of LDSTCompUnit self.load_mem_o = Signal(reset_less=True) # activate memory LOAD @@ -214,7 +215,12 @@ class LDSTCompUnit(Elaboratable): m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid # put the register directly onto the output - comb += self.data_o.eq(data_r) + with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)): + comb += self.data_o.eq(data_r) + + # put the register directly onto the address bus + with m.If(self.go_ad_i): + comb += self.addr_o.eq(data_r) return m diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 05de08fa..58bb131e 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -128,6 +128,7 @@ class CompUnitsBase(Elaboratable): self.req_rel_o = Signal(n_units, reset_less=True) self.load_mem_o = Signal(n_units, reset_less=True) self.stwd_mem_o = Signal(n_units, reset_less=True) + self.addr_o = Signal(rwid, reset_less=True) # in/out register data (note: not register#, actual data) self.data_o = Signal(rwid, reset_less=True) @@ -171,10 +172,12 @@ class CompUnitsBase(Elaboratable): # connect data register input/output # merge (OR) all integer FU / ALU outputs to a single value - # bit of a hack: treereduce needs a list with an item named "data_o" if self.units: - data_o = treereduce(self.units) + data_o = treereduce(self.units, "data_o") comb += self.data_o.eq(data_o) + if self.ldstmode: + addr_o = treereduce(self.units, "addr_o") + comb += self.addr_o.eq(addr_o) for i, alu in enumerate(self.units): comb += alu.src1_i.eq(self.src1_i) @@ -569,8 +572,8 @@ class Scoreboard(Elaboratable): comb += cul.go_ad_i.eq(cul.adr_rel_o) # connect up address data - comb += memfus.addrs_i[0].eq(cul.units[0].data_o) - comb += memfus.addrs_i[1].eq(cul.units[1].data_o) + comb += memfus.addrs_i[0].eq(cul.units[0].addr_o) + comb += memfus.addrs_i[1].eq(cul.units[1].addr_o) # connect loadable / storable to go_ld/go_st. # XXX should only be done when the memory ld/st has actually happened! diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py index 29fbda65..b1d6f1c6 100644 --- a/src/regfile/regfile.py +++ b/src/regfile/regfile.py @@ -10,7 +10,7 @@ import operator class Register(Elaboratable): - def __init__(self, width, writethru=False): + def __init__(self, width, writethru=True): self.width = width self.writethru = writethru self._rdports = [] @@ -65,16 +65,16 @@ class Register(Elaboratable): def ports(self): res = list(self) -def treereduce(tree): +def treereduce(tree, attr="data_o"): #print ("treereduce", tree) if not isinstance(tree, list): return tree if len(tree) == 1: - return tree[0].data_o + return getattr(tree[0], attr) if len(tree) == 2: - return tree[0].data_o | tree[1].data_o - splitpoint = len(tree) // 2 - return treereduce(tree[:splitpoint]) | treereduce(tree[splitpoint:]) + return getattr(tree[0], attr) | getattr(tree[1], attr) + split = len(tree) // 2 + return treereduce(tree[:split], attr) | treereduce(tree[split:], attr) class RegFileArray(Elaboratable): -- 2.30.2