From bc73c4c24daec96ad3e7ff904645c3095a4febe9 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 29 Oct 2019 09:17:48 +0000 Subject: [PATCH] [AArch64] Add main SVE ACLE tests Now that the PCS support is applied, this patch adds the main SVE ACLE tests. The idea is to test various combinations of operands for each ACLE function, with each combination using a specific register allocation and with each combination being wrapped its own test function. We then compare the full assembly output of these test functions against the expected/preferred sequences. This provides both optimisation and correctness testing, since ultimately the ACLE functions are defined in terms of the underlying SVE instructions. 2019-10-29 Richard Sandiford Kugan Vivekanandarajah Prathamesh Kulkarni gcc/testsuite/ * g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp: New file. * gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp: New file. * gcc.target/aarch64/sve/acle/asm: New test directory. Co-Authored-By: Kugan Vivekanandarajah Co-Authored-By: Prathamesh Kulkarni From-SVN: r277565 --- gcc/testsuite/ChangeLog | 8 + .../aarch64/sve/acle/aarch64-sve-acle-asm.exp | 83 ++ .../aarch64/sve/acle/aarch64-sve-acle-asm.exp | 79 ++ .../gcc.target/aarch64/sve/acle/asm/abd_f16.c | 552 ++++++++ .../gcc.target/aarch64/sve/acle/asm/abd_f32.c | 552 ++++++++ .../gcc.target/aarch64/sve/acle/asm/abd_f64.c | 552 ++++++++ .../gcc.target/aarch64/sve/acle/asm/abd_s16.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_s32.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_s64.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_s8.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_u16.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_u32.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_u64.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abd_u8.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/abs_f16.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/abs_f32.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/abs_f64.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/abs_s16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/abs_s32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/abs_s64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/abs_s8.c | 81 ++ .../aarch64/sve/acle/asm/acge_f16.c | 71 + .../aarch64/sve/acle/asm/acge_f32.c | 71 + .../aarch64/sve/acle/asm/acge_f64.c | 71 + .../aarch64/sve/acle/asm/acgt_f16.c | 71 + .../aarch64/sve/acle/asm/acgt_f32.c | 71 + .../aarch64/sve/acle/asm/acgt_f64.c | 71 + .../aarch64/sve/acle/asm/acle_f16.c | 71 + .../aarch64/sve/acle/asm/acle_f32.c | 71 + .../aarch64/sve/acle/asm/acle_f64.c | 71 + .../aarch64/sve/acle/asm/aclt_f16.c | 71 + .../aarch64/sve/acle/asm/aclt_f32.c | 71 + .../aarch64/sve/acle/asm/aclt_f64.c | 71 + .../gcc.target/aarch64/sve/acle/asm/add_f16.c | 577 ++++++++ .../aarch64/sve/acle/asm/add_f16_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/add_f32.c | 577 ++++++++ .../aarch64/sve/acle/asm/add_f32_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/add_f64.c | 577 ++++++++ .../aarch64/sve/acle/asm/add_f64_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/add_s16.c | 377 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_s32.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_s64.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_s8.c | 294 ++++ .../gcc.target/aarch64/sve/acle/asm/add_u16.c | 377 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_u32.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_u64.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/add_u8.c | 294 ++++ .../aarch64/sve/acle/asm/adda_f16.c | 22 + .../aarch64/sve/acle/asm/adda_f32.c | 22 + .../aarch64/sve/acle/asm/adda_f64.c | 22 + .../aarch64/sve/acle/asm/addv_f16.c | 21 + .../aarch64/sve/acle/asm/addv_f32.c | 21 + .../aarch64/sve/acle/asm/addv_f64.c | 21 + .../aarch64/sve/acle/asm/addv_s16.c | 13 + .../aarch64/sve/acle/asm/addv_s32.c | 13 + .../aarch64/sve/acle/asm/addv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/addv_s8.c | 13 + .../aarch64/sve/acle/asm/addv_u16.c | 13 + .../aarch64/sve/acle/asm/addv_u32.c | 13 + .../aarch64/sve/acle/asm/addv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/addv_u8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/adrb.c | 57 + .../gcc.target/aarch64/sve/acle/asm/adrd.c | 57 + .../gcc.target/aarch64/sve/acle/asm/adrh.c | 57 + .../gcc.target/aarch64/sve/acle/asm/adrw.c | 57 + .../gcc.target/aarch64/sve/acle/asm/and_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/and_s16.c | 422 ++++++ .../gcc.target/aarch64/sve/acle/asm/and_s32.c | 464 +++++++ .../gcc.target/aarch64/sve/acle/asm/and_s64.c | 510 +++++++ .../gcc.target/aarch64/sve/acle/asm/and_s8.c | 294 ++++ .../gcc.target/aarch64/sve/acle/asm/and_u16.c | 422 ++++++ .../gcc.target/aarch64/sve/acle/asm/and_u32.c | 464 +++++++ .../gcc.target/aarch64/sve/acle/asm/and_u64.c | 510 +++++++ .../gcc.target/aarch64/sve/acle/asm/and_u8.c | 294 ++++ .../aarch64/sve/acle/asm/andv_s16.c | 13 + .../aarch64/sve/acle/asm/andv_s32.c | 13 + .../aarch64/sve/acle/asm/andv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/andv_s8.c | 13 + .../aarch64/sve/acle/asm/andv_u16.c | 13 + .../aarch64/sve/acle/asm/andv_u32.c | 13 + .../aarch64/sve/acle/asm/andv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/andv_u8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/asr_s16.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/asr_s32.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/asr_s64.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/asr_s8.c | 340 +++++ .../aarch64/sve/acle/asm/asr_wide_s16.c | 325 +++++ .../aarch64/sve/acle/asm/asr_wide_s32.c | 325 +++++ .../aarch64/sve/acle/asm/asr_wide_s8.c | 325 +++++ .../aarch64/sve/acle/asm/asrd_s16.c | 177 +++ .../aarch64/sve/acle/asm/asrd_s32.c | 177 +++ .../aarch64/sve/acle/asm/asrd_s64.c | 177 +++ .../gcc.target/aarch64/sve/acle/asm/asrd_s8.c | 177 +++ .../gcc.target/aarch64/sve/acle/asm/bic_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/bic_s16.c | 367 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_s32.c | 363 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_s64.c | 363 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_s8.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/bic_u16.c | 367 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_u32.c | 363 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_u64.c | 363 +++++ .../gcc.target/aarch64/sve/acle/asm/bic_u8.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/brka_b.c | 54 + .../gcc.target/aarch64/sve/acle/asm/brkb_b.c | 54 + .../gcc.target/aarch64/sve/acle/asm/brkn_b.c | 27 + .../gcc.target/aarch64/sve/acle/asm/brkpa_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/brkpb_b.c | 30 + .../aarch64/sve/acle/asm/cadd_f16.c | 251 ++++ .../aarch64/sve/acle/asm/cadd_f32.c | 251 ++++ .../aarch64/sve/acle/asm/cadd_f64.c | 251 ++++ .../aarch64/sve/acle/asm/clasta_f16.c | 52 + .../aarch64/sve/acle/asm/clasta_f32.c | 52 + .../aarch64/sve/acle/asm/clasta_f64.c | 52 + .../aarch64/sve/acle/asm/clasta_s16.c | 52 + .../aarch64/sve/acle/asm/clasta_s32.c | 52 + .../aarch64/sve/acle/asm/clasta_s64.c | 52 + .../aarch64/sve/acle/asm/clasta_s8.c | 52 + .../aarch64/sve/acle/asm/clasta_u16.c | 52 + .../aarch64/sve/acle/asm/clasta_u32.c | 52 + .../aarch64/sve/acle/asm/clasta_u64.c | 52 + .../aarch64/sve/acle/asm/clasta_u8.c | 52 + .../aarch64/sve/acle/asm/clastb_f16.c | 52 + .../aarch64/sve/acle/asm/clastb_f32.c | 52 + .../aarch64/sve/acle/asm/clastb_f64.c | 52 + .../aarch64/sve/acle/asm/clastb_s16.c | 52 + .../aarch64/sve/acle/asm/clastb_s32.c | 52 + .../aarch64/sve/acle/asm/clastb_s64.c | 52 + .../aarch64/sve/acle/asm/clastb_s8.c | 52 + .../aarch64/sve/acle/asm/clastb_u16.c | 52 + .../aarch64/sve/acle/asm/clastb_u32.c | 52 + .../aarch64/sve/acle/asm/clastb_u64.c | 52 + .../aarch64/sve/acle/asm/clastb_u8.c | 52 + .../gcc.target/aarch64/sve/acle/asm/cls_s16.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cls_s32.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cls_s64.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cls_s8.c | 41 + .../gcc.target/aarch64/sve/acle/asm/clz_s16.c | 41 + .../gcc.target/aarch64/sve/acle/asm/clz_s32.c | 41 + .../gcc.target/aarch64/sve/acle/asm/clz_s64.c | 41 + .../gcc.target/aarch64/sve/acle/asm/clz_s8.c | 41 + .../gcc.target/aarch64/sve/acle/asm/clz_u16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/clz_u32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/clz_u64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/clz_u8.c | 81 ++ .../aarch64/sve/acle/asm/cmla_f16.c | 675 ++++++++++ .../aarch64/sve/acle/asm/cmla_f32.c | 675 ++++++++++ .../aarch64/sve/acle/asm/cmla_f64.c | 675 ++++++++++ .../aarch64/sve/acle/asm/cmla_lane_f16.c | 194 +++ .../aarch64/sve/acle/asm/cmla_lane_f32.c | 176 +++ .../aarch64/sve/acle/asm/cmpeq_f16.c | 50 + .../aarch64/sve/acle/asm/cmpeq_f32.c | 50 + .../aarch64/sve/acle/asm/cmpeq_f64.c | 50 + .../aarch64/sve/acle/asm/cmpeq_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_s64.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_u64.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpeq_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_f16.c | 66 + .../aarch64/sve/acle/asm/cmpge_f32.c | 66 + .../aarch64/sve/acle/asm/cmpge_f64.c | 66 + .../aarch64/sve/acle/asm/cmpge_s16.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_s32.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_s64.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_s8.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_u16.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_u32.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_u64.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_u8.c | 116 ++ .../aarch64/sve/acle/asm/cmpge_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_wide_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_wide_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmpge_wide_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_f16.c | 66 + .../aarch64/sve/acle/asm/cmpgt_f32.c | 66 + .../aarch64/sve/acle/asm/cmpgt_f64.c | 66 + .../aarch64/sve/acle/asm/cmpgt_s16.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_s32.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_s64.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_s8.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_u16.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_u32.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_u64.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_u8.c | 116 ++ .../aarch64/sve/acle/asm/cmpgt_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_wide_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_wide_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmpgt_wide_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmple_f16.c | 66 + .../aarch64/sve/acle/asm/cmple_f32.c | 66 + .../aarch64/sve/acle/asm/cmple_f64.c | 66 + .../aarch64/sve/acle/asm/cmple_s16.c | 116 ++ .../aarch64/sve/acle/asm/cmple_s32.c | 116 ++ .../aarch64/sve/acle/asm/cmple_s64.c | 116 ++ .../aarch64/sve/acle/asm/cmple_s8.c | 116 ++ .../aarch64/sve/acle/asm/cmple_u16.c | 116 ++ .../aarch64/sve/acle/asm/cmple_u32.c | 116 ++ .../aarch64/sve/acle/asm/cmple_u64.c | 116 ++ .../aarch64/sve/acle/asm/cmple_u8.c | 116 ++ .../aarch64/sve/acle/asm/cmple_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmple_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmple_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmple_wide_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmple_wide_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmple_wide_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_f16.c | 66 + .../aarch64/sve/acle/asm/cmplt_f32.c | 66 + .../aarch64/sve/acle/asm/cmplt_f64.c | 66 + .../aarch64/sve/acle/asm/cmplt_s16.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_s32.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_s64.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_s8.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_u16.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_u32.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_u64.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_u8.c | 116 ++ .../aarch64/sve/acle/asm/cmplt_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_wide_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_wide_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmplt_wide_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_f16.c | 50 + .../aarch64/sve/acle/asm/cmpne_f32.c | 50 + .../aarch64/sve/acle/asm/cmpne_f64.c | 50 + .../aarch64/sve/acle/asm/cmpne_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_s64.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_u16.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_u32.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_u64.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_u8.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_wide_s16.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_wide_s32.c | 96 ++ .../aarch64/sve/acle/asm/cmpne_wide_s8.c | 96 ++ .../aarch64/sve/acle/asm/cmpuo_f16.c | 51 + .../aarch64/sve/acle/asm/cmpuo_f32.c | 51 + .../aarch64/sve/acle/asm/cmpuo_f64.c | 51 + .../aarch64/sve/acle/asm/cnot_s16.c | 81 ++ .../aarch64/sve/acle/asm/cnot_s32.c | 81 ++ .../aarch64/sve/acle/asm/cnot_s64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnot_s8.c | 81 ++ .../aarch64/sve/acle/asm/cnot_u16.c | 81 ++ .../aarch64/sve/acle/asm/cnot_u32.c | 81 ++ .../aarch64/sve/acle/asm/cnot_u64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnot_u8.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnt_f16.c | 52 + .../gcc.target/aarch64/sve/acle/asm/cnt_f32.c | 52 + .../gcc.target/aarch64/sve/acle/asm/cnt_f64.c | 52 + .../gcc.target/aarch64/sve/acle/asm/cnt_s16.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cnt_s32.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cnt_s64.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cnt_s8.c | 41 + .../gcc.target/aarch64/sve/acle/asm/cnt_u16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnt_u32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnt_u64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cnt_u8.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/cntb.c | 280 ++++ .../aarch64/sve/acle/asm/cntb_pat.c | 432 ++++++ .../gcc.target/aarch64/sve/acle/asm/cntd.c | 278 ++++ .../aarch64/sve/acle/asm/cntd_pat.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/cnth.c | 280 ++++ .../aarch64/sve/acle/asm/cnth_pat.c | 426 ++++++ .../aarch64/sve/acle/asm/cntp_b16.c | 243 ++++ .../aarch64/sve/acle/asm/cntp_b32.c | 243 ++++ .../aarch64/sve/acle/asm/cntp_b64.c | 243 ++++ .../gcc.target/aarch64/sve/acle/asm/cntp_b8.c | 253 ++++ .../gcc.target/aarch64/sve/acle/asm/cntw.c | 279 ++++ .../aarch64/sve/acle/asm/cntw_pat.c | 426 ++++++ .../aarch64/sve/acle/asm/compact_f32.c | 21 + .../aarch64/sve/acle/asm/compact_f64.c | 21 + .../aarch64/sve/acle/asm/compact_s32.c | 21 + .../aarch64/sve/acle/asm/compact_s64.c | 21 + .../aarch64/sve/acle/asm/compact_u32.c | 21 + .../aarch64/sve/acle/asm/compact_u64.c | 21 + .../aarch64/sve/acle/asm/create2_1.c | 113 ++ .../aarch64/sve/acle/asm/create3_1.c | 124 ++ .../aarch64/sve/acle/asm/create4_1.c | 135 ++ .../gcc.target/aarch64/sve/acle/asm/cvt_f16.c | 731 ++++++++++ .../gcc.target/aarch64/sve/acle/asm/cvt_f32.c | 549 ++++++++ .../gcc.target/aarch64/sve/acle/asm/cvt_f64.c | 549 ++++++++ .../gcc.target/aarch64/sve/acle/asm/cvt_s16.c | 72 + .../gcc.target/aarch64/sve/acle/asm/cvt_s32.c | 210 +++ .../gcc.target/aarch64/sve/acle/asm/cvt_s64.c | 210 +++ .../gcc.target/aarch64/sve/acle/asm/cvt_u16.c | 72 + .../gcc.target/aarch64/sve/acle/asm/cvt_u32.c | 210 +++ .../gcc.target/aarch64/sve/acle/asm/cvt_u64.c | 210 +++ .../gcc.target/aarch64/sve/acle/asm/div_f16.c | 303 +++++ .../gcc.target/aarch64/sve/acle/asm/div_f32.c | 303 +++++ .../gcc.target/aarch64/sve/acle/asm/div_f64.c | 303 +++++ .../gcc.target/aarch64/sve/acle/asm/div_s32.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/div_s64.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/div_u32.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/div_u64.c | 237 ++++ .../aarch64/sve/acle/asm/divr_f16.c | 324 +++++ .../aarch64/sve/acle/asm/divr_f32.c | 324 +++++ .../aarch64/sve/acle/asm/divr_f64.c | 324 +++++ .../aarch64/sve/acle/asm/divr_s32.c | 247 ++++ .../aarch64/sve/acle/asm/divr_s64.c | 247 ++++ .../aarch64/sve/acle/asm/divr_u32.c | 247 ++++ .../aarch64/sve/acle/asm/divr_u64.c | 247 ++++ .../aarch64/sve/acle/asm/dot_lane_s32.c | 93 ++ .../aarch64/sve/acle/asm/dot_lane_s64.c | 74 + .../aarch64/sve/acle/asm/dot_lane_u32.c | 93 ++ .../aarch64/sve/acle/asm/dot_lane_u64.c | 74 + .../gcc.target/aarch64/sve/acle/asm/dot_s32.c | 86 ++ .../gcc.target/aarch64/sve/acle/asm/dot_s64.c | 86 ++ .../gcc.target/aarch64/sve/acle/asm/dot_u32.c | 86 ++ .../gcc.target/aarch64/sve/acle/asm/dot_u64.c | 86 ++ .../gcc.target/aarch64/sve/acle/asm/dup_b16.c | 32 + .../gcc.target/aarch64/sve/acle/asm/dup_b32.c | 32 + .../gcc.target/aarch64/sve/acle/asm/dup_b64.c | 32 + .../gcc.target/aarch64/sve/acle/asm/dup_b8.c | 32 + .../gcc.target/aarch64/sve/acle/asm/dup_f16.c | 215 +++ .../gcc.target/aarch64/sve/acle/asm/dup_f32.c | 212 +++ .../gcc.target/aarch64/sve/acle/asm/dup_f64.c | 212 +++ .../aarch64/sve/acle/asm/dup_lane_f16.c | 108 ++ .../aarch64/sve/acle/asm/dup_lane_f32.c | 110 ++ .../aarch64/sve/acle/asm/dup_lane_f64.c | 111 ++ .../aarch64/sve/acle/asm/dup_lane_s16.c | 126 ++ .../aarch64/sve/acle/asm/dup_lane_s32.c | 128 ++ .../aarch64/sve/acle/asm/dup_lane_s64.c | 130 ++ .../aarch64/sve/acle/asm/dup_lane_s8.c | 124 ++ .../aarch64/sve/acle/asm/dup_lane_u16.c | 126 ++ .../aarch64/sve/acle/asm/dup_lane_u32.c | 128 ++ .../aarch64/sve/acle/asm/dup_lane_u64.c | 130 ++ .../aarch64/sve/acle/asm/dup_lane_u8.c | 124 ++ .../gcc.target/aarch64/sve/acle/asm/dup_s16.c | 1193 +++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_s32.c | 1175 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_s64.c | 1175 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_s8.c | 383 ++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u16.c | 1193 +++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u32.c | 1175 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u64.c | 1175 ++++++++++++++++ .../gcc.target/aarch64/sve/acle/asm/dup_u8.c | 383 ++++++ .../aarch64/sve/acle/asm/dupq_b16.c | 276 ++++ .../aarch64/sve/acle/asm/dupq_b32.c | 132 ++ .../aarch64/sve/acle/asm/dupq_b64.c | 55 + .../gcc.target/aarch64/sve/acle/asm/dupq_b8.c | 413 ++++++ .../aarch64/sve/acle/asm/dupq_f16.c | 53 + .../aarch64/sve/acle/asm/dupq_f32.c | 53 + .../aarch64/sve/acle/asm/dupq_f64.c | 13 + .../aarch64/sve/acle/asm/dupq_lane_f16.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_f32.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_f64.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_s16.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_s32.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_s64.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_s8.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_u16.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_u32.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_u64.c | 48 + .../aarch64/sve/acle/asm/dupq_lane_u8.c | 48 + .../aarch64/sve/acle/asm/dupq_s16.c | 70 + .../aarch64/sve/acle/asm/dupq_s32.c | 61 + .../aarch64/sve/acle/asm/dupq_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/dupq_s8.c | 99 ++ .../aarch64/sve/acle/asm/dupq_u16.c | 70 + .../aarch64/sve/acle/asm/dupq_u32.c | 61 + .../aarch64/sve/acle/asm/dupq_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/dupq_u8.c | 99 ++ .../gcc.target/aarch64/sve/acle/asm/eor_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/eor_s16.c | 376 ++++++ .../gcc.target/aarch64/sve/acle/asm/eor_s32.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/eor_s64.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/eor_s8.c | 296 ++++ .../gcc.target/aarch64/sve/acle/asm/eor_u16.c | 376 ++++++ .../gcc.target/aarch64/sve/acle/asm/eor_u32.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/eor_u64.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/eor_u8.c | 296 ++++ .../aarch64/sve/acle/asm/eorv_s16.c | 13 + .../aarch64/sve/acle/asm/eorv_s32.c | 13 + .../aarch64/sve/acle/asm/eorv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/eorv_s8.c | 13 + .../aarch64/sve/acle/asm/eorv_u16.c | 13 + .../aarch64/sve/acle/asm/eorv_u32.c | 13 + .../aarch64/sve/acle/asm/eorv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/eorv_u8.c | 13 + .../aarch64/sve/acle/asm/expa_f16.c | 21 + .../aarch64/sve/acle/asm/expa_f32.c | 21 + .../aarch64/sve/acle/asm/expa_f64.c | 21 + .../gcc.target/aarch64/sve/acle/asm/ext_f16.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_f32.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_f64.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_s16.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_s32.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_s64.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_s8.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_u16.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_u32.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_u64.c | 73 + .../gcc.target/aarch64/sve/acle/asm/ext_u8.c | 73 + .../aarch64/sve/acle/asm/extb_s16.c | 81 ++ .../aarch64/sve/acle/asm/extb_s32.c | 81 ++ .../aarch64/sve/acle/asm/extb_s64.c | 81 ++ .../aarch64/sve/acle/asm/extb_u16.c | 82 ++ .../aarch64/sve/acle/asm/extb_u32.c | 82 ++ .../aarch64/sve/acle/asm/extb_u64.c | 82 ++ .../aarch64/sve/acle/asm/exth_s32.c | 81 ++ .../aarch64/sve/acle/asm/exth_s64.c | 81 ++ .../aarch64/sve/acle/asm/exth_u32.c | 82 ++ .../aarch64/sve/acle/asm/exth_u64.c | 82 ++ .../aarch64/sve/acle/asm/extw_s64.c | 81 ++ .../aarch64/sve/acle/asm/extw_u64.c | 82 ++ .../aarch64/sve/acle/asm/get2_f16.c | 55 + .../aarch64/sve/acle/asm/get2_f32.c | 55 + .../aarch64/sve/acle/asm/get2_f64.c | 55 + .../aarch64/sve/acle/asm/get2_s16.c | 55 + .../aarch64/sve/acle/asm/get2_s32.c | 55 + .../aarch64/sve/acle/asm/get2_s64.c | 55 + .../gcc.target/aarch64/sve/acle/asm/get2_s8.c | 55 + .../aarch64/sve/acle/asm/get2_u16.c | 55 + .../aarch64/sve/acle/asm/get2_u32.c | 55 + .../aarch64/sve/acle/asm/get2_u64.c | 55 + .../gcc.target/aarch64/sve/acle/asm/get2_u8.c | 55 + .../aarch64/sve/acle/asm/get3_f16.c | 108 ++ .../aarch64/sve/acle/asm/get3_f32.c | 108 ++ .../aarch64/sve/acle/asm/get3_f64.c | 108 ++ .../aarch64/sve/acle/asm/get3_s16.c | 108 ++ .../aarch64/sve/acle/asm/get3_s32.c | 108 ++ .../aarch64/sve/acle/asm/get3_s64.c | 108 ++ .../gcc.target/aarch64/sve/acle/asm/get3_s8.c | 108 ++ .../aarch64/sve/acle/asm/get3_u16.c | 108 ++ .../aarch64/sve/acle/asm/get3_u32.c | 108 ++ .../aarch64/sve/acle/asm/get3_u64.c | 108 ++ .../gcc.target/aarch64/sve/acle/asm/get3_u8.c | 108 ++ .../aarch64/sve/acle/asm/get4_f16.c | 179 +++ .../aarch64/sve/acle/asm/get4_f32.c | 179 +++ .../aarch64/sve/acle/asm/get4_f64.c | 179 +++ .../aarch64/sve/acle/asm/get4_s16.c | 179 +++ .../aarch64/sve/acle/asm/get4_s32.c | 179 +++ .../aarch64/sve/acle/asm/get4_s64.c | 179 +++ .../gcc.target/aarch64/sve/acle/asm/get4_s8.c | 179 +++ .../aarch64/sve/acle/asm/get4_u16.c | 179 +++ .../aarch64/sve/acle/asm/get4_u32.c | 179 +++ .../aarch64/sve/acle/asm/get4_u64.c | 179 +++ .../gcc.target/aarch64/sve/acle/asm/get4_u8.c | 179 +++ .../aarch64/sve/acle/asm/index_s16.c | 220 +++ .../aarch64/sve/acle/asm/index_s32.c | 220 +++ .../aarch64/sve/acle/asm/index_s64.c | 220 +++ .../aarch64/sve/acle/asm/index_s8.c | 220 +++ .../aarch64/sve/acle/asm/index_u16.c | 220 +++ .../aarch64/sve/acle/asm/index_u32.c | 220 +++ .../aarch64/sve/acle/asm/index_u64.c | 220 +++ .../aarch64/sve/acle/asm/index_u8.c | 220 +++ .../aarch64/sve/acle/asm/insr_f16.c | 51 + .../aarch64/sve/acle/asm/insr_f32.c | 51 + .../aarch64/sve/acle/asm/insr_f64.c | 51 + .../aarch64/sve/acle/asm/insr_s16.c | 56 + .../aarch64/sve/acle/asm/insr_s32.c | 56 + .../aarch64/sve/acle/asm/insr_s64.c | 56 + .../gcc.target/aarch64/sve/acle/asm/insr_s8.c | 56 + .../aarch64/sve/acle/asm/insr_u16.c | 56 + .../aarch64/sve/acle/asm/insr_u32.c | 56 + .../aarch64/sve/acle/asm/insr_u64.c | 56 + .../gcc.target/aarch64/sve/acle/asm/insr_u8.c | 56 + .../aarch64/sve/acle/asm/lasta_f16.c | 21 + .../aarch64/sve/acle/asm/lasta_f32.c | 21 + .../aarch64/sve/acle/asm/lasta_f64.c | 21 + .../aarch64/sve/acle/asm/lasta_s16.c | 12 + .../aarch64/sve/acle/asm/lasta_s32.c | 12 + .../aarch64/sve/acle/asm/lasta_s64.c | 12 + .../aarch64/sve/acle/asm/lasta_s8.c | 12 + .../aarch64/sve/acle/asm/lasta_u16.c | 12 + .../aarch64/sve/acle/asm/lasta_u32.c | 12 + .../aarch64/sve/acle/asm/lasta_u64.c | 12 + .../aarch64/sve/acle/asm/lasta_u8.c | 12 + .../aarch64/sve/acle/asm/lastb_f16.c | 21 + .../aarch64/sve/acle/asm/lastb_f32.c | 21 + .../aarch64/sve/acle/asm/lastb_f64.c | 21 + .../aarch64/sve/acle/asm/lastb_s16.c | 12 + .../aarch64/sve/acle/asm/lastb_s32.c | 12 + .../aarch64/sve/acle/asm/lastb_s64.c | 12 + .../aarch64/sve/acle/asm/lastb_s8.c | 12 + .../aarch64/sve/acle/asm/lastb_u16.c | 12 + .../aarch64/sve/acle/asm/lastb_u32.c | 12 + .../aarch64/sve/acle/asm/lastb_u64.c | 12 + .../aarch64/sve/acle/asm/lastb_u8.c | 12 + .../gcc.target/aarch64/sve/acle/asm/ld1_f16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_f32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_f64.c | 158 +++ .../aarch64/sve/acle/asm/ld1_gather_f32.c | 272 ++++ .../aarch64/sve/acle/asm/ld1_gather_f64.c | 348 +++++ .../aarch64/sve/acle/asm/ld1_gather_s32.c | 272 ++++ .../aarch64/sve/acle/asm/ld1_gather_s64.c | 348 +++++ .../aarch64/sve/acle/asm/ld1_gather_u32.c | 272 ++++ .../aarch64/sve/acle/asm/ld1_gather_u64.c | 348 +++++ .../gcc.target/aarch64/sve/acle/asm/ld1_s16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_s32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_s64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_s8.c | 162 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_u16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_u32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_u64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld1_u8.c | 162 +++ .../aarch64/sve/acle/asm/ld1rq_f16.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_f32.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_f64.c | 97 ++ .../aarch64/sve/acle/asm/ld1rq_s16.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_s32.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_s64.c | 97 ++ .../aarch64/sve/acle/asm/ld1rq_s8.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_u16.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_u32.c | 137 ++ .../aarch64/sve/acle/asm/ld1rq_u64.c | 97 ++ .../aarch64/sve/acle/asm/ld1rq_u8.c | 137 ++ .../aarch64/sve/acle/asm/ld1sb_gather_s32.c | 131 ++ .../aarch64/sve/acle/asm/ld1sb_gather_s64.c | 149 ++ .../aarch64/sve/acle/asm/ld1sb_gather_u32.c | 131 ++ .../aarch64/sve/acle/asm/ld1sb_gather_u64.c | 149 ++ .../aarch64/sve/acle/asm/ld1sb_s16.c | 162 +++ .../aarch64/sve/acle/asm/ld1sb_s32.c | 162 +++ .../aarch64/sve/acle/asm/ld1sb_s64.c | 162 +++ .../aarch64/sve/acle/asm/ld1sb_u16.c | 162 +++ .../aarch64/sve/acle/asm/ld1sb_u32.c | 162 +++ .../aarch64/sve/acle/asm/ld1sb_u64.c | 162 +++ .../aarch64/sve/acle/asm/ld1sh_gather_s32.c | 252 ++++ .../aarch64/sve/acle/asm/ld1sh_gather_s64.c | 288 ++++ .../aarch64/sve/acle/asm/ld1sh_gather_u32.c | 252 ++++ .../aarch64/sve/acle/asm/ld1sh_gather_u64.c | 288 ++++ .../aarch64/sve/acle/asm/ld1sh_s32.c | 158 +++ .../aarch64/sve/acle/asm/ld1sh_s64.c | 158 +++ .../aarch64/sve/acle/asm/ld1sh_u32.c | 158 +++ .../aarch64/sve/acle/asm/ld1sh_u64.c | 158 +++ .../aarch64/sve/acle/asm/ld1sw_gather_s64.c | 308 +++++ .../aarch64/sve/acle/asm/ld1sw_gather_u64.c | 308 +++++ .../aarch64/sve/acle/asm/ld1sw_s64.c | 158 +++ .../aarch64/sve/acle/asm/ld1sw_u64.c | 158 +++ .../aarch64/sve/acle/asm/ld1ub_gather_s32.c | 131 ++ .../aarch64/sve/acle/asm/ld1ub_gather_s64.c | 149 ++ .../aarch64/sve/acle/asm/ld1ub_gather_u32.c | 131 ++ .../aarch64/sve/acle/asm/ld1ub_gather_u64.c | 149 ++ .../aarch64/sve/acle/asm/ld1ub_s16.c | 162 +++ .../aarch64/sve/acle/asm/ld1ub_s32.c | 162 +++ .../aarch64/sve/acle/asm/ld1ub_s64.c | 162 +++ .../aarch64/sve/acle/asm/ld1ub_u16.c | 162 +++ .../aarch64/sve/acle/asm/ld1ub_u32.c | 162 +++ .../aarch64/sve/acle/asm/ld1ub_u64.c | 162 +++ .../aarch64/sve/acle/asm/ld1uh_gather_s32.c | 252 ++++ .../aarch64/sve/acle/asm/ld1uh_gather_s64.c | 288 ++++ .../aarch64/sve/acle/asm/ld1uh_gather_u32.c | 252 ++++ .../aarch64/sve/acle/asm/ld1uh_gather_u64.c | 288 ++++ .../aarch64/sve/acle/asm/ld1uh_s32.c | 158 +++ .../aarch64/sve/acle/asm/ld1uh_s64.c | 158 +++ .../aarch64/sve/acle/asm/ld1uh_u32.c | 158 +++ .../aarch64/sve/acle/asm/ld1uh_u64.c | 158 +++ .../aarch64/sve/acle/asm/ld1uw_gather_s64.c | 308 +++++ .../aarch64/sve/acle/asm/ld1uw_gather_u64.c | 308 +++++ .../aarch64/sve/acle/asm/ld1uw_s64.c | 158 +++ .../aarch64/sve/acle/asm/ld1uw_u64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_f16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_f32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_f64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_s16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_s32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_s64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_s8.c | 204 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_u16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_u32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_u64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/ld2_u8.c | 204 +++ .../gcc.target/aarch64/sve/acle/asm/ld3_f16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_f32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_f64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_s16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_s32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_s64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_s8.c | 246 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_u16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_u32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_u64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/ld3_u8.c | 246 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_f16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_f32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_f64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_s16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_s32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_s64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_s8.c | 290 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_u16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_u32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_u64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/ld4_u8.c | 290 ++++ .../aarch64/sve/acle/asm/ldff1_f16.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_f32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_f64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_gather_f32.c | 272 ++++ .../aarch64/sve/acle/asm/ldff1_gather_f64.c | 348 +++++ .../aarch64/sve/acle/asm/ldff1_gather_s32.c | 272 ++++ .../aarch64/sve/acle/asm/ldff1_gather_s64.c | 348 +++++ .../aarch64/sve/acle/asm/ldff1_gather_u32.c | 272 ++++ .../aarch64/sve/acle/asm/ldff1_gather_u64.c | 348 +++++ .../aarch64/sve/acle/asm/ldff1_s16.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_s32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_s64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_s8.c | 90 ++ .../aarch64/sve/acle/asm/ldff1_u16.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_u32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_u64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1_u8.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_gather_s32.c | 131 ++ .../aarch64/sve/acle/asm/ldff1sb_gather_s64.c | 149 ++ .../aarch64/sve/acle/asm/ldff1sb_gather_u32.c | 131 ++ .../aarch64/sve/acle/asm/ldff1sb_gather_u64.c | 149 ++ .../aarch64/sve/acle/asm/ldff1sb_s16.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_s32.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_s64.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_u16.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_u32.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sb_u64.c | 90 ++ .../aarch64/sve/acle/asm/ldff1sh_gather_s32.c | 252 ++++ .../aarch64/sve/acle/asm/ldff1sh_gather_s64.c | 288 ++++ .../aarch64/sve/acle/asm/ldff1sh_gather_u32.c | 252 ++++ .../aarch64/sve/acle/asm/ldff1sh_gather_u64.c | 288 ++++ .../aarch64/sve/acle/asm/ldff1sh_s32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1sh_s64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1sh_u32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1sh_u64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1sw_gather_s64.c | 308 +++++ .../aarch64/sve/acle/asm/ldff1sw_gather_u64.c | 308 +++++ .../aarch64/sve/acle/asm/ldff1sw_s64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1sw_u64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1ub_gather_s32.c | 131 ++ .../aarch64/sve/acle/asm/ldff1ub_gather_s64.c | 149 ++ .../aarch64/sve/acle/asm/ldff1ub_gather_u32.c | 131 ++ .../aarch64/sve/acle/asm/ldff1ub_gather_u64.c | 149 ++ .../aarch64/sve/acle/asm/ldff1ub_s16.c | 90 ++ .../aarch64/sve/acle/asm/ldff1ub_s32.c | 90 ++ .../aarch64/sve/acle/asm/ldff1ub_s64.c | 90 ++ .../aarch64/sve/acle/asm/ldff1ub_u16.c | 90 ++ .../aarch64/sve/acle/asm/ldff1ub_u32.c | 90 ++ .../aarch64/sve/acle/asm/ldff1ub_u64.c | 90 ++ .../aarch64/sve/acle/asm/ldff1uh_gather_s32.c | 252 ++++ .../aarch64/sve/acle/asm/ldff1uh_gather_s64.c | 288 ++++ .../aarch64/sve/acle/asm/ldff1uh_gather_u32.c | 252 ++++ .../aarch64/sve/acle/asm/ldff1uh_gather_u64.c | 288 ++++ .../aarch64/sve/acle/asm/ldff1uh_s32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1uh_s64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1uh_u32.c | 86 ++ .../aarch64/sve/acle/asm/ldff1uh_u64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1uw_gather_s64.c | 308 +++++ .../aarch64/sve/acle/asm/ldff1uw_gather_u64.c | 308 +++++ .../aarch64/sve/acle/asm/ldff1uw_s64.c | 86 ++ .../aarch64/sve/acle/asm/ldff1uw_u64.c | 86 ++ .../aarch64/sve/acle/asm/ldnf1_f16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_f32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_f64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_s16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_s32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_s8.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_u16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_u32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1_u8.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_s16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_s32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_u16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_u32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sb_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sh_s32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sh_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sh_u32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sh_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sw_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1sw_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_s16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_s32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_u16.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_u32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1ub_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uh_s32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uh_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uh_u32.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uh_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uw_s64.c | 154 +++ .../aarch64/sve/acle/asm/ldnf1uw_u64.c | 154 +++ .../aarch64/sve/acle/asm/ldnt1_f16.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_f32.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_f64.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_s16.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_s32.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_s64.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_s8.c | 162 +++ .../aarch64/sve/acle/asm/ldnt1_u16.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_u32.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_u64.c | 158 +++ .../aarch64/sve/acle/asm/ldnt1_u8.c | 162 +++ .../gcc.target/aarch64/sve/acle/asm/len_f16.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_f32.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_f64.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_s16.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_s32.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_s64.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_s8.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_u16.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_u32.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_u64.c | 12 + .../gcc.target/aarch64/sve/acle/asm/len_u8.c | 12 + .../gcc.target/aarch64/sve/acle/asm/lsl_s16.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_s32.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_s64.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_s8.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_u16.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_u32.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_u64.c | 351 +++++ .../gcc.target/aarch64/sve/acle/asm/lsl_u8.c | 351 +++++ .../aarch64/sve/acle/asm/lsl_wide_s16.c | 331 +++++ .../aarch64/sve/acle/asm/lsl_wide_s32.c | 331 +++++ .../aarch64/sve/acle/asm/lsl_wide_s8.c | 331 +++++ .../aarch64/sve/acle/asm/lsl_wide_u16.c | 331 +++++ .../aarch64/sve/acle/asm/lsl_wide_u32.c | 331 +++++ .../aarch64/sve/acle/asm/lsl_wide_u8.c | 331 +++++ .../gcc.target/aarch64/sve/acle/asm/lsr_u16.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/lsr_u32.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/lsr_u64.c | 340 +++++ .../gcc.target/aarch64/sve/acle/asm/lsr_u8.c | 340 +++++ .../aarch64/sve/acle/asm/lsr_wide_u16.c | 325 +++++ .../aarch64/sve/acle/asm/lsr_wide_u32.c | 325 +++++ .../aarch64/sve/acle/asm/lsr_wide_u8.c | 325 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_f16.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mad_f32.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mad_f64.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mad_s16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_s32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_s64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_s8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_u16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_u32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_u64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mad_u8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/max_f16.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/max_f32.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/max_f64.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/max_s16.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_s32.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_s64.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_s8.c | 273 ++++ .../gcc.target/aarch64/sve/acle/asm/max_u16.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_u32.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_u64.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/max_u8.c | 273 ++++ .../aarch64/sve/acle/asm/maxnm_f16.c | 425 ++++++ .../aarch64/sve/acle/asm/maxnm_f32.c | 425 ++++++ .../aarch64/sve/acle/asm/maxnm_f64.c | 425 ++++++ .../aarch64/sve/acle/asm/maxnmv_f16.c | 21 + .../aarch64/sve/acle/asm/maxnmv_f32.c | 21 + .../aarch64/sve/acle/asm/maxnmv_f64.c | 21 + .../aarch64/sve/acle/asm/maxv_f16.c | 21 + .../aarch64/sve/acle/asm/maxv_f32.c | 21 + .../aarch64/sve/acle/asm/maxv_f64.c | 21 + .../aarch64/sve/acle/asm/maxv_s16.c | 13 + .../aarch64/sve/acle/asm/maxv_s32.c | 13 + .../aarch64/sve/acle/asm/maxv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/maxv_s8.c | 13 + .../aarch64/sve/acle/asm/maxv_u16.c | 13 + .../aarch64/sve/acle/asm/maxv_u32.c | 13 + .../aarch64/sve/acle/asm/maxv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/maxv_u8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/min_f16.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/min_f32.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/min_f64.c | 425 ++++++ .../gcc.target/aarch64/sve/acle/asm/min_s16.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_s32.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_s64.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_s8.c | 273 ++++ .../gcc.target/aarch64/sve/acle/asm/min_u16.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_u32.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_u64.c | 293 ++++ .../gcc.target/aarch64/sve/acle/asm/min_u8.c | 273 ++++ .../aarch64/sve/acle/asm/minnm_f16.c | 425 ++++++ .../aarch64/sve/acle/asm/minnm_f32.c | 425 ++++++ .../aarch64/sve/acle/asm/minnm_f64.c | 425 ++++++ .../aarch64/sve/acle/asm/minnmv_f16.c | 21 + .../aarch64/sve/acle/asm/minnmv_f32.c | 21 + .../aarch64/sve/acle/asm/minnmv_f64.c | 21 + .../aarch64/sve/acle/asm/minv_f16.c | 21 + .../aarch64/sve/acle/asm/minv_f32.c | 21 + .../aarch64/sve/acle/asm/minv_f64.c | 21 + .../aarch64/sve/acle/asm/minv_s16.c | 13 + .../aarch64/sve/acle/asm/minv_s32.c | 13 + .../aarch64/sve/acle/asm/minv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/minv_s8.c | 13 + .../aarch64/sve/acle/asm/minv_u16.c | 13 + .../aarch64/sve/acle/asm/minv_u32.c | 13 + .../aarch64/sve/acle/asm/minv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/minv_u8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/mla_f16.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mla_f32.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mla_f64.c | 398 ++++++ .../aarch64/sve/acle/asm/mla_lane_f16.c | 128 ++ .../aarch64/sve/acle/asm/mla_lane_f32.c | 92 ++ .../aarch64/sve/acle/asm/mla_lane_f64.c | 83 ++ .../gcc.target/aarch64/sve/acle/asm/mla_s16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_s32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_s64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_s8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_u16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_u32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_u64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mla_u8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_f16.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mls_f32.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/mls_f64.c | 398 ++++++ .../aarch64/sve/acle/asm/mls_lane_f16.c | 128 ++ .../aarch64/sve/acle/asm/mls_lane_f32.c | 92 ++ .../aarch64/sve/acle/asm/mls_lane_f64.c | 83 ++ .../gcc.target/aarch64/sve/acle/asm/mls_s16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_s32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_s64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_s8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_u16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_u32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_u64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mls_u8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mov_b.c | 21 + .../gcc.target/aarch64/sve/acle/asm/msb_f16.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/msb_f32.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/msb_f64.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/msb_s16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_s32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_s64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_s8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_u16.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_u32.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_u64.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/msb_u8.c | 321 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_f16.c | 444 ++++++ .../aarch64/sve/acle/asm/mul_f16_notrap.c | 439 ++++++ .../gcc.target/aarch64/sve/acle/asm/mul_f32.c | 444 ++++++ .../aarch64/sve/acle/asm/mul_f32_notrap.c | 439 ++++++ .../gcc.target/aarch64/sve/acle/asm/mul_f64.c | 444 ++++++ .../aarch64/sve/acle/asm/mul_f64_notrap.c | 439 ++++++ .../aarch64/sve/acle/asm/mul_lane_f16.c | 114 ++ .../aarch64/sve/acle/asm/mul_lane_f32.c | 78 ++ .../aarch64/sve/acle/asm/mul_lane_f64.c | 69 + .../gcc.target/aarch64/sve/acle/asm/mul_s16.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_s32.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_s64.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_s8.c | 300 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_u16.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_u32.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_u64.c | 302 +++++ .../gcc.target/aarch64/sve/acle/asm/mul_u8.c | 300 +++++ .../aarch64/sve/acle/asm/mulh_s16.c | 237 ++++ .../aarch64/sve/acle/asm/mulh_s32.c | 237 ++++ .../aarch64/sve/acle/asm/mulh_s64.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/mulh_s8.c | 237 ++++ .../aarch64/sve/acle/asm/mulh_u16.c | 237 ++++ .../aarch64/sve/acle/asm/mulh_u32.c | 237 ++++ .../aarch64/sve/acle/asm/mulh_u64.c | 237 ++++ .../gcc.target/aarch64/sve/acle/asm/mulh_u8.c | 237 ++++ .../aarch64/sve/acle/asm/mulx_f16.c | 472 +++++++ .../aarch64/sve/acle/asm/mulx_f32.c | 472 +++++++ .../aarch64/sve/acle/asm/mulx_f64.c | 472 +++++++ .../gcc.target/aarch64/sve/acle/asm/nand_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/neg_f16.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/neg_f32.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/neg_f64.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/neg_s16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/neg_s32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/neg_s64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/neg_s8.c | 81 ++ .../aarch64/sve/acle/asm/nmad_f16.c | 398 ++++++ .../aarch64/sve/acle/asm/nmad_f32.c | 398 ++++++ .../aarch64/sve/acle/asm/nmad_f64.c | 398 ++++++ .../aarch64/sve/acle/asm/nmla_f16.c | 398 ++++++ .../aarch64/sve/acle/asm/nmla_f32.c | 398 ++++++ .../aarch64/sve/acle/asm/nmla_f64.c | 398 ++++++ .../aarch64/sve/acle/asm/nmls_f16.c | 398 ++++++ .../aarch64/sve/acle/asm/nmls_f32.c | 398 ++++++ .../aarch64/sve/acle/asm/nmls_f64.c | 398 ++++++ .../aarch64/sve/acle/asm/nmsb_f16.c | 398 ++++++ .../aarch64/sve/acle/asm/nmsb_f32.c | 398 ++++++ .../aarch64/sve/acle/asm/nmsb_f64.c | 398 ++++++ .../gcc.target/aarch64/sve/acle/asm/nor_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/not_b.c | 21 + .../gcc.target/aarch64/sve/acle/asm/not_s16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_s32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_s64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_s8.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_u16.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_u32.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_u64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/not_u8.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/orn_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/orr_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/orr_s16.c | 376 ++++++ .../gcc.target/aarch64/sve/acle/asm/orr_s32.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/orr_s64.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/orr_s8.c | 295 ++++ .../gcc.target/aarch64/sve/acle/asm/orr_u16.c | 376 ++++++ .../gcc.target/aarch64/sve/acle/asm/orr_u32.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/orr_u64.c | 372 +++++ .../gcc.target/aarch64/sve/acle/asm/orr_u8.c | 295 ++++ .../gcc.target/aarch64/sve/acle/asm/orv_s16.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_s32.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_s64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_s8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_u16.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_u32.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_u64.c | 13 + .../gcc.target/aarch64/sve/acle/asm/orv_u8.c | 13 + .../gcc.target/aarch64/sve/acle/asm/pfalse.c | 13 + .../aarch64/sve/acle/asm/pfirst_b.c | 22 + .../aarch64/sve/acle/asm/pnext_b16.c | 22 + .../aarch64/sve/acle/asm/pnext_b32.c | 22 + .../aarch64/sve/acle/asm/pnext_b64.c | 22 + .../aarch64/sve/acle/asm/pnext_b8.c | 22 + .../gcc.target/aarch64/sve/acle/asm/prfb.c | 245 ++++ .../aarch64/sve/acle/asm/prfb_gather.c | 223 +++ .../gcc.target/aarch64/sve/acle/asm/prfd.c | 245 ++++ .../aarch64/sve/acle/asm/prfd_gather.c | 225 ++++ .../gcc.target/aarch64/sve/acle/asm/prfh.c | 245 ++++ .../aarch64/sve/acle/asm/prfh_gather.c | 225 ++++ .../gcc.target/aarch64/sve/acle/asm/prfw.c | 245 ++++ .../aarch64/sve/acle/asm/prfw_gather.c | 225 ++++ .../aarch64/sve/acle/asm/ptest_any.c | 77 ++ .../aarch64/sve/acle/asm/ptest_first.c | 77 ++ .../aarch64/sve/acle/asm/ptest_last.c | 77 ++ .../gcc.target/aarch64/sve/acle/asm/ptrue.c | 40 + .../aarch64/sve/acle/asm/ptrue_pat_b16.c | 156 +++ .../aarch64/sve/acle/asm/ptrue_pat_b32.c | 156 +++ .../aarch64/sve/acle/asm/ptrue_pat_b64.c | 156 +++ .../aarch64/sve/acle/asm/ptrue_pat_b8.c | 156 +++ .../aarch64/sve/acle/asm/qadd_s16.c | 123 ++ .../aarch64/sve/acle/asm/qadd_s32.c | 123 ++ .../aarch64/sve/acle/asm/qadd_s64.c | 123 ++ .../gcc.target/aarch64/sve/acle/asm/qadd_s8.c | 123 ++ .../aarch64/sve/acle/asm/qadd_u16.c | 126 ++ .../aarch64/sve/acle/asm/qadd_u32.c | 126 ++ .../aarch64/sve/acle/asm/qadd_u64.c | 126 ++ .../gcc.target/aarch64/sve/acle/asm/qadd_u8.c | 123 ++ .../aarch64/sve/acle/asm/qdecb_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qdecb_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qdecb_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qdecb_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qdecb_s32.c | 58 + .../aarch64/sve/acle/asm/qdecb_s64.c | 58 + .../aarch64/sve/acle/asm/qdecb_u32.c | 58 + .../aarch64/sve/acle/asm/qdecb_u64.c | 58 + .../aarch64/sve/acle/asm/qdecd_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qdecd_pat_s64.c | 401 ++++++ .../aarch64/sve/acle/asm/qdecd_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qdecd_pat_u64.c | 401 ++++++ .../aarch64/sve/acle/asm/qdecd_s32.c | 58 + .../aarch64/sve/acle/asm/qdecd_s64.c | 113 ++ .../aarch64/sve/acle/asm/qdecd_u32.c | 58 + .../aarch64/sve/acle/asm/qdecd_u64.c | 113 ++ .../aarch64/sve/acle/asm/qdech_pat_s16.c | 202 +++ .../aarch64/sve/acle/asm/qdech_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qdech_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qdech_pat_u16.c | 202 +++ .../aarch64/sve/acle/asm/qdech_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qdech_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qdech_s16.c | 58 + .../aarch64/sve/acle/asm/qdech_s32.c | 58 + .../aarch64/sve/acle/asm/qdech_s64.c | 58 + .../aarch64/sve/acle/asm/qdech_u16.c | 58 + .../aarch64/sve/acle/asm/qdech_u32.c | 58 + .../aarch64/sve/acle/asm/qdech_u64.c | 58 + .../aarch64/sve/acle/asm/qdecp_s16.c | 22 + .../aarch64/sve/acle/asm/qdecp_s32.c | 98 ++ .../aarch64/sve/acle/asm/qdecp_s64.c | 98 ++ .../aarch64/sve/acle/asm/qdecp_u16.c | 22 + .../aarch64/sve/acle/asm/qdecp_u32.c | 98 ++ .../aarch64/sve/acle/asm/qdecp_u64.c | 98 ++ .../aarch64/sve/acle/asm/qdecw_pat_s32.c | 401 ++++++ .../aarch64/sve/acle/asm/qdecw_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qdecw_pat_u32.c | 401 ++++++ .../aarch64/sve/acle/asm/qdecw_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qdecw_s32.c | 113 ++ .../aarch64/sve/acle/asm/qdecw_s64.c | 58 + .../aarch64/sve/acle/asm/qdecw_u32.c | 113 ++ .../aarch64/sve/acle/asm/qdecw_u64.c | 58 + .../aarch64/sve/acle/asm/qincb_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qincb_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qincb_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qincb_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qincb_s32.c | 58 + .../aarch64/sve/acle/asm/qincb_s64.c | 58 + .../aarch64/sve/acle/asm/qincb_u32.c | 58 + .../aarch64/sve/acle/asm/qincb_u64.c | 58 + .../aarch64/sve/acle/asm/qincd_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qincd_pat_s64.c | 401 ++++++ .../aarch64/sve/acle/asm/qincd_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qincd_pat_u64.c | 401 ++++++ .../aarch64/sve/acle/asm/qincd_s32.c | 58 + .../aarch64/sve/acle/asm/qincd_s64.c | 113 ++ .../aarch64/sve/acle/asm/qincd_u32.c | 58 + .../aarch64/sve/acle/asm/qincd_u64.c | 113 ++ .../aarch64/sve/acle/asm/qinch_pat_s16.c | 202 +++ .../aarch64/sve/acle/asm/qinch_pat_s32.c | 202 +++ .../aarch64/sve/acle/asm/qinch_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qinch_pat_u16.c | 202 +++ .../aarch64/sve/acle/asm/qinch_pat_u32.c | 202 +++ .../aarch64/sve/acle/asm/qinch_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qinch_s16.c | 58 + .../aarch64/sve/acle/asm/qinch_s32.c | 58 + .../aarch64/sve/acle/asm/qinch_s64.c | 58 + .../aarch64/sve/acle/asm/qinch_u16.c | 58 + .../aarch64/sve/acle/asm/qinch_u32.c | 58 + .../aarch64/sve/acle/asm/qinch_u64.c | 58 + .../aarch64/sve/acle/asm/qincp_s16.c | 22 + .../aarch64/sve/acle/asm/qincp_s32.c | 98 ++ .../aarch64/sve/acle/asm/qincp_s64.c | 98 ++ .../aarch64/sve/acle/asm/qincp_u16.c | 22 + .../aarch64/sve/acle/asm/qincp_u32.c | 98 ++ .../aarch64/sve/acle/asm/qincp_u64.c | 98 ++ .../aarch64/sve/acle/asm/qincw_pat_s32.c | 401 ++++++ .../aarch64/sve/acle/asm/qincw_pat_s64.c | 202 +++ .../aarch64/sve/acle/asm/qincw_pat_u32.c | 401 ++++++ .../aarch64/sve/acle/asm/qincw_pat_u64.c | 202 +++ .../aarch64/sve/acle/asm/qincw_s32.c | 113 ++ .../aarch64/sve/acle/asm/qincw_s64.c | 58 + .../aarch64/sve/acle/asm/qincw_u32.c | 113 ++ .../aarch64/sve/acle/asm/qincw_u64.c | 58 + .../aarch64/sve/acle/asm/qsub_s16.c | 123 ++ .../aarch64/sve/acle/asm/qsub_s32.c | 123 ++ .../aarch64/sve/acle/asm/qsub_s64.c | 123 ++ .../gcc.target/aarch64/sve/acle/asm/qsub_s8.c | 123 ++ .../aarch64/sve/acle/asm/qsub_u16.c | 126 ++ .../aarch64/sve/acle/asm/qsub_u32.c | 126 ++ .../aarch64/sve/acle/asm/qsub_u64.c | 126 ++ .../gcc.target/aarch64/sve/acle/asm/qsub_u8.c | 123 ++ .../aarch64/sve/acle/asm/rbit_s16.c | 81 ++ .../aarch64/sve/acle/asm/rbit_s32.c | 81 ++ .../aarch64/sve/acle/asm/rbit_s64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/rbit_s8.c | 81 ++ .../aarch64/sve/acle/asm/rbit_u16.c | 81 ++ .../aarch64/sve/acle/asm/rbit_u32.c | 81 ++ .../aarch64/sve/acle/asm/rbit_u64.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/rbit_u8.c | 81 ++ .../gcc.target/aarch64/sve/acle/asm/rdffr_1.c | 59 + .../aarch64/sve/acle/asm/recpe_f16.c | 21 + .../aarch64/sve/acle/asm/recpe_f32.c | 21 + .../aarch64/sve/acle/asm/recpe_f64.c | 21 + .../aarch64/sve/acle/asm/recps_f16.c | 30 + .../aarch64/sve/acle/asm/recps_f32.c | 30 + .../aarch64/sve/acle/asm/recps_f64.c | 30 + .../aarch64/sve/acle/asm/recpx_f16.c | 103 ++ .../aarch64/sve/acle/asm/recpx_f32.c | 103 ++ .../aarch64/sve/acle/asm/recpx_f64.c | 103 ++ .../aarch64/sve/acle/asm/reinterpret_f16.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_f32.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_f64.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_s16.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_s32.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_s64.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_s8.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_u16.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_u32.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_u64.c | 190 +++ .../aarch64/sve/acle/asm/reinterpret_u8.c | 190 +++ .../gcc.target/aarch64/sve/acle/asm/rev_b16.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_b32.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_b64.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_b8.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_f16.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_f32.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_f64.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_s16.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_s32.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_s64.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_s8.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_u16.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_u32.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_u64.c | 21 + .../gcc.target/aarch64/sve/acle/asm/rev_u8.c | 21 + .../aarch64/sve/acle/asm/revb_s16.c | 81 ++ .../aarch64/sve/acle/asm/revb_s32.c | 81 ++ .../aarch64/sve/acle/asm/revb_s64.c | 81 ++ .../aarch64/sve/acle/asm/revb_u16.c | 81 ++ .../aarch64/sve/acle/asm/revb_u32.c | 81 ++ .../aarch64/sve/acle/asm/revb_u64.c | 81 ++ .../aarch64/sve/acle/asm/revh_s32.c | 81 ++ .../aarch64/sve/acle/asm/revh_s64.c | 81 ++ .../aarch64/sve/acle/asm/revh_u32.c | 81 ++ .../aarch64/sve/acle/asm/revh_u64.c | 81 ++ .../aarch64/sve/acle/asm/revw_s64.c | 81 ++ .../aarch64/sve/acle/asm/revw_u64.c | 81 ++ .../aarch64/sve/acle/asm/rinta_f16.c | 103 ++ .../aarch64/sve/acle/asm/rinta_f32.c | 103 ++ .../aarch64/sve/acle/asm/rinta_f64.c | 103 ++ .../aarch64/sve/acle/asm/rinti_f16.c | 103 ++ .../aarch64/sve/acle/asm/rinti_f32.c | 103 ++ .../aarch64/sve/acle/asm/rinti_f64.c | 103 ++ .../aarch64/sve/acle/asm/rintm_f16.c | 103 ++ .../aarch64/sve/acle/asm/rintm_f32.c | 103 ++ .../aarch64/sve/acle/asm/rintm_f64.c | 103 ++ .../aarch64/sve/acle/asm/rintn_f16.c | 103 ++ .../aarch64/sve/acle/asm/rintn_f32.c | 103 ++ .../aarch64/sve/acle/asm/rintn_f64.c | 103 ++ .../aarch64/sve/acle/asm/rintp_f16.c | 103 ++ .../aarch64/sve/acle/asm/rintp_f32.c | 103 ++ .../aarch64/sve/acle/asm/rintp_f64.c | 103 ++ .../aarch64/sve/acle/asm/rintx_f16.c | 103 ++ .../aarch64/sve/acle/asm/rintx_f32.c | 103 ++ .../aarch64/sve/acle/asm/rintx_f64.c | 103 ++ .../aarch64/sve/acle/asm/rintz_f16.c | 103 ++ .../aarch64/sve/acle/asm/rintz_f32.c | 103 ++ .../aarch64/sve/acle/asm/rintz_f64.c | 103 ++ .../aarch64/sve/acle/asm/rsqrte_f16.c | 21 + .../aarch64/sve/acle/asm/rsqrte_f32.c | 21 + .../aarch64/sve/acle/asm/rsqrte_f64.c | 21 + .../aarch64/sve/acle/asm/rsqrts_f16.c | 30 + .../aarch64/sve/acle/asm/rsqrts_f32.c | 30 + .../aarch64/sve/acle/asm/rsqrts_f64.c | 30 + .../aarch64/sve/acle/asm/scale_f16.c | 330 +++++ .../aarch64/sve/acle/asm/scale_f32.c | 330 +++++ .../aarch64/sve/acle/asm/scale_f64.c | 330 +++++ .../gcc.target/aarch64/sve/acle/asm/sel_b.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_f16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_f32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_f64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_s16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_s32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_s64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_s8.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_u16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_u32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_u64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/sel_u8.c | 30 + .../aarch64/sve/acle/asm/set2_f16.c | 41 + .../aarch64/sve/acle/asm/set2_f32.c | 41 + .../aarch64/sve/acle/asm/set2_f64.c | 41 + .../aarch64/sve/acle/asm/set2_s16.c | 41 + .../aarch64/sve/acle/asm/set2_s32.c | 41 + .../aarch64/sve/acle/asm/set2_s64.c | 41 + .../gcc.target/aarch64/sve/acle/asm/set2_s8.c | 41 + .../aarch64/sve/acle/asm/set2_u16.c | 41 + .../aarch64/sve/acle/asm/set2_u32.c | 41 + .../aarch64/sve/acle/asm/set2_u64.c | 41 + .../gcc.target/aarch64/sve/acle/asm/set2_u8.c | 41 + .../aarch64/sve/acle/asm/set3_f16.c | 63 + .../aarch64/sve/acle/asm/set3_f32.c | 63 + .../aarch64/sve/acle/asm/set3_f64.c | 63 + .../aarch64/sve/acle/asm/set3_s16.c | 63 + .../aarch64/sve/acle/asm/set3_s32.c | 63 + .../aarch64/sve/acle/asm/set3_s64.c | 63 + .../gcc.target/aarch64/sve/acle/asm/set3_s8.c | 63 + .../aarch64/sve/acle/asm/set3_u16.c | 63 + .../aarch64/sve/acle/asm/set3_u32.c | 63 + .../aarch64/sve/acle/asm/set3_u64.c | 63 + .../gcc.target/aarch64/sve/acle/asm/set3_u8.c | 63 + .../aarch64/sve/acle/asm/set4_f16.c | 87 ++ .../aarch64/sve/acle/asm/set4_f32.c | 87 ++ .../aarch64/sve/acle/asm/set4_f64.c | 87 ++ .../aarch64/sve/acle/asm/set4_s16.c | 87 ++ .../aarch64/sve/acle/asm/set4_s32.c | 87 ++ .../aarch64/sve/acle/asm/set4_s64.c | 87 ++ .../gcc.target/aarch64/sve/acle/asm/set4_s8.c | 87 ++ .../aarch64/sve/acle/asm/set4_u16.c | 87 ++ .../aarch64/sve/acle/asm/set4_u32.c | 87 ++ .../aarch64/sve/acle/asm/set4_u64.c | 87 ++ .../gcc.target/aarch64/sve/acle/asm/set4_u8.c | 87 ++ .../aarch64/sve/acle/asm/splice_f16.c | 33 + .../aarch64/sve/acle/asm/splice_f32.c | 33 + .../aarch64/sve/acle/asm/splice_f64.c | 33 + .../aarch64/sve/acle/asm/splice_s16.c | 33 + .../aarch64/sve/acle/asm/splice_s32.c | 33 + .../aarch64/sve/acle/asm/splice_s64.c | 33 + .../aarch64/sve/acle/asm/splice_s8.c | 33 + .../aarch64/sve/acle/asm/splice_u16.c | 33 + .../aarch64/sve/acle/asm/splice_u32.c | 33 + .../aarch64/sve/acle/asm/splice_u64.c | 33 + .../aarch64/sve/acle/asm/splice_u8.c | 33 + .../aarch64/sve/acle/asm/sqrt_f16.c | 103 ++ .../aarch64/sve/acle/asm/sqrt_f32.c | 103 ++ .../aarch64/sve/acle/asm/sqrt_f64.c | 103 ++ .../gcc.target/aarch64/sve/acle/asm/st1_f16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_f32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_f64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_s16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_s32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_s64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_s8.c | 162 +++ .../aarch64/sve/acle/asm/st1_scatter_f32.c | 227 ++++ .../aarch64/sve/acle/asm/st1_scatter_f64.c | 303 +++++ .../aarch64/sve/acle/asm/st1_scatter_s32.c | 227 ++++ .../aarch64/sve/acle/asm/st1_scatter_s64.c | 303 +++++ .../aarch64/sve/acle/asm/st1_scatter_u32.c | 227 ++++ .../aarch64/sve/acle/asm/st1_scatter_u64.c | 303 +++++ .../gcc.target/aarch64/sve/acle/asm/st1_u16.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_u32.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_u64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st1_u8.c | 162 +++ .../aarch64/sve/acle/asm/st1b_s16.c | 162 +++ .../aarch64/sve/acle/asm/st1b_s32.c | 162 +++ .../aarch64/sve/acle/asm/st1b_s64.c | 162 +++ .../aarch64/sve/acle/asm/st1b_scatter_s32.c | 104 ++ .../aarch64/sve/acle/asm/st1b_scatter_s64.c | 122 ++ .../aarch64/sve/acle/asm/st1b_scatter_u32.c | 104 ++ .../aarch64/sve/acle/asm/st1b_scatter_u64.c | 122 ++ .../aarch64/sve/acle/asm/st1b_u16.c | 162 +++ .../aarch64/sve/acle/asm/st1b_u32.c | 162 +++ .../aarch64/sve/acle/asm/st1b_u64.c | 162 +++ .../aarch64/sve/acle/asm/st1h_s32.c | 158 +++ .../aarch64/sve/acle/asm/st1h_s64.c | 158 +++ .../aarch64/sve/acle/asm/st1h_scatter_s32.c | 207 +++ .../aarch64/sve/acle/asm/st1h_scatter_s64.c | 243 ++++ .../aarch64/sve/acle/asm/st1h_scatter_u32.c | 207 +++ .../aarch64/sve/acle/asm/st1h_scatter_u64.c | 243 ++++ .../aarch64/sve/acle/asm/st1h_u32.c | 158 +++ .../aarch64/sve/acle/asm/st1h_u64.c | 158 +++ .../aarch64/sve/acle/asm/st1w_s64.c | 158 +++ .../aarch64/sve/acle/asm/st1w_scatter_s64.c | 263 ++++ .../aarch64/sve/acle/asm/st1w_scatter_u64.c | 263 ++++ .../aarch64/sve/acle/asm/st1w_u64.c | 158 +++ .../gcc.target/aarch64/sve/acle/asm/st2_f16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_f32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_f64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_s16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_s32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_s64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_s8.c | 204 +++ .../gcc.target/aarch64/sve/acle/asm/st2_u16.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_u32.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_u64.c | 200 +++ .../gcc.target/aarch64/sve/acle/asm/st2_u8.c | 204 +++ .../gcc.target/aarch64/sve/acle/asm/st3_f16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_f32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_f64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_s16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_s32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_s64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_s8.c | 246 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_u16.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_u32.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_u64.c | 242 ++++ .../gcc.target/aarch64/sve/acle/asm/st3_u8.c | 246 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_f16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_f32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_f64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_s16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_s32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_s64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_s8.c | 290 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_u16.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_u32.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_u64.c | 286 ++++ .../gcc.target/aarch64/sve/acle/asm/st4_u8.c | 290 ++++ .../aarch64/sve/acle/asm/stnt1_f16.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_f32.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_f64.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_s16.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_s32.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_s64.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_s8.c | 162 +++ .../aarch64/sve/acle/asm/stnt1_u16.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_u32.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_u64.c | 158 +++ .../aarch64/sve/acle/asm/stnt1_u8.c | 162 +++ .../gcc.target/aarch64/sve/acle/asm/sub_f16.c | 577 ++++++++ .../aarch64/sve/acle/asm/sub_f16_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/sub_f32.c | 577 ++++++++ .../aarch64/sve/acle/asm/sub_f32_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/sub_f64.c | 577 ++++++++ .../aarch64/sve/acle/asm/sub_f64_notrap.c | 572 ++++++++ .../gcc.target/aarch64/sve/acle/asm/sub_s16.c | 377 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_s32.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_s64.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_s8.c | 294 ++++ .../gcc.target/aarch64/sve/acle/asm/sub_u16.c | 377 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_u32.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_u64.c | 426 ++++++ .../gcc.target/aarch64/sve/acle/asm/sub_u8.c | 294 ++++ .../aarch64/sve/acle/asm/subr_f16.c | 444 ++++++ .../aarch64/sve/acle/asm/subr_f16_notrap.c | 439 ++++++ .../aarch64/sve/acle/asm/subr_f32.c | 444 ++++++ .../aarch64/sve/acle/asm/subr_f32_notrap.c | 439 ++++++ .../aarch64/sve/acle/asm/subr_f64.c | 444 ++++++ .../aarch64/sve/acle/asm/subr_f64_notrap.c | 439 ++++++ .../aarch64/sve/acle/asm/subr_s16.c | 324 +++++ .../aarch64/sve/acle/asm/subr_s32.c | 344 +++++ .../aarch64/sve/acle/asm/subr_s64.c | 344 +++++ .../gcc.target/aarch64/sve/acle/asm/subr_s8.c | 294 ++++ .../aarch64/sve/acle/asm/subr_u16.c | 324 +++++ .../aarch64/sve/acle/asm/subr_u32.c | 344 +++++ .../aarch64/sve/acle/asm/subr_u64.c | 344 +++++ .../gcc.target/aarch64/sve/acle/asm/subr_u8.c | 294 ++++ .../gcc.target/aarch64/sve/acle/asm/tbl_f16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_f32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_f64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_s16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_s32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_s64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_s8.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_u16.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_u32.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_u64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/tbl_u8.c | 30 + .../aarch64/sve/acle/asm/test_sve_acle.h | 330 +++++ .../aarch64/sve/acle/asm/tmad_f16.c | 96 ++ .../aarch64/sve/acle/asm/tmad_f32.c | 96 ++ .../aarch64/sve/acle/asm/tmad_f64.c | 96 ++ .../aarch64/sve/acle/asm/trn1_b16.c | 30 + .../aarch64/sve/acle/asm/trn1_b32.c | 30 + .../aarch64/sve/acle/asm/trn1_b64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn1_b8.c | 30 + .../aarch64/sve/acle/asm/trn1_f16.c | 30 + .../aarch64/sve/acle/asm/trn1_f32.c | 30 + .../aarch64/sve/acle/asm/trn1_f64.c | 30 + .../aarch64/sve/acle/asm/trn1_s16.c | 30 + .../aarch64/sve/acle/asm/trn1_s32.c | 30 + .../aarch64/sve/acle/asm/trn1_s64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn1_s8.c | 30 + .../aarch64/sve/acle/asm/trn1_u16.c | 30 + .../aarch64/sve/acle/asm/trn1_u32.c | 30 + .../aarch64/sve/acle/asm/trn1_u64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn1_u8.c | 30 + .../aarch64/sve/acle/asm/trn2_b16.c | 30 + .../aarch64/sve/acle/asm/trn2_b32.c | 30 + .../aarch64/sve/acle/asm/trn2_b64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn2_b8.c | 30 + .../aarch64/sve/acle/asm/trn2_f16.c | 30 + .../aarch64/sve/acle/asm/trn2_f32.c | 30 + .../aarch64/sve/acle/asm/trn2_f64.c | 30 + .../aarch64/sve/acle/asm/trn2_s16.c | 30 + .../aarch64/sve/acle/asm/trn2_s32.c | 30 + .../aarch64/sve/acle/asm/trn2_s64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn2_s8.c | 30 + .../aarch64/sve/acle/asm/trn2_u16.c | 30 + .../aarch64/sve/acle/asm/trn2_u32.c | 30 + .../aarch64/sve/acle/asm/trn2_u64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/trn2_u8.c | 30 + .../aarch64/sve/acle/asm/tsmul_f16.c | 30 + .../aarch64/sve/acle/asm/tsmul_f32.c | 30 + .../aarch64/sve/acle/asm/tsmul_f64.c | 30 + .../aarch64/sve/acle/asm/tssel_f16.c | 30 + .../aarch64/sve/acle/asm/tssel_f32.c | 30 + .../aarch64/sve/acle/asm/tssel_f64.c | 30 + .../aarch64/sve/acle/asm/undef2_1.c | 80 ++ .../aarch64/sve/acle/asm/undef3_1.c | 80 ++ .../aarch64/sve/acle/asm/undef4_1.c | 80 ++ .../gcc.target/aarch64/sve/acle/asm/undef_1.c | 80 ++ .../aarch64/sve/acle/asm/unpkhi_b.c | 21 + .../aarch64/sve/acle/asm/unpkhi_s16.c | 21 + .../aarch64/sve/acle/asm/unpkhi_s32.c | 21 + .../aarch64/sve/acle/asm/unpkhi_s64.c | 21 + .../aarch64/sve/acle/asm/unpkhi_u16.c | 21 + .../aarch64/sve/acle/asm/unpkhi_u32.c | 21 + .../aarch64/sve/acle/asm/unpkhi_u64.c | 21 + .../aarch64/sve/acle/asm/unpklo_b.c | 21 + .../aarch64/sve/acle/asm/unpklo_s16.c | 21 + .../aarch64/sve/acle/asm/unpklo_s32.c | 21 + .../aarch64/sve/acle/asm/unpklo_s64.c | 21 + .../aarch64/sve/acle/asm/unpklo_u16.c | 21 + .../aarch64/sve/acle/asm/unpklo_u32.c | 21 + .../aarch64/sve/acle/asm/unpklo_u64.c | 21 + .../aarch64/sve/acle/asm/uzp1_b16.c | 30 + .../aarch64/sve/acle/asm/uzp1_b32.c | 30 + .../aarch64/sve/acle/asm/uzp1_b64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/uzp1_b8.c | 30 + .../aarch64/sve/acle/asm/uzp1_f16.c | 30 + .../aarch64/sve/acle/asm/uzp1_f32.c | 30 + .../aarch64/sve/acle/asm/uzp1_f64.c | 30 + .../aarch64/sve/acle/asm/uzp1_s16.c | 30 + .../aarch64/sve/acle/asm/uzp1_s32.c | 30 + .../aarch64/sve/acle/asm/uzp1_s64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/uzp1_s8.c | 30 + .../aarch64/sve/acle/asm/uzp1_u16.c | 30 + .../aarch64/sve/acle/asm/uzp1_u32.c | 30 + .../aarch64/sve/acle/asm/uzp1_u64.c | 30 + .../gcc.target/aarch64/sve/acle/asm/uzp1_u8.c | 30 + .../aarch64/sve/acle/asm/uzp2_b16.c | 30 + .../aarch64/sve/acle/asm/uzp2_b32.c | 30 + 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gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef2_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef3_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef4_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_b.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_b.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u32.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u64.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u8.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e2656d54e37..c1df721a4a7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2019-10-29 Richard Sandiford + Kugan Vivekanandarajah + Prathamesh Kulkarni + + * g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp: New file. + * gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp: New file. + * gcc.target/aarch64/sve/acle/asm: New test directory. + 2019-10-29 Richard Sandiford * gcc.target/aarch64/sve/pcs/aarch64-sve-pcs.exp: New file. diff --git a/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp new file mode 100644 index 00000000000..e9d624ff80f --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp @@ -0,0 +1,83 @@ +# Assembly-based regression-test driver for the SVE ACLE +# Copyright (C) 2009-2019 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . */ + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if { ![istarget aarch64*-*-*] } { + return +} + +# Load support procs. +load_lib g++-dg.exp + +# Initialize `dg'. +dg-init + +# Force SVE if we're not testing it already. +if { [check_effective_target_aarch64_sve] } { + set sve_flags "" +} else { + set sve_flags "-march=armv8.2-a+sve" +} + +global gcc_runtest_parallelize_limit_minor +if { [info exists gcc_runtest_parallelize_limit_minor] } { + set old_limit_minor $gcc_runtest_parallelize_limit_minor + set gcc_runtest_parallelize_limit_minor 1 +} + +torture-init +set-torture-options { + "-std=c++98 -O0 -g" + "-std=c++98 -O1 -g" + "-std=c++11 -O2 -g" + "-std=c++14 -O3 -g" + "-std=c++17 -Og -g" + "-std=c++2a -Os -g" + "-std=gnu++98 -O2 -fno-schedule-insns -DCHECK_ASM --save-temps" + "-std=gnu++11 -Ofast -g" + "-std=gnu++17 -O3 -g" + "-std=gnu++2a -O0 -g" +} { + "-DTEST_FULL" + "-DTEST_OVERLOADS" +} + +# Main loop. +set gcc_subdir [string replace $subdir 0 2 gcc] +set files [glob -nocomplain $srcdir/$gcc_subdir/asm/*.c] +set save-dg-do-what-default ${dg-do-what-default} +if { [check_effective_target_aarch64_asm_sve_ok] + && [check_effective_target_aarch64_variant_pcs] } { + set dg-do-what-default assemble +} else { + set dg-do-what-default compile +} +gcc-dg-runtest [lsort $files] "" "$sve_flags -fno-ipa-icf" +set dg-do-what-default ${save-dg-do-what-default} + +torture-finish + +if { [info exists gcc_runtest_parallelize_limit_minor] } { + set gcc_runtest_parallelize_limit_minor $old_limit_minor +} + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp new file mode 100644 index 00000000000..7ce85a41407 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp @@ -0,0 +1,79 @@ +# Assembly-based regression-test driver for the SVE ACLE +# Copyright (C) 2009-2019 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . */ + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Force SVE if we're not testing it already. +if { [check_effective_target_aarch64_sve] } { + set sve_flags "" +} else { + set sve_flags "-march=armv8.2-a+sve" +} + +global gcc_runtest_parallelize_limit_minor +if { [info exists gcc_runtest_parallelize_limit_minor] } { + set old_limit_minor $gcc_runtest_parallelize_limit_minor + set gcc_runtest_parallelize_limit_minor 1 +} + +torture-init +set-torture-options { + "-std=c90 -O0 -g" + "-std=c90 -O1 -g" + "-std=c99 -O2 -g" + "-std=c11 -O3 -g" + "-std=gnu90 -O2 -fno-schedule-insns -DCHECK_ASM --save-temps" + "-std=gnu99 -Ofast -g" + "-std=gnu11 -Os -g" +} { + "-DTEST_FULL" + "-DTEST_OVERLOADS" +} + +# Main loop. +set files [glob -nocomplain $srcdir/$subdir/asm/*.c] +set save-dg-do-what-default ${dg-do-what-default} +if { [check_effective_target_aarch64_asm_sve_ok] + && [check_effective_target_aarch64_variant_pcs] } { + set dg-do-what-default assemble +} else { + set dg-do-what-default compile +} +gcc-dg-runtest [lsort $files] "" "$sve_flags -fno-ipa-icf" +set dg-do-what-default ${save-dg-do-what-default} + +torture-finish + +if { [info exists gcc_runtest_parallelize_limit_minor] } { + set gcc_runtest_parallelize_limit_minor $old_limit_minor +} + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f16.c new file mode 100644 index 00000000000..c019f248d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f16.c @@ -0,0 +1,552 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_f16_m_tied1: +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_m_tied1, svfloat16_t, + z0 = svabd_f16_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fabd z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_m_tied2, svfloat16_t, + z0 = svabd_f16_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_f16_m_untied: +** movprfx z0, z1 +** fabd z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_m_untied, svfloat16_t, + z0 = svabd_f16_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svabd_n_f16_m (p0, z0, d4), + z0 = svabd_m (p0, z0, d4)) + +/* +** abd_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svabd_n_f16_m (p0, z1, d4), + z0 = svabd_m (p0, z1, d4)) + +/* +** abd_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_m_tied1, svfloat16_t, + z0 = svabd_n_f16_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_m_untied, svfloat16_t, + z0 = svabd_n_f16_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_z_tied1, svfloat16_t, + z0 = svabd_f16_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_z_tied2, svfloat16_t, + z0 = svabd_f16_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f16_z_untied, svfloat16_t, + z0 = svabd_f16_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svabd_n_f16_z (p0, z0, d4), + z0 = svabd_z (p0, z0, d4)) + +/* +** abd_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svabd_n_f16_z (p0, z1, d4), + z0 = svabd_z (p0, z1, d4)) + +/* +** abd_1_f16_z_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_z_tied1, svfloat16_t, + z0 = svabd_n_f16_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_f16_z_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_z_untied, svfloat16_t, + z0 = svabd_n_f16_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_0p5_f16_z_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f16_z_tied1, svfloat16_t, + z0 = svabd_n_f16_z (p0, z0, 0.5), + z0 = svabd_z (p0, z0, 0.5)) + +/* +** abd_0p5_f16_z_untied: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f16_z_untied, svfloat16_t, + z0 = svabd_n_f16_z (p0, z1, 0.5), + z0 = svabd_z (p0, z1, 0.5)) + +/* +** abd_m1_f16_z_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f16_z_tied1, svfloat16_t, + z0 = svabd_n_f16_z (p0, z0, -1), + z0 = svabd_z (p0, z0, -1)) + +/* +** abd_m1_f16_z_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f16_z_untied, svfloat16_t, + z0 = svabd_n_f16_z (p0, z1, -1), + z0 = svabd_z (p0, z1, -1)) + +/* +** abd_m0p5_f16_z_tied1: +** fmov (z[0-9]+\.h), #-(?:0\.5|5\.0e-1) +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f16_z_tied1, svfloat16_t, + z0 = svabd_n_f16_z (p0, z0, -0.5), + z0 = svabd_z (p0, z0, -0.5)) + +/* +** abd_m0p5_f16_z_untied: +** fmov (z[0-9]+\.h), #-(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.h, p0/z, z1\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f16_z_untied, svfloat16_t, + z0 = svabd_n_f16_z (p0, z1, -0.5), + z0 = svabd_z (p0, z1, -0.5)) + +/* +** abd_m2_f16_z: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m2_f16_z, svfloat16_t, + z0 = svabd_n_f16_z (p0, z0, -2), + z0 = svabd_z (p0, z0, -2)) + +/* +** abd_f16_x_tied1: +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_x_tied1, svfloat16_t, + z0 = svabd_f16_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_f16_x_tied2: +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_f16_x_tied2, svfloat16_t, + z0 = svabd_f16_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_f16_x_untied: +** ( +** movprfx z0, z1 +** fabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f16_x_untied, svfloat16_t, + z0 = svabd_f16_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svabd_n_f16_x (p0, z0, d4), + z0 = svabd_x (p0, z0, d4)) + +/* +** abd_h4_f16_x_untied: +** mov z0\.h, h4 +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (abd_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svabd_n_f16_x (p0, z1, d4), + z0 = svabd_x (p0, z1, d4)) + +/* +** abd_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_f16_x_untied: +** fmov z0\.h, #1\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_1_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) + +/* +** abd_0p5_f16_x_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (p0, z0, 0.5), + z0 = svabd_x (p0, z0, 0.5)) + +/* +** abd_0p5_f16_x_untied: +** fmov z0\.h, #(?:0\.5|5\.0e-1) +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (p0, z1, 0.5), + z0 = svabd_x (p0, z1, 0.5)) + +/* +** abd_m1_f16_x_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (p0, z0, -1), + z0 = svabd_x (p0, z0, -1)) + +/* +** abd_m1_f16_x_untied: +** fmov z0\.h, #-1\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (p0, z1, -1), + z0 = svabd_x (p0, z1, -1)) + +/* +** abd_m0p5_f16_x_tied1: +** fmov (z[0-9]+\.h), #-(?:0\.5|5\.0e-1) +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (p0, z0, -0.5), + z0 = svabd_x (p0, z0, -0.5)) + +/* +** abd_m0p5_f16_x_untied: +** fmov z0\.h, #-(?:0\.5|5\.0e-1) +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (p0, z1, -0.5), + z0 = svabd_x (p0, z1, -0.5)) + +/* +** abd_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_2_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (p0, z0, 2), + z0 = svabd_x (p0, z0, 2)) + +/* +** abd_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_2_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (p0, z1, 2), + z0 = svabd_x (p0, z1, 2)) + +/* +** ptrue_abd_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f16_x_tied1, svfloat16_t, + z0 = svabd_f16_x (svptrue_b16 (), z0, z1), + z0 = svabd_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_abd_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f16_x_tied2, svfloat16_t, + z0 = svabd_f16_x (svptrue_b16 (), z1, z0), + z0 = svabd_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_abd_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f16_x_untied, svfloat16_t, + z0 = svabd_f16_x (svptrue_b16 (), z1, z2), + z0 = svabd_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_abd_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svabd_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_abd_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svabd_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_abd_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svabd_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_abd_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svabd_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_abd_m1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svabd_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_abd_m1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svabd_x (svptrue_b16 (), z1, -1)) + +/* +** ptrue_abd_m0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z0, -0.5), + z0 = svabd_x (svptrue_b16 (), z0, -0.5)) + +/* +** ptrue_abd_m0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z1, -0.5), + z0 = svabd_x (svptrue_b16 (), z1, -0.5)) + +/* +** ptrue_abd_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f16_x_tied1, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svabd_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_abd_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f16_x_untied, svfloat16_t, + z0 = svabd_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svabd_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f32.c new file mode 100644 index 00000000000..bff37580c43 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f32.c @@ -0,0 +1,552 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_f32_m_tied1: +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_m_tied1, svfloat32_t, + z0 = svabd_f32_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fabd z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_m_tied2, svfloat32_t, + z0 = svabd_f32_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_f32_m_untied: +** movprfx z0, z1 +** fabd z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_m_untied, svfloat32_t, + z0 = svabd_f32_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_m_tied1, svfloat32_t, float, + z0 = svabd_n_f32_m (p0, z0, d4), + z0 = svabd_m (p0, z0, d4)) + +/* +** abd_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_m_untied, svfloat32_t, float, + z0 = svabd_n_f32_m (p0, z1, d4), + z0 = svabd_m (p0, z1, d4)) + +/* +** abd_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_m_tied1, svfloat32_t, + z0 = svabd_n_f32_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_m_untied, svfloat32_t, + z0 = svabd_n_f32_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_z_tied1, svfloat32_t, + z0 = svabd_f32_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_z_tied2, svfloat32_t, + z0 = svabd_f32_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f32_z_untied, svfloat32_t, + z0 = svabd_f32_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_z_tied1, svfloat32_t, float, + z0 = svabd_n_f32_z (p0, z0, d4), + z0 = svabd_z (p0, z0, d4)) + +/* +** abd_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_z_untied, svfloat32_t, float, + z0 = svabd_n_f32_z (p0, z1, d4), + z0 = svabd_z (p0, z1, d4)) + +/* +** abd_1_f32_z_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_z_tied1, svfloat32_t, + z0 = svabd_n_f32_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_f32_z_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_z_untied, svfloat32_t, + z0 = svabd_n_f32_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_0p5_f32_z_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f32_z_tied1, svfloat32_t, + z0 = svabd_n_f32_z (p0, z0, 0.5), + z0 = svabd_z (p0, z0, 0.5)) + +/* +** abd_0p5_f32_z_untied: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f32_z_untied, svfloat32_t, + z0 = svabd_n_f32_z (p0, z1, 0.5), + z0 = svabd_z (p0, z1, 0.5)) + +/* +** abd_m1_f32_z_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f32_z_tied1, svfloat32_t, + z0 = svabd_n_f32_z (p0, z0, -1), + z0 = svabd_z (p0, z0, -1)) + +/* +** abd_m1_f32_z_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f32_z_untied, svfloat32_t, + z0 = svabd_n_f32_z (p0, z1, -1), + z0 = svabd_z (p0, z1, -1)) + +/* +** abd_m0p5_f32_z_tied1: +** fmov (z[0-9]+\.s), #-(?:0\.5|5\.0e-1) +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f32_z_tied1, svfloat32_t, + z0 = svabd_n_f32_z (p0, z0, -0.5), + z0 = svabd_z (p0, z0, -0.5)) + +/* +** abd_m0p5_f32_z_untied: +** fmov (z[0-9]+\.s), #-(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.s, p0/z, z1\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f32_z_untied, svfloat32_t, + z0 = svabd_n_f32_z (p0, z1, -0.5), + z0 = svabd_z (p0, z1, -0.5)) + +/* +** abd_m2_f32_z: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m2_f32_z, svfloat32_t, + z0 = svabd_n_f32_z (p0, z0, -2), + z0 = svabd_z (p0, z0, -2)) + +/* +** abd_f32_x_tied1: +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_x_tied1, svfloat32_t, + z0 = svabd_f32_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_f32_x_tied2: +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_f32_x_tied2, svfloat32_t, + z0 = svabd_f32_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_f32_x_untied: +** ( +** movprfx z0, z1 +** fabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f32_x_untied, svfloat32_t, + z0 = svabd_f32_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_x_tied1, svfloat32_t, float, + z0 = svabd_n_f32_x (p0, z0, d4), + z0 = svabd_x (p0, z0, d4)) + +/* +** abd_s4_f32_x_untied: +** mov z0\.s, s4 +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (abd_s4_f32_x_untied, svfloat32_t, float, + z0 = svabd_n_f32_x (p0, z1, d4), + z0 = svabd_x (p0, z1, d4)) + +/* +** abd_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_f32_x_untied: +** fmov z0\.s, #1\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_1_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) + +/* +** abd_0p5_f32_x_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (p0, z0, 0.5), + z0 = svabd_x (p0, z0, 0.5)) + +/* +** abd_0p5_f32_x_untied: +** fmov z0\.s, #(?:0\.5|5\.0e-1) +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (p0, z1, 0.5), + z0 = svabd_x (p0, z1, 0.5)) + +/* +** abd_m1_f32_x_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (p0, z0, -1), + z0 = svabd_x (p0, z0, -1)) + +/* +** abd_m1_f32_x_untied: +** fmov z0\.s, #-1\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (p0, z1, -1), + z0 = svabd_x (p0, z1, -1)) + +/* +** abd_m0p5_f32_x_tied1: +** fmov (z[0-9]+\.s), #-(?:0\.5|5\.0e-1) +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (p0, z0, -0.5), + z0 = svabd_x (p0, z0, -0.5)) + +/* +** abd_m0p5_f32_x_untied: +** fmov z0\.s, #-(?:0\.5|5\.0e-1) +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (p0, z1, -0.5), + z0 = svabd_x (p0, z1, -0.5)) + +/* +** abd_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_2_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (p0, z0, 2), + z0 = svabd_x (p0, z0, 2)) + +/* +** abd_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_2_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (p0, z1, 2), + z0 = svabd_x (p0, z1, 2)) + +/* +** ptrue_abd_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f32_x_tied1, svfloat32_t, + z0 = svabd_f32_x (svptrue_b32 (), z0, z1), + z0 = svabd_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_abd_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f32_x_tied2, svfloat32_t, + z0 = svabd_f32_x (svptrue_b32 (), z1, z0), + z0 = svabd_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_abd_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f32_x_untied, svfloat32_t, + z0 = svabd_f32_x (svptrue_b32 (), z1, z2), + z0 = svabd_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_abd_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svabd_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_abd_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svabd_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_abd_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svabd_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_abd_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svabd_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_abd_m1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svabd_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_abd_m1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svabd_x (svptrue_b32 (), z1, -1)) + +/* +** ptrue_abd_m0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z0, -0.5), + z0 = svabd_x (svptrue_b32 (), z0, -0.5)) + +/* +** ptrue_abd_m0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z1, -0.5), + z0 = svabd_x (svptrue_b32 (), z1, -0.5)) + +/* +** ptrue_abd_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f32_x_tied1, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svabd_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_abd_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f32_x_untied, svfloat32_t, + z0 = svabd_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svabd_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f64.c new file mode 100644 index 00000000000..c1e5f14e619 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_f64.c @@ -0,0 +1,552 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_f64_m_tied1: +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_m_tied1, svfloat64_t, + z0 = svabd_f64_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_f64_m_tied2, svfloat64_t, + z0 = svabd_f64_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_f64_m_untied: +** movprfx z0, z1 +** fabd z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_m_untied, svfloat64_t, + z0 = svabd_f64_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_m_tied1, svfloat64_t, double, + z0 = svabd_n_f64_m (p0, z0, d4), + z0 = svabd_m (p0, z0, d4)) + +/* +** abd_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_m_untied, svfloat64_t, double, + z0 = svabd_n_f64_m (p0, z1, d4), + z0 = svabd_m (p0, z1, d4)) + +/* +** abd_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_m_tied1, svfloat64_t, + z0 = svabd_n_f64_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_m_untied, svfloat64_t, + z0 = svabd_n_f64_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_z_tied1, svfloat64_t, + z0 = svabd_f64_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_z_tied2, svfloat64_t, + z0 = svabd_f64_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f64_z_untied, svfloat64_t, + z0 = svabd_f64_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_z_tied1, svfloat64_t, double, + z0 = svabd_n_f64_z (p0, z0, d4), + z0 = svabd_z (p0, z0, d4)) + +/* +** abd_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_z_untied, svfloat64_t, double, + z0 = svabd_n_f64_z (p0, z1, d4), + z0 = svabd_z (p0, z1, d4)) + +/* +** abd_1_f64_z_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_z_tied1, svfloat64_t, + z0 = svabd_n_f64_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_f64_z_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_z_untied, svfloat64_t, + z0 = svabd_n_f64_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_0p5_f64_z_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f64_z_tied1, svfloat64_t, + z0 = svabd_n_f64_z (p0, z0, 0.5), + z0 = svabd_z (p0, z0, 0.5)) + +/* +** abd_0p5_f64_z_untied: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f64_z_untied, svfloat64_t, + z0 = svabd_n_f64_z (p0, z1, 0.5), + z0 = svabd_z (p0, z1, 0.5)) + +/* +** abd_m1_f64_z_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f64_z_tied1, svfloat64_t, + z0 = svabd_n_f64_z (p0, z0, -1), + z0 = svabd_z (p0, z0, -1)) + +/* +** abd_m1_f64_z_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f64_z_untied, svfloat64_t, + z0 = svabd_n_f64_z (p0, z1, -1), + z0 = svabd_z (p0, z1, -1)) + +/* +** abd_m0p5_f64_z_tied1: +** fmov (z[0-9]+\.d), #-(?:0\.5|5\.0e-1) +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f64_z_tied1, svfloat64_t, + z0 = svabd_n_f64_z (p0, z0, -0.5), + z0 = svabd_z (p0, z0, -0.5)) + +/* +** abd_m0p5_f64_z_untied: +** fmov (z[0-9]+\.d), #-(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.d, p0/z, z1\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f64_z_untied, svfloat64_t, + z0 = svabd_n_f64_z (p0, z1, -0.5), + z0 = svabd_z (p0, z1, -0.5)) + +/* +** abd_m2_f64_z: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m2_f64_z, svfloat64_t, + z0 = svabd_n_f64_z (p0, z0, -2), + z0 = svabd_z (p0, z0, -2)) + +/* +** abd_f64_x_tied1: +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_x_tied1, svfloat64_t, + z0 = svabd_f64_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_f64_x_tied2: +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_f64_x_tied2, svfloat64_t, + z0 = svabd_f64_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_f64_x_untied: +** ( +** movprfx z0, z1 +** fabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_f64_x_untied, svfloat64_t, + z0 = svabd_f64_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_x_tied1, svfloat64_t, double, + z0 = svabd_n_f64_x (p0, z0, d4), + z0 = svabd_x (p0, z0, d4)) + +/* +** abd_d4_f64_x_untied: +** mov z0\.d, d4 +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (abd_d4_f64_x_untied, svfloat64_t, double, + z0 = svabd_n_f64_x (p0, z1, d4), + z0 = svabd_x (p0, z1, d4)) + +/* +** abd_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_f64_x_untied: +** fmov z0\.d, #1\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_1_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) + +/* +** abd_0p5_f64_x_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (p0, z0, 0.5), + z0 = svabd_x (p0, z0, 0.5)) + +/* +** abd_0p5_f64_x_untied: +** fmov z0\.d, #(?:0\.5|5\.0e-1) +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_0p5_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (p0, z1, 0.5), + z0 = svabd_x (p0, z1, 0.5)) + +/* +** abd_m1_f64_x_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (p0, z0, -1), + z0 = svabd_x (p0, z0, -1)) + +/* +** abd_m1_f64_x_untied: +** fmov z0\.d, #-1\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_m1_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (p0, z1, -1), + z0 = svabd_x (p0, z1, -1)) + +/* +** abd_m0p5_f64_x_tied1: +** fmov (z[0-9]+\.d), #-(?:0\.5|5\.0e-1) +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (p0, z0, -0.5), + z0 = svabd_x (p0, z0, -0.5)) + +/* +** abd_m0p5_f64_x_untied: +** fmov z0\.d, #-(?:0\.5|5\.0e-1) +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_m0p5_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (p0, z1, -0.5), + z0 = svabd_x (p0, z1, -0.5)) + +/* +** abd_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_2_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (p0, z0, 2), + z0 = svabd_x (p0, z0, 2)) + +/* +** abd_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_2_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (p0, z1, 2), + z0 = svabd_x (p0, z1, 2)) + +/* +** ptrue_abd_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f64_x_tied1, svfloat64_t, + z0 = svabd_f64_x (svptrue_b64 (), z0, z1), + z0 = svabd_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_abd_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f64_x_tied2, svfloat64_t, + z0 = svabd_f64_x (svptrue_b64 (), z1, z0), + z0 = svabd_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_abd_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_f64_x_untied, svfloat64_t, + z0 = svabd_f64_x (svptrue_b64 (), z1, z2), + z0 = svabd_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_abd_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svabd_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_abd_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_1_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svabd_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_abd_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svabd_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_abd_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_0p5_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svabd_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_abd_m1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svabd_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_abd_m1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m1_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svabd_x (svptrue_b64 (), z1, -1)) + +/* +** ptrue_abd_m0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z0, -0.5), + z0 = svabd_x (svptrue_b64 (), z0, -0.5)) + +/* +** ptrue_abd_m0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_m0p5_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z1, -0.5), + z0 = svabd_x (svptrue_b64 (), z1, -0.5)) + +/* +** ptrue_abd_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f64_x_tied1, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svabd_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_abd_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abd_2_f64_x_untied, svfloat64_t, + z0 = svabd_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svabd_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c new file mode 100644 index 00000000000..e2d0c0fb7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_s16_m_tied1: +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_m_tied1, svint16_t, + z0 = svabd_s16_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sabd z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_m_tied2, svint16_t, + z0 = svabd_s16_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_s16_m_untied: +** movprfx z0, z1 +** sabd z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_m_untied, svint16_t, + z0 = svabd_s16_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svabd_n_s16_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_m_untied, svint16_t, int16_t, + z0 = svabd_n_s16_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_m_tied1, svint16_t, + z0 = svabd_n_s16_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_m_untied, svint16_t, + z0 = svabd_n_s16_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_z_tied1, svint16_t, + z0 = svabd_s16_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_z_tied2, svint16_t, + z0 = svabd_s16_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** sabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s16_z_untied, svint16_t, + z0 = svabd_s16_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svabd_n_s16_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** sabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_z_untied, svint16_t, int16_t, + z0 = svabd_n_s16_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_z_tied1, svint16_t, + z0 = svabd_n_s16_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** sabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_z_untied, svint16_t, + z0 = svabd_n_s16_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_s16_x_tied1: +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_x_tied1, svint16_t, + z0 = svabd_s16_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_s16_x_tied2: +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_s16_x_tied2, svint16_t, + z0 = svabd_s16_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_s16_x_untied: +** ( +** movprfx z0, z1 +** sabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s16_x_untied, svint16_t, + z0 = svabd_s16_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svabd_n_s16_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_s16_x_untied: +** mov z0\.h, w0 +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s16_x_untied, svint16_t, int16_t, + z0 = svabd_n_s16_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_s16_x_tied1: +** mov (z[0-9]+\.h), #1 +** sabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_x_tied1, svint16_t, + z0 = svabd_n_s16_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_s16_x_untied: +** mov z0\.h, #1 +** sabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_1_s16_x_untied, svint16_t, + z0 = svabd_n_s16_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s32.c new file mode 100644 index 00000000000..5c95ec04df1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_s32_m_tied1: +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_m_tied1, svint32_t, + z0 = svabd_s32_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sabd z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_m_tied2, svint32_t, + z0 = svabd_s32_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_s32_m_untied: +** movprfx z0, z1 +** sabd z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_m_untied, svint32_t, + z0 = svabd_s32_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svabd_n_s32_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_m_untied, svint32_t, int32_t, + z0 = svabd_n_s32_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_m_tied1, svint32_t, + z0 = svabd_n_s32_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_m_untied, svint32_t, + z0 = svabd_n_s32_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_z_tied1, svint32_t, + z0 = svabd_s32_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_z_tied2, svint32_t, + z0 = svabd_s32_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** sabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s32_z_untied, svint32_t, + z0 = svabd_s32_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svabd_n_s32_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_z_untied, svint32_t, int32_t, + z0 = svabd_n_s32_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_z_tied1, svint32_t, + z0 = svabd_n_s32_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_z_untied, svint32_t, + z0 = svabd_n_s32_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_s32_x_tied1: +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_x_tied1, svint32_t, + z0 = svabd_s32_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_s32_x_tied2: +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_s32_x_tied2, svint32_t, + z0 = svabd_s32_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_s32_x_untied: +** ( +** movprfx z0, z1 +** sabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s32_x_untied, svint32_t, + z0 = svabd_s32_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svabd_n_s32_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_s32_x_untied: +** mov z0\.s, w0 +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s32_x_untied, svint32_t, int32_t, + z0 = svabd_n_s32_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_s32_x_tied1: +** mov (z[0-9]+\.s), #1 +** sabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_x_tied1, svint32_t, + z0 = svabd_n_s32_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_s32_x_untied: +** mov z0\.s, #1 +** sabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_1_s32_x_untied, svint32_t, + z0 = svabd_n_s32_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s64.c new file mode 100644 index 00000000000..2402ecf2918 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_s64_m_tied1: +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_m_tied1, svint64_t, + z0 = svabd_s64_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_s64_m_tied2, svint64_t, + z0 = svabd_s64_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_s64_m_untied: +** movprfx z0, z1 +** sabd z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_m_untied, svint64_t, + z0 = svabd_s64_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svabd_n_s64_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_m_untied, svint64_t, int64_t, + z0 = svabd_n_s64_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_m_tied1, svint64_t, + z0 = svabd_n_s64_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_m_untied, svint64_t, + z0 = svabd_n_s64_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_z_tied1, svint64_t, + z0 = svabd_s64_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_z_tied2, svint64_t, + z0 = svabd_s64_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** sabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s64_z_untied, svint64_t, + z0 = svabd_s64_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svabd_n_s64_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_z_untied, svint64_t, int64_t, + z0 = svabd_n_s64_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_z_tied1, svint64_t, + z0 = svabd_n_s64_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_z_untied, svint64_t, + z0 = svabd_n_s64_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_s64_x_tied1: +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_x_tied1, svint64_t, + z0 = svabd_s64_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_s64_x_tied2: +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_s64_x_tied2, svint64_t, + z0 = svabd_s64_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_s64_x_untied: +** ( +** movprfx z0, z1 +** sabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s64_x_untied, svint64_t, + z0 = svabd_s64_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svabd_n_s64_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_x0_s64_x_untied: +** mov z0\.d, x0 +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_s64_x_untied, svint64_t, int64_t, + z0 = svabd_n_s64_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_s64_x_tied1: +** mov (z[0-9]+\.d), #1 +** sabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_x_tied1, svint64_t, + z0 = svabd_n_s64_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_s64_x_untied: +** mov z0\.d, #1 +** sabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_1_s64_x_untied, svint64_t, + z0 = svabd_n_s64_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c new file mode 100644 index 00000000000..49a2cc388f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_s8_m_tied1: +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_m_tied1, svint8_t, + z0 = svabd_s8_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sabd z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_m_tied2, svint8_t, + z0 = svabd_s8_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_s8_m_untied: +** movprfx z0, z1 +** sabd z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_m_untied, svint8_t, + z0 = svabd_s8_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svabd_n_s8_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_m_untied, svint8_t, int8_t, + z0 = svabd_n_s8_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_m_tied1, svint8_t, + z0 = svabd_n_s8_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_m_untied, svint8_t, + z0 = svabd_n_s8_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_z_tied1, svint8_t, + z0 = svabd_s8_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_z_tied2, svint8_t, + z0 = svabd_s8_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** sabd z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s8_z_untied, svint8_t, + z0 = svabd_s8_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svabd_n_s8_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** sabd z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_z_untied, svint8_t, int8_t, + z0 = svabd_n_s8_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_z_tied1, svint8_t, + z0 = svabd_n_s8_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** sabd z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_z_untied, svint8_t, + z0 = svabd_n_s8_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_s8_x_tied1: +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_x_tied1, svint8_t, + z0 = svabd_s8_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_s8_x_tied2: +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_s8_x_tied2, svint8_t, + z0 = svabd_s8_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_s8_x_untied: +** ( +** movprfx z0, z1 +** sabd z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_s8_x_untied, svint8_t, + z0 = svabd_s8_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svabd_n_s8_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_s8_x_untied: +** mov z0\.b, w0 +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_s8_x_untied, svint8_t, int8_t, + z0 = svabd_n_s8_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_s8_x_tied1: +** mov (z[0-9]+\.b), #1 +** sabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_x_tied1, svint8_t, + z0 = svabd_n_s8_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_s8_x_untied: +** mov z0\.b, #1 +** sabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_1_s8_x_untied, svint8_t, + z0 = svabd_n_s8_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c new file mode 100644 index 00000000000..60aa9429ea6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_u16_m_tied1: +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_m_tied1, svuint16_t, + z0 = svabd_u16_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uabd z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_m_tied2, svuint16_t, + z0 = svabd_u16_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_u16_m_untied: +** movprfx z0, z1 +** uabd z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_m_untied, svuint16_t, + z0 = svabd_u16_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svabd_n_u16_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svabd_n_u16_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_m_tied1, svuint16_t, + z0 = svabd_n_u16_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_m_untied, svuint16_t, + z0 = svabd_n_u16_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_z_tied1, svuint16_t, + z0 = svabd_u16_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_z_tied2, svuint16_t, + z0 = svabd_u16_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** uabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u16_z_untied, svuint16_t, + z0 = svabd_u16_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svabd_n_u16_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** uabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svabd_n_u16_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_z_tied1, svuint16_t, + z0 = svabd_n_u16_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** uabd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_z_untied, svuint16_t, + z0 = svabd_n_u16_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_u16_x_tied1: +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_x_tied1, svuint16_t, + z0 = svabd_u16_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_u16_x_tied2: +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_u16_x_tied2, svuint16_t, + z0 = svabd_u16_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_u16_x_untied: +** ( +** movprfx z0, z1 +** uabd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u16_x_untied, svuint16_t, + z0 = svabd_u16_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svabd_n_u16_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_u16_x_untied: +** mov z0\.h, w0 +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svabd_n_u16_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_u16_x_tied1: +** mov (z[0-9]+\.h), #1 +** uabd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_x_tied1, svuint16_t, + z0 = svabd_n_u16_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_u16_x_untied: +** mov z0\.h, #1 +** uabd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abd_1_u16_x_untied, svuint16_t, + z0 = svabd_n_u16_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u32.c new file mode 100644 index 00000000000..bc24107837c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_u32_m_tied1: +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_m_tied1, svuint32_t, + z0 = svabd_u32_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uabd z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_m_tied2, svuint32_t, + z0 = svabd_u32_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_u32_m_untied: +** movprfx z0, z1 +** uabd z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_m_untied, svuint32_t, + z0 = svabd_u32_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svabd_n_u32_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svabd_n_u32_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_m_tied1, svuint32_t, + z0 = svabd_n_u32_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_m_untied, svuint32_t, + z0 = svabd_n_u32_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_z_tied1, svuint32_t, + z0 = svabd_u32_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_z_tied2, svuint32_t, + z0 = svabd_u32_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** uabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u32_z_untied, svuint32_t, + z0 = svabd_u32_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svabd_n_u32_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** uabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svabd_n_u32_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_z_tied1, svuint32_t, + z0 = svabd_n_u32_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** uabd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_z_untied, svuint32_t, + z0 = svabd_n_u32_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_u32_x_tied1: +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_x_tied1, svuint32_t, + z0 = svabd_u32_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_u32_x_tied2: +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_u32_x_tied2, svuint32_t, + z0 = svabd_u32_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_u32_x_untied: +** ( +** movprfx z0, z1 +** uabd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u32_x_untied, svuint32_t, + z0 = svabd_u32_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svabd_n_u32_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_u32_x_untied: +** mov z0\.s, w0 +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svabd_n_u32_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_u32_x_tied1: +** mov (z[0-9]+\.s), #1 +** uabd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_x_tied1, svuint32_t, + z0 = svabd_n_u32_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_u32_x_untied: +** mov z0\.s, #1 +** uabd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abd_1_u32_x_untied, svuint32_t, + z0 = svabd_n_u32_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u64.c new file mode 100644 index 00000000000..d2cdaa06a5a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_u64_m_tied1: +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_m_tied1, svuint64_t, + z0 = svabd_u64_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_u64_m_tied2, svuint64_t, + z0 = svabd_u64_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_u64_m_untied: +** movprfx z0, z1 +** uabd z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_m_untied, svuint64_t, + z0 = svabd_u64_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svabd_n_u64_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svabd_n_u64_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_m_tied1, svuint64_t, + z0 = svabd_n_u64_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_m_untied, svuint64_t, + z0 = svabd_n_u64_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_z_tied1, svuint64_t, + z0 = svabd_u64_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_z_tied2, svuint64_t, + z0 = svabd_u64_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** uabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u64_z_untied, svuint64_t, + z0 = svabd_u64_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svabd_n_u64_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** uabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svabd_n_u64_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_z_tied1, svuint64_t, + z0 = svabd_n_u64_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** uabd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_z_untied, svuint64_t, + z0 = svabd_n_u64_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_u64_x_tied1: +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_x_tied1, svuint64_t, + z0 = svabd_u64_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_u64_x_tied2: +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_u64_x_tied2, svuint64_t, + z0 = svabd_u64_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_u64_x_untied: +** ( +** movprfx z0, z1 +** uabd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u64_x_untied, svuint64_t, + z0 = svabd_u64_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svabd_n_u64_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_x0_u64_x_untied: +** mov z0\.d, x0 +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (abd_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svabd_n_u64_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_u64_x_tied1: +** mov (z[0-9]+\.d), #1 +** uabd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_x_tied1, svuint64_t, + z0 = svabd_n_u64_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_u64_x_untied: +** mov z0\.d, #1 +** uabd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abd_1_u64_x_untied, svuint64_t, + z0 = svabd_n_u64_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c new file mode 100644 index 00000000000..454ef153cc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abd_u8_m_tied1: +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_m_tied1, svuint8_t, + z0 = svabd_u8_m (p0, z0, z1), + z0 = svabd_m (p0, z0, z1)) + +/* +** abd_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uabd z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_m_tied2, svuint8_t, + z0 = svabd_u8_m (p0, z1, z0), + z0 = svabd_m (p0, z1, z0)) + +/* +** abd_u8_m_untied: +** movprfx z0, z1 +** uabd z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_m_untied, svuint8_t, + z0 = svabd_u8_m (p0, z1, z2), + z0 = svabd_m (p0, z1, z2)) + +/* +** abd_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svabd_n_u8_m (p0, z0, x0), + z0 = svabd_m (p0, z0, x0)) + +/* +** abd_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svabd_n_u8_m (p0, z1, x0), + z0 = svabd_m (p0, z1, x0)) + +/* +** abd_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_m_tied1, svuint8_t, + z0 = svabd_n_u8_m (p0, z0, 1), + z0 = svabd_m (p0, z0, 1)) + +/* +** abd_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_m_untied, svuint8_t, + z0 = svabd_n_u8_m (p0, z1, 1), + z0 = svabd_m (p0, z1, 1)) + +/* +** abd_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_z_tied1, svuint8_t, + z0 = svabd_u8_z (p0, z0, z1), + z0 = svabd_z (p0, z0, z1)) + +/* +** abd_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_z_tied2, svuint8_t, + z0 = svabd_u8_z (p0, z1, z0), + z0 = svabd_z (p0, z1, z0)) + +/* +** abd_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** uabd z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u8_z_untied, svuint8_t, + z0 = svabd_u8_z (p0, z1, z2), + z0 = svabd_z (p0, z1, z2)) + +/* +** abd_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svabd_n_u8_z (p0, z0, x0), + z0 = svabd_z (p0, z0, x0)) + +/* +** abd_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** uabd z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svabd_n_u8_z (p0, z1, x0), + z0 = svabd_z (p0, z1, x0)) + +/* +** abd_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_z_tied1, svuint8_t, + z0 = svabd_n_u8_z (p0, z0, 1), + z0 = svabd_z (p0, z0, 1)) + +/* +** abd_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** uabd z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_z_untied, svuint8_t, + z0 = svabd_n_u8_z (p0, z1, 1), + z0 = svabd_z (p0, z1, 1)) + +/* +** abd_u8_x_tied1: +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_x_tied1, svuint8_t, + z0 = svabd_u8_x (p0, z0, z1), + z0 = svabd_x (p0, z0, z1)) + +/* +** abd_u8_x_tied2: +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_u8_x_tied2, svuint8_t, + z0 = svabd_u8_x (p0, z1, z0), + z0 = svabd_x (p0, z1, z0)) + +/* +** abd_u8_x_untied: +** ( +** movprfx z0, z1 +** uabd z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (abd_u8_x_untied, svuint8_t, + z0 = svabd_u8_x (p0, z1, z2), + z0 = svabd_x (p0, z1, z2)) + +/* +** abd_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svabd_n_u8_x (p0, z0, x0), + z0 = svabd_x (p0, z0, x0)) + +/* +** abd_w0_u8_x_untied: +** mov z0\.b, w0 +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (abd_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svabd_n_u8_x (p0, z1, x0), + z0 = svabd_x (p0, z1, x0)) + +/* +** abd_1_u8_x_tied1: +** mov (z[0-9]+\.b), #1 +** uabd z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_x_tied1, svuint8_t, + z0 = svabd_n_u8_x (p0, z0, 1), + z0 = svabd_x (p0, z0, 1)) + +/* +** abd_1_u8_x_untied: +** mov z0\.b, #1 +** uabd z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abd_1_u8_x_untied, svuint8_t, + z0 = svabd_n_u8_x (p0, z1, 1), + z0 = svabd_x (p0, z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c new file mode 100644 index 00000000000..2aa8736e645 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_f16_m_tied12: +** fabs z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_m_tied12, svfloat16_t, + z0 = svabs_f16_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_f16_m_tied1: +** fabs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_m_tied1, svfloat16_t, + z0 = svabs_f16_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fabs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_m_tied2, svfloat16_t, + z0 = svabs_f16_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_f16_m_untied: +** movprfx z0, z2 +** fabs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_m_untied, svfloat16_t, + z0 = svabs_f16_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** fabs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_z_tied1, svfloat16_t, + z0 = svabs_f16_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fabs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_z_untied, svfloat16_t, + z0 = svabs_f16_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_f16_x_tied1: +** fabs z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_x_tied1, svfloat16_t, + z0 = svabs_f16_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_f16_x_untied: +** fabs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_f16_x_untied, svfloat16_t, + z0 = svabs_f16_x (p0, z1), + z0 = svabs_x (p0, z1)) + +/* +** ptrue_abs_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f16_x_tied1, svfloat16_t, + z0 = svabs_f16_x (svptrue_b16 (), z0), + z0 = svabs_x (svptrue_b16 (), z0)) + +/* +** ptrue_abs_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f16_x_untied, svfloat16_t, + z0 = svabs_f16_x (svptrue_b16 (), z1), + z0 = svabs_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c new file mode 100644 index 00000000000..30286afc7b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_f32_m_tied12: +** fabs z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_m_tied12, svfloat32_t, + z0 = svabs_f32_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_f32_m_tied1: +** fabs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_m_tied1, svfloat32_t, + z0 = svabs_f32_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fabs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_m_tied2, svfloat32_t, + z0 = svabs_f32_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_f32_m_untied: +** movprfx z0, z2 +** fabs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_m_untied, svfloat32_t, + z0 = svabs_f32_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fabs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_z_tied1, svfloat32_t, + z0 = svabs_f32_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fabs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_z_untied, svfloat32_t, + z0 = svabs_f32_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_f32_x_tied1: +** fabs z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_x_tied1, svfloat32_t, + z0 = svabs_f32_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_f32_x_untied: +** fabs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_f32_x_untied, svfloat32_t, + z0 = svabs_f32_x (p0, z1), + z0 = svabs_x (p0, z1)) + +/* +** ptrue_abs_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f32_x_tied1, svfloat32_t, + z0 = svabs_f32_x (svptrue_b32 (), z0), + z0 = svabs_x (svptrue_b32 (), z0)) + +/* +** ptrue_abs_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f32_x_untied, svfloat32_t, + z0 = svabs_f32_x (svptrue_b32 (), z1), + z0 = svabs_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c new file mode 100644 index 00000000000..28ef9fbba23 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_f64_m_tied12: +** fabs z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_m_tied12, svfloat64_t, + z0 = svabs_f64_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_f64_m_tied1: +** fabs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_m_tied1, svfloat64_t, + z0 = svabs_f64_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fabs z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (abs_f64_m_tied2, svfloat64_t, + z0 = svabs_f64_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_f64_m_untied: +** movprfx z0, z2 +** fabs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_m_untied, svfloat64_t, + z0 = svabs_f64_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fabs z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (abs_f64_z_tied1, svfloat64_t, + z0 = svabs_f64_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fabs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_z_untied, svfloat64_t, + z0 = svabs_f64_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_f64_x_tied1: +** fabs z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_x_tied1, svfloat64_t, + z0 = svabs_f64_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_f64_x_untied: +** fabs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_f64_x_untied, svfloat64_t, + z0 = svabs_f64_x (p0, z1), + z0 = svabs_x (p0, z1)) + +/* +** ptrue_abs_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f64_x_tied1, svfloat64_t, + z0 = svabs_f64_x (svptrue_b64 (), z0), + z0 = svabs_x (svptrue_b64 (), z0)) + +/* +** ptrue_abs_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_abs_f64_x_untied, svfloat64_t, + z0 = svabs_f64_x (svptrue_b64 (), z1), + z0 = svabs_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c new file mode 100644 index 00000000000..3b16a9c4f03 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_s16_m_tied12: +** abs z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_m_tied12, svint16_t, + z0 = svabs_s16_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_s16_m_tied1: +** abs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_m_tied1, svint16_t, + z0 = svabs_s16_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** abs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_m_tied2, svint16_t, + z0 = svabs_s16_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_s16_m_untied: +** movprfx z0, z2 +** abs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_m_untied, svint16_t, + z0 = svabs_s16_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** abs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_z_tied1, svint16_t, + z0 = svabs_s16_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** abs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_z_untied, svint16_t, + z0 = svabs_s16_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_s16_x_tied1: +** abs z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_x_tied1, svint16_t, + z0 = svabs_s16_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_s16_x_untied: +** abs z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (abs_s16_x_untied, svint16_t, + z0 = svabs_s16_x (p0, z1), + z0 = svabs_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c new file mode 100644 index 00000000000..14bcbd50c46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_s32_m_tied12: +** abs z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_m_tied12, svint32_t, + z0 = svabs_s32_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_s32_m_tied1: +** abs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_m_tied1, svint32_t, + z0 = svabs_s32_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** abs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_m_tied2, svint32_t, + z0 = svabs_s32_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_s32_m_untied: +** movprfx z0, z2 +** abs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_m_untied, svint32_t, + z0 = svabs_s32_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** abs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_z_tied1, svint32_t, + z0 = svabs_s32_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** abs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_z_untied, svint32_t, + z0 = svabs_s32_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_s32_x_tied1: +** abs z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_x_tied1, svint32_t, + z0 = svabs_s32_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_s32_x_untied: +** abs z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (abs_s32_x_untied, svint32_t, + z0 = svabs_s32_x (p0, z1), + z0 = svabs_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c new file mode 100644 index 00000000000..c7b60ff4843 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_s64_m_tied12: +** abs z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_m_tied12, svint64_t, + z0 = svabs_s64_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_s64_m_tied1: +** abs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_m_tied1, svint64_t, + z0 = svabs_s64_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** abs z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (abs_s64_m_tied2, svint64_t, + z0 = svabs_s64_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_s64_m_untied: +** movprfx z0, z2 +** abs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_m_untied, svint64_t, + z0 = svabs_s64_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** abs z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (abs_s64_z_tied1, svint64_t, + z0 = svabs_s64_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** abs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_z_untied, svint64_t, + z0 = svabs_s64_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_s64_x_tied1: +** abs z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_x_tied1, svint64_t, + z0 = svabs_s64_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_s64_x_untied: +** abs z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (abs_s64_x_untied, svint64_t, + z0 = svabs_s64_x (p0, z1), + z0 = svabs_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c new file mode 100644 index 00000000000..0bc64c078a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** abs_s8_m_tied12: +** abs z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_m_tied12, svint8_t, + z0 = svabs_s8_m (z0, p0, z0), + z0 = svabs_m (z0, p0, z0)) + +/* +** abs_s8_m_tied1: +** abs z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_m_tied1, svint8_t, + z0 = svabs_s8_m (z0, p0, z1), + z0 = svabs_m (z0, p0, z1)) + +/* +** abs_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** abs z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_m_tied2, svint8_t, + z0 = svabs_s8_m (z1, p0, z0), + z0 = svabs_m (z1, p0, z0)) + +/* +** abs_s8_m_untied: +** movprfx z0, z2 +** abs z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_m_untied, svint8_t, + z0 = svabs_s8_m (z2, p0, z1), + z0 = svabs_m (z2, p0, z1)) + +/* +** abs_s8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** abs z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_z_tied1, svint8_t, + z0 = svabs_s8_z (p0, z0), + z0 = svabs_z (p0, z0)) + +/* +** abs_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** abs z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_z_untied, svint8_t, + z0 = svabs_s8_z (p0, z1), + z0 = svabs_z (p0, z1)) + +/* +** abs_s8_x_tied1: +** abs z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_x_tied1, svint8_t, + z0 = svabs_s8_x (p0, z0), + z0 = svabs_x (p0, z0)) + +/* +** abs_s8_x_untied: +** abs z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (abs_s8_x_untied, svint8_t, + z0 = svabs_s8_x (p0, z1), + z0 = svabs_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c new file mode 100644 index 00000000000..acef17309b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f16.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acge_f16_tied: +** ( +** facge p0\.h, p0/z, z0\.h, z1\.h +** | +** facle p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f16_tied, svfloat16_t, + p0 = svacge_f16 (p0, z0, z1), + p0 = svacge (p0, z0, z1)) + +/* +** acge_f16_untied: +** ( +** facge p0\.h, p1/z, z0\.h, z1\.h +** | +** facle p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f16_untied, svfloat16_t, + p0 = svacge_f16 (p1, z0, z1), + p0 = svacge (p1, z0, z1)) + +/* +** acge_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** facge p0\.h, p1/z, z0\.h, \1 +** | +** facle p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZD (acge_h4_f16, svfloat16_t, float16_t, + p0 = svacge_n_f16 (p1, z0, d4), + p0 = svacge (p1, z0, d4)) + +/* +** acge_0_f16: +** mov (z[0-9]+\.h), #0 +** ( +** facge p0\.h, p1/z, z0\.h, \1 +** | +** facle p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acge_0_f16, svfloat16_t, + p0 = svacge_n_f16 (p1, z0, 0), + p0 = svacge (p1, z0, 0)) + +/* +** acge_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** facge p0\.h, p1/z, z0\.h, \1 +** | +** facle p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acge_1_f16, svfloat16_t, + p0 = svacge_n_f16 (p1, z0, 1), + p0 = svacge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c new file mode 100644 index 00000000000..c3d195ab89f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f32.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acge_f32_tied: +** ( +** facge p0\.s, p0/z, z0\.s, z1\.s +** | +** facle p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f32_tied, svfloat32_t, + p0 = svacge_f32 (p0, z0, z1), + p0 = svacge (p0, z0, z1)) + +/* +** acge_f32_untied: +** ( +** facge p0\.s, p1/z, z0\.s, z1\.s +** | +** facle p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f32_untied, svfloat32_t, + p0 = svacge_f32 (p1, z0, z1), + p0 = svacge (p1, z0, z1)) + +/* +** acge_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** facge p0\.s, p1/z, z0\.s, \1 +** | +** facle p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZD (acge_s4_f32, svfloat32_t, float32_t, + p0 = svacge_n_f32 (p1, z0, d4), + p0 = svacge (p1, z0, d4)) + +/* +** acge_0_f32: +** mov (z[0-9]+\.s), #0 +** ( +** facge p0\.s, p1/z, z0\.s, \1 +** | +** facle p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acge_0_f32, svfloat32_t, + p0 = svacge_n_f32 (p1, z0, 0), + p0 = svacge (p1, z0, 0)) + +/* +** acge_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** facge p0\.s, p1/z, z0\.s, \1 +** | +** facle p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acge_1_f32, svfloat32_t, + p0 = svacge_n_f32 (p1, z0, 1), + p0 = svacge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c new file mode 100644 index 00000000000..207ce93a236 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acge_f64.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acge_f64_tied: +** ( +** facge p0\.d, p0/z, z0\.d, z1\.d +** | +** facle p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f64_tied, svfloat64_t, + p0 = svacge_f64 (p0, z0, z1), + p0 = svacge (p0, z0, z1)) + +/* +** acge_f64_untied: +** ( +** facge p0\.d, p1/z, z0\.d, z1\.d +** | +** facle p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acge_f64_untied, svfloat64_t, + p0 = svacge_f64 (p1, z0, z1), + p0 = svacge (p1, z0, z1)) + +/* +** acge_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** facge p0\.d, p1/z, z0\.d, \1 +** | +** facle p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZD (acge_d4_f64, svfloat64_t, float64_t, + p0 = svacge_n_f64 (p1, z0, d4), + p0 = svacge (p1, z0, d4)) + +/* +** acge_0_f64: +** mov (z[0-9]+\.d), #0 +** ( +** facge p0\.d, p1/z, z0\.d, \1 +** | +** facle p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acge_0_f64, svfloat64_t, + p0 = svacge_n_f64 (p1, z0, 0), + p0 = svacge (p1, z0, 0)) + +/* +** acge_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** facge p0\.d, p1/z, z0\.d, \1 +** | +** facle p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acge_1_f64, svfloat64_t, + p0 = svacge_n_f64 (p1, z0, 1), + p0 = svacge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c new file mode 100644 index 00000000000..53c63351cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f16.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acgt_f16_tied: +** ( +** facgt p0\.h, p0/z, z0\.h, z1\.h +** | +** faclt p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f16_tied, svfloat16_t, + p0 = svacgt_f16 (p0, z0, z1), + p0 = svacgt (p0, z0, z1)) + +/* +** acgt_f16_untied: +** ( +** facgt p0\.h, p1/z, z0\.h, z1\.h +** | +** faclt p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f16_untied, svfloat16_t, + p0 = svacgt_f16 (p1, z0, z1), + p0 = svacgt (p1, z0, z1)) + +/* +** acgt_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** facgt p0\.h, p1/z, z0\.h, \1 +** | +** faclt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZD (acgt_h4_f16, svfloat16_t, float16_t, + p0 = svacgt_n_f16 (p1, z0, d4), + p0 = svacgt (p1, z0, d4)) + +/* +** acgt_0_f16: +** mov (z[0-9]+\.h), #0 +** ( +** facgt p0\.h, p1/z, z0\.h, \1 +** | +** faclt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_0_f16, svfloat16_t, + p0 = svacgt_n_f16 (p1, z0, 0), + p0 = svacgt (p1, z0, 0)) + +/* +** acgt_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** facgt p0\.h, p1/z, z0\.h, \1 +** | +** faclt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_1_f16, svfloat16_t, + p0 = svacgt_n_f16 (p1, z0, 1), + p0 = svacgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c new file mode 100644 index 00000000000..d71c84ea611 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f32.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acgt_f32_tied: +** ( +** facgt p0\.s, p0/z, z0\.s, z1\.s +** | +** faclt p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f32_tied, svfloat32_t, + p0 = svacgt_f32 (p0, z0, z1), + p0 = svacgt (p0, z0, z1)) + +/* +** acgt_f32_untied: +** ( +** facgt p0\.s, p1/z, z0\.s, z1\.s +** | +** faclt p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f32_untied, svfloat32_t, + p0 = svacgt_f32 (p1, z0, z1), + p0 = svacgt (p1, z0, z1)) + +/* +** acgt_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** facgt p0\.s, p1/z, z0\.s, \1 +** | +** faclt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZD (acgt_s4_f32, svfloat32_t, float32_t, + p0 = svacgt_n_f32 (p1, z0, d4), + p0 = svacgt (p1, z0, d4)) + +/* +** acgt_0_f32: +** mov (z[0-9]+\.s), #0 +** ( +** facgt p0\.s, p1/z, z0\.s, \1 +** | +** faclt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_0_f32, svfloat32_t, + p0 = svacgt_n_f32 (p1, z0, 0), + p0 = svacgt (p1, z0, 0)) + +/* +** acgt_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** facgt p0\.s, p1/z, z0\.s, \1 +** | +** faclt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_1_f32, svfloat32_t, + p0 = svacgt_n_f32 (p1, z0, 1), + p0 = svacgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c new file mode 100644 index 00000000000..15d549e1836 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acgt_f64.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acgt_f64_tied: +** ( +** facgt p0\.d, p0/z, z0\.d, z1\.d +** | +** faclt p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f64_tied, svfloat64_t, + p0 = svacgt_f64 (p0, z0, z1), + p0 = svacgt (p0, z0, z1)) + +/* +** acgt_f64_untied: +** ( +** facgt p0\.d, p1/z, z0\.d, z1\.d +** | +** faclt p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_f64_untied, svfloat64_t, + p0 = svacgt_f64 (p1, z0, z1), + p0 = svacgt (p1, z0, z1)) + +/* +** acgt_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** facgt p0\.d, p1/z, z0\.d, \1 +** | +** faclt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZD (acgt_d4_f64, svfloat64_t, float64_t, + p0 = svacgt_n_f64 (p1, z0, d4), + p0 = svacgt (p1, z0, d4)) + +/* +** acgt_0_f64: +** mov (z[0-9]+\.d), #0 +** ( +** facgt p0\.d, p1/z, z0\.d, \1 +** | +** faclt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_0_f64, svfloat64_t, + p0 = svacgt_n_f64 (p1, z0, 0), + p0 = svacgt (p1, z0, 0)) + +/* +** acgt_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** facgt p0\.d, p1/z, z0\.d, \1 +** | +** faclt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acgt_1_f64, svfloat64_t, + p0 = svacgt_n_f64 (p1, z0, 1), + p0 = svacgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c new file mode 100644 index 00000000000..ed6721d5719 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f16.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acle_f16_tied: +** ( +** facge p0\.h, p0/z, z1\.h, z0\.h +** | +** facle p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f16_tied, svfloat16_t, + p0 = svacle_f16 (p0, z0, z1), + p0 = svacle (p0, z0, z1)) + +/* +** acle_f16_untied: +** ( +** facge p0\.h, p1/z, z1\.h, z0\.h +** | +** facle p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f16_untied, svfloat16_t, + p0 = svacle_f16 (p1, z0, z1), + p0 = svacle (p1, z0, z1)) + +/* +** acle_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** facge p0\.h, p1/z, \1, z0\.h +** | +** facle p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (acle_h4_f16, svfloat16_t, float16_t, + p0 = svacle_n_f16 (p1, z0, d4), + p0 = svacle (p1, z0, d4)) + +/* +** acle_0_f16: +** mov (z[0-9]+\.h), #0 +** ( +** facge p0\.h, p1/z, \1, z0\.h +** | +** facle p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_0_f16, svfloat16_t, + p0 = svacle_n_f16 (p1, z0, 0), + p0 = svacle (p1, z0, 0)) + +/* +** acle_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** facge p0\.h, p1/z, \1, z0\.h +** | +** facle p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_1_f16, svfloat16_t, + p0 = svacle_n_f16 (p1, z0, 1), + p0 = svacle (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c new file mode 100644 index 00000000000..7fc9da701d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f32.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acle_f32_tied: +** ( +** facge p0\.s, p0/z, z1\.s, z0\.s +** | +** facle p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f32_tied, svfloat32_t, + p0 = svacle_f32 (p0, z0, z1), + p0 = svacle (p0, z0, z1)) + +/* +** acle_f32_untied: +** ( +** facge p0\.s, p1/z, z1\.s, z0\.s +** | +** facle p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f32_untied, svfloat32_t, + p0 = svacle_f32 (p1, z0, z1), + p0 = svacle (p1, z0, z1)) + +/* +** acle_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** facge p0\.s, p1/z, \1, z0\.s +** | +** facle p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (acle_s4_f32, svfloat32_t, float32_t, + p0 = svacle_n_f32 (p1, z0, d4), + p0 = svacle (p1, z0, d4)) + +/* +** acle_0_f32: +** mov (z[0-9]+\.s), #0 +** ( +** facge p0\.s, p1/z, \1, z0\.s +** | +** facle p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_0_f32, svfloat32_t, + p0 = svacle_n_f32 (p1, z0, 0), + p0 = svacle (p1, z0, 0)) + +/* +** acle_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** facge p0\.s, p1/z, \1, z0\.s +** | +** facle p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_1_f32, svfloat32_t, + p0 = svacle_n_f32 (p1, z0, 1), + p0 = svacle (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c new file mode 100644 index 00000000000..ecbb8e5007c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/acle_f64.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** acle_f64_tied: +** ( +** facge p0\.d, p0/z, z1\.d, z0\.d +** | +** facle p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f64_tied, svfloat64_t, + p0 = svacle_f64 (p0, z0, z1), + p0 = svacle (p0, z0, z1)) + +/* +** acle_f64_untied: +** ( +** facge p0\.d, p1/z, z1\.d, z0\.d +** | +** facle p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (acle_f64_untied, svfloat64_t, + p0 = svacle_f64 (p1, z0, z1), + p0 = svacle (p1, z0, z1)) + +/* +** acle_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** facge p0\.d, p1/z, \1, z0\.d +** | +** facle p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (acle_d4_f64, svfloat64_t, float64_t, + p0 = svacle_n_f64 (p1, z0, d4), + p0 = svacle (p1, z0, d4)) + +/* +** acle_0_f64: +** mov (z[0-9]+\.d), #0 +** ( +** facge p0\.d, p1/z, \1, z0\.d +** | +** facle p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_0_f64, svfloat64_t, + p0 = svacle_n_f64 (p1, z0, 0), + p0 = svacle (p1, z0, 0)) + +/* +** acle_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** facge p0\.d, p1/z, \1, z0\.d +** | +** facle p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (acle_1_f64, svfloat64_t, + p0 = svacle_n_f64 (p1, z0, 1), + p0 = svacle (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c new file mode 100644 index 00000000000..e5f5040c7d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f16.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** aclt_f16_tied: +** ( +** facgt p0\.h, p0/z, z1\.h, z0\.h +** | +** faclt p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f16_tied, svfloat16_t, + p0 = svaclt_f16 (p0, z0, z1), + p0 = svaclt (p0, z0, z1)) + +/* +** aclt_f16_untied: +** ( +** facgt p0\.h, p1/z, z1\.h, z0\.h +** | +** faclt p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f16_untied, svfloat16_t, + p0 = svaclt_f16 (p1, z0, z1), + p0 = svaclt (p1, z0, z1)) + +/* +** aclt_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** facgt p0\.h, p1/z, \1, z0\.h +** | +** faclt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (aclt_h4_f16, svfloat16_t, float16_t, + p0 = svaclt_n_f16 (p1, z0, d4), + p0 = svaclt (p1, z0, d4)) + +/* +** aclt_0_f16: +** mov (z[0-9]+\.h), #0 +** ( +** facgt p0\.h, p1/z, \1, z0\.h +** | +** faclt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_0_f16, svfloat16_t, + p0 = svaclt_n_f16 (p1, z0, 0), + p0 = svaclt (p1, z0, 0)) + +/* +** aclt_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** facgt p0\.h, p1/z, \1, z0\.h +** | +** faclt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_1_f16, svfloat16_t, + p0 = svaclt_n_f16 (p1, z0, 1), + p0 = svaclt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c new file mode 100644 index 00000000000..f40826445f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f32.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** aclt_f32_tied: +** ( +** facgt p0\.s, p0/z, z1\.s, z0\.s +** | +** faclt p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f32_tied, svfloat32_t, + p0 = svaclt_f32 (p0, z0, z1), + p0 = svaclt (p0, z0, z1)) + +/* +** aclt_f32_untied: +** ( +** facgt p0\.s, p1/z, z1\.s, z0\.s +** | +** faclt p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f32_untied, svfloat32_t, + p0 = svaclt_f32 (p1, z0, z1), + p0 = svaclt (p1, z0, z1)) + +/* +** aclt_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** facgt p0\.s, p1/z, \1, z0\.s +** | +** faclt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (aclt_s4_f32, svfloat32_t, float32_t, + p0 = svaclt_n_f32 (p1, z0, d4), + p0 = svaclt (p1, z0, d4)) + +/* +** aclt_0_f32: +** mov (z[0-9]+\.s), #0 +** ( +** facgt p0\.s, p1/z, \1, z0\.s +** | +** faclt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_0_f32, svfloat32_t, + p0 = svaclt_n_f32 (p1, z0, 0), + p0 = svaclt (p1, z0, 0)) + +/* +** aclt_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** facgt p0\.s, p1/z, \1, z0\.s +** | +** faclt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_1_f32, svfloat32_t, + p0 = svaclt_n_f32 (p1, z0, 1), + p0 = svaclt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c new file mode 100644 index 00000000000..0170b330700 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/aclt_f64.c @@ -0,0 +1,71 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** aclt_f64_tied: +** ( +** facgt p0\.d, p0/z, z1\.d, z0\.d +** | +** faclt p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f64_tied, svfloat64_t, + p0 = svaclt_f64 (p0, z0, z1), + p0 = svaclt (p0, z0, z1)) + +/* +** aclt_f64_untied: +** ( +** facgt p0\.d, p1/z, z1\.d, z0\.d +** | +** faclt p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_f64_untied, svfloat64_t, + p0 = svaclt_f64 (p1, z0, z1), + p0 = svaclt (p1, z0, z1)) + +/* +** aclt_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** facgt p0\.d, p1/z, \1, z0\.d +** | +** faclt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (aclt_d4_f64, svfloat64_t, float64_t, + p0 = svaclt_n_f64 (p1, z0, d4), + p0 = svaclt (p1, z0, d4)) + +/* +** aclt_0_f64: +** mov (z[0-9]+\.d), #0 +** ( +** facgt p0\.d, p1/z, \1, z0\.d +** | +** faclt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_0_f64, svfloat64_t, + p0 = svaclt_n_f64 (p1, z0, 0), + p0 = svaclt (p1, z0, 0)) + +/* +** aclt_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** facgt p0\.d, p1/z, \1, z0\.d +** | +** faclt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (aclt_1_f64, svfloat64_t, + p0 = svaclt_n_f64 (p1, z0, 1), + p0 = svaclt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16.c new file mode 100644 index 00000000000..7228e5dd57d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_tied1, svfloat16_t, + z0 = svadd_f16_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_tied2, svfloat16_t, + z0 = svadd_f16_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_untied, svfloat16_t, + z0 = svadd_f16_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f16_m: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f16_m, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_tied1, svfloat16_t, + z0 = svadd_f16_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_tied2, svfloat16_t, + z0 = svadd_f16_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_untied, svfloat16_t, + z0 = svadd_f16_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f16_z: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f16_z, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_tied1, svfloat16_t, + z0 = svadd_f16_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f16_x_tied2: +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_tied2, svfloat16_t, + z0 = svadd_f16_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f16_x_untied: +** ( +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_untied, svfloat16_t, + z0 = svadd_f16_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_h4_f16_x_untied: +** mov z0\.h, h4 +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_2_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_2_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f16_x_tied1: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_tied1, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z0, z1), + z0 = svadd_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_add_f16_x_tied2: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_tied2, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z1, z0), + z0 = svadd_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_add_f16_x_untied: +** fadd z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_untied, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z1, z2), + z0 = svadd_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_add_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svadd_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_add_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svadd_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_add_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svadd_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svadd_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_add_m1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svadd_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_add_m1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svadd_x (svptrue_b16 (), z1, -1)) + +/* +** ptrue_add_m0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, -0.5), + z0 = svadd_x (svptrue_b16 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, -0.5), + z0 = svadd_x (svptrue_b16 (), z1, -0.5)) + +/* +** ptrue_add_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svadd_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_add_2_f16_x_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svadd_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16_notrap.c new file mode 100644 index 00000000000..f6330acee1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f16_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_tied1, svfloat16_t, + z0 = svadd_f16_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_tied2, svfloat16_t, + z0 = svadd_f16_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_m_untied, svfloat16_t, + z0 = svadd_f16_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_m_tied1, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_m_untied, svfloat16_t, + z0 = svadd_n_f16_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f16_m: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f16_m, svfloat16_t, + z0 = svadd_n_f16_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_tied1, svfloat16_t, + z0 = svadd_f16_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_tied2, svfloat16_t, + z0 = svadd_f16_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f16_z_untied, svfloat16_t, + z0 = svadd_f16_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_z_tied1, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_z_untied, svfloat16_t, + z0 = svadd_n_f16_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f16_z: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f16_z, svfloat16_t, + z0 = svadd_n_f16_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f16_x_tied1: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_tied1, svfloat16_t, + z0 = svadd_f16_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f16_x_tied2: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_tied2, svfloat16_t, + z0 = svadd_f16_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f16_x_untied: +** fadd z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (add_f16_x_untied, svfloat16_t, + z0 = svadd_f16_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svadd_n_f16_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_h4_f16_x_untied: +** mov (z[0-9]+\.h), h4 +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZD (add_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svadd_n_f16_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_2_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f16_x_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (add_2_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f16_x_tied1: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_tied1, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z0, z1), + z0 = svadd_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_add_f16_x_tied2: +** fadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_tied2, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z1, z0), + z0 = svadd_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_add_f16_x_untied: +** fadd z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f16_x_untied, svfloat16_t, + z0 = svadd_f16_x (svptrue_b16 (), z1, z2), + z0 = svadd_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_add_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svadd_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_add_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svadd_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_add_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svadd_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svadd_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_add_m1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svadd_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_add_m1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svadd_x (svptrue_b16 (), z1, -1)) + +/* +** ptrue_add_m0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, -0.5), + z0 = svadd_x (svptrue_b16 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, -0.5), + z0 = svadd_x (svptrue_b16 (), z1, -0.5)) + +/* +** ptrue_add_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f16_x_tied1, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svadd_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_add_2_f16_x_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f16_x_untied, svfloat16_t, + z0 = svadd_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svadd_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32.c new file mode 100644 index 00000000000..b5f4e962303 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_tied1, svfloat32_t, + z0 = svadd_f32_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_tied2, svfloat32_t, + z0 = svadd_f32_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_untied, svfloat32_t, + z0 = svadd_f32_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_m_tied1, svfloat32_t, float, + z0 = svadd_n_f32_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_m_untied, svfloat32_t, float, + z0 = svadd_n_f32_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f32_m: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f32_m, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_tied1, svfloat32_t, + z0 = svadd_f32_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_tied2, svfloat32_t, + z0 = svadd_f32_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_untied, svfloat32_t, + z0 = svadd_f32_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_z_tied1, svfloat32_t, float, + z0 = svadd_n_f32_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_z_untied, svfloat32_t, float, + z0 = svadd_n_f32_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f32_z: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f32_z, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_tied1, svfloat32_t, + z0 = svadd_f32_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f32_x_tied2: +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_tied2, svfloat32_t, + z0 = svadd_f32_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f32_x_untied: +** ( +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_untied, svfloat32_t, + z0 = svadd_f32_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_x_tied1, svfloat32_t, float, + z0 = svadd_n_f32_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_s4_f32_x_untied: +** mov z0\.s, s4 +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_x_untied, svfloat32_t, float, + z0 = svadd_n_f32_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_2_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_2_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f32_x_tied1: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_tied1, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z0, z1), + z0 = svadd_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_add_f32_x_tied2: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_tied2, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z1, z0), + z0 = svadd_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_add_f32_x_untied: +** fadd z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_untied, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z1, z2), + z0 = svadd_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_add_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svadd_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_add_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svadd_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_add_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svadd_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svadd_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_add_m1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svadd_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_add_m1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svadd_x (svptrue_b32 (), z1, -1)) + +/* +** ptrue_add_m0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, -0.5), + z0 = svadd_x (svptrue_b32 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, -0.5), + z0 = svadd_x (svptrue_b32 (), z1, -0.5)) + +/* +** ptrue_add_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svadd_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_add_2_f32_x_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svadd_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32_notrap.c new file mode 100644 index 00000000000..062e5fd672d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f32_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_tied1, svfloat32_t, + z0 = svadd_f32_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_tied2, svfloat32_t, + z0 = svadd_f32_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_m_untied, svfloat32_t, + z0 = svadd_f32_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_m_tied1, svfloat32_t, float, + z0 = svadd_n_f32_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_m_untied, svfloat32_t, float, + z0 = svadd_n_f32_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_m_tied1, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_m_untied, svfloat32_t, + z0 = svadd_n_f32_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f32_m: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f32_m, svfloat32_t, + z0 = svadd_n_f32_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_tied1, svfloat32_t, + z0 = svadd_f32_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_tied2, svfloat32_t, + z0 = svadd_f32_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f32_z_untied, svfloat32_t, + z0 = svadd_f32_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_z_tied1, svfloat32_t, float, + z0 = svadd_n_f32_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_z_untied, svfloat32_t, float, + z0 = svadd_n_f32_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_z_tied1, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_z_untied, svfloat32_t, + z0 = svadd_n_f32_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f32_z: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f32_z, svfloat32_t, + z0 = svadd_n_f32_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f32_x_tied1: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_tied1, svfloat32_t, + z0 = svadd_f32_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f32_x_tied2: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_tied2, svfloat32_t, + z0 = svadd_f32_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f32_x_untied: +** fadd z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (add_f32_x_untied, svfloat32_t, + z0 = svadd_f32_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_x_tied1, svfloat32_t, float, + z0 = svadd_n_f32_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_s4_f32_x_untied: +** mov (z[0-9]+\.s), s4 +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZD (add_s4_f32_x_untied, svfloat32_t, float, + z0 = svadd_n_f32_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_2_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f32_x_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (add_2_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f32_x_tied1: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_tied1, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z0, z1), + z0 = svadd_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_add_f32_x_tied2: +** fadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_tied2, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z1, z0), + z0 = svadd_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_add_f32_x_untied: +** fadd z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f32_x_untied, svfloat32_t, + z0 = svadd_f32_x (svptrue_b32 (), z1, z2), + z0 = svadd_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_add_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svadd_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_add_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svadd_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_add_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svadd_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svadd_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_add_m1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svadd_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_add_m1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svadd_x (svptrue_b32 (), z1, -1)) + +/* +** ptrue_add_m0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, -0.5), + z0 = svadd_x (svptrue_b32 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, -0.5), + z0 = svadd_x (svptrue_b32 (), z1, -0.5)) + +/* +** ptrue_add_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f32_x_tied1, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svadd_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_add_2_f32_x_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f32_x_untied, svfloat32_t, + z0 = svadd_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svadd_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64.c new file mode 100644 index 00000000000..7185f3acf1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_tied1, svfloat64_t, + z0 = svadd_f64_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_tied2, svfloat64_t, + z0 = svadd_f64_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_untied, svfloat64_t, + z0 = svadd_f64_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_m_tied1, svfloat64_t, double, + z0 = svadd_n_f64_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_m_untied, svfloat64_t, double, + z0 = svadd_n_f64_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f64_m: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f64_m, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_tied1, svfloat64_t, + z0 = svadd_f64_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_tied2, svfloat64_t, + z0 = svadd_f64_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_untied, svfloat64_t, + z0 = svadd_f64_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_z_tied1, svfloat64_t, double, + z0 = svadd_n_f64_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_z_untied, svfloat64_t, double, + z0 = svadd_n_f64_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f64_z: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f64_z, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_tied1, svfloat64_t, + z0 = svadd_f64_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f64_x_tied2: +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_tied2, svfloat64_t, + z0 = svadd_f64_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f64_x_untied: +** ( +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_untied, svfloat64_t, + z0 = svadd_f64_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_x_tied1, svfloat64_t, double, + z0 = svadd_n_f64_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_d4_f64_x_untied: +** mov z0\.d, d4 +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_x_untied, svfloat64_t, double, + z0 = svadd_n_f64_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_2_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_2_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f64_x_tied1: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_tied1, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z0, z1), + z0 = svadd_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_add_f64_x_tied2: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_tied2, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z1, z0), + z0 = svadd_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_add_f64_x_untied: +** fadd z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_untied, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z1, z2), + z0 = svadd_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_add_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svadd_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_add_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svadd_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_add_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svadd_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svadd_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_add_m1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svadd_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_add_m1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svadd_x (svptrue_b64 (), z1, -1)) + +/* +** ptrue_add_m0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, -0.5), + z0 = svadd_x (svptrue_b64 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, -0.5), + z0 = svadd_x (svptrue_b64 (), z1, -0.5)) + +/* +** ptrue_add_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svadd_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_add_2_f64_x_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svadd_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64_notrap.c new file mode 100644 index 00000000000..6d095b507d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_f64_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_tied1, svfloat64_t, + z0 = svadd_f64_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_tied2, svfloat64_t, + z0 = svadd_f64_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_m_untied, svfloat64_t, + z0 = svadd_f64_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_m_tied1, svfloat64_t, double, + z0 = svadd_n_f64_m (p0, z0, d4), + z0 = svadd_m (p0, z0, d4)) + +/* +** add_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_m_untied, svfloat64_t, double, + z0 = svadd_n_f64_m (p0, z1, d4), + z0 = svadd_m (p0, z1, d4)) + +/* +** add_1_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_0p5_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, 0.5), + z0 = svadd_m (p0, z0, 0.5)) + +/* +** add_0p5_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, 0.5), + z0 = svadd_m (p0, z1, 0.5)) + +/* +** add_m1_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_m1_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, -1), + z0 = svadd_m (p0, z1, -1)) + +/* +** add_m0p5_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_m_tied1, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -0.5), + z0 = svadd_m (p0, z0, -0.5)) + +/* +** add_m0p5_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_m_untied, svfloat64_t, + z0 = svadd_n_f64_m (p0, z1, -0.5), + z0 = svadd_m (p0, z1, -0.5)) + +/* +** add_m2_f64_m: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f64_m, svfloat64_t, + z0 = svadd_n_f64_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_tied1, svfloat64_t, + z0 = svadd_f64_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_tied2, svfloat64_t, + z0 = svadd_f64_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_f64_z_untied, svfloat64_t, + z0 = svadd_f64_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_z_tied1, svfloat64_t, double, + z0 = svadd_n_f64_z (p0, z0, d4), + z0 = svadd_z (p0, z0, d4)) + +/* +** add_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_z_untied, svfloat64_t, double, + z0 = svadd_n_f64_z (p0, z1, d4), + z0 = svadd_z (p0, z1, d4)) + +/* +** add_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, 0.5), + z0 = svadd_z (p0, z0, 0.5)) + +/* +** add_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, 0.5), + z0 = svadd_z (p0, z1, 0.5)) + +/* +** add_m1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -1), + z0 = svadd_z (p0, z0, -1)) + +/* +** add_m1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, -1), + z0 = svadd_z (p0, z1, -1)) + +/* +** add_m0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_z_tied1, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -0.5), + z0 = svadd_z (p0, z0, -0.5)) + +/* +** add_m0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_z_untied, svfloat64_t, + z0 = svadd_n_f64_z (p0, z1, -0.5), + z0 = svadd_z (p0, z1, -0.5)) + +/* +** add_m2_f64_z: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_f64_z, svfloat64_t, + z0 = svadd_n_f64_z (p0, z0, -2), + z0 = svadd_z (p0, z0, -2)) + +/* +** add_f64_x_tied1: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_tied1, svfloat64_t, + z0 = svadd_f64_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_f64_x_tied2: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_tied2, svfloat64_t, + z0 = svadd_f64_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_f64_x_untied: +** fadd z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (add_f64_x_untied, svfloat64_t, + z0 = svadd_f64_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_x_tied1, svfloat64_t, double, + z0 = svadd_n_f64_x (p0, z0, d4), + z0 = svadd_x (p0, z0, d4)) + +/* +** add_d4_f64_x_untied: +** mov (z[0-9]+\.d), d4 +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZD (add_d4_f64_x_untied, svfloat64_t, double, + z0 = svadd_n_f64_x (p0, z1, d4), + z0 = svadd_x (p0, z1, d4)) + +/* +** add_1_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_0p5_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 0.5), + z0 = svadd_x (p0, z0, 0.5)) + +/* +** add_0p5_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 0.5), + z0 = svadd_x (p0, z1, 0.5)) + +/* +** add_m1_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m1_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (add_m1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, -1), + z0 = svadd_x (p0, z1, -1)) + +/* +** add_m0p5_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, -0.5), + z0 = svadd_x (p0, z0, -0.5)) + +/* +** add_m0p5_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (add_m0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, -0.5), + z0 = svadd_x (p0, z1, -0.5)) + +/* +** add_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_2_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (p0, z0, 2), + z0 = svadd_x (p0, z0, 2)) + +/* +** add_2_f64_x_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (add_2_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (p0, z1, 2), + z0 = svadd_x (p0, z1, 2)) + +/* +** ptrue_add_f64_x_tied1: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_tied1, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z0, z1), + z0 = svadd_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_add_f64_x_tied2: +** fadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_tied2, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z1, z0), + z0 = svadd_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_add_f64_x_untied: +** fadd z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_f64_x_untied, svfloat64_t, + z0 = svadd_f64_x (svptrue_b64 (), z1, z2), + z0 = svadd_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_add_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svadd_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_add_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svadd_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_add_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svadd_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_add_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svadd_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_add_m1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svadd_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_add_m1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m1_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svadd_x (svptrue_b64 (), z1, -1)) + +/* +** ptrue_add_m0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, -0.5), + z0 = svadd_x (svptrue_b64 (), z0, -0.5)) + +/* +** ptrue_add_m0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_m0p5_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, -0.5), + z0 = svadd_x (svptrue_b64 (), z1, -0.5)) + +/* +** ptrue_add_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f64_x_tied1, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svadd_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_add_2_f64_x_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_add_2_f64_x_untied, svfloat64_t, + z0 = svadd_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svadd_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c new file mode 100644 index 00000000000..c0883edf9ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c @@ -0,0 +1,377 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_s16_m_tied1: +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_s16_m_tied1, svint16_t, + z0 = svadd_s16_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (add_s16_m_tied2, svint16_t, + z0 = svadd_s16_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_s16_m_untied: +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (add_s16_m_untied, svint16_t, + z0 = svadd_s16_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svadd_n_s16_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_m_untied, svint16_t, int16_t, + z0 = svadd_n_s16_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_m_tied1, svint16_t, + z0 = svadd_n_s16_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_m_untied, svint16_t, + z0 = svadd_n_s16_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_s16_m: +** mov (z[0-9]+\.h), #-2 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_s16_m, svint16_t, + z0 = svadd_n_s16_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_s16_z_tied1, svint16_t, + z0 = svadd_s16_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_s16_z_tied2, svint16_t, + z0 = svadd_s16_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_s16_z_untied, svint16_t, + z0 = svadd_s16_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svadd_n_s16_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_z_untied, svint16_t, int16_t, + z0 = svadd_n_s16_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_z_tied1, svint16_t, + z0 = svadd_n_s16_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_z_untied, svint16_t, + z0 = svadd_n_s16_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_s16_x_tied1: +** add z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_s16_x_tied1, svint16_t, + z0 = svadd_s16_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_s16_x_tied2: +** add z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_s16_x_tied2, svint16_t, + z0 = svadd_s16_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_s16_x_untied: +** add z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (add_s16_x_untied, svint16_t, + z0 = svadd_s16_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svadd_n_s16_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_s16_x_untied: +** mov (z[0-9]+\.h), w0 +** add z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s16_x_untied, svint16_t, int16_t, + z0 = svadd_n_s16_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_s16_x_tied1: +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_x_tied1, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_s16_x_untied: +** movprfx z0, z1 +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s16_x_untied, svint16_t, + z0 = svadd_n_s16_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_s16_x: +** add z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_s16_x: +** add z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_s16_x: +** add z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_s16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_257_s16_x: +** mov (z[0-9]+)\.b, #1 +** add z0\.h, (z0\.h, \1\.h|\1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_257_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 257), + z0 = svadd_x (p0, z0, 257)) + +/* +** add_512_s16_x: +** add z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_s16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_m1_s16_x: +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_s16_x: +** sub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_s16_x: +** sub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_s16_x: +** sub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_s16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m256_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m257_s16_x: +** mov (z[0-9]+\.h), #-257 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_m257_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -257), + z0 = svadd_x (p0, z0, -257)) + +/* +** add_m512_s16_x: +** add z0\.h, z0\.h, #65024 +** ret +*/ +TEST_UNIFORM_Z (add_m512_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_s16_x: +** add z0\.h, z0\.h, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_s16_x, svint16_t, + z0 = svadd_n_s16_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s32.c new file mode 100644 index 00000000000..887038ba3c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s32.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_s32_m_tied1: +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_s32_m_tied1, svint32_t, + z0 = svadd_s32_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (add_s32_m_tied2, svint32_t, + z0 = svadd_s32_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_s32_m_untied: +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (add_s32_m_untied, svint32_t, + z0 = svadd_s32_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svadd_n_s32_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_m_untied, svint32_t, int32_t, + z0 = svadd_n_s32_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_m_tied1, svint32_t, + z0 = svadd_n_s32_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_m_untied, svint32_t, + z0 = svadd_n_s32_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_s32_m: +** mov (z[0-9]+\.s), #-2 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_s32_m, svint32_t, + z0 = svadd_n_s32_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_s32_z_tied1, svint32_t, + z0 = svadd_s32_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_s32_z_tied2, svint32_t, + z0 = svadd_s32_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_s32_z_untied, svint32_t, + z0 = svadd_s32_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svadd_n_s32_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_z_untied, svint32_t, int32_t, + z0 = svadd_n_s32_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_z_tied1, svint32_t, + z0 = svadd_n_s32_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_z_untied, svint32_t, + z0 = svadd_n_s32_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_s32_x_tied1: +** add z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_s32_x_tied1, svint32_t, + z0 = svadd_s32_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_s32_x_tied2: +** add z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_s32_x_tied2, svint32_t, + z0 = svadd_s32_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_s32_x_untied: +** add z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (add_s32_x_untied, svint32_t, + z0 = svadd_s32_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svadd_n_s32_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_s32_x_untied: +** mov (z[0-9]+\.s), w0 +** add z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s32_x_untied, svint32_t, int32_t, + z0 = svadd_n_s32_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_s32_x_tied1: +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_x_tied1, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_s32_x_untied: +** movprfx z0, z1 +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s32_x_untied, svint32_t, + z0 = svadd_n_s32_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_s32_x: +** add z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_s32_x: +** add z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_s32_x: +** add z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_s32_x: +** add z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_511_s32_x: +** mov (z[0-9]+\.s), #511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_511_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 511), + z0 = svadd_x (p0, z0, 511)) + +/* +** add_512_s32_x: +** add z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_s32_x: +** add z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_65535_s32_x: +** mov (z[0-9]+\.s), #65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_65535_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 65535), + z0 = svadd_x (p0, z0, 65535)) + +/* +** add_65536_s32_x: +** mov (z[0-9]+\.s), #65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_65536_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, 65536), + z0 = svadd_x (p0, z0, 65536)) + +/* +** add_m1_s32_x: +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_s32_x: +** sub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_s32_x: +** sub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_s32_x: +** sub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_s32_x: +** sub z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (add_m256_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m511_s32_x: +** mov (z[0-9]+\.s), #-511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m511_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -511), + z0 = svadd_x (p0, z0, -511)) + +/* +** add_m512_s32_x: +** sub z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (add_m512_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_s32_x: +** sub z0\.s, z0\.s, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) + +/* +** add_m65280_s32_x: +** sub z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m65280_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -0xff00), + z0 = svadd_x (p0, z0, -0xff00)) + +/* +** add_m65535_s32_x: +** mov (z[0-9]+\.s), #-65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m65535_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -65535), + z0 = svadd_x (p0, z0, -65535)) + +/* +** add_m65536_s32_x: +** mov (z[0-9]+\.s), #-65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m65536_s32_x, svint32_t, + z0 = svadd_n_s32_x (p0, z0, -65536), + z0 = svadd_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s64.c new file mode 100644 index 00000000000..aab63ef6211 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s64.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_s64_m_tied1: +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_s64_m_tied1, svint64_t, + z0 = svadd_s64_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_s64_m_tied2, svint64_t, + z0 = svadd_s64_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_s64_m_untied: +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (add_s64_m_untied, svint64_t, + z0 = svadd_s64_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svadd_n_s64_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_m_untied, svint64_t, int64_t, + z0 = svadd_n_s64_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_m_tied1, svint64_t, + z0 = svadd_n_s64_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_m_untied, svint64_t, + z0 = svadd_n_s64_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_s64_m: +** mov (z[0-9]+\.d), #-2 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_s64_m, svint64_t, + z0 = svadd_n_s64_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_s64_z_tied1, svint64_t, + z0 = svadd_s64_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_s64_z_tied2, svint64_t, + z0 = svadd_s64_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_s64_z_untied, svint64_t, + z0 = svadd_s64_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svadd_n_s64_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_z_untied, svint64_t, int64_t, + z0 = svadd_n_s64_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_z_tied1, svint64_t, + z0 = svadd_n_s64_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_z_untied, svint64_t, + z0 = svadd_n_s64_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_s64_x_tied1: +** add z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_s64_x_tied1, svint64_t, + z0 = svadd_s64_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_s64_x_tied2: +** add z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_s64_x_tied2, svint64_t, + z0 = svadd_s64_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_s64_x_untied: +** add z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (add_s64_x_untied, svint64_t, + z0 = svadd_s64_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svadd_n_s64_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** add z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_s64_x_untied, svint64_t, int64_t, + z0 = svadd_n_s64_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_s64_x_tied1: +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_x_tied1, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_s64_x_untied: +** movprfx z0, z1 +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s64_x_untied, svint64_t, + z0 = svadd_n_s64_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_s64_x: +** add z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_s64_x: +** add z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_s64_x: +** add z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_s64_x: +** add z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_511_s64_x: +** mov (z[0-9]+\.d), #511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_511_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 511), + z0 = svadd_x (p0, z0, 511)) + +/* +** add_512_s64_x: +** add z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_s64_x: +** add z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_65535_s64_x: +** mov (z[0-9]+\.d), #65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_65535_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 65535), + z0 = svadd_x (p0, z0, 65535)) + +/* +** add_65536_s64_x: +** mov (z[0-9]+\.d), #65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_65536_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, 65536), + z0 = svadd_x (p0, z0, 65536)) + +/* +** add_m1_s64_x: +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_s64_x: +** sub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_s64_x: +** sub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_s64_x: +** sub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_s64_x: +** sub z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (add_m256_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m511_s64_x: +** mov (z[0-9]+\.d), #-511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m511_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -511), + z0 = svadd_x (p0, z0, -511)) + +/* +** add_m512_s64_x: +** sub z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (add_m512_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_s64_x: +** sub z0\.d, z0\.d, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) + +/* +** add_m65280_s64_x: +** sub z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m65280_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -0xff00), + z0 = svadd_x (p0, z0, -0xff00)) + +/* +** add_m65535_s64_x: +** mov (z[0-9]+\.d), #-65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m65535_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -65535), + z0 = svadd_x (p0, z0, -65535)) + +/* +** add_m65536_s64_x: +** mov (z[0-9]+\.d), #-65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m65536_s64_x, svint64_t, + z0 = svadd_n_s64_x (p0, z0, -65536), + z0 = svadd_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c new file mode 100644 index 00000000000..0889c189d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_s8_m_tied1: +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_s8_m_tied1, svint8_t, + z0 = svadd_s8_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (add_s8_m_tied2, svint8_t, + z0 = svadd_s8_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_s8_m_untied: +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (add_s8_m_untied, svint8_t, + z0 = svadd_s8_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svadd_n_s8_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_m_untied, svint8_t, int8_t, + z0 = svadd_n_s8_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_m_tied1, svint8_t, + z0 = svadd_n_s8_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_m_untied, svint8_t, + z0 = svadd_n_s8_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m1_s8_m: +** mov (z[0-9]+\.b), #-1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_s8_m, svint8_t, + z0 = svadd_n_s8_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_s8_z_tied1, svint8_t, + z0 = svadd_s8_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_s8_z_tied2, svint8_t, + z0 = svadd_s8_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (add_s8_z_untied, svint8_t, + z0 = svadd_s8_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svadd_n_s8_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_z_untied, svint8_t, int8_t, + z0 = svadd_n_s8_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_z_tied1, svint8_t, + z0 = svadd_n_s8_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_z_untied, svint8_t, + z0 = svadd_n_s8_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_s8_x_tied1: +** add z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (add_s8_x_tied1, svint8_t, + z0 = svadd_s8_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_s8_x_tied2: +** add z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (add_s8_x_tied2, svint8_t, + z0 = svadd_s8_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_s8_x_untied: +** add z0\.b, (z1\.b, z2\.b|z2\.b, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (add_s8_x_untied, svint8_t, + z0 = svadd_s8_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** add z0\.b, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svadd_n_s8_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_s8_x_untied: +** mov (z[0-9]+\.b), w0 +** add z0\.b, (z1\.b, \1|\1, z1\.b) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_s8_x_untied, svint8_t, int8_t, + z0 = svadd_n_s8_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_s8_x_tied1: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_x_tied1, svint8_t, + z0 = svadd_n_s8_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_s8_x_untied: +** movprfx z0, z1 +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_s8_x_untied, svint8_t, + z0 = svadd_n_s8_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_s8_x: +** add z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_s8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_s8_x: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_m1_s8_x: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m1_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_s8_x: +** add z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (add_m127_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_s8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_s8_x, svint8_t, + z0 = svadd_n_s8_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c new file mode 100644 index 00000000000..25cb90353d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c @@ -0,0 +1,377 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_u16_m_tied1: +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_u16_m_tied1, svuint16_t, + z0 = svadd_u16_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (add_u16_m_tied2, svuint16_t, + z0 = svadd_u16_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_u16_m_untied: +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (add_u16_m_untied, svuint16_t, + z0 = svadd_u16_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svadd_n_u16_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svadd_n_u16_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_m_tied1, svuint16_t, + z0 = svadd_n_u16_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_m_untied, svuint16_t, + z0 = svadd_n_u16_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_u16_m: +** mov (z[0-9]+\.h), #-2 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_u16_m, svuint16_t, + z0 = svadd_n_u16_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_u16_z_tied1, svuint16_t, + z0 = svadd_u16_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (add_u16_z_tied2, svuint16_t, + z0 = svadd_u16_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_u16_z_untied, svuint16_t, + z0 = svadd_u16_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svadd_n_u16_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svadd_n_u16_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_z_tied1, svuint16_t, + z0 = svadd_n_u16_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_z_untied, svuint16_t, + z0 = svadd_n_u16_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_u16_x_tied1: +** add z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_u16_x_tied1, svuint16_t, + z0 = svadd_u16_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_u16_x_tied2: +** add z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_u16_x_tied2, svuint16_t, + z0 = svadd_u16_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_u16_x_untied: +** add z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (add_u16_x_untied, svuint16_t, + z0 = svadd_u16_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svadd_n_u16_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_u16_x_untied: +** mov (z[0-9]+\.h), w0 +** add z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svadd_n_u16_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_u16_x_tied1: +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_x_tied1, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_u16_x_untied: +** movprfx z0, z1 +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u16_x_untied, svuint16_t, + z0 = svadd_n_u16_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_u16_x: +** add z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_u16_x: +** add z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_u16_x: +** add z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_u16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_257_u16_x: +** mov (z[0-9]+)\.b, #1 +** add z0\.h, (z0\.h, \1\.h|\1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_257_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 257), + z0 = svadd_x (p0, z0, 257)) + +/* +** add_512_u16_x: +** add z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_u16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_m1_u16_x: +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_u16_x: +** sub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_u16_x: +** sub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_u16_x: +** sub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_u16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m256_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m257_u16_x: +** mov (z[0-9]+\.h), #-257 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (add_m257_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -257), + z0 = svadd_x (p0, z0, -257)) + +/* +** add_m512_u16_x: +** add z0\.h, z0\.h, #65024 +** ret +*/ +TEST_UNIFORM_Z (add_m512_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_u16_x: +** add z0\.h, z0\.h, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_u16_x, svuint16_t, + z0 = svadd_n_u16_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u32.c new file mode 100644 index 00000000000..ee979489b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u32.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_u32_m_tied1: +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_u32_m_tied1, svuint32_t, + z0 = svadd_u32_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (add_u32_m_tied2, svuint32_t, + z0 = svadd_u32_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_u32_m_untied: +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (add_u32_m_untied, svuint32_t, + z0 = svadd_u32_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svadd_n_u32_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svadd_n_u32_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_m_tied1, svuint32_t, + z0 = svadd_n_u32_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_m_untied, svuint32_t, + z0 = svadd_n_u32_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_u32_m: +** mov (z[0-9]+\.s), #-2 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_u32_m, svuint32_t, + z0 = svadd_n_u32_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_u32_z_tied1, svuint32_t, + z0 = svadd_u32_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (add_u32_z_tied2, svuint32_t, + z0 = svadd_u32_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_u32_z_untied, svuint32_t, + z0 = svadd_u32_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svadd_n_u32_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svadd_n_u32_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_z_tied1, svuint32_t, + z0 = svadd_n_u32_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_z_untied, svuint32_t, + z0 = svadd_n_u32_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_u32_x_tied1: +** add z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_u32_x_tied1, svuint32_t, + z0 = svadd_u32_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_u32_x_tied2: +** add z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_u32_x_tied2, svuint32_t, + z0 = svadd_u32_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_u32_x_untied: +** add z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (add_u32_x_untied, svuint32_t, + z0 = svadd_u32_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svadd_n_u32_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_u32_x_untied: +** mov (z[0-9]+\.s), w0 +** add z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svadd_n_u32_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_u32_x_tied1: +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_x_tied1, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_u32_x_untied: +** movprfx z0, z1 +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u32_x_untied, svuint32_t, + z0 = svadd_n_u32_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_u32_x: +** add z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_u32_x: +** add z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_u32_x: +** add z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_u32_x: +** add z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_511_u32_x: +** mov (z[0-9]+\.s), #511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_511_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 511), + z0 = svadd_x (p0, z0, 511)) + +/* +** add_512_u32_x: +** add z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_u32_x: +** add z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_65535_u32_x: +** mov (z[0-9]+\.s), #65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_65535_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 65535), + z0 = svadd_x (p0, z0, 65535)) + +/* +** add_65536_u32_x: +** mov (z[0-9]+\.s), #65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_65536_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, 65536), + z0 = svadd_x (p0, z0, 65536)) + +/* +** add_m1_u32_x: +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_u32_x: +** sub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_u32_x: +** sub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_u32_x: +** sub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_u32_x: +** sub z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (add_m256_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m511_u32_x: +** mov (z[0-9]+\.s), #-511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m511_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -511), + z0 = svadd_x (p0, z0, -511)) + +/* +** add_m512_u32_x: +** sub z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (add_m512_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_u32_x: +** sub z0\.s, z0\.s, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) + +/* +** add_m65280_u32_x: +** sub z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m65280_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -0xff00), + z0 = svadd_x (p0, z0, -0xff00)) + +/* +** add_m65535_u32_x: +** mov (z[0-9]+\.s), #-65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m65535_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -65535), + z0 = svadd_x (p0, z0, -65535)) + +/* +** add_m65536_u32_x: +** mov (z[0-9]+\.s), #-65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (add_m65536_u32_x, svuint32_t, + z0 = svadd_n_u32_x (p0, z0, -65536), + z0 = svadd_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u64.c new file mode 100644 index 00000000000..25d2972a695 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u64.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_u64_m_tied1: +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_u64_m_tied1, svuint64_t, + z0 = svadd_u64_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_u64_m_tied2, svuint64_t, + z0 = svadd_u64_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_u64_m_untied: +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (add_u64_m_untied, svuint64_t, + z0 = svadd_u64_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svadd_n_u64_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svadd_n_u64_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_m_tied1, svuint64_t, + z0 = svadd_n_u64_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_m_untied, svuint64_t, + z0 = svadd_n_u64_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m2_u64_m: +** mov (z[0-9]+\.d), #-2 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m2_u64_m, svuint64_t, + z0 = svadd_n_u64_m (p0, z0, -2), + z0 = svadd_m (p0, z0, -2)) + +/* +** add_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_u64_z_tied1, svuint64_t, + z0 = svadd_u64_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (add_u64_z_tied2, svuint64_t, + z0 = svadd_u64_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_u64_z_untied, svuint64_t, + z0 = svadd_u64_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svadd_n_u64_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svadd_n_u64_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_z_tied1, svuint64_t, + z0 = svadd_n_u64_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_z_untied, svuint64_t, + z0 = svadd_n_u64_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_u64_x_tied1: +** add z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_u64_x_tied1, svuint64_t, + z0 = svadd_u64_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_u64_x_tied2: +** add z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_u64_x_tied2, svuint64_t, + z0 = svadd_u64_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_u64_x_untied: +** add z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (add_u64_x_untied, svuint64_t, + z0 = svadd_u64_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svadd_n_u64_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** add z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (add_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svadd_n_u64_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_u64_x_tied1: +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_x_tied1, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_u64_x_untied: +** movprfx z0, z1 +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u64_x_untied, svuint64_t, + z0 = svadd_n_u64_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_u64_x: +** add z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_u64_x: +** add z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_u64_x: +** add z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_256_u64_x: +** add z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (add_256_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 256), + z0 = svadd_x (p0, z0, 256)) + +/* +** add_511_u64_x: +** mov (z[0-9]+\.d), #511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_511_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 511), + z0 = svadd_x (p0, z0, 511)) + +/* +** add_512_u64_x: +** add z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (add_512_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 512), + z0 = svadd_x (p0, z0, 512)) + +/* +** add_65280_u64_x: +** add z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_65280_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 0xff00), + z0 = svadd_x (p0, z0, 0xff00)) + +/* +** add_65535_u64_x: +** mov (z[0-9]+\.d), #65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_65535_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 65535), + z0 = svadd_x (p0, z0, 65535)) + +/* +** add_65536_u64_x: +** mov (z[0-9]+\.d), #65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_65536_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, 65536), + z0 = svadd_x (p0, z0, 65536)) + +/* +** add_m1_u64_x: +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_u64_x: +** sub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (add_m127_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_u64_x: +** sub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) + +/* +** add_m255_u64_x: +** sub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m255_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -255), + z0 = svadd_x (p0, z0, -255)) + +/* +** add_m256_u64_x: +** sub z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (add_m256_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -256), + z0 = svadd_x (p0, z0, -256)) + +/* +** add_m511_u64_x: +** mov (z[0-9]+\.d), #-511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m511_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -511), + z0 = svadd_x (p0, z0, -511)) + +/* +** add_m512_u64_x: +** sub z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (add_m512_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -512), + z0 = svadd_x (p0, z0, -512)) + +/* +** add_m32768_u64_x: +** sub z0\.d, z0\.d, #32768 +** ret +*/ +TEST_UNIFORM_Z (add_m32768_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -0x8000), + z0 = svadd_x (p0, z0, -0x8000)) + +/* +** add_m65280_u64_x: +** sub z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (add_m65280_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -0xff00), + z0 = svadd_x (p0, z0, -0xff00)) + +/* +** add_m65535_u64_x: +** mov (z[0-9]+\.d), #-65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m65535_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -65535), + z0 = svadd_x (p0, z0, -65535)) + +/* +** add_m65536_u64_x: +** mov (z[0-9]+\.d), #-65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (add_m65536_u64_x, svuint64_t, + z0 = svadd_n_u64_x (p0, z0, -65536), + z0 = svadd_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c new file mode 100644 index 00000000000..06b68c97ce8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** add_u8_m_tied1: +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_u8_m_tied1, svuint8_t, + z0 = svadd_u8_m (p0, z0, z1), + z0 = svadd_m (p0, z0, z1)) + +/* +** add_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (add_u8_m_tied2, svuint8_t, + z0 = svadd_u8_m (p0, z1, z0), + z0 = svadd_m (p0, z1, z0)) + +/* +** add_u8_m_untied: +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (add_u8_m_untied, svuint8_t, + z0 = svadd_u8_m (p0, z1, z2), + z0 = svadd_m (p0, z1, z2)) + +/* +** add_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svadd_n_u8_m (p0, z0, x0), + z0 = svadd_m (p0, z0, x0)) + +/* +** add_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svadd_n_u8_m (p0, z1, x0), + z0 = svadd_m (p0, z1, x0)) + +/* +** add_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_m_tied1, svuint8_t, + z0 = svadd_n_u8_m (p0, z0, 1), + z0 = svadd_m (p0, z0, 1)) + +/* +** add_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_m_untied, svuint8_t, + z0 = svadd_n_u8_m (p0, z1, 1), + z0 = svadd_m (p0, z1, 1)) + +/* +** add_m1_u8_m: +** mov (z[0-9]+\.b), #-1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_m1_u8_m, svuint8_t, + z0 = svadd_n_u8_m (p0, z0, -1), + z0 = svadd_m (p0, z0, -1)) + +/* +** add_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_u8_z_tied1, svuint8_t, + z0 = svadd_u8_z (p0, z0, z1), + z0 = svadd_z (p0, z0, z1)) + +/* +** add_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (add_u8_z_tied2, svuint8_t, + z0 = svadd_u8_z (p0, z1, z0), + z0 = svadd_z (p0, z1, z0)) + +/* +** add_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (add_u8_z_untied, svuint8_t, + z0 = svadd_u8_z (p0, z1, z2), + z0 = svadd_z (p0, z1, z2)) + +/* +** add_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svadd_n_u8_z (p0, z0, x0), + z0 = svadd_z (p0, z0, x0)) + +/* +** add_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svadd_n_u8_z (p0, z1, x0), + z0 = svadd_z (p0, z1, x0)) + +/* +** add_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_z_tied1, svuint8_t, + z0 = svadd_n_u8_z (p0, z0, 1), + z0 = svadd_z (p0, z0, 1)) + +/* +** add_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_z_untied, svuint8_t, + z0 = svadd_n_u8_z (p0, z1, 1), + z0 = svadd_z (p0, z1, 1)) + +/* +** add_u8_x_tied1: +** add z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (add_u8_x_tied1, svuint8_t, + z0 = svadd_u8_x (p0, z0, z1), + z0 = svadd_x (p0, z0, z1)) + +/* +** add_u8_x_tied2: +** add z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (add_u8_x_tied2, svuint8_t, + z0 = svadd_u8_x (p0, z1, z0), + z0 = svadd_x (p0, z1, z0)) + +/* +** add_u8_x_untied: +** add z0\.b, (z1\.b, z2\.b|z2\.b, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (add_u8_x_untied, svuint8_t, + z0 = svadd_u8_x (p0, z1, z2), + z0 = svadd_x (p0, z1, z2)) + +/* +** add_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** add z0\.b, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svadd_n_u8_x (p0, z0, x0), + z0 = svadd_x (p0, z0, x0)) + +/* +** add_w0_u8_x_untied: +** mov (z[0-9]+\.b), w0 +** add z0\.b, (z1\.b, \1|\1, z1\.b) +** ret +*/ +TEST_UNIFORM_ZX (add_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svadd_n_u8_x (p0, z1, x0), + z0 = svadd_x (p0, z1, x0)) + +/* +** add_1_u8_x_tied1: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_x_tied1, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, 1), + z0 = svadd_x (p0, z0, 1)) + +/* +** add_1_u8_x_untied: +** movprfx z0, z1 +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (add_1_u8_x_untied, svuint8_t, + z0 = svadd_n_u8_x (p0, z1, 1), + z0 = svadd_x (p0, z1, 1)) + +/* +** add_127_u8_x: +** add z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (add_127_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, 127), + z0 = svadd_x (p0, z0, 127)) + +/* +** add_128_u8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (add_128_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, 128), + z0 = svadd_x (p0, z0, 128)) + +/* +** add_255_u8_x: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (add_255_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, 255), + z0 = svadd_x (p0, z0, 255)) + +/* +** add_m1_u8_x: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (add_m1_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, -1), + z0 = svadd_x (p0, z0, -1)) + +/* +** add_m127_u8_x: +** add z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (add_m127_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, -127), + z0 = svadd_x (p0, z0, -127)) + +/* +** add_m128_u8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (add_m128_u8_x, svuint8_t, + z0 = svadd_n_u8_x (p0, z0, -128), + z0 = svadd_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c new file mode 100644 index 00000000000..6c6bfa1c294 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adda_d0_f16: +** fadda h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (adda_d0_f16, float16_t, svfloat16_t, + d0 = svadda_f16 (p0, d0, z2), + d0 = svadda (p0, d0, z2)) + +/* +** adda_d1_f16: +** mov v0\.h\[0\], v1\.h\[0\] +** fadda h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (adda_d1_f16, float16_t, svfloat16_t, + d0 = svadda_f16 (p0, d1, z2), + d0 = svadda (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c new file mode 100644 index 00000000000..8b2a1dd1c68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f32.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adda_d0_f32: +** fadda s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (adda_d0_f32, float32_t, svfloat32_t, + d0 = svadda_f32 (p0, d0, z2), + d0 = svadda (p0, d0, z2)) + +/* +** adda_d1_f32: +** fmov s0, s1 +** fadda s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (adda_d1_f32, float32_t, svfloat32_t, + d0 = svadda_f32 (p0, d1, z2), + d0 = svadda (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c new file mode 100644 index 00000000000..90a56420a6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adda_f64.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adda_d0_f64: +** fadda d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (adda_d0_f64, float64_t, svfloat64_t, + d0 = svadda_f64 (p0, d0, z2), + d0 = svadda (p0, d0, z2)) + +/* +** adda_d1_f64: +** fmov d0, d1 +** fadda d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (adda_d1_f64, float64_t, svfloat64_t, + d0 = svadda_f64 (p0, d1, z2), + d0 = svadda (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f16.c new file mode 100644 index 00000000000..7bb0c1de474 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_d0_f16_tied: +** faddv h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (addv_d0_f16_tied, float16_t, svfloat16_t, + d0 = svaddv_f16 (p0, z0), + d0 = svaddv (p0, z0)) + +/* +** addv_d0_f16_untied: +** faddv h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (addv_d0_f16_untied, float16_t, svfloat16_t, + d0 = svaddv_f16 (p0, z1), + d0 = svaddv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f32.c new file mode 100644 index 00000000000..51c6219107b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_d0_f32_tied: +** faddv s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (addv_d0_f32_tied, float32_t, svfloat32_t, + d0 = svaddv_f32 (p0, z0), + d0 = svaddv (p0, z0)) + +/* +** addv_d0_f32_untied: +** faddv s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (addv_d0_f32_untied, float32_t, svfloat32_t, + d0 = svaddv_f32 (p0, z1), + d0 = svaddv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f64.c new file mode 100644 index 00000000000..882866210c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_d0_f64_tied: +** faddv d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (addv_d0_f64_tied, float64_t, svfloat64_t, + d0 = svaddv_f64 (p0, z0), + d0 = svaddv (p0, z0)) + +/* +** addv_d0_f64_untied: +** faddv d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (addv_d0_f64_untied, float64_t, svfloat64_t, + d0 = svaddv_f64 (p0, z1), + d0 = svaddv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s16.c new file mode 100644 index 00000000000..05429a47e91 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_s16: +** saddv (d[0-9]+), p0, z0\.h +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_s16, int64_t, svint16_t, + x0 = svaddv_s16 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s32.c new file mode 100644 index 00000000000..5f7789a9aeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_s32: +** saddv (d[0-9]+), p0, z0\.s +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_s32, int64_t, svint32_t, + x0 = svaddv_s32 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s64.c new file mode 100644 index 00000000000..76c48009187 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_s64: +** uaddv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_s64, int64_t, svint64_t, + x0 = svaddv_s64 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s8.c new file mode 100644 index 00000000000..8ccb2bf4f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_s8: +** saddv (d[0-9]+), p0, z0\.b +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_s8, int64_t, svint8_t, + x0 = svaddv_s8 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u16.c new file mode 100644 index 00000000000..6371921fe0c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_u16: +** uaddv (d[0-9]+), p0, z0\.h +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_u16, uint64_t, svuint16_t, + x0 = svaddv_u16 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u32.c new file mode 100644 index 00000000000..bdd0ed1f920 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_u32: +** uaddv (d[0-9]+), p0, z0\.s +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_u32, uint64_t, svuint32_t, + x0 = svaddv_u32 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u64.c new file mode 100644 index 00000000000..7b1995d3f9d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_u64: +** uaddv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_u64, uint64_t, svuint64_t, + x0 = svaddv_u64 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u8.c new file mode 100644 index 00000000000..0e972f09306 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/addv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** addv_x0_u8: +** uaddv (d[0-9]+), p0, z0\.b +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (addv_x0_u8, uint64_t, svuint8_t, + x0 = svaddv_u8 (p0, z0), + x0 = svaddv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrb.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrb.c new file mode 100644 index 00000000000..a61eec9712e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrb.c @@ -0,0 +1,57 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adrb_u32base_s32offset: +** adr z0\.s, \[z0\.s, z1\.s\] +** ret +*/ +TEST_ADR (adrb_u32base_s32offset, svuint32_t, svint32_t, + z0 = svadrb_u32base_s32offset (z0, z1), + z0 = svadrb_offset (z0, z1)) + +/* +** adrb_u32base_u32offset: +** adr z0\.s, \[z0\.s, z1\.s\] +** ret +*/ +TEST_ADR (adrb_u32base_u32offset, svuint32_t, svuint32_t, + z0 = svadrb_u32base_u32offset (z0, z1), + z0 = svadrb_offset (z0, z1)) + +/* +** adrb_u64base_s64offset: +** adr z0\.d, \[z0\.d, z1\.d\] +** ret +*/ +TEST_ADR (adrb_u64base_s64offset, svuint64_t, svint64_t, + z0 = svadrb_u64base_s64offset (z0, z1), + z0 = svadrb_offset (z0, z1)) + +/* +** adrb_ext_u64base_s64offset: +** adr z0\.d, \[z0\.d, z1\.d, sxtw\] +** ret +*/ +TEST_ADR (adrb_ext_u64base_s64offset, svuint64_t, svint64_t, + z0 = svadrb_u64base_s64offset (z0, svextw_s64_x (svptrue_b64 (), z1)), + z0 = svadrb_offset (z0, svextw_x (svptrue_b64 (), z1))) + +/* +** adrb_u64base_u64offset: +** adr z0\.d, \[z0\.d, z1\.d\] +** ret +*/ +TEST_ADR (adrb_u64base_u64offset, svuint64_t, svuint64_t, + z0 = svadrb_u64base_u64offset (z0, z1), + z0 = svadrb_offset (z0, z1)) + +/* +** adrb_ext_u64base_u64offset: +** adr z0\.d, \[z0\.d, z1\.d, uxtw\] +** ret +*/ +TEST_ADR (adrb_ext_u64base_u64offset, svuint64_t, svuint64_t, + z0 = svadrb_u64base_u64offset (z0, svextw_u64_x (svptrue_b64 (), z1)), + z0 = svadrb_offset (z0, svextw_x (svptrue_b64 (), z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrd.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrd.c new file mode 100644 index 00000000000..970485bd67d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrd.c @@ -0,0 +1,57 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adrd_u32base_s32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 3\] +** ret +*/ +TEST_ADR (adrd_u32base_s32index, svuint32_t, svint32_t, + z0 = svadrd_u32base_s32index (z0, z1), + z0 = svadrd_index (z0, z1)) + +/* +** adrd_u32base_u32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 3\] +** ret +*/ +TEST_ADR (adrd_u32base_u32index, svuint32_t, svuint32_t, + z0 = svadrd_u32base_u32index (z0, z1), + z0 = svadrd_index (z0, z1)) + +/* +** adrd_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 3\] +** ret +*/ +TEST_ADR (adrd_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrd_u64base_s64index (z0, z1), + z0 = svadrd_index (z0, z1)) + +/* +** adrd_ext_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, sxtw 3\] +** ret +*/ +TEST_ADR (adrd_ext_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrd_u64base_s64index (z0, svextw_s64_x (svptrue_b64 (), z1)), + z0 = svadrd_index (z0, svextw_x (svptrue_b64 (), z1))) + +/* +** adrd_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 3\] +** ret +*/ +TEST_ADR (adrd_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrd_u64base_u64index (z0, z1), + z0 = svadrd_index (z0, z1)) + +/* +** adrd_ext_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, uxtw 3\] +** ret +*/ +TEST_ADR (adrd_ext_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrd_u64base_u64index (z0, svextw_u64_x (svptrue_b64 (), z1)), + z0 = svadrd_index (z0, svextw_x (svptrue_b64 (), z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrh.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrh.c new file mode 100644 index 00000000000..d06f51fe35b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrh.c @@ -0,0 +1,57 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adrh_u32base_s32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 1\] +** ret +*/ +TEST_ADR (adrh_u32base_s32index, svuint32_t, svint32_t, + z0 = svadrh_u32base_s32index (z0, z1), + z0 = svadrh_index (z0, z1)) + +/* +** adrh_u32base_u32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 1\] +** ret +*/ +TEST_ADR (adrh_u32base_u32index, svuint32_t, svuint32_t, + z0 = svadrh_u32base_u32index (z0, z1), + z0 = svadrh_index (z0, z1)) + +/* +** adrh_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 1\] +** ret +*/ +TEST_ADR (adrh_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrh_u64base_s64index (z0, z1), + z0 = svadrh_index (z0, z1)) + +/* +** adrh_ext_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, sxtw 1\] +** ret +*/ +TEST_ADR (adrh_ext_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrh_u64base_s64index (z0, svextw_s64_x (svptrue_b64 (), z1)), + z0 = svadrh_index (z0, svextw_x (svptrue_b64 (), z1))) + +/* +** adrh_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 1\] +** ret +*/ +TEST_ADR (adrh_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrh_u64base_u64index (z0, z1), + z0 = svadrh_index (z0, z1)) + +/* +** adrh_ext_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, uxtw 1\] +** ret +*/ +TEST_ADR (adrh_ext_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrh_u64base_u64index (z0, svextw_u64_x (svptrue_b64 (), z1)), + z0 = svadrh_index (z0, svextw_x (svptrue_b64 (), z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrw.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrw.c new file mode 100644 index 00000000000..b23f25a1125 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/adrw.c @@ -0,0 +1,57 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** adrw_u32base_s32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 2\] +** ret +*/ +TEST_ADR (adrw_u32base_s32index, svuint32_t, svint32_t, + z0 = svadrw_u32base_s32index (z0, z1), + z0 = svadrw_index (z0, z1)) + +/* +** adrw_u32base_u32index: +** adr z0\.s, \[z0\.s, z1\.s, lsl 2\] +** ret +*/ +TEST_ADR (adrw_u32base_u32index, svuint32_t, svuint32_t, + z0 = svadrw_u32base_u32index (z0, z1), + z0 = svadrw_index (z0, z1)) + +/* +** adrw_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 2\] +** ret +*/ +TEST_ADR (adrw_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrw_u64base_s64index (z0, z1), + z0 = svadrw_index (z0, z1)) + +/* +** adrw_ext_u64base_s64index: +** adr z0\.d, \[z0\.d, z1\.d, sxtw 2\] +** ret +*/ +TEST_ADR (adrw_ext_u64base_s64index, svuint64_t, svint64_t, + z0 = svadrw_u64base_s64index (z0, svextw_s64_x (svptrue_b64 (), z1)), + z0 = svadrw_index (z0, svextw_x (svptrue_b64 (), z1))) + +/* +** adrw_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, lsl 2\] +** ret +*/ +TEST_ADR (adrw_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrw_u64base_u64index (z0, z1), + z0 = svadrw_index (z0, z1)) + +/* +** adrw_ext_u64base_u64index: +** adr z0\.d, \[z0\.d, z1\.d, uxtw 2\] +** ret +*/ +TEST_ADR (adrw_ext_u64base_u64index, svuint64_t, svuint64_t, + z0 = svadrw_u64base_u64index (z0, svextw_u64_x (svptrue_b64 (), z1)), + z0 = svadrw_index (z0, svextw_x (svptrue_b64 (), z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_b.c new file mode 100644 index 00000000000..f0c4ff1b159 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_b_z_tied1: +** and p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (and_b_z_tied1, + p0 = svand_b_z (p3, p0, p1), + p0 = svand_z (p3, p0, p1)) + +/* +** and_b_z_tied2: +** and p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (and_b_z_tied2, + p0 = svand_b_z (p3, p1, p0), + p0 = svand_z (p3, p1, p0)) + +/* +** and_b_z_untied: +** and p0\.b, p3/z, (p1\.b, p2\.b|p2\.b, p1\.b) +** ret +*/ +TEST_UNIFORM_P (and_b_z_untied, + p0 = svand_b_z (p3, p1, p2), + p0 = svand_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c new file mode 100644 index 00000000000..d54613e915d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c @@ -0,0 +1,422 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_s16_m_tied1: +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_s16_m_tied1, svint16_t, + z0 = svand_s16_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (and_s16_m_tied2, svint16_t, + z0 = svand_s16_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_s16_m_untied: +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (and_s16_m_untied, svint16_t, + z0 = svand_s16_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svand_n_s16_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_m_untied, svint16_t, int16_t, + z0 = svand_n_s16_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_m_tied1, svint16_t, + z0 = svand_n_s16_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_m_untied, svint16_t, + z0 = svand_n_s16_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_s16_m: +** mov (z[0-9]+\.h), #-2 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_s16_m, svint16_t, + z0 = svand_n_s16_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_s16_m_tied1: +** uxtb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_s16_m_tied1, svint16_t, + z0 = svand_n_s16_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_s16_m_untied: +** movprfx z0, z1 +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_s16_m_untied, svint16_t, + z0 = svand_n_s16_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_s16_z_tied1, svint16_t, + z0 = svand_s16_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_s16_z_tied2, svint16_t, + z0 = svand_s16_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (and_s16_z_untied, svint16_t, + z0 = svand_s16_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svand_n_s16_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_z_untied, svint16_t, int16_t, + z0 = svand_n_s16_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_z_tied1, svint16_t, + z0 = svand_n_s16_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_z_untied, svint16_t, + z0 = svand_n_s16_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_s16_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** uxtb z0\.h, p0/m, \1\.h +** | +** mov (z[0-9]+\.h), #255 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_s16_z_tied1, svint16_t, + z0 = svand_n_s16_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_s16_z_untied, svint16_t, + z0 = svand_n_s16_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_s16_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s16_x_tied1, svint16_t, + z0 = svand_s16_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_s16_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s16_x_tied2, svint16_t, + z0 = svand_s16_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_s16_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s16_x_untied, svint16_t, + z0 = svand_s16_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_s16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svand_n_s16_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_s16_x_untied: +** mov (z[0-9]+)\.h, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s16_x_untied, svint16_t, int16_t, + z0 = svand_n_s16_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_s16_x_tied1: +** and z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_x_tied1, svint16_t, + z0 = svand_n_s16_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_s16_x_untied: +** movprfx z0, z1 +** and z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s16_x_untied, svint16_t, + z0 = svand_n_s16_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_s16_x: +** and z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_s16_x: +** and z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_s16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_s16_x: +** and z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* +** and_257_s16_x: +** and z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (and_257_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_s16_x: +** and z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_s16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_s16_x: +** and z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_s16_x: +** and z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_s16_x: +** and z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_s16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_s16_x: +** and z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_s16_x: +** and z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_s16_x: +** and z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_s16_x: +** mov (z[0-9]+)\.h, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_s16_x, svint16_t, + z0 = svand_n_s16_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s32.c new file mode 100644 index 00000000000..7f4082b327b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s32.c @@ -0,0 +1,464 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_s32_m_tied1: +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_s32_m_tied1, svint32_t, + z0 = svand_s32_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (and_s32_m_tied2, svint32_t, + z0 = svand_s32_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_s32_m_untied: +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (and_s32_m_untied, svint32_t, + z0 = svand_s32_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svand_n_s32_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_m_untied, svint32_t, int32_t, + z0 = svand_n_s32_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_m_tied1, svint32_t, + z0 = svand_n_s32_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_m_untied, svint32_t, + z0 = svand_n_s32_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_s32_m: +** mov (z[0-9]+\.s), #-2 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_s32_m, svint32_t, + z0 = svand_n_s32_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_s32_m_tied1: +** uxtb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_s32_m_tied1, svint32_t, + z0 = svand_n_s32_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_s32_m_untied: +** movprfx z0, z1 +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_s32_m_untied, svint32_t, + z0 = svand_n_s32_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_65535_s32_m_tied1: +** uxth z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_s32_m_tied1, svint32_t, + z0 = svand_n_s32_m (p0, z0, 65535), + z0 = svand_m (p0, z0, 65535)) + +/* +** and_65535_s32_m_untied: +** movprfx z0, z1 +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_s32_m_untied, svint32_t, + z0 = svand_n_s32_m (p0, z1, 65535), + z0 = svand_m (p0, z1, 65535)) + +/* +** and_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_s32_z_tied1, svint32_t, + z0 = svand_s32_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_s32_z_tied2, svint32_t, + z0 = svand_s32_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (and_s32_z_untied, svint32_t, + z0 = svand_s32_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svand_n_s32_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_z_untied, svint32_t, int32_t, + z0 = svand_n_s32_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_z_tied1, svint32_t, + z0 = svand_n_s32_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_z_untied, svint32_t, + z0 = svand_n_s32_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_s32_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxtb z0\.s, p0/m, \1\.s +** | +** mov (z[0-9]+\.s), #255 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_s32_z_tied1, svint32_t, + z0 = svand_n_s32_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_s32_z_untied, svint32_t, + z0 = svand_n_s32_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_65535_s32_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxth z0\.s, p0/m, \1\.s +** | +** mov (z[0-9]+\.s), #65535 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_65535_s32_z_tied1, svint32_t, + z0 = svand_n_s32_z (p0, z0, 65535), + z0 = svand_z (p0, z0, 65535)) + +/* +** and_65535_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_s32_z_untied, svint32_t, + z0 = svand_n_s32_z (p0, z1, 65535), + z0 = svand_z (p0, z1, 65535)) + +/* +** and_s32_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s32_x_tied1, svint32_t, + z0 = svand_s32_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_s32_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s32_x_tied2, svint32_t, + z0 = svand_s32_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_s32_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s32_x_untied, svint32_t, + z0 = svand_s32_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_s32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svand_n_s32_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_s32_x_untied: +** mov (z[0-9]+)\.s, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s32_x_untied, svint32_t, int32_t, + z0 = svand_n_s32_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_s32_x_tied1: +** and z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_x_tied1, svint32_t, + z0 = svand_n_s32_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_s32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s32_x_untied, svint32_t, + z0 = svand_n_s32_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_s32_x: +** and z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_s32_x: +** and z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_s32_x: +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_s32_x: +** and z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (and_257_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_s32_x: +** and z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_s32_x: +** and z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_s32_x: +** and z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_s32_x: +** and z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_s32_x: +** and z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_s32_x: +** and z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_s32_x: +** and z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_s32_x: +** and z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_s32_x: +** and z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_s32_x: +** mov (z[0-9]+)\.s, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_s32_x, svint32_t, + z0 = svand_n_s32_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s64.c new file mode 100644 index 00000000000..8868258dca6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s64.c @@ -0,0 +1,510 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_s64_m_tied1: +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_s64_m_tied1, svint64_t, + z0 = svand_s64_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_s64_m_tied2, svint64_t, + z0 = svand_s64_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_s64_m_untied: +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (and_s64_m_untied, svint64_t, + z0 = svand_s64_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svand_n_s64_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_m_untied, svint64_t, int64_t, + z0 = svand_n_s64_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_m_tied1, svint64_t, + z0 = svand_n_s64_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_m_untied, svint64_t, + z0 = svand_n_s64_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_s64_m: +** mov (z[0-9]+\.d), #-2 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_s64_m, svint64_t, + z0 = svand_n_s64_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_s64_m_tied1: +** uxtb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_s64_m_tied1, svint64_t, + z0 = svand_n_s64_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_s64_m_untied: +** movprfx z0, z1 +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_s64_m_untied, svint64_t, + z0 = svand_n_s64_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_65535_s64_m_tied1: +** uxth z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_s64_m_tied1, svint64_t, + z0 = svand_n_s64_m (p0, z0, 65535), + z0 = svand_m (p0, z0, 65535)) + +/* +** and_65535_s64_m_untied: +** movprfx z0, z1 +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_s64_m_untied, svint64_t, + z0 = svand_n_s64_m (p0, z1, 65535), + z0 = svand_m (p0, z1, 65535)) + +/* +** and_0xffffffff_s64_m_tied1: +** uxtw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_s64_m_tied1, svint64_t, + z0 = svand_n_s64_m (p0, z0, 0xffffffff), + z0 = svand_m (p0, z0, 0xffffffff)) + +/* +** and_0xffffffff_s64_m_untied: +** movprfx z0, z1 +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_s64_m_untied, svint64_t, + z0 = svand_n_s64_m (p0, z1, 0xffffffff), + z0 = svand_m (p0, z1, 0xffffffff)) + +/* +** and_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_s64_z_tied1, svint64_t, + z0 = svand_s64_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_s64_z_tied2, svint64_t, + z0 = svand_s64_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (and_s64_z_untied, svint64_t, + z0 = svand_s64_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svand_n_s64_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_z_untied, svint64_t, int64_t, + z0 = svand_n_s64_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_z_tied1, svint64_t, + z0 = svand_n_s64_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_z_untied, svint64_t, + z0 = svand_n_s64_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_s64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtb z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #255 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_s64_z_tied1, svint64_t, + z0 = svand_n_s64_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_s64_z_untied, svint64_t, + z0 = svand_n_s64_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_65535_s64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxth z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #65535 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_65535_s64_z_tied1, svint64_t, + z0 = svand_n_s64_z (p0, z0, 65535), + z0 = svand_z (p0, z0, 65535)) + +/* +** and_65535_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_s64_z_untied, svint64_t, + z0 = svand_n_s64_z (p0, z1, 65535), + z0 = svand_z (p0, z1, 65535)) + +/* +** and_0xffffffff_s64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtw z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #4294967295 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_s64_z_tied1, svint64_t, + z0 = svand_n_s64_z (p0, z0, 0xffffffff), + z0 = svand_z (p0, z0, 0xffffffff)) + +/* +** and_0xffffffff_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_s64_z_untied, svint64_t, + z0 = svand_n_s64_z (p0, z1, 0xffffffff), + z0 = svand_z (p0, z1, 0xffffffff)) + +/* +** and_s64_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s64_x_tied1, svint64_t, + z0 = svand_s64_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_s64_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s64_x_tied2, svint64_t, + z0 = svand_s64_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_s64_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s64_x_untied, svint64_t, + z0 = svand_s64_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svand_n_s64_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** and z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_s64_x_untied, svint64_t, int64_t, + z0 = svand_n_s64_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_s64_x_tied1: +** and z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_x_tied1, svint64_t, + z0 = svand_n_s64_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_s64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s64_x_untied, svint64_t, + z0 = svand_n_s64_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_s64_x: +** and z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_s64_x: +** and z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_s64_x: +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_s64_x: +** and z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (and_257_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_s64_x: +** and z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_s64_x: +** and z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_s64_x: +** and z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_s64_x: +** and z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_s64_x: +** and z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_s64_x: +** mov (z[0-9]+\.d), #5 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_s64_x, svint64_t, + z0 = svand_n_s64_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c new file mode 100644 index 00000000000..61d168d3fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_s8_m_tied1: +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_s8_m_tied1, svint8_t, + z0 = svand_s8_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (and_s8_m_tied2, svint8_t, + z0 = svand_s8_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_s8_m_untied: +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (and_s8_m_untied, svint8_t, + z0 = svand_s8_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svand_n_s8_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_m_untied, svint8_t, int8_t, + z0 = svand_n_s8_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_m_tied1, svint8_t, + z0 = svand_n_s8_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_m_untied, svint8_t, + z0 = svand_n_s8_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_s8_m: +** mov (z[0-9]+\.b), #-2 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_s8_m, svint8_t, + z0 = svand_n_s8_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_s8_z_tied1, svint8_t, + z0 = svand_s8_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_s8_z_tied2, svint8_t, + z0 = svand_s8_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (and_s8_z_untied, svint8_t, + z0 = svand_s8_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svand_n_s8_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_z_untied, svint8_t, int8_t, + z0 = svand_n_s8_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_z_tied1, svint8_t, + z0 = svand_n_s8_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_z_untied, svint8_t, + z0 = svand_n_s8_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_s8_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s8_x_tied1, svint8_t, + z0 = svand_s8_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_s8_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s8_x_tied2, svint8_t, + z0 = svand_s8_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_s8_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_s8_x_untied, svint8_t, + z0 = svand_s8_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_s8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svand_n_s8_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_s8_x_untied: +** mov (z[0-9]+)\.b, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_s8_x_untied, svint8_t, int8_t, + z0 = svand_n_s8_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_s8_x_tied1: +** and z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_x_tied1, svint8_t, + z0 = svand_n_s8_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_s8_x_untied: +** movprfx z0, z1 +** and z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_s8_x_untied, svint8_t, + z0 = svand_n_s8_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_s8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_s8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_s8_x: +** ret +*/ +TEST_UNIFORM_Z (and_255_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_m127_s8_x: +** and z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_s8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_5_s8_x: +** mov (z[0-9]+)\.b, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_s8_x, svint8_t, + z0 = svand_n_s8_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c new file mode 100644 index 00000000000..875a08d71d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c @@ -0,0 +1,422 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_u16_m_tied1: +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_u16_m_tied1, svuint16_t, + z0 = svand_u16_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (and_u16_m_tied2, svuint16_t, + z0 = svand_u16_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_u16_m_untied: +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (and_u16_m_untied, svuint16_t, + z0 = svand_u16_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svand_n_u16_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svand_n_u16_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_m_tied1, svuint16_t, + z0 = svand_n_u16_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_m_untied, svuint16_t, + z0 = svand_n_u16_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_u16_m: +** mov (z[0-9]+\.h), #-2 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_u16_m, svuint16_t, + z0 = svand_n_u16_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_u16_m_tied1: +** uxtb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_u16_m_tied1, svuint16_t, + z0 = svand_n_u16_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_u16_m_untied: +** movprfx z0, z1 +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_u16_m_untied, svuint16_t, + z0 = svand_n_u16_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_u16_z_tied1, svuint16_t, + z0 = svand_u16_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_u16_z_tied2, svuint16_t, + z0 = svand_u16_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (and_u16_z_untied, svuint16_t, + z0 = svand_u16_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svand_n_u16_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svand_n_u16_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_z_tied1, svuint16_t, + z0 = svand_n_u16_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_z_untied, svuint16_t, + z0 = svand_n_u16_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_u16_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** uxtb z0\.h, p0/m, \1\.h +** | +** mov (z[0-9]+\.h), #255 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_u16_z_tied1, svuint16_t, + z0 = svand_n_u16_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (and_255_u16_z_untied, svuint16_t, + z0 = svand_n_u16_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_u16_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u16_x_tied1, svuint16_t, + z0 = svand_u16_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_u16_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u16_x_tied2, svuint16_t, + z0 = svand_u16_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_u16_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u16_x_untied, svuint16_t, + z0 = svand_u16_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_u16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svand_n_u16_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_u16_x_untied: +** mov (z[0-9]+)\.h, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svand_n_u16_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_u16_x_tied1: +** and z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_x_tied1, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_u16_x_untied: +** movprfx z0, z1 +** and z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u16_x_untied, svuint16_t, + z0 = svand_n_u16_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_u16_x: +** and z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_u16_x: +** and z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_u16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_u16_x: +** and z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* +** and_257_u16_x: +** and z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (and_257_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_u16_x: +** and z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_u16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_u16_x: +** and z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_u16_x: +** and z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_u16_x: +** and z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_u16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_u16_x: +** and z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_u16_x: +** and z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_u16_x: +** and z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_u16_x: +** mov (z[0-9]+)\.h, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_u16_x, svuint16_t, + z0 = svand_n_u16_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u32.c new file mode 100644 index 00000000000..80ff503963f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u32.c @@ -0,0 +1,464 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_u32_m_tied1: +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_u32_m_tied1, svuint32_t, + z0 = svand_u32_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (and_u32_m_tied2, svuint32_t, + z0 = svand_u32_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_u32_m_untied: +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (and_u32_m_untied, svuint32_t, + z0 = svand_u32_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svand_n_u32_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svand_n_u32_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_m_tied1, svuint32_t, + z0 = svand_n_u32_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_m_untied, svuint32_t, + z0 = svand_n_u32_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_u32_m: +** mov (z[0-9]+\.s), #-2 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_u32_m, svuint32_t, + z0 = svand_n_u32_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_u32_m_tied1: +** uxtb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_u32_m_tied1, svuint32_t, + z0 = svand_n_u32_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_u32_m_untied: +** movprfx z0, z1 +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_u32_m_untied, svuint32_t, + z0 = svand_n_u32_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_65535_u32_m_tied1: +** uxth z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_u32_m_tied1, svuint32_t, + z0 = svand_n_u32_m (p0, z0, 65535), + z0 = svand_m (p0, z0, 65535)) + +/* +** and_65535_u32_m_untied: +** movprfx z0, z1 +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_u32_m_untied, svuint32_t, + z0 = svand_n_u32_m (p0, z1, 65535), + z0 = svand_m (p0, z1, 65535)) + +/* +** and_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_u32_z_tied1, svuint32_t, + z0 = svand_u32_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_u32_z_tied2, svuint32_t, + z0 = svand_u32_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (and_u32_z_untied, svuint32_t, + z0 = svand_u32_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svand_n_u32_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svand_n_u32_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_z_tied1, svuint32_t, + z0 = svand_n_u32_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_z_untied, svuint32_t, + z0 = svand_n_u32_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_u32_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxtb z0\.s, p0/m, \1\.s +** | +** mov (z[0-9]+\.s), #255 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_u32_z_tied1, svuint32_t, + z0 = svand_n_u32_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_255_u32_z_untied, svuint32_t, + z0 = svand_n_u32_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_65535_u32_z_tied1: +** ( +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxth z0\.s, p0/m, \1\.s +** | +** mov (z[0-9]+\.s), #65535 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_65535_u32_z_tied1, svuint32_t, + z0 = svand_n_u32_z (p0, z0, 65535), + z0 = svand_z (p0, z0, 65535)) + +/* +** and_65535_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (and_65535_u32_z_untied, svuint32_t, + z0 = svand_n_u32_z (p0, z1, 65535), + z0 = svand_z (p0, z1, 65535)) + +/* +** and_u32_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u32_x_tied1, svuint32_t, + z0 = svand_u32_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_u32_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u32_x_tied2, svuint32_t, + z0 = svand_u32_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_u32_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u32_x_untied, svuint32_t, + z0 = svand_u32_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_u32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svand_n_u32_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_u32_x_untied: +** mov (z[0-9]+)\.s, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svand_n_u32_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_u32_x_tied1: +** and z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_x_tied1, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_u32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u32_x_untied, svuint32_t, + z0 = svand_n_u32_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_u32_x: +** and z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_u32_x: +** and z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_u32_x: +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_u32_x: +** and z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (and_257_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_u32_x: +** and z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_u32_x: +** and z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_u32_x: +** and z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_u32_x: +** and z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_u32_x: +** and z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_u32_x: +** and z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_u32_x: +** and z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_u32_x: +** and z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_u32_x: +** and z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_u32_x: +** mov (z[0-9]+)\.s, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_u32_x, svuint32_t, + z0 = svand_n_u32_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u64.c new file mode 100644 index 00000000000..906b19c3735 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u64.c @@ -0,0 +1,510 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_u64_m_tied1: +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_u64_m_tied1, svuint64_t, + z0 = svand_u64_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_u64_m_tied2, svuint64_t, + z0 = svand_u64_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_u64_m_untied: +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (and_u64_m_untied, svuint64_t, + z0 = svand_u64_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svand_n_u64_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svand_n_u64_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_m_tied1, svuint64_t, + z0 = svand_n_u64_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_m_untied, svuint64_t, + z0 = svand_n_u64_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_u64_m: +** mov (z[0-9]+\.d), #-2 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_u64_m, svuint64_t, + z0 = svand_n_u64_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_255_u64_m_tied1: +** uxtb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_u64_m_tied1, svuint64_t, + z0 = svand_n_u64_m (p0, z0, 255), + z0 = svand_m (p0, z0, 255)) + +/* +** and_255_u64_m_untied: +** movprfx z0, z1 +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_u64_m_untied, svuint64_t, + z0 = svand_n_u64_m (p0, z1, 255), + z0 = svand_m (p0, z1, 255)) + +/* +** and_65535_u64_m_tied1: +** uxth z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_u64_m_tied1, svuint64_t, + z0 = svand_n_u64_m (p0, z0, 65535), + z0 = svand_m (p0, z0, 65535)) + +/* +** and_65535_u64_m_untied: +** movprfx z0, z1 +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_u64_m_untied, svuint64_t, + z0 = svand_n_u64_m (p0, z1, 65535), + z0 = svand_m (p0, z1, 65535)) + +/* +** and_0xffffffff_u64_m_tied1: +** uxtw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_u64_m_tied1, svuint64_t, + z0 = svand_n_u64_m (p0, z0, 0xffffffff), + z0 = svand_m (p0, z0, 0xffffffff)) + +/* +** and_0xffffffff_u64_m_untied: +** movprfx z0, z1 +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_u64_m_untied, svuint64_t, + z0 = svand_n_u64_m (p0, z1, 0xffffffff), + z0 = svand_m (p0, z1, 0xffffffff)) + +/* +** and_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_u64_z_tied1, svuint64_t, + z0 = svand_u64_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_u64_z_tied2, svuint64_t, + z0 = svand_u64_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (and_u64_z_untied, svuint64_t, + z0 = svand_u64_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svand_n_u64_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svand_n_u64_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_z_tied1, svuint64_t, + z0 = svand_n_u64_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_z_untied, svuint64_t, + z0 = svand_n_u64_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_255_u64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtb z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #255 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_255_u64_z_tied1, svuint64_t, + z0 = svand_n_u64_z (p0, z0, 255), + z0 = svand_z (p0, z0, 255)) + +/* +** and_255_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_255_u64_z_untied, svuint64_t, + z0 = svand_n_u64_z (p0, z1, 255), + z0 = svand_z (p0, z1, 255)) + +/* +** and_65535_u64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxth z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #65535 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_65535_u64_z_tied1, svuint64_t, + z0 = svand_n_u64_z (p0, z0, 65535), + z0 = svand_z (p0, z0, 65535)) + +/* +** and_65535_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_65535_u64_z_untied, svuint64_t, + z0 = svand_n_u64_z (p0, z1, 65535), + z0 = svand_z (p0, z1, 65535)) + +/* +** and_0xffffffff_u64_z_tied1: +** ( +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtw z0\.d, p0/m, \1 +** | +** mov (z[0-9]+\.d), #4294967295 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ) +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_u64_z_tied1, svuint64_t, + z0 = svand_n_u64_z (p0, z0, 0xffffffff), + z0 = svand_z (p0, z0, 0xffffffff)) + +/* +** and_0xffffffff_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (and_0xffffffff_u64_z_untied, svuint64_t, + z0 = svand_n_u64_z (p0, z1, 0xffffffff), + z0 = svand_z (p0, z1, 0xffffffff)) + +/* +** and_u64_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u64_x_tied1, svuint64_t, + z0 = svand_u64_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_u64_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u64_x_tied2, svuint64_t, + z0 = svand_u64_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_u64_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u64_x_untied, svuint64_t, + z0 = svand_u64_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svand_n_u64_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** and z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svand_n_u64_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_u64_x_tied1: +** and z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_x_tied1, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_u64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u64_x_untied, svuint64_t, + z0 = svand_n_u64_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_u64_x: +** and z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_u64_x: +** and z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_u64_x: +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (and_255_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_256_u64_x: +** and z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (and_256_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 256), + z0 = svand_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (and_257_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 257), + z0 = svand_x (p0, z0, 257)) + +/* +** and_512_u64_x: +** and z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (and_512_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 512), + z0 = svand_x (p0, z0, 512)) + +/* +** and_65280_u64_x: +** and z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (and_65280_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 0xff00), + z0 = svand_x (p0, z0, 0xff00)) + +/* +** and_m127_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_m255_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (and_m255_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -255), + z0 = svand_x (p0, z0, -255)) + +/* +** and_m256_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (and_m256_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -256), + z0 = svand_x (p0, z0, -256)) + +/* +** and_m257_u64_x: +** and z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (and_m257_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -257), + z0 = svand_x (p0, z0, -257)) + +/* +** and_m512_u64_x: +** and z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (and_m512_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -512), + z0 = svand_x (p0, z0, -512)) + +/* +** and_m32768_u64_x: +** and z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (and_m32768_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, -0x8000), + z0 = svand_x (p0, z0, -0x8000)) + +/* +** and_5_u64_x: +** mov (z[0-9]+\.d), #5 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_u64_x, svuint64_t, + z0 = svand_n_u64_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c new file mode 100644 index 00000000000..b0f1c9529f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** and_u8_m_tied1: +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_u8_m_tied1, svuint8_t, + z0 = svand_u8_m (p0, z0, z1), + z0 = svand_m (p0, z0, z1)) + +/* +** and_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (and_u8_m_tied2, svuint8_t, + z0 = svand_u8_m (p0, z1, z0), + z0 = svand_m (p0, z1, z0)) + +/* +** and_u8_m_untied: +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (and_u8_m_untied, svuint8_t, + z0 = svand_u8_m (p0, z1, z2), + z0 = svand_m (p0, z1, z2)) + +/* +** and_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svand_n_u8_m (p0, z0, x0), + z0 = svand_m (p0, z0, x0)) + +/* +** and_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svand_n_u8_m (p0, z1, x0), + z0 = svand_m (p0, z1, x0)) + +/* +** and_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_m_tied1, svuint8_t, + z0 = svand_n_u8_m (p0, z0, 1), + z0 = svand_m (p0, z0, 1)) + +/* +** and_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_m_untied, svuint8_t, + z0 = svand_n_u8_m (p0, z1, 1), + z0 = svand_m (p0, z1, 1)) + +/* +** and_m2_u8_m: +** mov (z[0-9]+\.b), #-2 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_m2_u8_m, svuint8_t, + z0 = svand_n_u8_m (p0, z0, -2), + z0 = svand_m (p0, z0, -2)) + +/* +** and_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_u8_z_tied1, svuint8_t, + z0 = svand_u8_z (p0, z0, z1), + z0 = svand_z (p0, z0, z1)) + +/* +** and_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (and_u8_z_tied2, svuint8_t, + z0 = svand_u8_z (p0, z1, z0), + z0 = svand_z (p0, z1, z0)) + +/* +** and_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (and_u8_z_untied, svuint8_t, + z0 = svand_u8_z (p0, z1, z2), + z0 = svand_z (p0, z1, z2)) + +/* +** and_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svand_n_u8_z (p0, z0, x0), + z0 = svand_z (p0, z0, x0)) + +/* +** and_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svand_n_u8_z (p0, z1, x0), + z0 = svand_z (p0, z1, x0)) + +/* +** and_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_z_tied1, svuint8_t, + z0 = svand_n_u8_z (p0, z0, 1), + z0 = svand_z (p0, z0, 1)) + +/* +** and_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_z_untied, svuint8_t, + z0 = svand_n_u8_z (p0, z1, 1), + z0 = svand_z (p0, z1, 1)) + +/* +** and_u8_x_tied1: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u8_x_tied1, svuint8_t, + z0 = svand_u8_x (p0, z0, z1), + z0 = svand_x (p0, z0, z1)) + +/* +** and_u8_x_tied2: +** and z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u8_x_tied2, svuint8_t, + z0 = svand_u8_x (p0, z1, z0), + z0 = svand_x (p0, z1, z0)) + +/* +** and_u8_x_untied: +** and z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (and_u8_x_untied, svuint8_t, + z0 = svand_u8_x (p0, z1, z2), + z0 = svand_x (p0, z1, z2)) + +/* +** and_w0_u8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svand_n_u8_x (p0, z0, x0), + z0 = svand_x (p0, z0, x0)) + +/* +** and_w0_u8_x_untied: +** mov (z[0-9]+)\.b, w0 +** and z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (and_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svand_n_u8_x (p0, z1, x0), + z0 = svand_x (p0, z1, x0)) + +/* +** and_1_u8_x_tied1: +** and z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_x_tied1, svuint8_t, + z0 = svand_n_u8_x (p0, z0, 1), + z0 = svand_x (p0, z0, 1)) + +/* +** and_1_u8_x_untied: +** movprfx z0, z1 +** and z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (and_1_u8_x_untied, svuint8_t, + z0 = svand_n_u8_x (p0, z1, 1), + z0 = svand_x (p0, z1, 1)) + +/* +** and_127_u8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (and_127_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, 127), + z0 = svand_x (p0, z0, 127)) + +/* +** and_128_u8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_128_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, 128), + z0 = svand_x (p0, z0, 128)) + +/* +** and_255_u8_x: +** ret +*/ +TEST_UNIFORM_Z (and_255_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, 255), + z0 = svand_x (p0, z0, 255)) + +/* +** and_m127_u8_x: +** and z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (and_m127_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, -127), + z0 = svand_x (p0, z0, -127)) + +/* +** and_m128_u8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (and_m128_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, -128), + z0 = svand_x (p0, z0, -128)) + +/* +** and_5_u8_x: +** mov (z[0-9]+)\.b, #5 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (and_5_u8_x, svuint8_t, + z0 = svand_n_u8_x (p0, z0, 5), + z0 = svand_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s16.c new file mode 100644 index 00000000000..16761b823bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_s16: +** andv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (andv_x0_s16, int16_t, svint16_t, + x0 = svandv_s16 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s32.c new file mode 100644 index 00000000000..bccc91e219b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_s32: +** andv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (andv_x0_s32, int32_t, svint32_t, + x0 = svandv_s32 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s64.c new file mode 100644 index 00000000000..53488b6e38a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_s64: +** andv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (andv_x0_s64, int64_t, svint64_t, + x0 = svandv_s64 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s8.c new file mode 100644 index 00000000000..052f74c7f0e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_s8: +** andv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (andv_x0_s8, int8_t, svint8_t, + x0 = svandv_s8 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u16.c new file mode 100644 index 00000000000..03328022d1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_u16: +** andv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (andv_x0_u16, uint16_t, svuint16_t, + x0 = svandv_u16 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u32.c new file mode 100644 index 00000000000..a1677e7039e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_u32: +** andv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (andv_x0_u32, uint32_t, svuint32_t, + x0 = svandv_u32 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u64.c new file mode 100644 index 00000000000..d45422693a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_u64: +** andv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (andv_x0_u64, uint64_t, svuint64_t, + x0 = svandv_u64 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u8.c new file mode 100644 index 00000000000..b07f6b6e69c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/andv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** andv_x0_u8: +** andv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (andv_x0_u8, uint8_t, svuint8_t, + x0 = svandv_u8 (p0, z0), + x0 = svandv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c new file mode 100644 index 00000000000..877bf10685a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (asr_s16_m_tied1, svint16_t, svuint16_t, + z0 = svasr_s16_m (p0, z0, z4), + z0 = svasr_m (p0, z0, z4)) + +/* +** asr_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** asr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (asr_s16_m_tied2, svint16_t, svuint16_t, + z0_res = svasr_s16_m (p0, z4, z0), + z0_res = svasr_m (p0, z4, z0)) + +/* +** asr_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (asr_s16_m_untied, svint16_t, svuint16_t, + z0 = svasr_s16_m (p0, z1, z4), + z0 = svasr_m (p0, z1, z4)) + +/* +** asr_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_m_tied1, svint16_t, uint16_t, + z0 = svasr_n_s16_m (p0, z0, x0), + z0 = svasr_m (p0, z0, x0)) + +/* +** asr_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_m_untied, svint16_t, uint16_t, + z0 = svasr_n_s16_m (p0, z1, x0), + z0 = svasr_m (p0, z1, x0)) + +/* +** asr_1_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_m_tied1, svint16_t, + z0 = svasr_n_s16_m (p0, z0, 1), + z0 = svasr_m (p0, z0, 1)) + +/* +** asr_1_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_m_untied, svint16_t, + z0 = svasr_n_s16_m (p0, z1, 1), + z0 = svasr_m (p0, z1, 1)) + +/* +** asr_15_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_m_tied1, svint16_t, + z0 = svasr_n_s16_m (p0, z0, 15), + z0 = svasr_m (p0, z0, 15)) + +/* +** asr_15_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_m_untied, svint16_t, + z0 = svasr_n_s16_m (p0, z1, 15), + z0 = svasr_m (p0, z1, 15)) + +/* +** asr_16_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_m_tied1, svint16_t, + z0 = svasr_n_s16_m (p0, z0, 16), + z0 = svasr_m (p0, z0, 16)) + +/* +** asr_16_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_m_untied, svint16_t, + z0 = svasr_n_s16_m (p0, z1, 16), + z0 = svasr_m (p0, z1, 16)) + +/* +** asr_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (asr_s16_z_tied1, svint16_t, svuint16_t, + z0 = svasr_s16_z (p0, z0, z4), + z0 = svasr_z (p0, z0, z4)) + +/* +** asr_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** asrr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z_REV (asr_s16_z_tied2, svint16_t, svuint16_t, + z0_res = svasr_s16_z (p0, z4, z0), + z0_res = svasr_z (p0, z4, z0)) + +/* +** asr_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, z4\.h +** | +** movprfx z0\.h, p0/z, z4\.h +** asrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_DUAL_Z (asr_s16_z_untied, svint16_t, svuint16_t, + z0 = svasr_s16_z (p0, z1, z4), + z0 = svasr_z (p0, z1, z4)) + +/* +** asr_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_z_tied1, svint16_t, uint16_t, + z0 = svasr_n_s16_z (p0, z0, x0), + z0 = svasr_z (p0, z0, x0)) + +/* +** asr_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** asrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_z_untied, svint16_t, uint16_t, + z0 = svasr_n_s16_z (p0, z1, x0), + z0 = svasr_z (p0, z1, x0)) + +/* +** asr_1_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_z_tied1, svint16_t, + z0 = svasr_n_s16_z (p0, z0, 1), + z0 = svasr_z (p0, z0, 1)) + +/* +** asr_1_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_z_untied, svint16_t, + z0 = svasr_n_s16_z (p0, z1, 1), + z0 = svasr_z (p0, z1, 1)) + +/* +** asr_15_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_z_tied1, svint16_t, + z0 = svasr_n_s16_z (p0, z0, 15), + z0 = svasr_z (p0, z0, 15)) + +/* +** asr_15_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_z_untied, svint16_t, + z0 = svasr_n_s16_z (p0, z1, 15), + z0 = svasr_z (p0, z1, 15)) + +/* +** asr_16_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_z_tied1, svint16_t, + z0 = svasr_n_s16_z (p0, z0, 16), + z0 = svasr_z (p0, z0, 16)) + +/* +** asr_16_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_z_untied, svint16_t, + z0 = svasr_n_s16_z (p0, z1, 16), + z0 = svasr_z (p0, z1, 16)) + +/* +** asr_s16_x_tied1: +** asr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (asr_s16_x_tied1, svint16_t, svuint16_t, + z0 = svasr_s16_x (p0, z0, z4), + z0 = svasr_x (p0, z0, z4)) + +/* +** asr_s16_x_tied2: +** asrr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z_REV (asr_s16_x_tied2, svint16_t, svuint16_t, + z0_res = svasr_s16_x (p0, z4, z0), + z0_res = svasr_x (p0, z4, z0)) + +/* +** asr_s16_x_untied: +** ( +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, z4\.h +** | +** movprfx z0, z4 +** asrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_DUAL_Z (asr_s16_x_untied, svint16_t, svuint16_t, + z0 = svasr_s16_x (p0, z1, z4), + z0 = svasr_x (p0, z1, z4)) + +/* +** asr_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_x_tied1, svint16_t, uint16_t, + z0 = svasr_n_s16_x (p0, z0, x0), + z0 = svasr_x (p0, z0, x0)) + +/* +** asr_w0_s16_x_untied: +** mov z0\.h, w0 +** asrr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s16_x_untied, svint16_t, uint16_t, + z0 = svasr_n_s16_x (p0, z1, x0), + z0 = svasr_x (p0, z1, x0)) + +/* +** asr_1_s16_x_tied1: +** asr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_x_tied1, svint16_t, + z0 = svasr_n_s16_x (p0, z0, 1), + z0 = svasr_x (p0, z0, 1)) + +/* +** asr_1_s16_x_untied: +** asr z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s16_x_untied, svint16_t, + z0 = svasr_n_s16_x (p0, z1, 1), + z0 = svasr_x (p0, z1, 1)) + +/* +** asr_15_s16_x_tied1: +** asr z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_x_tied1, svint16_t, + z0 = svasr_n_s16_x (p0, z0, 15), + z0 = svasr_x (p0, z0, 15)) + +/* +** asr_15_s16_x_untied: +** asr z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_15_s16_x_untied, svint16_t, + z0 = svasr_n_s16_x (p0, z1, 15), + z0 = svasr_x (p0, z1, 15)) + +/* +** asr_16_s16_x_tied1: +** asr z0\.h, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_x_tied1, svint16_t, + z0 = svasr_n_s16_x (p0, z0, 16), + z0 = svasr_x (p0, z0, 16)) + +/* +** asr_16_s16_x_untied: +** asr z0\.h, z1\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_16_s16_x_untied, svint16_t, + z0 = svasr_n_s16_x (p0, z1, 16), + z0 = svasr_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s32.c new file mode 100644 index 00000000000..0f5a3737243 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s32.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (asr_s32_m_tied1, svint32_t, svuint32_t, + z0 = svasr_s32_m (p0, z0, z4), + z0 = svasr_m (p0, z0, z4)) + +/* +** asr_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** asr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (asr_s32_m_tied2, svint32_t, svuint32_t, + z0_res = svasr_s32_m (p0, z4, z0), + z0_res = svasr_m (p0, z4, z0)) + +/* +** asr_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (asr_s32_m_untied, svint32_t, svuint32_t, + z0 = svasr_s32_m (p0, z1, z4), + z0 = svasr_m (p0, z1, z4)) + +/* +** asr_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_m_tied1, svint32_t, uint32_t, + z0 = svasr_n_s32_m (p0, z0, x0), + z0 = svasr_m (p0, z0, x0)) + +/* +** asr_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_m_untied, svint32_t, uint32_t, + z0 = svasr_n_s32_m (p0, z1, x0), + z0 = svasr_m (p0, z1, x0)) + +/* +** asr_1_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_m_tied1, svint32_t, + z0 = svasr_n_s32_m (p0, z0, 1), + z0 = svasr_m (p0, z0, 1)) + +/* +** asr_1_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_m_untied, svint32_t, + z0 = svasr_n_s32_m (p0, z1, 1), + z0 = svasr_m (p0, z1, 1)) + +/* +** asr_31_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_m_tied1, svint32_t, + z0 = svasr_n_s32_m (p0, z0, 31), + z0 = svasr_m (p0, z0, 31)) + +/* +** asr_31_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_m_untied, svint32_t, + z0 = svasr_n_s32_m (p0, z1, 31), + z0 = svasr_m (p0, z1, 31)) + +/* +** asr_32_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_m_tied1, svint32_t, + z0 = svasr_n_s32_m (p0, z0, 32), + z0 = svasr_m (p0, z0, 32)) + +/* +** asr_32_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_m_untied, svint32_t, + z0 = svasr_n_s32_m (p0, z1, 32), + z0 = svasr_m (p0, z1, 32)) + +/* +** asr_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (asr_s32_z_tied1, svint32_t, svuint32_t, + z0 = svasr_s32_z (p0, z0, z4), + z0 = svasr_z (p0, z0, z4)) + +/* +** asr_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** asrr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z_REV (asr_s32_z_tied2, svint32_t, svuint32_t, + z0_res = svasr_s32_z (p0, z4, z0), + z0_res = svasr_z (p0, z4, z0)) + +/* +** asr_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, z4\.s +** | +** movprfx z0\.s, p0/z, z4\.s +** asrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_DUAL_Z (asr_s32_z_untied, svint32_t, svuint32_t, + z0 = svasr_s32_z (p0, z1, z4), + z0 = svasr_z (p0, z1, z4)) + +/* +** asr_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_z_tied1, svint32_t, uint32_t, + z0 = svasr_n_s32_z (p0, z0, x0), + z0 = svasr_z (p0, z0, x0)) + +/* +** asr_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** asrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_z_untied, svint32_t, uint32_t, + z0 = svasr_n_s32_z (p0, z1, x0), + z0 = svasr_z (p0, z1, x0)) + +/* +** asr_1_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_z_tied1, svint32_t, + z0 = svasr_n_s32_z (p0, z0, 1), + z0 = svasr_z (p0, z0, 1)) + +/* +** asr_1_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_z_untied, svint32_t, + z0 = svasr_n_s32_z (p0, z1, 1), + z0 = svasr_z (p0, z1, 1)) + +/* +** asr_31_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_z_tied1, svint32_t, + z0 = svasr_n_s32_z (p0, z0, 31), + z0 = svasr_z (p0, z0, 31)) + +/* +** asr_31_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_z_untied, svint32_t, + z0 = svasr_n_s32_z (p0, z1, 31), + z0 = svasr_z (p0, z1, 31)) + +/* +** asr_32_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_z_tied1, svint32_t, + z0 = svasr_n_s32_z (p0, z0, 32), + z0 = svasr_z (p0, z0, 32)) + +/* +** asr_32_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_z_untied, svint32_t, + z0 = svasr_n_s32_z (p0, z1, 32), + z0 = svasr_z (p0, z1, 32)) + +/* +** asr_s32_x_tied1: +** asr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (asr_s32_x_tied1, svint32_t, svuint32_t, + z0 = svasr_s32_x (p0, z0, z4), + z0 = svasr_x (p0, z0, z4)) + +/* +** asr_s32_x_tied2: +** asrr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z_REV (asr_s32_x_tied2, svint32_t, svuint32_t, + z0_res = svasr_s32_x (p0, z4, z0), + z0_res = svasr_x (p0, z4, z0)) + +/* +** asr_s32_x_untied: +** ( +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, z4\.s +** | +** movprfx z0, z4 +** asrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_DUAL_Z (asr_s32_x_untied, svint32_t, svuint32_t, + z0 = svasr_s32_x (p0, z1, z4), + z0 = svasr_x (p0, z1, z4)) + +/* +** asr_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_x_tied1, svint32_t, uint32_t, + z0 = svasr_n_s32_x (p0, z0, x0), + z0 = svasr_x (p0, z0, x0)) + +/* +** asr_w0_s32_x_untied: +** mov z0\.s, w0 +** asrr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s32_x_untied, svint32_t, uint32_t, + z0 = svasr_n_s32_x (p0, z1, x0), + z0 = svasr_x (p0, z1, x0)) + +/* +** asr_1_s32_x_tied1: +** asr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_x_tied1, svint32_t, + z0 = svasr_n_s32_x (p0, z0, 1), + z0 = svasr_x (p0, z0, 1)) + +/* +** asr_1_s32_x_untied: +** asr z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s32_x_untied, svint32_t, + z0 = svasr_n_s32_x (p0, z1, 1), + z0 = svasr_x (p0, z1, 1)) + +/* +** asr_31_s32_x_tied1: +** asr z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_x_tied1, svint32_t, + z0 = svasr_n_s32_x (p0, z0, 31), + z0 = svasr_x (p0, z0, 31)) + +/* +** asr_31_s32_x_untied: +** asr z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_31_s32_x_untied, svint32_t, + z0 = svasr_n_s32_x (p0, z1, 31), + z0 = svasr_x (p0, z1, 31)) + +/* +** asr_32_s32_x_tied1: +** asr z0\.s, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_x_tied1, svint32_t, + z0 = svasr_n_s32_x (p0, z0, 32), + z0 = svasr_x (p0, z0, 32)) + +/* +** asr_32_s32_x_untied: +** asr z0\.s, z1\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_32_s32_x_untied, svint32_t, + z0 = svasr_n_s32_x (p0, z1, 32), + z0 = svasr_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s64.c new file mode 100644 index 00000000000..80cae07c3f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s64.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_s64_m_tied1: +** asr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_s64_m_tied1, svint64_t, svuint64_t, + z0 = svasr_s64_m (p0, z0, z4), + z0 = svasr_m (p0, z0, z4)) + +/* +** asr_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** asr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_s64_m_tied2, svint64_t, svuint64_t, + z0_res = svasr_s64_m (p0, z4, z0), + z0_res = svasr_m (p0, z4, z0)) + +/* +** asr_s64_m_untied: +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_s64_m_untied, svint64_t, svuint64_t, + z0 = svasr_s64_m (p0, z1, z4), + z0 = svasr_m (p0, z1, z4)) + +/* +** asr_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_m_tied1, svint64_t, uint64_t, + z0 = svasr_n_s64_m (p0, z0, x0), + z0 = svasr_m (p0, z0, x0)) + +/* +** asr_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_m_untied, svint64_t, uint64_t, + z0 = svasr_n_s64_m (p0, z1, x0), + z0 = svasr_m (p0, z1, x0)) + +/* +** asr_1_s64_m_tied1: +** asr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_m_tied1, svint64_t, + z0 = svasr_n_s64_m (p0, z0, 1), + z0 = svasr_m (p0, z0, 1)) + +/* +** asr_1_s64_m_untied: +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_m_untied, svint64_t, + z0 = svasr_n_s64_m (p0, z1, 1), + z0 = svasr_m (p0, z1, 1)) + +/* +** asr_63_s64_m_tied1: +** asr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_m_tied1, svint64_t, + z0 = svasr_n_s64_m (p0, z0, 63), + z0 = svasr_m (p0, z0, 63)) + +/* +** asr_63_s64_m_untied: +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_m_untied, svint64_t, + z0 = svasr_n_s64_m (p0, z1, 63), + z0 = svasr_m (p0, z1, 63)) + +/* +** asr_64_s64_m_tied1: +** asr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_m_tied1, svint64_t, + z0 = svasr_n_s64_m (p0, z0, 64), + z0 = svasr_m (p0, z0, 64)) + +/* +** asr_64_s64_m_untied: +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_m_untied, svint64_t, + z0 = svasr_n_s64_m (p0, z1, 64), + z0 = svasr_m (p0, z1, 64)) + +/* +** asr_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_s64_z_tied1, svint64_t, svuint64_t, + z0 = svasr_s64_z (p0, z0, z4), + z0 = svasr_z (p0, z0, z4)) + +/* +** asr_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** asrr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z_REV (asr_s64_z_tied2, svint64_t, svuint64_t, + z0_res = svasr_s64_z (p0, z4, z0), + z0_res = svasr_z (p0, z4, z0)) + +/* +** asr_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** asr z0\.d, p0/m, z0\.d, z4\.d +** | +** movprfx z0\.d, p0/z, z4\.d +** asrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_DUAL_Z (asr_s64_z_untied, svint64_t, svuint64_t, + z0 = svasr_s64_z (p0, z1, z4), + z0 = svasr_z (p0, z1, z4)) + +/* +** asr_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** asr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_z_tied1, svint64_t, uint64_t, + z0 = svasr_n_s64_z (p0, z0, x0), + z0 = svasr_z (p0, z0, x0)) + +/* +** asr_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** asr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** asrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_z_untied, svint64_t, uint64_t, + z0 = svasr_n_s64_z (p0, z1, x0), + z0 = svasr_z (p0, z1, x0)) + +/* +** asr_1_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_z_tied1, svint64_t, + z0 = svasr_n_s64_z (p0, z0, 1), + z0 = svasr_z (p0, z0, 1)) + +/* +** asr_1_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_z_untied, svint64_t, + z0 = svasr_n_s64_z (p0, z1, 1), + z0 = svasr_z (p0, z1, 1)) + +/* +** asr_63_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_z_tied1, svint64_t, + z0 = svasr_n_s64_z (p0, z0, 63), + z0 = svasr_z (p0, z0, 63)) + +/* +** asr_63_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_z_untied, svint64_t, + z0 = svasr_n_s64_z (p0, z1, 63), + z0 = svasr_z (p0, z1, 63)) + +/* +** asr_64_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_z_tied1, svint64_t, + z0 = svasr_n_s64_z (p0, z0, 64), + z0 = svasr_z (p0, z0, 64)) + +/* +** asr_64_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_z_untied, svint64_t, + z0 = svasr_n_s64_z (p0, z1, 64), + z0 = svasr_z (p0, z1, 64)) + +/* +** asr_s64_x_tied1: +** asr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_s64_x_tied1, svint64_t, svuint64_t, + z0 = svasr_s64_x (p0, z0, z4), + z0 = svasr_x (p0, z0, z4)) + +/* +** asr_s64_x_tied2: +** asrr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z_REV (asr_s64_x_tied2, svint64_t, svuint64_t, + z0_res = svasr_s64_x (p0, z4, z0), + z0_res = svasr_x (p0, z4, z0)) + +/* +** asr_s64_x_untied: +** ( +** movprfx z0, z1 +** asr z0\.d, p0/m, z0\.d, z4\.d +** | +** movprfx z0, z4 +** asrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_DUAL_Z (asr_s64_x_untied, svint64_t, svuint64_t, + z0 = svasr_s64_x (p0, z1, z4), + z0 = svasr_x (p0, z1, z4)) + +/* +** asr_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_x_tied1, svint64_t, uint64_t, + z0 = svasr_n_s64_x (p0, z0, x0), + z0 = svasr_x (p0, z0, x0)) + +/* +** asr_x0_s64_x_untied: +** mov z0\.d, x0 +** asrr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (asr_x0_s64_x_untied, svint64_t, uint64_t, + z0 = svasr_n_s64_x (p0, z1, x0), + z0 = svasr_x (p0, z1, x0)) + +/* +** asr_1_s64_x_tied1: +** asr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_x_tied1, svint64_t, + z0 = svasr_n_s64_x (p0, z0, 1), + z0 = svasr_x (p0, z0, 1)) + +/* +** asr_1_s64_x_untied: +** asr z0\.d, z1\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s64_x_untied, svint64_t, + z0 = svasr_n_s64_x (p0, z1, 1), + z0 = svasr_x (p0, z1, 1)) + +/* +** asr_63_s64_x_tied1: +** asr z0\.d, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_x_tied1, svint64_t, + z0 = svasr_n_s64_x (p0, z0, 63), + z0 = svasr_x (p0, z0, 63)) + +/* +** asr_63_s64_x_untied: +** asr z0\.d, z1\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (asr_63_s64_x_untied, svint64_t, + z0 = svasr_n_s64_x (p0, z1, 63), + z0 = svasr_x (p0, z1, 63)) + +/* +** asr_64_s64_x_tied1: +** asr z0\.d, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_x_tied1, svint64_t, + z0 = svasr_n_s64_x (p0, z0, 64), + z0 = svasr_x (p0, z0, 64)) + +/* +** asr_64_s64_x_untied: +** asr z0\.d, z1\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asr_64_s64_x_untied, svint64_t, + z0 = svasr_n_s64_x (p0, z1, 64), + z0 = svasr_x (p0, z1, 64)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c new file mode 100644 index 00000000000..992e93fdef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (asr_s8_m_tied1, svint8_t, svuint8_t, + z0 = svasr_s8_m (p0, z0, z4), + z0 = svasr_m (p0, z0, z4)) + +/* +** asr_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** asr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_DUAL_Z_REV (asr_s8_m_tied2, svint8_t, svuint8_t, + z0_res = svasr_s8_m (p0, z4, z0), + z0_res = svasr_m (p0, z4, z0)) + +/* +** asr_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (asr_s8_m_untied, svint8_t, svuint8_t, + z0 = svasr_s8_m (p0, z1, z4), + z0 = svasr_m (p0, z1, z4)) + +/* +** asr_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_m_tied1, svint8_t, uint8_t, + z0 = svasr_n_s8_m (p0, z0, x0), + z0 = svasr_m (p0, z0, x0)) + +/* +** asr_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_m_untied, svint8_t, uint8_t, + z0 = svasr_n_s8_m (p0, z1, x0), + z0 = svasr_m (p0, z1, x0)) + +/* +** asr_1_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_m_tied1, svint8_t, + z0 = svasr_n_s8_m (p0, z0, 1), + z0 = svasr_m (p0, z0, 1)) + +/* +** asr_1_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_m_untied, svint8_t, + z0 = svasr_n_s8_m (p0, z1, 1), + z0 = svasr_m (p0, z1, 1)) + +/* +** asr_7_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_m_tied1, svint8_t, + z0 = svasr_n_s8_m (p0, z0, 7), + z0 = svasr_m (p0, z0, 7)) + +/* +** asr_7_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_m_untied, svint8_t, + z0 = svasr_n_s8_m (p0, z1, 7), + z0 = svasr_m (p0, z1, 7)) + +/* +** asr_8_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_m_tied1, svint8_t, + z0 = svasr_n_s8_m (p0, z0, 8), + z0 = svasr_m (p0, z0, 8)) + +/* +** asr_8_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_m_untied, svint8_t, + z0 = svasr_n_s8_m (p0, z1, 8), + z0 = svasr_m (p0, z1, 8)) + +/* +** asr_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (asr_s8_z_tied1, svint8_t, svuint8_t, + z0 = svasr_s8_z (p0, z0, z4), + z0 = svasr_z (p0, z0, z4)) + +/* +** asr_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** asrr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z_REV (asr_s8_z_tied2, svint8_t, svuint8_t, + z0_res = svasr_s8_z (p0, z4, z0), + z0_res = svasr_z (p0, z4, z0)) + +/* +** asr_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, z4\.b +** | +** movprfx z0\.b, p0/z, z4\.b +** asrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_DUAL_Z (asr_s8_z_untied, svint8_t, svuint8_t, + z0 = svasr_s8_z (p0, z1, z4), + z0 = svasr_z (p0, z1, z4)) + +/* +** asr_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_z_tied1, svint8_t, uint8_t, + z0 = svasr_n_s8_z (p0, z0, x0), + z0 = svasr_z (p0, z0, x0)) + +/* +** asr_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** asrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_z_untied, svint8_t, uint8_t, + z0 = svasr_n_s8_z (p0, z1, x0), + z0 = svasr_z (p0, z1, x0)) + +/* +** asr_1_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_z_tied1, svint8_t, + z0 = svasr_n_s8_z (p0, z0, 1), + z0 = svasr_z (p0, z0, 1)) + +/* +** asr_1_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_z_untied, svint8_t, + z0 = svasr_n_s8_z (p0, z1, 1), + z0 = svasr_z (p0, z1, 1)) + +/* +** asr_7_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_z_tied1, svint8_t, + z0 = svasr_n_s8_z (p0, z0, 7), + z0 = svasr_z (p0, z0, 7)) + +/* +** asr_7_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_z_untied, svint8_t, + z0 = svasr_n_s8_z (p0, z1, 7), + z0 = svasr_z (p0, z1, 7)) + +/* +** asr_8_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_z_tied1, svint8_t, + z0 = svasr_n_s8_z (p0, z0, 8), + z0 = svasr_z (p0, z0, 8)) + +/* +** asr_8_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_z_untied, svint8_t, + z0 = svasr_n_s8_z (p0, z1, 8), + z0 = svasr_z (p0, z1, 8)) + +/* +** asr_s8_x_tied1: +** asr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (asr_s8_x_tied1, svint8_t, svuint8_t, + z0 = svasr_s8_x (p0, z0, z4), + z0 = svasr_x (p0, z0, z4)) + +/* +** asr_s8_x_tied2: +** asrr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z_REV (asr_s8_x_tied2, svint8_t, svuint8_t, + z0_res = svasr_s8_x (p0, z4, z0), + z0_res = svasr_x (p0, z4, z0)) + +/* +** asr_s8_x_untied: +** ( +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, z4\.b +** | +** movprfx z0, z4 +** asrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_DUAL_Z (asr_s8_x_untied, svint8_t, svuint8_t, + z0 = svasr_s8_x (p0, z1, z4), + z0 = svasr_x (p0, z1, z4)) + +/* +** asr_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_x_tied1, svint8_t, uint8_t, + z0 = svasr_n_s8_x (p0, z0, x0), + z0 = svasr_x (p0, z0, x0)) + +/* +** asr_w0_s8_x_untied: +** mov z0\.b, w0 +** asrr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (asr_w0_s8_x_untied, svint8_t, uint8_t, + z0 = svasr_n_s8_x (p0, z1, x0), + z0 = svasr_x (p0, z1, x0)) + +/* +** asr_1_s8_x_tied1: +** asr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_x_tied1, svint8_t, + z0 = svasr_n_s8_x (p0, z0, 1), + z0 = svasr_x (p0, z0, 1)) + +/* +** asr_1_s8_x_untied: +** asr z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_1_s8_x_untied, svint8_t, + z0 = svasr_n_s8_x (p0, z1, 1), + z0 = svasr_x (p0, z1, 1)) + +/* +** asr_7_s8_x_tied1: +** asr z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_x_tied1, svint8_t, + z0 = svasr_n_s8_x (p0, z0, 7), + z0 = svasr_x (p0, z0, 7)) + +/* +** asr_7_s8_x_untied: +** asr z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_7_s8_x_untied, svint8_t, + z0 = svasr_n_s8_x (p0, z1, 7), + z0 = svasr_x (p0, z1, 7)) + +/* +** asr_8_s8_x_tied1: +** asr z0\.b, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_x_tied1, svint8_t, + z0 = svasr_n_s8_x (p0, z0, 8), + z0 = svasr_x (p0, z0, 8)) + +/* +** asr_8_s8_x_untied: +** asr z0\.b, z1\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_8_s8_x_untied, svint8_t, + z0 = svasr_n_s8_x (p0, z1, 8), + z0 = svasr_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s16.c new file mode 100644 index 00000000000..b74ae33e100 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s16.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_wide_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_m_tied1, svint16_t, svuint64_t, + z0 = svasr_wide_s16_m (p0, z0, z4), + z0 = svasr_wide_m (p0, z0, z4)) + +/* +** asr_wide_s16_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s16_m_tied2, svint16_t, svuint64_t, + z0_res = svasr_wide_s16_m (p0, z4, z0), + z0_res = svasr_wide_m (p0, z4, z0)) + +/* +** asr_wide_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_m_untied, svint16_t, svuint64_t, + z0 = svasr_wide_s16_m (p0, z1, z4), + z0 = svasr_wide_m (p0, z1, z4)) + +/* +** asr_wide_x0_s16_m_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_m_tied1, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_m (p0, z0, x0), + z0 = svasr_wide_m (p0, z0, x0)) + +/* +** asr_wide_x0_s16_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_m_untied, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_m (p0, z1, x0), + z0 = svasr_wide_m (p0, z1, x0)) + +/* +** asr_wide_1_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_m_tied1, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z0, 1), + z0 = svasr_wide_m (p0, z0, 1)) + +/* +** asr_wide_1_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_m_untied, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z1, 1), + z0 = svasr_wide_m (p0, z1, 1)) + +/* +** asr_wide_15_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_m_tied1, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z0, 15), + z0 = svasr_wide_m (p0, z0, 15)) + +/* +** asr_wide_15_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_m_untied, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z1, 15), + z0 = svasr_wide_m (p0, z1, 15)) + +/* +** asr_wide_16_s16_m_tied1: +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_m_tied1, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z0, 16), + z0 = svasr_wide_m (p0, z0, 16)) + +/* +** asr_wide_16_s16_m_untied: +** movprfx z0, z1 +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_m_untied, svint16_t, + z0 = svasr_wide_n_s16_m (p0, z1, 16), + z0 = svasr_wide_m (p0, z1, 16)) + +/* +** asr_wide_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_z_tied1, svint16_t, svuint64_t, + z0 = svasr_wide_s16_z (p0, z0, z4), + z0 = svasr_wide_z (p0, z0, z4)) + +/* +** asr_wide_s16_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.h, p0/z, z4\.h +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s16_z_tied2, svint16_t, svuint64_t, + z0_res = svasr_wide_s16_z (p0, z4, z0), + z0_res = svasr_wide_z (p0, z4, z0)) + +/* +** asr_wide_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_z_untied, svint16_t, svuint64_t, + z0 = svasr_wide_s16_z (p0, z1, z4), + z0 = svasr_wide_z (p0, z1, z4)) + +/* +** asr_wide_x0_s16_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_z_tied1, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_z (p0, z0, x0), + z0 = svasr_wide_z (p0, z0, x0)) + +/* +** asr_wide_x0_s16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_z_untied, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_z (p0, z1, x0), + z0 = svasr_wide_z (p0, z1, x0)) + +/* +** asr_wide_1_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_z_tied1, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z0, 1), + z0 = svasr_wide_z (p0, z0, 1)) + +/* +** asr_wide_1_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_z_untied, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z1, 1), + z0 = svasr_wide_z (p0, z1, 1)) + +/* +** asr_wide_15_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_z_tied1, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z0, 15), + z0 = svasr_wide_z (p0, z0, 15)) + +/* +** asr_wide_15_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_z_untied, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z1, 15), + z0 = svasr_wide_z (p0, z1, 15)) + +/* +** asr_wide_16_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_z_tied1, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z0, 16), + z0 = svasr_wide_z (p0, z0, 16)) + +/* +** asr_wide_16_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_z_untied, svint16_t, + z0 = svasr_wide_n_s16_z (p0, z1, 16), + z0 = svasr_wide_z (p0, z1, 16)) + +/* +** asr_wide_s16_x_tied1: +** asr z0\.h, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_x_tied1, svint16_t, svuint64_t, + z0 = svasr_wide_s16_x (p0, z0, z4), + z0 = svasr_wide_x (p0, z0, z4)) + +/* +** asr_wide_s16_x_tied2: +** asr z0\.h, z4\.h, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s16_x_tied2, svint16_t, svuint64_t, + z0_res = svasr_wide_s16_x (p0, z4, z0), + z0_res = svasr_wide_x (p0, z4, z0)) + +/* +** asr_wide_s16_x_untied: +** asr z0\.h, z1\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s16_x_untied, svint16_t, svuint64_t, + z0 = svasr_wide_s16_x (p0, z1, z4), + z0 = svasr_wide_x (p0, z1, z4)) + +/* +** asr_wide_x0_s16_x_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_x_tied1, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_x (p0, z0, x0), + z0 = svasr_wide_x (p0, z0, x0)) + +/* +** asr_wide_x0_s16_x_untied: +** mov (z[0-9]+\.d), x0 +** asr z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s16_x_untied, svint16_t, uint64_t, + z0 = svasr_wide_n_s16_x (p0, z1, x0), + z0 = svasr_wide_x (p0, z1, x0)) + +/* +** asr_wide_1_s16_x_tied1: +** asr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_x_tied1, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z0, 1), + z0 = svasr_wide_x (p0, z0, 1)) + +/* +** asr_wide_1_s16_x_untied: +** asr z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s16_x_untied, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z1, 1), + z0 = svasr_wide_x (p0, z1, 1)) + +/* +** asr_wide_15_s16_x_tied1: +** asr z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_x_tied1, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z0, 15), + z0 = svasr_wide_x (p0, z0, 15)) + +/* +** asr_wide_15_s16_x_untied: +** asr z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_15_s16_x_untied, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z1, 15), + z0 = svasr_wide_x (p0, z1, 15)) + +/* +** asr_wide_16_s16_x_tied1: +** asr z0\.h, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_x_tied1, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z0, 16), + z0 = svasr_wide_x (p0, z0, 16)) + +/* +** asr_wide_16_s16_x_untied: +** asr z0\.h, z1\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_16_s16_x_untied, svint16_t, + z0 = svasr_wide_n_s16_x (p0, z1, 16), + z0 = svasr_wide_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s32.c new file mode 100644 index 00000000000..8698aef26c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s32.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_wide_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_m_tied1, svint32_t, svuint64_t, + z0 = svasr_wide_s32_m (p0, z0, z4), + z0 = svasr_wide_m (p0, z0, z4)) + +/* +** asr_wide_s32_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s32_m_tied2, svint32_t, svuint64_t, + z0_res = svasr_wide_s32_m (p0, z4, z0), + z0_res = svasr_wide_m (p0, z4, z0)) + +/* +** asr_wide_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_m_untied, svint32_t, svuint64_t, + z0 = svasr_wide_s32_m (p0, z1, z4), + z0 = svasr_wide_m (p0, z1, z4)) + +/* +** asr_wide_x0_s32_m_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_m_tied1, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_m (p0, z0, x0), + z0 = svasr_wide_m (p0, z0, x0)) + +/* +** asr_wide_x0_s32_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_m_untied, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_m (p0, z1, x0), + z0 = svasr_wide_m (p0, z1, x0)) + +/* +** asr_wide_1_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_m_tied1, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z0, 1), + z0 = svasr_wide_m (p0, z0, 1)) + +/* +** asr_wide_1_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_m_untied, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z1, 1), + z0 = svasr_wide_m (p0, z1, 1)) + +/* +** asr_wide_31_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_m_tied1, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z0, 31), + z0 = svasr_wide_m (p0, z0, 31)) + +/* +** asr_wide_31_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_m_untied, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z1, 31), + z0 = svasr_wide_m (p0, z1, 31)) + +/* +** asr_wide_32_s32_m_tied1: +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_m_tied1, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z0, 32), + z0 = svasr_wide_m (p0, z0, 32)) + +/* +** asr_wide_32_s32_m_untied: +** movprfx z0, z1 +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_m_untied, svint32_t, + z0 = svasr_wide_n_s32_m (p0, z1, 32), + z0 = svasr_wide_m (p0, z1, 32)) + +/* +** asr_wide_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_z_tied1, svint32_t, svuint64_t, + z0 = svasr_wide_s32_z (p0, z0, z4), + z0 = svasr_wide_z (p0, z0, z4)) + +/* +** asr_wide_s32_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.s, p0/z, z4\.s +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s32_z_tied2, svint32_t, svuint64_t, + z0_res = svasr_wide_s32_z (p0, z4, z0), + z0_res = svasr_wide_z (p0, z4, z0)) + +/* +** asr_wide_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_z_untied, svint32_t, svuint64_t, + z0 = svasr_wide_s32_z (p0, z1, z4), + z0 = svasr_wide_z (p0, z1, z4)) + +/* +** asr_wide_x0_s32_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_z_tied1, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_z (p0, z0, x0), + z0 = svasr_wide_z (p0, z0, x0)) + +/* +** asr_wide_x0_s32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_z_untied, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_z (p0, z1, x0), + z0 = svasr_wide_z (p0, z1, x0)) + +/* +** asr_wide_1_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_z_tied1, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z0, 1), + z0 = svasr_wide_z (p0, z0, 1)) + +/* +** asr_wide_1_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_z_untied, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z1, 1), + z0 = svasr_wide_z (p0, z1, 1)) + +/* +** asr_wide_31_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_z_tied1, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z0, 31), + z0 = svasr_wide_z (p0, z0, 31)) + +/* +** asr_wide_31_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_z_untied, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z1, 31), + z0 = svasr_wide_z (p0, z1, 31)) + +/* +** asr_wide_32_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_z_tied1, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z0, 32), + z0 = svasr_wide_z (p0, z0, 32)) + +/* +** asr_wide_32_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_z_untied, svint32_t, + z0 = svasr_wide_n_s32_z (p0, z1, 32), + z0 = svasr_wide_z (p0, z1, 32)) + +/* +** asr_wide_s32_x_tied1: +** asr z0\.s, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_x_tied1, svint32_t, svuint64_t, + z0 = svasr_wide_s32_x (p0, z0, z4), + z0 = svasr_wide_x (p0, z0, z4)) + +/* +** asr_wide_s32_x_tied2: +** asr z0\.s, z4\.s, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s32_x_tied2, svint32_t, svuint64_t, + z0_res = svasr_wide_s32_x (p0, z4, z0), + z0_res = svasr_wide_x (p0, z4, z0)) + +/* +** asr_wide_s32_x_untied: +** asr z0\.s, z1\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s32_x_untied, svint32_t, svuint64_t, + z0 = svasr_wide_s32_x (p0, z1, z4), + z0 = svasr_wide_x (p0, z1, z4)) + +/* +** asr_wide_x0_s32_x_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_x_tied1, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_x (p0, z0, x0), + z0 = svasr_wide_x (p0, z0, x0)) + +/* +** asr_wide_x0_s32_x_untied: +** mov (z[0-9]+\.d), x0 +** asr z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s32_x_untied, svint32_t, uint64_t, + z0 = svasr_wide_n_s32_x (p0, z1, x0), + z0 = svasr_wide_x (p0, z1, x0)) + +/* +** asr_wide_1_s32_x_tied1: +** asr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_x_tied1, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z0, 1), + z0 = svasr_wide_x (p0, z0, 1)) + +/* +** asr_wide_1_s32_x_untied: +** asr z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s32_x_untied, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z1, 1), + z0 = svasr_wide_x (p0, z1, 1)) + +/* +** asr_wide_31_s32_x_tied1: +** asr z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_x_tied1, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z0, 31), + z0 = svasr_wide_x (p0, z0, 31)) + +/* +** asr_wide_31_s32_x_untied: +** asr z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_31_s32_x_untied, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z1, 31), + z0 = svasr_wide_x (p0, z1, 31)) + +/* +** asr_wide_32_s32_x_tied1: +** asr z0\.s, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_x_tied1, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z0, 32), + z0 = svasr_wide_x (p0, z0, 32)) + +/* +** asr_wide_32_s32_x_untied: +** asr z0\.s, z1\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_32_s32_x_untied, svint32_t, + z0 = svasr_wide_n_s32_x (p0, z1, 32), + z0 = svasr_wide_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s8.c new file mode 100644 index 00000000000..77b1669392d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_wide_s8.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asr_wide_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_m_tied1, svint8_t, svuint64_t, + z0 = svasr_wide_s8_m (p0, z0, z4), + z0 = svasr_wide_m (p0, z0, z4)) + +/* +** asr_wide_s8_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s8_m_tied2, svint8_t, svuint64_t, + z0_res = svasr_wide_s8_m (p0, z4, z0), + z0_res = svasr_wide_m (p0, z4, z0)) + +/* +** asr_wide_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_m_untied, svint8_t, svuint64_t, + z0 = svasr_wide_s8_m (p0, z1, z4), + z0 = svasr_wide_m (p0, z1, z4)) + +/* +** asr_wide_x0_s8_m_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_m_tied1, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_m (p0, z0, x0), + z0 = svasr_wide_m (p0, z0, x0)) + +/* +** asr_wide_x0_s8_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_m_untied, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_m (p0, z1, x0), + z0 = svasr_wide_m (p0, z1, x0)) + +/* +** asr_wide_1_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_m_tied1, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z0, 1), + z0 = svasr_wide_m (p0, z0, 1)) + +/* +** asr_wide_1_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_m_untied, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z1, 1), + z0 = svasr_wide_m (p0, z1, 1)) + +/* +** asr_wide_7_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_m_tied1, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z0, 7), + z0 = svasr_wide_m (p0, z0, 7)) + +/* +** asr_wide_7_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_m_untied, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z1, 7), + z0 = svasr_wide_m (p0, z1, 7)) + +/* +** asr_wide_8_s8_m_tied1: +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_m_tied1, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z0, 8), + z0 = svasr_wide_m (p0, z0, 8)) + +/* +** asr_wide_8_s8_m_untied: +** movprfx z0, z1 +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_m_untied, svint8_t, + z0 = svasr_wide_n_s8_m (p0, z1, 8), + z0 = svasr_wide_m (p0, z1, 8)) + +/* +** asr_wide_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_z_tied1, svint8_t, svuint64_t, + z0 = svasr_wide_s8_z (p0, z0, z4), + z0 = svasr_wide_z (p0, z0, z4)) + +/* +** asr_wide_s8_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.b, p0/z, z4\.b +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s8_z_tied2, svint8_t, svuint64_t, + z0_res = svasr_wide_s8_z (p0, z4, z0), + z0_res = svasr_wide_z (p0, z4, z0)) + +/* +** asr_wide_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_z_untied, svint8_t, svuint64_t, + z0 = svasr_wide_s8_z (p0, z1, z4), + z0 = svasr_wide_z (p0, z1, z4)) + +/* +** asr_wide_x0_s8_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_z_tied1, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_z (p0, z0, x0), + z0 = svasr_wide_z (p0, z0, x0)) + +/* +** asr_wide_x0_s8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_z_untied, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_z (p0, z1, x0), + z0 = svasr_wide_z (p0, z1, x0)) + +/* +** asr_wide_1_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_z_tied1, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z0, 1), + z0 = svasr_wide_z (p0, z0, 1)) + +/* +** asr_wide_1_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_z_untied, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z1, 1), + z0 = svasr_wide_z (p0, z1, 1)) + +/* +** asr_wide_7_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_z_tied1, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z0, 7), + z0 = svasr_wide_z (p0, z0, 7)) + +/* +** asr_wide_7_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_z_untied, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z1, 7), + z0 = svasr_wide_z (p0, z1, 7)) + +/* +** asr_wide_8_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_z_tied1, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z0, 8), + z0 = svasr_wide_z (p0, z0, 8)) + +/* +** asr_wide_8_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_z_untied, svint8_t, + z0 = svasr_wide_n_s8_z (p0, z1, 8), + z0 = svasr_wide_z (p0, z1, 8)) + +/* +** asr_wide_s8_x_tied1: +** asr z0\.b, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_x_tied1, svint8_t, svuint64_t, + z0 = svasr_wide_s8_x (p0, z0, z4), + z0 = svasr_wide_x (p0, z0, z4)) + +/* +** asr_wide_s8_x_tied2: +** asr z0\.b, z4\.b, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (asr_wide_s8_x_tied2, svint8_t, svuint64_t, + z0_res = svasr_wide_s8_x (p0, z4, z0), + z0_res = svasr_wide_x (p0, z4, z0)) + +/* +** asr_wide_s8_x_untied: +** asr z0\.b, z1\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (asr_wide_s8_x_untied, svint8_t, svuint64_t, + z0 = svasr_wide_s8_x (p0, z1, z4), + z0 = svasr_wide_x (p0, z1, z4)) + +/* +** asr_wide_x0_s8_x_tied1: +** mov (z[0-9]+\.d), x0 +** asr z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_x_tied1, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_x (p0, z0, x0), + z0 = svasr_wide_x (p0, z0, x0)) + +/* +** asr_wide_x0_s8_x_untied: +** mov (z[0-9]+\.d), x0 +** asr z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (asr_wide_x0_s8_x_untied, svint8_t, uint64_t, + z0 = svasr_wide_n_s8_x (p0, z1, x0), + z0 = svasr_wide_x (p0, z1, x0)) + +/* +** asr_wide_1_s8_x_tied1: +** asr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_x_tied1, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z0, 1), + z0 = svasr_wide_x (p0, z0, 1)) + +/* +** asr_wide_1_s8_x_untied: +** asr z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_1_s8_x_untied, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z1, 1), + z0 = svasr_wide_x (p0, z1, 1)) + +/* +** asr_wide_7_s8_x_tied1: +** asr z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_x_tied1, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z0, 7), + z0 = svasr_wide_x (p0, z0, 7)) + +/* +** asr_wide_7_s8_x_untied: +** asr z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_7_s8_x_untied, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z1, 7), + z0 = svasr_wide_x (p0, z1, 7)) + +/* +** asr_wide_8_s8_x_tied1: +** asr z0\.b, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_x_tied1, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z0, 8), + z0 = svasr_wide_x (p0, z0, 8)) + +/* +** asr_wide_8_s8_x_untied: +** asr z0\.b, z1\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asr_wide_8_s8_x_untied, svint8_t, + z0 = svasr_wide_n_s8_x (p0, z1, 8), + z0 = svasr_wide_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s16.c new file mode 100644 index 00000000000..40bbce04216 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s16.c @@ -0,0 +1,177 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asrd_1_s16_m_tied1: +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_m_tied1, svint16_t, + z0 = svasrd_n_s16_m (p0, z0, 1), + z0 = svasrd_m (p0, z0, 1)) + +/* +** asrd_1_s16_m_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_m_untied, svint16_t, + z0 = svasrd_n_s16_m (p0, z1, 1), + z0 = svasrd_m (p0, z1, 1)) + +/* +** asrd_2_s16_m_tied1: +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_m_tied1, svint16_t, + z0 = svasrd_n_s16_m (p0, z0, 2), + z0 = svasrd_m (p0, z0, 2)) + +/* +** asrd_2_s16_m_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_m_untied, svint16_t, + z0 = svasrd_n_s16_m (p0, z1, 2), + z0 = svasrd_m (p0, z1, 2)) + +/* +** asrd_16_s16_m_tied1: +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_m_tied1, svint16_t, + z0 = svasrd_n_s16_m (p0, z0, 16), + z0 = svasrd_m (p0, z0, 16)) + +/* +** asrd_16_s16_m_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_m_untied, svint16_t, + z0 = svasrd_n_s16_m (p0, z1, 16), + z0 = svasrd_m (p0, z1, 16)) + +/* +** asrd_1_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_z_tied1, svint16_t, + z0 = svasrd_n_s16_z (p0, z0, 1), + z0 = svasrd_z (p0, z0, 1)) + +/* +** asrd_1_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_z_untied, svint16_t, + z0 = svasrd_n_s16_z (p0, z1, 1), + z0 = svasrd_z (p0, z1, 1)) + +/* +** asrd_2_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_z_tied1, svint16_t, + z0 = svasrd_n_s16_z (p0, z0, 2), + z0 = svasrd_z (p0, z0, 2)) + +/* +** asrd_2_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_z_untied, svint16_t, + z0 = svasrd_n_s16_z (p0, z1, 2), + z0 = svasrd_z (p0, z1, 2)) + +/* +** asrd_16_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_z_tied1, svint16_t, + z0 = svasrd_n_s16_z (p0, z0, 16), + z0 = svasrd_z (p0, z0, 16)) + +/* +** asrd_16_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_z_untied, svint16_t, + z0 = svasrd_n_s16_z (p0, z1, 16), + z0 = svasrd_z (p0, z1, 16)) + +/* +** asrd_1_s16_x_tied1: +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_x_tied1, svint16_t, + z0 = svasrd_n_s16_x (p0, z0, 1), + z0 = svasrd_x (p0, z0, 1)) + +/* +** asrd_1_s16_x_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s16_x_untied, svint16_t, + z0 = svasrd_n_s16_x (p0, z1, 1), + z0 = svasrd_x (p0, z1, 1)) + +/* +** asrd_2_s16_x_tied1: +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_x_tied1, svint16_t, + z0 = svasrd_n_s16_x (p0, z0, 2), + z0 = svasrd_x (p0, z0, 2)) + +/* +** asrd_2_s16_x_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s16_x_untied, svint16_t, + z0 = svasrd_n_s16_x (p0, z1, 2), + z0 = svasrd_x (p0, z1, 2)) + +/* +** asrd_16_s16_x_tied1: +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_x_tied1, svint16_t, + z0 = svasrd_n_s16_x (p0, z0, 16), + z0 = svasrd_x (p0, z0, 16)) + +/* +** asrd_16_s16_x_untied: +** movprfx z0, z1 +** asrd z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (asrd_16_s16_x_untied, svint16_t, + z0 = svasrd_n_s16_x (p0, z1, 16), + z0 = svasrd_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s32.c new file mode 100644 index 00000000000..0760b03deed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s32.c @@ -0,0 +1,177 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asrd_1_s32_m_tied1: +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_m_tied1, svint32_t, + z0 = svasrd_n_s32_m (p0, z0, 1), + z0 = svasrd_m (p0, z0, 1)) + +/* +** asrd_1_s32_m_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_m_untied, svint32_t, + z0 = svasrd_n_s32_m (p0, z1, 1), + z0 = svasrd_m (p0, z1, 1)) + +/* +** asrd_2_s32_m_tied1: +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_m_tied1, svint32_t, + z0 = svasrd_n_s32_m (p0, z0, 2), + z0 = svasrd_m (p0, z0, 2)) + +/* +** asrd_2_s32_m_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_m_untied, svint32_t, + z0 = svasrd_n_s32_m (p0, z1, 2), + z0 = svasrd_m (p0, z1, 2)) + +/* +** asrd_32_s32_m_tied1: +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_m_tied1, svint32_t, + z0 = svasrd_n_s32_m (p0, z0, 32), + z0 = svasrd_m (p0, z0, 32)) + +/* +** asrd_32_s32_m_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_m_untied, svint32_t, + z0 = svasrd_n_s32_m (p0, z1, 32), + z0 = svasrd_m (p0, z1, 32)) + +/* +** asrd_1_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_z_tied1, svint32_t, + z0 = svasrd_n_s32_z (p0, z0, 1), + z0 = svasrd_z (p0, z0, 1)) + +/* +** asrd_1_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_z_untied, svint32_t, + z0 = svasrd_n_s32_z (p0, z1, 1), + z0 = svasrd_z (p0, z1, 1)) + +/* +** asrd_2_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_z_tied1, svint32_t, + z0 = svasrd_n_s32_z (p0, z0, 2), + z0 = svasrd_z (p0, z0, 2)) + +/* +** asrd_2_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_z_untied, svint32_t, + z0 = svasrd_n_s32_z (p0, z1, 2), + z0 = svasrd_z (p0, z1, 2)) + +/* +** asrd_32_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_z_tied1, svint32_t, + z0 = svasrd_n_s32_z (p0, z0, 32), + z0 = svasrd_z (p0, z0, 32)) + +/* +** asrd_32_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_z_untied, svint32_t, + z0 = svasrd_n_s32_z (p0, z1, 32), + z0 = svasrd_z (p0, z1, 32)) + +/* +** asrd_1_s32_x_tied1: +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_x_tied1, svint32_t, + z0 = svasrd_n_s32_x (p0, z0, 1), + z0 = svasrd_x (p0, z0, 1)) + +/* +** asrd_1_s32_x_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s32_x_untied, svint32_t, + z0 = svasrd_n_s32_x (p0, z1, 1), + z0 = svasrd_x (p0, z1, 1)) + +/* +** asrd_2_s32_x_tied1: +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_x_tied1, svint32_t, + z0 = svasrd_n_s32_x (p0, z0, 2), + z0 = svasrd_x (p0, z0, 2)) + +/* +** asrd_2_s32_x_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s32_x_untied, svint32_t, + z0 = svasrd_n_s32_x (p0, z1, 2), + z0 = svasrd_x (p0, z1, 2)) + +/* +** asrd_32_s32_x_tied1: +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_x_tied1, svint32_t, + z0 = svasrd_n_s32_x (p0, z0, 32), + z0 = svasrd_x (p0, z0, 32)) + +/* +** asrd_32_s32_x_untied: +** movprfx z0, z1 +** asrd z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (asrd_32_s32_x_untied, svint32_t, + z0 = svasrd_n_s32_x (p0, z1, 32), + z0 = svasrd_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s64.c new file mode 100644 index 00000000000..0ef26c9fe81 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s64.c @@ -0,0 +1,177 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asrd_1_s64_m_tied1: +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_m_tied1, svint64_t, + z0 = svasrd_n_s64_m (p0, z0, 1), + z0 = svasrd_m (p0, z0, 1)) + +/* +** asrd_1_s64_m_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_m_untied, svint64_t, + z0 = svasrd_n_s64_m (p0, z1, 1), + z0 = svasrd_m (p0, z1, 1)) + +/* +** asrd_2_s64_m_tied1: +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_m_tied1, svint64_t, + z0 = svasrd_n_s64_m (p0, z0, 2), + z0 = svasrd_m (p0, z0, 2)) + +/* +** asrd_2_s64_m_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_m_untied, svint64_t, + z0 = svasrd_n_s64_m (p0, z1, 2), + z0 = svasrd_m (p0, z1, 2)) + +/* +** asrd_64_s64_m_tied1: +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_m_tied1, svint64_t, + z0 = svasrd_n_s64_m (p0, z0, 64), + z0 = svasrd_m (p0, z0, 64)) + +/* +** asrd_64_s64_m_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_m_untied, svint64_t, + z0 = svasrd_n_s64_m (p0, z1, 64), + z0 = svasrd_m (p0, z1, 64)) + +/* +** asrd_1_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_z_tied1, svint64_t, + z0 = svasrd_n_s64_z (p0, z0, 1), + z0 = svasrd_z (p0, z0, 1)) + +/* +** asrd_1_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_z_untied, svint64_t, + z0 = svasrd_n_s64_z (p0, z1, 1), + z0 = svasrd_z (p0, z1, 1)) + +/* +** asrd_2_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_z_tied1, svint64_t, + z0 = svasrd_n_s64_z (p0, z0, 2), + z0 = svasrd_z (p0, z0, 2)) + +/* +** asrd_2_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_z_untied, svint64_t, + z0 = svasrd_n_s64_z (p0, z1, 2), + z0 = svasrd_z (p0, z1, 2)) + +/* +** asrd_64_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_z_tied1, svint64_t, + z0 = svasrd_n_s64_z (p0, z0, 64), + z0 = svasrd_z (p0, z0, 64)) + +/* +** asrd_64_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_z_untied, svint64_t, + z0 = svasrd_n_s64_z (p0, z1, 64), + z0 = svasrd_z (p0, z1, 64)) + +/* +** asrd_1_s64_x_tied1: +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_x_tied1, svint64_t, + z0 = svasrd_n_s64_x (p0, z0, 1), + z0 = svasrd_x (p0, z0, 1)) + +/* +** asrd_1_s64_x_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s64_x_untied, svint64_t, + z0 = svasrd_n_s64_x (p0, z1, 1), + z0 = svasrd_x (p0, z1, 1)) + +/* +** asrd_2_s64_x_tied1: +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_x_tied1, svint64_t, + z0 = svasrd_n_s64_x (p0, z0, 2), + z0 = svasrd_x (p0, z0, 2)) + +/* +** asrd_2_s64_x_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s64_x_untied, svint64_t, + z0 = svasrd_n_s64_x (p0, z1, 2), + z0 = svasrd_x (p0, z1, 2)) + +/* +** asrd_64_s64_x_tied1: +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_x_tied1, svint64_t, + z0 = svasrd_n_s64_x (p0, z0, 64), + z0 = svasrd_x (p0, z0, 64)) + +/* +** asrd_64_s64_x_untied: +** movprfx z0, z1 +** asrd z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (asrd_64_s64_x_untied, svint64_t, + z0 = svasrd_n_s64_x (p0, z1, 64), + z0 = svasrd_x (p0, z1, 64)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s8.c new file mode 100644 index 00000000000..9249ffbcb64 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asrd_s8.c @@ -0,0 +1,177 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** asrd_1_s8_m_tied1: +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_m_tied1, svint8_t, + z0 = svasrd_n_s8_m (p0, z0, 1), + z0 = svasrd_m (p0, z0, 1)) + +/* +** asrd_1_s8_m_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_m_untied, svint8_t, + z0 = svasrd_n_s8_m (p0, z1, 1), + z0 = svasrd_m (p0, z1, 1)) + +/* +** asrd_2_s8_m_tied1: +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_m_tied1, svint8_t, + z0 = svasrd_n_s8_m (p0, z0, 2), + z0 = svasrd_m (p0, z0, 2)) + +/* +** asrd_2_s8_m_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_m_untied, svint8_t, + z0 = svasrd_n_s8_m (p0, z1, 2), + z0 = svasrd_m (p0, z1, 2)) + +/* +** asrd_8_s8_m_tied1: +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_m_tied1, svint8_t, + z0 = svasrd_n_s8_m (p0, z0, 8), + z0 = svasrd_m (p0, z0, 8)) + +/* +** asrd_8_s8_m_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_m_untied, svint8_t, + z0 = svasrd_n_s8_m (p0, z1, 8), + z0 = svasrd_m (p0, z1, 8)) + +/* +** asrd_1_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_z_tied1, svint8_t, + z0 = svasrd_n_s8_z (p0, z0, 1), + z0 = svasrd_z (p0, z0, 1)) + +/* +** asrd_1_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_z_untied, svint8_t, + z0 = svasrd_n_s8_z (p0, z1, 1), + z0 = svasrd_z (p0, z1, 1)) + +/* +** asrd_2_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_z_tied1, svint8_t, + z0 = svasrd_n_s8_z (p0, z0, 2), + z0 = svasrd_z (p0, z0, 2)) + +/* +** asrd_2_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_z_untied, svint8_t, + z0 = svasrd_n_s8_z (p0, z1, 2), + z0 = svasrd_z (p0, z1, 2)) + +/* +** asrd_8_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_z_tied1, svint8_t, + z0 = svasrd_n_s8_z (p0, z0, 8), + z0 = svasrd_z (p0, z0, 8)) + +/* +** asrd_8_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_z_untied, svint8_t, + z0 = svasrd_n_s8_z (p0, z1, 8), + z0 = svasrd_z (p0, z1, 8)) + +/* +** asrd_1_s8_x_tied1: +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_x_tied1, svint8_t, + z0 = svasrd_n_s8_x (p0, z0, 1), + z0 = svasrd_x (p0, z0, 1)) + +/* +** asrd_1_s8_x_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (asrd_1_s8_x_untied, svint8_t, + z0 = svasrd_n_s8_x (p0, z1, 1), + z0 = svasrd_x (p0, z1, 1)) + +/* +** asrd_2_s8_x_tied1: +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_x_tied1, svint8_t, + z0 = svasrd_n_s8_x (p0, z0, 2), + z0 = svasrd_x (p0, z0, 2)) + +/* +** asrd_2_s8_x_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (asrd_2_s8_x_untied, svint8_t, + z0 = svasrd_n_s8_x (p0, z1, 2), + z0 = svasrd_x (p0, z1, 2)) + +/* +** asrd_8_s8_x_tied1: +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_x_tied1, svint8_t, + z0 = svasrd_n_s8_x (p0, z0, 8), + z0 = svasrd_x (p0, z0, 8)) + +/* +** asrd_8_s8_x_untied: +** movprfx z0, z1 +** asrd z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (asrd_8_s8_x_untied, svint8_t, + z0 = svasrd_n_s8_x (p0, z1, 8), + z0 = svasrd_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_b.c new file mode 100644 index 00000000000..9d41aeaa2fd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_b_z_tied1: +** bic p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (bic_b_z_tied1, + p0 = svbic_b_z (p3, p0, p1), + p0 = svbic_z (p3, p0, p1)) + +/* +** bic_b_z_tied2: +** bic p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (bic_b_z_tied2, + p0 = svbic_b_z (p3, p1, p0), + p0 = svbic_z (p3, p1, p0)) + +/* +** bic_b_z_untied: +** bic p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (bic_b_z_untied, + p0 = svbic_b_z (p3, p1, p2), + p0 = svbic_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c new file mode 100644 index 00000000000..c80f5697f5f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c @@ -0,0 +1,367 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_s16_m_tied1: +** bic z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_m_tied1, svint16_t, + z0 = svbic_s16_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_m_tied2, svint16_t, + z0 = svbic_s16_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_s16_m_untied: +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_m_untied, svint16_t, + z0 = svbic_s16_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svbic_n_s16_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_m_untied, svint16_t, int16_t, + z0 = svbic_n_s16_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_s16_m_tied1: +** mov (z[0-9]+\.h), #-2 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_m_tied1, svint16_t, + z0 = svbic_n_s16_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #-2 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_m_untied, svint16_t, + z0 = svbic_n_s16_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_s16_m: +** mov (z[0-9]+\.h), #1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_s16_m, svint16_t, + z0 = svbic_n_s16_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** bic z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_z_tied1, svint16_t, + z0 = svbic_s16_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_s16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_z_tied2, svint16_t, + z0 = svbic_s16_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bic_s16_z_untied, svint16_t, + z0 = svbic_s16_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svbic_n_s16_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_s16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_z_untied, svint16_t, int16_t, + z0 = svbic_n_s16_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_s16_z_tied1: +** mov (z[0-9]+\.h), #-2 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_z_tied1, svint16_t, + z0 = svbic_n_s16_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_s16_z_untied: +** mov (z[0-9]+\.h), #-2 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_z_untied, svint16_t, + z0 = svbic_n_s16_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_s16_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s16_x_tied1, svint16_t, + z0 = svbic_s16_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_s16_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s16_x_tied2, svint16_t, + z0 = svbic_s16_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_s16_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s16_x_untied, svint16_t, + z0 = svbic_s16_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_s16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svbic_n_s16_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_s16_x_untied: +** mov (z[0-9]+)\.h, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s16_x_untied, svint16_t, int16_t, + z0 = svbic_n_s16_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_s16_x_tied1: +** and z0\.h, z0\.h, #0xfffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_x_tied1, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_s16_x_untied: +** movprfx z0, z1 +** and z0\.h, z0\.h, #0xfffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s16_x_untied, svint16_t, + z0 = svbic_n_s16_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_s16_x: +** and z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_s16_x: +** and z0\.h, z0\.h, #0xff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_s16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_s16_x: +** and z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* +** bic_257_s16_x: +** and z0\.h, z0\.h, #0xfefe +** ret +*/ +TEST_UNIFORM_Z (bic_257_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_s16_x: +** and z0\.h, z0\.h, #0xfdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_s16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_s16_x: +** and z0\.h, z0\.h, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_s16_x: +** and z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_s16_x: +** and z0\.h, z0\.h, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_s16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_s16_x: +** and z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_s16_x: +** and z0\.h, z0\.h, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_s16_x: +** and z0\.h, z0\.h, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_s16_x: +** mov (z[0-9]+)\.h, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_s16_x, svint16_t, + z0 = svbic_n_s16_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s32.c new file mode 100644 index 00000000000..9e388e499b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s32.c @@ -0,0 +1,363 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_s32_m_tied1: +** bic z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_m_tied1, svint32_t, + z0 = svbic_s32_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_m_tied2, svint32_t, + z0 = svbic_s32_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_s32_m_untied: +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_m_untied, svint32_t, + z0 = svbic_s32_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svbic_n_s32_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_m_untied, svint32_t, int32_t, + z0 = svbic_n_s32_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_s32_m_tied1: +** mov (z[0-9]+\.s), #-2 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_m_tied1, svint32_t, + z0 = svbic_n_s32_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #-2 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_m_untied, svint32_t, + z0 = svbic_n_s32_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_s32_m: +** mov (z[0-9]+\.s), #1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_s32_m, svint32_t, + z0 = svbic_n_s32_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** bic z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_z_tied1, svint32_t, + z0 = svbic_s32_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_s32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_z_tied2, svint32_t, + z0 = svbic_s32_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bic_s32_z_untied, svint32_t, + z0 = svbic_s32_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svbic_n_s32_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_s32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_z_untied, svint32_t, int32_t, + z0 = svbic_n_s32_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_s32_z_tied1: +** mov (z[0-9]+\.s), #-2 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_z_tied1, svint32_t, + z0 = svbic_n_s32_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_s32_z_untied: +** mov (z[0-9]+\.s), #-2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_z_untied, svint32_t, + z0 = svbic_n_s32_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_s32_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s32_x_tied1, svint32_t, + z0 = svbic_s32_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_s32_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s32_x_tied2, svint32_t, + z0 = svbic_s32_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_s32_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s32_x_untied, svint32_t, + z0 = svbic_s32_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_s32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svbic_n_s32_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_s32_x_untied: +** mov (z[0-9]+)\.s, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s32_x_untied, svint32_t, int32_t, + z0 = svbic_n_s32_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_s32_x_tied1: +** and z0\.s, z0\.s, #0xfffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_x_tied1, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_s32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0xfffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s32_x_untied, svint32_t, + z0 = svbic_n_s32_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_s32_x: +** and z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_s32_x: +** and z0\.s, z0\.s, #0xffffff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_s32_x: +** and z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_s32_x: +** and z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (bic_257_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_s32_x: +** and z0\.s, z0\.s, #0xfffffdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_s32_x: +** and z0\.s, z0\.s, #0xffff00ff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_s32_x: +** and z0\.s, z0\.s, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_s32_x: +** and z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_s32_x: +** and z0\.s, z0\.s, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_s32_x: +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_s32_x: +** and z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_s32_x: +** and z0\.s, z0\.s, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_s32_x: +** and z0\.s, z0\.s, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_s32_x: +** mov (z[0-9]+)\.s, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_s32_x, svint32_t, + z0 = svbic_n_s32_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s64.c new file mode 100644 index 00000000000..bf953681547 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s64.c @@ -0,0 +1,363 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_s64_m_tied1: +** bic z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_m_tied1, svint64_t, + z0 = svbic_s64_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_s64_m_tied2, svint64_t, + z0 = svbic_s64_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_s64_m_untied: +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_m_untied, svint64_t, + z0 = svbic_s64_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svbic_n_s64_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_m_untied, svint64_t, int64_t, + z0 = svbic_n_s64_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_s64_m_tied1: +** mov (z[0-9]+\.d), #-2 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_m_tied1, svint64_t, + z0 = svbic_n_s64_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #-2 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_m_untied, svint64_t, + z0 = svbic_n_s64_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_s64_m: +** mov (z[0-9]+\.d), #1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_s64_m, svint64_t, + z0 = svbic_n_s64_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** bic z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_z_tied1, svint64_t, + z0 = svbic_s64_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_s64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_s64_z_tied2, svint64_t, + z0 = svbic_s64_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_z_untied, svint64_t, + z0 = svbic_s64_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svbic_n_s64_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_x0_s64_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_z_untied, svint64_t, int64_t, + z0 = svbic_n_s64_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_s64_z_tied1: +** mov (z[0-9]+\.d), #-2 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_z_tied1, svint64_t, + z0 = svbic_n_s64_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_s64_z_untied: +** mov (z[0-9]+\.d), #-2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_z_untied, svint64_t, + z0 = svbic_n_s64_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_s64_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_x_tied1, svint64_t, + z0 = svbic_s64_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_s64_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_x_tied2, svint64_t, + z0 = svbic_s64_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_s64_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s64_x_untied, svint64_t, + z0 = svbic_s64_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svbic_n_s64_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_s64_x_untied, svint64_t, int64_t, + z0 = svbic_n_s64_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_s64_x_tied1: +** and z0\.d, z0\.d, #0xfffffffffffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_x_tied1, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_s64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0xfffffffffffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s64_x_untied, svint64_t, + z0 = svbic_n_s64_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_s64_x: +** and z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_s64_x: +** and z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (bic_257_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_s64_x: +** and z0\.d, z0\.d, #0xfffffffffffffdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_s64_x: +** and z0\.d, z0\.d, #0xffffffffffff00ff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_s64_x: +** and z0\.d, z0\.d, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_s64_x: +** and z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_s64_x: +** and z0\.d, z0\.d, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_s64_x: +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_s64_x: +** and z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_s64_x: +** and z0\.d, z0\.d, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_s64_x: +** and z0\.d, z0\.d, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_s64_x: +** mov (z[0-9]+\.d), #-6 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_s64_x, svint64_t, + z0 = svbic_n_s64_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c new file mode 100644 index 00000000000..0958a340393 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_s8_m_tied1: +** bic z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_m_tied1, svint8_t, + z0 = svbic_s8_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_m_tied2, svint8_t, + z0 = svbic_s8_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_s8_m_untied: +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_m_untied, svint8_t, + z0 = svbic_s8_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svbic_n_s8_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_m_untied, svint8_t, int8_t, + z0 = svbic_n_s8_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_s8_m_tied1: +** mov (z[0-9]+\.b), #-2 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_m_tied1, svint8_t, + z0 = svbic_n_s8_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #-2 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_m_untied, svint8_t, + z0 = svbic_n_s8_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_s8_m: +** mov (z[0-9]+\.b), #1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_s8_m, svint8_t, + z0 = svbic_n_s8_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** bic z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_z_tied1, svint8_t, + z0 = svbic_s8_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_s8_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_z_tied2, svint8_t, + z0 = svbic_s8_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bic_s8_z_untied, svint8_t, + z0 = svbic_s8_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svbic_n_s8_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_s8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_z_untied, svint8_t, int8_t, + z0 = svbic_n_s8_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_s8_z_tied1: +** mov (z[0-9]+\.b), #-2 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_z_tied1, svint8_t, + z0 = svbic_n_s8_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_s8_z_untied: +** mov (z[0-9]+\.b), #-2 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_z_untied, svint8_t, + z0 = svbic_n_s8_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_s8_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s8_x_tied1, svint8_t, + z0 = svbic_s8_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_s8_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s8_x_tied2, svint8_t, + z0 = svbic_s8_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_s8_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_s8_x_untied, svint8_t, + z0 = svbic_s8_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_s8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svbic_n_s8_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_s8_x_untied: +** mov (z[0-9]+)\.b, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_s8_x_untied, svint8_t, int8_t, + z0 = svbic_n_s8_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_s8_x_tied1: +** and z0\.b, z0\.b, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_x_tied1, svint8_t, + z0 = svbic_n_s8_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_s8_x_untied: +** movprfx z0, z1 +** and z0\.b, z0\.b, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_1_s8_x_untied, svint8_t, + z0 = svbic_n_s8_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_s8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_s8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_s8_x: +** mov z0\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (bic_255_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_m127_s8_x: +** and z0\.b, z0\.b, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_s8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_5_s8_x: +** mov (z[0-9]+)\.b, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_s8_x, svint8_t, + z0 = svbic_n_s8_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c new file mode 100644 index 00000000000..30209ffb418 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c @@ -0,0 +1,367 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_u16_m_tied1: +** bic z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_m_tied1, svuint16_t, + z0 = svbic_u16_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_m_tied2, svuint16_t, + z0 = svbic_u16_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_u16_m_untied: +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_m_untied, svuint16_t, + z0 = svbic_u16_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svbic_n_u16_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svbic_n_u16_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_u16_m_tied1: +** mov (z[0-9]+\.h), #-2 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_m_tied1, svuint16_t, + z0 = svbic_n_u16_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #-2 +** movprfx z0, z1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_m_untied, svuint16_t, + z0 = svbic_n_u16_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_u16_m: +** mov (z[0-9]+\.h), #1 +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_u16_m, svuint16_t, + z0 = svbic_n_u16_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** bic z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_z_tied1, svuint16_t, + z0 = svbic_u16_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_u16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_z_tied2, svuint16_t, + z0 = svbic_u16_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bic_u16_z_untied, svuint16_t, + z0 = svbic_u16_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svbic_n_u16_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_u16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z1\.h +** bic z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svbic_n_u16_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_u16_z_tied1: +** mov (z[0-9]+\.h), #-2 +** movprfx z0\.h, p0/z, z0\.h +** and z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_z_tied1, svuint16_t, + z0 = svbic_n_u16_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_u16_z_untied: +** mov (z[0-9]+\.h), #-2 +** ( +** movprfx z0\.h, p0/z, z1\.h +** and z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** and z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_z_untied, svuint16_t, + z0 = svbic_n_u16_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_u16_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u16_x_tied1, svuint16_t, + z0 = svbic_u16_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_u16_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u16_x_tied2, svuint16_t, + z0 = svbic_u16_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_u16_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u16_x_untied, svuint16_t, + z0 = svbic_u16_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_u16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svbic_n_u16_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_u16_x_untied: +** mov (z[0-9]+)\.h, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svbic_n_u16_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_u16_x_tied1: +** and z0\.h, z0\.h, #0xfffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_x_tied1, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_u16_x_untied: +** movprfx z0, z1 +** and z0\.h, z0\.h, #0xfffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u16_x_untied, svuint16_t, + z0 = svbic_n_u16_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_u16_x: +** and z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_u16_x: +** and z0\.h, z0\.h, #0xff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_u16_x: +** and z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_u16_x: +** and z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* +** bic_257_u16_x: +** and z0\.h, z0\.h, #0xfefe +** ret +*/ +TEST_UNIFORM_Z (bic_257_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_u16_x: +** and z0\.h, z0\.h, #0xfdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_u16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_u16_x: +** and z0\.h, z0\.h, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_u16_x: +** and z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_u16_x: +** and z0\.h, z0\.h, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_u16_x: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_u16_x: +** and z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_u16_x: +** and z0\.h, z0\.h, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_u16_x: +** and z0\.h, z0\.h, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_u16_x: +** mov (z[0-9]+)\.h, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_u16_x, svuint16_t, + z0 = svbic_n_u16_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u32.c new file mode 100644 index 00000000000..b308b599b43 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u32.c @@ -0,0 +1,363 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_u32_m_tied1: +** bic z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_m_tied1, svuint32_t, + z0 = svbic_u32_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_m_tied2, svuint32_t, + z0 = svbic_u32_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_u32_m_untied: +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_m_untied, svuint32_t, + z0 = svbic_u32_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svbic_n_u32_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svbic_n_u32_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_u32_m_tied1: +** mov (z[0-9]+\.s), #-2 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_m_tied1, svuint32_t, + z0 = svbic_n_u32_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #-2 +** movprfx z0, z1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_m_untied, svuint32_t, + z0 = svbic_n_u32_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_u32_m: +** mov (z[0-9]+\.s), #1 +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_u32_m, svuint32_t, + z0 = svbic_n_u32_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** bic z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_z_tied1, svuint32_t, + z0 = svbic_u32_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_u32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_z_tied2, svuint32_t, + z0 = svbic_u32_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bic_u32_z_untied, svuint32_t, + z0 = svbic_u32_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svbic_n_u32_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_u32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z1\.s +** bic z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svbic_n_u32_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_u32_z_tied1: +** mov (z[0-9]+\.s), #-2 +** movprfx z0\.s, p0/z, z0\.s +** and z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_z_tied1, svuint32_t, + z0 = svbic_n_u32_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_u32_z_untied: +** mov (z[0-9]+\.s), #-2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** and z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** and z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_z_untied, svuint32_t, + z0 = svbic_n_u32_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_u32_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u32_x_tied1, svuint32_t, + z0 = svbic_u32_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_u32_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u32_x_tied2, svuint32_t, + z0 = svbic_u32_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_u32_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u32_x_untied, svuint32_t, + z0 = svbic_u32_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_u32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svbic_n_u32_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_u32_x_untied: +** mov (z[0-9]+)\.s, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svbic_n_u32_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_u32_x_tied1: +** and z0\.s, z0\.s, #0xfffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_x_tied1, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_u32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0xfffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u32_x_untied, svuint32_t, + z0 = svbic_n_u32_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_u32_x: +** and z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_u32_x: +** and z0\.s, z0\.s, #0xffffff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_u32_x: +** and z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_u32_x: +** and z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (bic_257_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_u32_x: +** and z0\.s, z0\.s, #0xfffffdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_u32_x: +** and z0\.s, z0\.s, #0xffff00ff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_u32_x: +** and z0\.s, z0\.s, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_u32_x: +** and z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_u32_x: +** and z0\.s, z0\.s, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_u32_x: +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_u32_x: +** and z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_u32_x: +** and z0\.s, z0\.s, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_u32_x: +** and z0\.s, z0\.s, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_u32_x: +** mov (z[0-9]+)\.s, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_u32_x, svuint32_t, + z0 = svbic_n_u32_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u64.c new file mode 100644 index 00000000000..e82db1e94fd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u64.c @@ -0,0 +1,363 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_u64_m_tied1: +** bic z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_m_tied1, svuint64_t, + z0 = svbic_u64_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_u64_m_tied2, svuint64_t, + z0 = svbic_u64_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_u64_m_untied: +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_m_untied, svuint64_t, + z0 = svbic_u64_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svbic_n_u64_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svbic_n_u64_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_u64_m_tied1: +** mov (z[0-9]+\.d), #-2 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_m_tied1, svuint64_t, + z0 = svbic_n_u64_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #-2 +** movprfx z0, z1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_m_untied, svuint64_t, + z0 = svbic_n_u64_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_u64_m: +** mov (z[0-9]+\.d), #1 +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_u64_m, svuint64_t, + z0 = svbic_n_u64_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** bic z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_z_tied1, svuint64_t, + z0 = svbic_u64_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_u64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_u64_z_tied2, svuint64_t, + z0 = svbic_u64_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_z_untied, svuint64_t, + z0 = svbic_u64_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svbic_n_u64_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_x0_u64_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z1\.d +** bic z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svbic_n_u64_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_u64_z_tied1: +** mov (z[0-9]+\.d), #-2 +** movprfx z0\.d, p0/z, z0\.d +** and z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_z_tied1, svuint64_t, + z0 = svbic_n_u64_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_u64_z_untied: +** mov (z[0-9]+\.d), #-2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** and z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** and z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_z_untied, svuint64_t, + z0 = svbic_n_u64_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_u64_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_x_tied1, svuint64_t, + z0 = svbic_u64_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_u64_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_x_tied2, svuint64_t, + z0 = svbic_u64_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_u64_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u64_x_untied, svuint64_t, + z0 = svbic_u64_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svbic_n_u64_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** bic z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svbic_n_u64_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_u64_x_tied1: +** and z0\.d, z0\.d, #0xfffffffffffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_x_tied1, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_u64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0xfffffffffffffffe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u64_x_untied, svuint64_t, + z0 = svbic_n_u64_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_u64_x: +** and z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (bic_255_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_256_u64_x: +** and z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (bic_256_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 256), + z0 = svbic_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (bic_257_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 257), + z0 = svbic_x (p0, z0, 257)) + +/* +** bic_512_u64_x: +** and z0\.d, z0\.d, #0xfffffffffffffdff +** ret +*/ +TEST_UNIFORM_Z (bic_512_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 512), + z0 = svbic_x (p0, z0, 512)) + +/* +** bic_65280_u64_x: +** and z0\.d, z0\.d, #0xffffffffffff00ff +** ret +*/ +TEST_UNIFORM_Z (bic_65280_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 0xff00), + z0 = svbic_x (p0, z0, 0xff00)) + +/* +** bic_m127_u64_x: +** and z0\.d, z0\.d, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_u64_x: +** and z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_m255_u64_x: +** and z0\.d, z0\.d, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_m255_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -255), + z0 = svbic_x (p0, z0, -255)) + +/* +** bic_m256_u64_x: +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (bic_m256_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -256), + z0 = svbic_x (p0, z0, -256)) + +/* +** bic_m257_u64_x: +** and z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (bic_m257_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -257), + z0 = svbic_x (p0, z0, -257)) + +/* +** bic_m512_u64_x: +** and z0\.d, z0\.d, #0x1ff +** ret +*/ +TEST_UNIFORM_Z (bic_m512_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -512), + z0 = svbic_x (p0, z0, -512)) + +/* +** bic_m32768_u64_x: +** and z0\.d, z0\.d, #0x7fff +** ret +*/ +TEST_UNIFORM_Z (bic_m32768_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, -0x8000), + z0 = svbic_x (p0, z0, -0x8000)) + +/* +** bic_5_u64_x: +** mov (z[0-9]+\.d), #-6 +** and z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_u64_x, svuint64_t, + z0 = svbic_n_u64_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c new file mode 100644 index 00000000000..80c489b9cdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** bic_u8_m_tied1: +** bic z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_m_tied1, svuint8_t, + z0 = svbic_u8_m (p0, z0, z1), + z0 = svbic_m (p0, z0, z1)) + +/* +** bic_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_m_tied2, svuint8_t, + z0 = svbic_u8_m (p0, z1, z0), + z0 = svbic_m (p0, z1, z0)) + +/* +** bic_u8_m_untied: +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_m_untied, svuint8_t, + z0 = svbic_u8_m (p0, z1, z2), + z0 = svbic_m (p0, z1, z2)) + +/* +** bic_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svbic_n_u8_m (p0, z0, x0), + z0 = svbic_m (p0, z0, x0)) + +/* +** bic_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svbic_n_u8_m (p0, z1, x0), + z0 = svbic_m (p0, z1, x0)) + +/* +** bic_1_u8_m_tied1: +** mov (z[0-9]+\.b), #-2 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_m_tied1, svuint8_t, + z0 = svbic_n_u8_m (p0, z0, 1), + z0 = svbic_m (p0, z0, 1)) + +/* +** bic_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #-2 +** movprfx z0, z1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_m_untied, svuint8_t, + z0 = svbic_n_u8_m (p0, z1, 1), + z0 = svbic_m (p0, z1, 1)) + +/* +** bic_m2_u8_m: +** mov (z[0-9]+\.b), #1 +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_m2_u8_m, svuint8_t, + z0 = svbic_n_u8_m (p0, z0, -2), + z0 = svbic_m (p0, z0, -2)) + +/* +** bic_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** bic z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_z_tied1, svuint8_t, + z0 = svbic_u8_z (p0, z0, z1), + z0 = svbic_z (p0, z0, z1)) + +/* +** bic_u8_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_z_tied2, svuint8_t, + z0 = svbic_u8_z (p0, z1, z0), + z0 = svbic_z (p0, z1, z0)) + +/* +** bic_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bic_u8_z_untied, svuint8_t, + z0 = svbic_u8_z (p0, z1, z2), + z0 = svbic_z (p0, z1, z2)) + +/* +** bic_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svbic_n_u8_z (p0, z0, x0), + z0 = svbic_z (p0, z0, x0)) + +/* +** bic_w0_u8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z1\.b +** bic z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svbic_n_u8_z (p0, z1, x0), + z0 = svbic_z (p0, z1, x0)) + +/* +** bic_1_u8_z_tied1: +** mov (z[0-9]+\.b), #-2 +** movprfx z0\.b, p0/z, z0\.b +** and z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_z_tied1, svuint8_t, + z0 = svbic_n_u8_z (p0, z0, 1), + z0 = svbic_z (p0, z0, 1)) + +/* +** bic_1_u8_z_untied: +** mov (z[0-9]+\.b), #-2 +** ( +** movprfx z0\.b, p0/z, z1\.b +** and z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** and z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_z_untied, svuint8_t, + z0 = svbic_n_u8_z (p0, z1, 1), + z0 = svbic_z (p0, z1, 1)) + +/* +** bic_u8_x_tied1: +** bic z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u8_x_tied1, svuint8_t, + z0 = svbic_u8_x (p0, z0, z1), + z0 = svbic_x (p0, z0, z1)) + +/* +** bic_u8_x_tied2: +** bic z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u8_x_tied2, svuint8_t, + z0 = svbic_u8_x (p0, z1, z0), + z0 = svbic_x (p0, z1, z0)) + +/* +** bic_u8_x_untied: +** bic z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bic_u8_x_untied, svuint8_t, + z0 = svbic_u8_x (p0, z1, z2), + z0 = svbic_x (p0, z1, z2)) + +/* +** bic_w0_u8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** bic z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svbic_n_u8_x (p0, z0, x0), + z0 = svbic_x (p0, z0, x0)) + +/* +** bic_w0_u8_x_untied: +** mov (z[0-9]+)\.b, w0 +** bic z0\.d, z1\.d, \1\.d +** ret +*/ +TEST_UNIFORM_ZX (bic_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svbic_n_u8_x (p0, z1, x0), + z0 = svbic_x (p0, z1, x0)) + +/* +** bic_1_u8_x_tied1: +** and z0\.b, z0\.b, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_x_tied1, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, 1), + z0 = svbic_x (p0, z0, 1)) + +/* +** bic_1_u8_x_untied: +** movprfx z0, z1 +** and z0\.b, z0\.b, #0xfe +** ret +*/ +TEST_UNIFORM_Z (bic_1_u8_x_untied, svuint8_t, + z0 = svbic_n_u8_x (p0, z1, 1), + z0 = svbic_x (p0, z1, 1)) + +/* +** bic_127_u8_x: +** and z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (bic_127_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, 127), + z0 = svbic_x (p0, z0, 127)) + +/* +** bic_128_u8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_128_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, 128), + z0 = svbic_x (p0, z0, 128)) + +/* +** bic_255_u8_x: +** mov z0\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (bic_255_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, 255), + z0 = svbic_x (p0, z0, 255)) + +/* +** bic_m127_u8_x: +** and z0\.b, z0\.b, #0x7e +** ret +*/ +TEST_UNIFORM_Z (bic_m127_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, -127), + z0 = svbic_x (p0, z0, -127)) + +/* +** bic_m128_u8_x: +** and z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (bic_m128_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, -128), + z0 = svbic_x (p0, z0, -128)) + +/* +** bic_5_u8_x: +** mov (z[0-9]+)\.b, #-6 +** and z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (bic_5_u8_x, svuint8_t, + z0 = svbic_n_u8_x (p0, z0, 5), + z0 = svbic_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c new file mode 100644 index 00000000000..63426cf947d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brka_b.c @@ -0,0 +1,54 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** brka_b_m_tied12: +** brka p0\.b, p3/m, p0\.b +** ret +*/ +TEST_UNIFORM_P (brka_b_m_tied12, + p0 = svbrka_b_m (p0, p3, p0), + p0 = svbrka_m (p0, p3, p0)) + +/* +** brka_b_m_tied1: +** brka p0\.b, p3/m, p1\.b +** ret +*/ +TEST_UNIFORM_P (brka_b_m_tied1, + p0 = svbrka_b_m (p0, p3, p1), + p0 = svbrka_m (p0, p3, p1)) + +/* Bad RA choice: no preferred output sequence. */ +TEST_UNIFORM_P (brka_b_m_tied2, + p0 = svbrka_b_m (p1, p3, p0), + p0 = svbrka_m (p1, p3, p0)) + +/* +** brka_b_m_untied: +** mov p0\.b, p2\.b +** brka p0\.b, p3/m, p1\.b +** ret +*/ +TEST_UNIFORM_P (brka_b_m_untied, + p0 = svbrka_b_m (p2, p3, p1), + p0 = svbrka_m (p2, p3, p1)) + +/* +** brka_b_z_tied1: +** brka p0\.b, p3/z, p0\.b +** ret +*/ +TEST_UNIFORM_P (brka_b_z_tied1, + p0 = svbrka_b_z (p3, p0), + p0 = svbrka_z (p3, p0)) + +/* +** brka_b_z_untied: +** brka p0\.b, p3/z, p1\.b +** ret +*/ +TEST_UNIFORM_P (brka_b_z_untied, + p0 = svbrka_b_z (p3, p1), + p0 = svbrka_z (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c new file mode 100644 index 00000000000..4f9a2c2d7b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkb_b.c @@ -0,0 +1,54 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** brkb_b_m_tied12: +** brkb p0\.b, p3/m, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkb_b_m_tied12, + p0 = svbrkb_b_m (p0, p3, p0), + p0 = svbrkb_m (p0, p3, p0)) + +/* +** brkb_b_m_tied1: +** brkb p0\.b, p3/m, p1\.b +** ret +*/ +TEST_UNIFORM_P (brkb_b_m_tied1, + p0 = svbrkb_b_m (p0, p3, p1), + p0 = svbrkb_m (p0, p3, p1)) + +/* Bad RA choice: no preferred output sequence. */ +TEST_UNIFORM_P (brkb_b_m_tied2, + p0 = svbrkb_b_m (p1, p3, p0), + p0 = svbrkb_m (p1, p3, p0)) + +/* +** brkb_b_m_untied: +** mov p0\.b, p2\.b +** brkb p0\.b, p3/m, p1\.b +** ret +*/ +TEST_UNIFORM_P (brkb_b_m_untied, + p0 = svbrkb_b_m (p2, p3, p1), + p0 = svbrkb_m (p2, p3, p1)) + +/* +** brkb_b_z_tied1: +** brkb p0\.b, p3/z, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkb_b_z_tied1, + p0 = svbrkb_b_z (p3, p0), + p0 = svbrkb_z (p3, p0)) + +/* +** brkb_b_z_untied: +** brkb p0\.b, p3/z, p1\.b +** ret +*/ +TEST_UNIFORM_P (brkb_b_z_untied, + p0 = svbrkb_b_z (p3, p1), + p0 = svbrkb_z (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c new file mode 100644 index 00000000000..229a5fff9eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkn_b.c @@ -0,0 +1,27 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* Bad RA choice: no preferred output sequence. */ +TEST_UNIFORM_P (brkn_b_z_tied1, + p0 = svbrkn_b_z (p3, p0, p1), + p0 = svbrkn_z (p3, p0, p1)) + +/* +** brkn_b_z_tied2: +** brkn p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkn_b_z_tied2, + p0 = svbrkn_b_z (p3, p1, p0), + p0 = svbrkn_z (p3, p1, p0)) + +/* +** brkn_b_z_untied: +** mov p0\.b, p2\.b +** brkn p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkn_b_z_untied, + p0 = svbrkn_b_z (p3, p1, p2), + p0 = svbrkn_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpa_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpa_b.c new file mode 100644 index 00000000000..2c074e3893b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpa_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** brkpa_b_z_tied1: +** brkpa p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (brkpa_b_z_tied1, + p0 = svbrkpa_b_z (p3, p0, p1), + p0 = svbrkpa_z (p3, p0, p1)) + +/* +** brkpa_b_z_tied2: +** brkpa p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkpa_b_z_tied2, + p0 = svbrkpa_b_z (p3, p1, p0), + p0 = svbrkpa_z (p3, p1, p0)) + +/* +** brkpa_b_z_untied: +** brkpa p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (brkpa_b_z_untied, + p0 = svbrkpa_b_z (p3, p1, p2), + p0 = svbrkpa_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpb_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpb_b.c new file mode 100644 index 00000000000..b41797ee192 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/brkpb_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** brkpb_b_z_tied1: +** brkpb p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (brkpb_b_z_tied1, + p0 = svbrkpb_b_z (p3, p0, p1), + p0 = svbrkpb_z (p3, p0, p1)) + +/* +** brkpb_b_z_tied2: +** brkpb p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (brkpb_b_z_tied2, + p0 = svbrkpb_b_z (p3, p1, p0), + p0 = svbrkpb_z (p3, p1, p0)) + +/* +** brkpb_b_z_untied: +** brkpb p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (brkpb_b_z_untied, + p0 = svbrkpb_b_z (p3, p1, p2), + p0 = svbrkpb_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f16.c new file mode 100644 index 00000000000..e89c7845595 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f16.c @@ -0,0 +1,251 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cadd_90_f16_m_tied1: +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_m_tied1, svfloat16_t, + z0 = svcadd_f16_m (p0, z0, z1, 90), + z0 = svcadd_m (p0, z0, z1, 90)) + +/* +** cadd_90_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_m_tied2, svfloat16_t, + z0 = svcadd_f16_m (p0, z1, z0, 90), + z0 = svcadd_m (p0, z1, z0, 90)) + +/* +** cadd_90_f16_m_untied: +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_m_untied, svfloat16_t, + z0 = svcadd_f16_m (p0, z1, z2, 90), + z0 = svcadd_m (p0, z1, z2, 90)) + +/* +** cadd_270_f16_m_tied1: +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_m_tied1, svfloat16_t, + z0 = svcadd_f16_m (p0, z0, z1, 270), + z0 = svcadd_m (p0, z0, z1, 270)) + +/* +** cadd_270_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_m_tied2, svfloat16_t, + z0 = svcadd_f16_m (p0, z1, z0, 270), + z0 = svcadd_m (p0, z1, z0, 270)) + +/* +** cadd_270_f16_m_untied: +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_m_untied, svfloat16_t, + z0 = svcadd_f16_m (p0, z1, z2, 270), + z0 = svcadd_m (p0, z1, z2, 270)) + +/* +** cadd_90_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_z_tied1, svfloat16_t, + z0 = svcadd_f16_z (p0, z0, z1, 90), + z0 = svcadd_z (p0, z0, z1, 90)) + +/* +** cadd_90_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_z_tied2, svfloat16_t, + z0 = svcadd_f16_z (p0, z1, z0, 90), + z0 = svcadd_z (p0, z1, z0, 90)) + +/* +** cadd_90_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_z_untied, svfloat16_t, + z0 = svcadd_f16_z (p0, z1, z2, 90), + z0 = svcadd_z (p0, z1, z2, 90)) + +/* +** cadd_270_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_z_tied1, svfloat16_t, + z0 = svcadd_f16_z (p0, z0, z1, 270), + z0 = svcadd_z (p0, z0, z1, 270)) + +/* +** cadd_270_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_z_tied2, svfloat16_t, + z0 = svcadd_f16_z (p0, z1, z0, 270), + z0 = svcadd_z (p0, z1, z0, 270)) + +/* +** cadd_270_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_z_untied, svfloat16_t, + z0 = svcadd_f16_z (p0, z1, z2, 270), + z0 = svcadd_z (p0, z1, z2, 270)) + +/* +** cadd_90_f16_x_tied1: +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_x_tied1, svfloat16_t, + z0 = svcadd_f16_x (p0, z0, z1, 90), + z0 = svcadd_x (p0, z0, z1, 90)) + +/* +** cadd_90_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_x_tied2, svfloat16_t, + z0 = svcadd_f16_x (p0, z1, z0, 90), + z0 = svcadd_x (p0, z1, z0, 90)) + +/* +** cadd_90_f16_x_untied: +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f16_x_untied, svfloat16_t, + z0 = svcadd_f16_x (p0, z1, z2, 90), + z0 = svcadd_x (p0, z1, z2, 90)) + +/* +** cadd_270_f16_x_tied1: +** fcadd z0\.h, p0/m, z0\.h, z1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_x_tied1, svfloat16_t, + z0 = svcadd_f16_x (p0, z0, z1, 270), + z0 = svcadd_x (p0, z0, z1, 270)) + +/* +** cadd_270_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_x_tied2, svfloat16_t, + z0 = svcadd_f16_x (p0, z1, z0, 270), + z0 = svcadd_x (p0, z1, z0, 270)) + +/* +** cadd_270_f16_x_untied: +** movprfx z0, z1 +** fcadd z0\.h, p0/m, z0\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f16_x_untied, svfloat16_t, + z0 = svcadd_f16_x (p0, z1, z2, 270), + z0 = svcadd_x (p0, z1, z2, 270)) + +/* +** ptrue_cadd_90_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f16_x_tied1, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z0, z1, 90), + z0 = svcadd_x (svptrue_b16 (), z0, z1, 90)) + +/* +** ptrue_cadd_90_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f16_x_tied2, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z1, z0, 90), + z0 = svcadd_x (svptrue_b16 (), z1, z0, 90)) + +/* +** ptrue_cadd_90_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f16_x_untied, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z1, z2, 90), + z0 = svcadd_x (svptrue_b16 (), z1, z2, 90)) + +/* +** ptrue_cadd_270_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f16_x_tied1, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z0, z1, 270), + z0 = svcadd_x (svptrue_b16 (), z0, z1, 270)) + +/* +** ptrue_cadd_270_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f16_x_tied2, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z1, z0, 270), + z0 = svcadd_x (svptrue_b16 (), z1, z0, 270)) + +/* +** ptrue_cadd_270_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f16_x_untied, svfloat16_t, + z0 = svcadd_f16_x (svptrue_b16 (), z1, z2, 270), + z0 = svcadd_x (svptrue_b16 (), z1, z2, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f32.c new file mode 100644 index 00000000000..ed5c16ff3d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f32.c @@ -0,0 +1,251 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cadd_90_f32_m_tied1: +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_m_tied1, svfloat32_t, + z0 = svcadd_f32_m (p0, z0, z1, 90), + z0 = svcadd_m (p0, z0, z1, 90)) + +/* +** cadd_90_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_m_tied2, svfloat32_t, + z0 = svcadd_f32_m (p0, z1, z0, 90), + z0 = svcadd_m (p0, z1, z0, 90)) + +/* +** cadd_90_f32_m_untied: +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_m_untied, svfloat32_t, + z0 = svcadd_f32_m (p0, z1, z2, 90), + z0 = svcadd_m (p0, z1, z2, 90)) + +/* +** cadd_270_f32_m_tied1: +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_m_tied1, svfloat32_t, + z0 = svcadd_f32_m (p0, z0, z1, 270), + z0 = svcadd_m (p0, z0, z1, 270)) + +/* +** cadd_270_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_m_tied2, svfloat32_t, + z0 = svcadd_f32_m (p0, z1, z0, 270), + z0 = svcadd_m (p0, z1, z0, 270)) + +/* +** cadd_270_f32_m_untied: +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_m_untied, svfloat32_t, + z0 = svcadd_f32_m (p0, z1, z2, 270), + z0 = svcadd_m (p0, z1, z2, 270)) + +/* +** cadd_90_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_z_tied1, svfloat32_t, + z0 = svcadd_f32_z (p0, z0, z1, 90), + z0 = svcadd_z (p0, z0, z1, 90)) + +/* +** cadd_90_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_z_tied2, svfloat32_t, + z0 = svcadd_f32_z (p0, z1, z0, 90), + z0 = svcadd_z (p0, z1, z0, 90)) + +/* +** cadd_90_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_z_untied, svfloat32_t, + z0 = svcadd_f32_z (p0, z1, z2, 90), + z0 = svcadd_z (p0, z1, z2, 90)) + +/* +** cadd_270_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_z_tied1, svfloat32_t, + z0 = svcadd_f32_z (p0, z0, z1, 270), + z0 = svcadd_z (p0, z0, z1, 270)) + +/* +** cadd_270_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_z_tied2, svfloat32_t, + z0 = svcadd_f32_z (p0, z1, z0, 270), + z0 = svcadd_z (p0, z1, z0, 270)) + +/* +** cadd_270_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_z_untied, svfloat32_t, + z0 = svcadd_f32_z (p0, z1, z2, 270), + z0 = svcadd_z (p0, z1, z2, 270)) + +/* +** cadd_90_f32_x_tied1: +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_x_tied1, svfloat32_t, + z0 = svcadd_f32_x (p0, z0, z1, 90), + z0 = svcadd_x (p0, z0, z1, 90)) + +/* +** cadd_90_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_x_tied2, svfloat32_t, + z0 = svcadd_f32_x (p0, z1, z0, 90), + z0 = svcadd_x (p0, z1, z0, 90)) + +/* +** cadd_90_f32_x_untied: +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f32_x_untied, svfloat32_t, + z0 = svcadd_f32_x (p0, z1, z2, 90), + z0 = svcadd_x (p0, z1, z2, 90)) + +/* +** cadd_270_f32_x_tied1: +** fcadd z0\.s, p0/m, z0\.s, z1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_x_tied1, svfloat32_t, + z0 = svcadd_f32_x (p0, z0, z1, 270), + z0 = svcadd_x (p0, z0, z1, 270)) + +/* +** cadd_270_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_x_tied2, svfloat32_t, + z0 = svcadd_f32_x (p0, z1, z0, 270), + z0 = svcadd_x (p0, z1, z0, 270)) + +/* +** cadd_270_f32_x_untied: +** movprfx z0, z1 +** fcadd z0\.s, p0/m, z0\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f32_x_untied, svfloat32_t, + z0 = svcadd_f32_x (p0, z1, z2, 270), + z0 = svcadd_x (p0, z1, z2, 270)) + +/* +** ptrue_cadd_90_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f32_x_tied1, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z0, z1, 90), + z0 = svcadd_x (svptrue_b32 (), z0, z1, 90)) + +/* +** ptrue_cadd_90_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f32_x_tied2, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z1, z0, 90), + z0 = svcadd_x (svptrue_b32 (), z1, z0, 90)) + +/* +** ptrue_cadd_90_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f32_x_untied, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z1, z2, 90), + z0 = svcadd_x (svptrue_b32 (), z1, z2, 90)) + +/* +** ptrue_cadd_270_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f32_x_tied1, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z0, z1, 270), + z0 = svcadd_x (svptrue_b32 (), z0, z1, 270)) + +/* +** ptrue_cadd_270_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f32_x_tied2, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z1, z0, 270), + z0 = svcadd_x (svptrue_b32 (), z1, z0, 270)) + +/* +** ptrue_cadd_270_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f32_x_untied, svfloat32_t, + z0 = svcadd_f32_x (svptrue_b32 (), z1, z2, 270), + z0 = svcadd_x (svptrue_b32 (), z1, z2, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f64.c new file mode 100644 index 00000000000..0ada881c598 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cadd_f64.c @@ -0,0 +1,251 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cadd_90_f64_m_tied1: +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_m_tied1, svfloat64_t, + z0 = svcadd_f64_m (p0, z0, z1, 90), + z0 = svcadd_m (p0, z0, z1, 90)) + +/* +** cadd_90_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_m_tied2, svfloat64_t, + z0 = svcadd_f64_m (p0, z1, z0, 90), + z0 = svcadd_m (p0, z1, z0, 90)) + +/* +** cadd_90_f64_m_untied: +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_m_untied, svfloat64_t, + z0 = svcadd_f64_m (p0, z1, z2, 90), + z0 = svcadd_m (p0, z1, z2, 90)) + +/* +** cadd_270_f64_m_tied1: +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_m_tied1, svfloat64_t, + z0 = svcadd_f64_m (p0, z0, z1, 270), + z0 = svcadd_m (p0, z0, z1, 270)) + +/* +** cadd_270_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_m_tied2, svfloat64_t, + z0 = svcadd_f64_m (p0, z1, z0, 270), + z0 = svcadd_m (p0, z1, z0, 270)) + +/* +** cadd_270_f64_m_untied: +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_m_untied, svfloat64_t, + z0 = svcadd_f64_m (p0, z1, z2, 270), + z0 = svcadd_m (p0, z1, z2, 270)) + +/* +** cadd_90_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_z_tied1, svfloat64_t, + z0 = svcadd_f64_z (p0, z0, z1, 90), + z0 = svcadd_z (p0, z0, z1, 90)) + +/* +** cadd_90_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcadd z0\.d, p0/m, z0\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_z_tied2, svfloat64_t, + z0 = svcadd_f64_z (p0, z1, z0, 90), + z0 = svcadd_z (p0, z1, z0, 90)) + +/* +** cadd_90_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_z_untied, svfloat64_t, + z0 = svcadd_f64_z (p0, z1, z2, 90), + z0 = svcadd_z (p0, z1, z2, 90)) + +/* +** cadd_270_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_z_tied1, svfloat64_t, + z0 = svcadd_f64_z (p0, z0, z1, 270), + z0 = svcadd_z (p0, z0, z1, 270)) + +/* +** cadd_270_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcadd z0\.d, p0/m, z0\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_z_tied2, svfloat64_t, + z0 = svcadd_f64_z (p0, z1, z0, 270), + z0 = svcadd_z (p0, z1, z0, 270)) + +/* +** cadd_270_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_z_untied, svfloat64_t, + z0 = svcadd_f64_z (p0, z1, z2, 270), + z0 = svcadd_z (p0, z1, z2, 270)) + +/* +** cadd_90_f64_x_tied1: +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_x_tied1, svfloat64_t, + z0 = svcadd_f64_x (p0, z0, z1, 90), + z0 = svcadd_x (p0, z0, z1, 90)) + +/* +** cadd_90_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_x_tied2, svfloat64_t, + z0 = svcadd_f64_x (p0, z1, z0, 90), + z0 = svcadd_x (p0, z1, z0, 90)) + +/* +** cadd_90_f64_x_untied: +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cadd_90_f64_x_untied, svfloat64_t, + z0 = svcadd_f64_x (p0, z1, z2, 90), + z0 = svcadd_x (p0, z1, z2, 90)) + +/* +** cadd_270_f64_x_tied1: +** fcadd z0\.d, p0/m, z0\.d, z1\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_x_tied1, svfloat64_t, + z0 = svcadd_f64_x (p0, z0, z1, 270), + z0 = svcadd_x (p0, z0, z1, 270)) + +/* +** cadd_270_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_x_tied2, svfloat64_t, + z0 = svcadd_f64_x (p0, z1, z0, 270), + z0 = svcadd_x (p0, z1, z0, 270)) + +/* +** cadd_270_f64_x_untied: +** movprfx z0, z1 +** fcadd z0\.d, p0/m, z0\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cadd_270_f64_x_untied, svfloat64_t, + z0 = svcadd_f64_x (p0, z1, z2, 270), + z0 = svcadd_x (p0, z1, z2, 270)) + +/* +** ptrue_cadd_90_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f64_x_tied1, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z0, z1, 90), + z0 = svcadd_x (svptrue_b64 (), z0, z1, 90)) + +/* +** ptrue_cadd_90_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f64_x_tied2, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z1, z0, 90), + z0 = svcadd_x (svptrue_b64 (), z1, z0, 90)) + +/* +** ptrue_cadd_90_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_90_f64_x_untied, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z1, z2, 90), + z0 = svcadd_x (svptrue_b64 (), z1, z2, 90)) + +/* +** ptrue_cadd_270_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f64_x_tied1, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z0, z1, 270), + z0 = svcadd_x (svptrue_b64 (), z0, z1, 270)) + +/* +** ptrue_cadd_270_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f64_x_tied2, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z1, z0, 270), + z0 = svcadd_x (svptrue_b64 (), z1, z0, 270)) + +/* +** ptrue_cadd_270_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cadd_270_f64_x_untied, svfloat64_t, + z0 = svcadd_f64_x (svptrue_b64 (), z1, z2, 270), + z0 = svcadd_x (svptrue_b64 (), z1, z2, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c new file mode 100644 index 00000000000..d9a980f60c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_f16_tied1: +** clasta z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_f16_tied1, svfloat16_t, + z0 = svclasta_f16 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_f16_tied2, svfloat16_t, + z0 = svclasta_f16 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_f16_untied: +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_f16_untied, svfloat16_t, + z0 = svclasta_f16 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_d0_f16: +** clasta h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d0_f16, float16_t, svfloat16_t, + d0 = svclasta_n_f16 (p0, d0, z2), + d0 = svclasta (p0, d0, z2)) + +/* +** clasta_d1_f16: +** mov v0\.h\[0\], v1\.h\[0\] +** clasta h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d1_f16, float16_t, svfloat16_t, + d0 = svclasta_n_f16 (p0, d1, z2), + d0 = svclasta (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c new file mode 100644 index 00000000000..cac01fa6d64 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_f32_tied1: +** clasta z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_f32_tied1, svfloat32_t, + z0 = svclasta_f32 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_f32_tied2, svfloat32_t, + z0 = svclasta_f32 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_f32_untied: +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_f32_untied, svfloat32_t, + z0 = svclasta_f32 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_d0_f32: +** clasta s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d0_f32, float32_t, svfloat32_t, + d0 = svclasta_n_f32 (p0, d0, z2), + d0 = svclasta (p0, d0, z2)) + +/* +** clasta_d1_f32: +** fmov s0, s1 +** clasta s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d1_f32, float32_t, svfloat32_t, + d0 = svclasta_n_f32 (p0, d1, z2), + d0 = svclasta (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c new file mode 100644 index 00000000000..43b93553ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_f64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_f64_tied1: +** clasta z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_f64_tied1, svfloat64_t, + z0 = svclasta_f64 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clasta_f64_tied2, svfloat64_t, + z0 = svclasta_f64 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_f64_untied: +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_f64_untied, svfloat64_t, + z0 = svclasta_f64 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_d0_f64: +** clasta d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d0_f64, float64_t, svfloat64_t, + d0 = svclasta_n_f64 (p0, d0, z2), + d0 = svclasta (p0, d0, z2)) + +/* +** clasta_d1_f64: +** fmov d0, d1 +** clasta d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (clasta_d1_f64, float64_t, svfloat64_t, + d0 = svclasta_n_f64 (p0, d1, z2), + d0 = svclasta (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s16.c new file mode 100644 index 00000000000..f5e4f85ce33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_s16_tied1: +** clasta z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_s16_tied1, svint16_t, + z0 = svclasta_s16 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_s16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_s16_tied2, svint16_t, + z0 = svclasta_s16 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_s16_untied: +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_s16_untied, svint16_t, + z0 = svclasta_s16 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_s16: +** clasta w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_s16, int16_t, svint16_t, + x0 = svclasta_n_s16 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_s16: +** mov w0, w1 +** clasta w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_s16, int16_t, svint16_t, + x0 = svclasta_n_s16 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s32.c new file mode 100644 index 00000000000..fbd82e77825 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_s32_tied1: +** clasta z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_s32_tied1, svint32_t, + z0 = svclasta_s32 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_s32_tied2, svint32_t, + z0 = svclasta_s32 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_s32_untied: +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_s32_untied, svint32_t, + z0 = svclasta_s32 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_s32: +** clasta w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_s32, int32_t, svint32_t, + x0 = svclasta_n_s32 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_s32: +** mov w0, w1 +** clasta w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_s32, int32_t, svint32_t, + x0 = svclasta_n_s32 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s64.c new file mode 100644 index 00000000000..08edf157bb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_s64_tied1: +** clasta z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_s64_tied1, svint64_t, + z0 = svclasta_s64 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_s64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clasta_s64_tied2, svint64_t, + z0 = svclasta_s64 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_s64_untied: +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_s64_untied, svint64_t, + z0 = svclasta_s64 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_s64: +** clasta x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_s64, int64_t, svint64_t, + x0 = svclasta_n_s64 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_s64: +** mov x0, x1 +** clasta x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_s64, int64_t, svint64_t, + x0 = svclasta_n_s64 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s8.c new file mode 100644 index 00000000000..286f16a9d8e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_s8.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_s8_tied1: +** clasta z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_s8_tied1, svint8_t, + z0 = svclasta_s8 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_s8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_s8_tied2, svint8_t, + z0 = svclasta_s8 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_s8_untied: +** movprfx z0, z1 +** clasta z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_s8_untied, svint8_t, + z0 = svclasta_s8 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_s8: +** clasta w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_s8, int8_t, svint8_t, + x0 = svclasta_n_s8 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_s8: +** mov w0, w1 +** clasta w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_s8, int8_t, svint8_t, + x0 = svclasta_n_s8 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u16.c new file mode 100644 index 00000000000..40c6dca9081 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_u16_tied1: +** clasta z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_u16_tied1, svuint16_t, + z0 = svclasta_u16 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_u16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_u16_tied2, svuint16_t, + z0 = svclasta_u16 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_u16_untied: +** movprfx z0, z1 +** clasta z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clasta_u16_untied, svuint16_t, + z0 = svclasta_u16 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_u16: +** clasta w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_u16, uint16_t, svuint16_t, + x0 = svclasta_n_u16 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_u16: +** mov w0, w1 +** clasta w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_u16, uint16_t, svuint16_t, + x0 = svclasta_n_u16 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u32.c new file mode 100644 index 00000000000..6c46e13cf2a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_u32_tied1: +** clasta z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_u32_tied1, svuint32_t, + z0 = svclasta_u32 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_u32_tied2, svuint32_t, + z0 = svclasta_u32 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_u32_untied: +** movprfx z0, z1 +** clasta z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clasta_u32_untied, svuint32_t, + z0 = svclasta_u32 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_u32: +** clasta w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_u32, uint32_t, svuint32_t, + x0 = svclasta_n_u32 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_u32: +** mov w0, w1 +** clasta w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_u32, uint32_t, svuint32_t, + x0 = svclasta_n_u32 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u64.c new file mode 100644 index 00000000000..99ad41e502e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_u64_tied1: +** clasta z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_u64_tied1, svuint64_t, + z0 = svclasta_u64 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_u64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clasta_u64_tied2, svuint64_t, + z0 = svclasta_u64 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_u64_untied: +** movprfx z0, z1 +** clasta z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clasta_u64_untied, svuint64_t, + z0 = svclasta_u64 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_u64: +** clasta x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_u64, uint64_t, svuint64_t, + x0 = svclasta_n_u64 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_u64: +** mov x0, x1 +** clasta x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_u64, uint64_t, svuint64_t, + x0 = svclasta_n_u64 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u8.c new file mode 100644 index 00000000000..eb438f4ea22 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clasta_u8.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clasta_u8_tied1: +** clasta z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_u8_tied1, svuint8_t, + z0 = svclasta_u8 (p0, z0, z1), + z0 = svclasta (p0, z0, z1)) + +/* +** clasta_u8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clasta z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_u8_tied2, svuint8_t, + z0 = svclasta_u8 (p0, z1, z0), + z0 = svclasta (p0, z1, z0)) + +/* +** clasta_u8_untied: +** movprfx z0, z1 +** clasta z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (clasta_u8_untied, svuint8_t, + z0 = svclasta_u8 (p0, z1, z2), + z0 = svclasta (p0, z1, z2)) + +/* +** clasta_x0_u8: +** clasta w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x0_u8, uint8_t, svuint8_t, + x0 = svclasta_n_u8 (p0, x0, z0), + x0 = svclasta (p0, x0, z0)) + +/* +** clasta_x1_u8: +** mov w0, w1 +** clasta w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clasta_x1_u8, uint8_t, svuint8_t, + x0 = svclasta_n_u8 (p0, x1, z0), + x0 = svclasta (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c new file mode 100644 index 00000000000..e56d7688a1c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_f16_tied1: +** clastb z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_f16_tied1, svfloat16_t, + z0 = svclastb_f16 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_f16_tied2, svfloat16_t, + z0 = svclastb_f16 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_f16_untied: +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_f16_untied, svfloat16_t, + z0 = svclastb_f16 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_d0_f16: +** clastb h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d0_f16, float16_t, svfloat16_t, + d0 = svclastb_n_f16 (p0, d0, z2), + d0 = svclastb (p0, d0, z2)) + +/* +** clastb_d1_f16: +** mov v0\.h\[0\], v1\.h\[0\] +** clastb h0, p0, h0, z2\.h +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d1_f16, float16_t, svfloat16_t, + d0 = svclastb_n_f16 (p0, d1, z2), + d0 = svclastb (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c new file mode 100644 index 00000000000..c580d13064b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_f32_tied1: +** clastb z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_f32_tied1, svfloat32_t, + z0 = svclastb_f32 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_f32_tied2, svfloat32_t, + z0 = svclastb_f32 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_f32_untied: +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_f32_untied, svfloat32_t, + z0 = svclastb_f32 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_d0_f32: +** clastb s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d0_f32, float32_t, svfloat32_t, + d0 = svclastb_n_f32 (p0, d0, z2), + d0 = svclastb (p0, d0, z2)) + +/* +** clastb_d1_f32: +** fmov s0, s1 +** clastb s0, p0, s0, z2\.s +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d1_f32, float32_t, svfloat32_t, + d0 = svclastb_n_f32 (p0, d1, z2), + d0 = svclastb (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c new file mode 100644 index 00000000000..217a76f5112 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_f64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_f64_tied1: +** clastb z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_f64_tied1, svfloat64_t, + z0 = svclastb_f64 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clastb_f64_tied2, svfloat64_t, + z0 = svclastb_f64 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_f64_untied: +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_f64_untied, svfloat64_t, + z0 = svclastb_f64 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_d0_f64: +** clastb d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d0_f64, float64_t, svfloat64_t, + d0 = svclastb_n_f64 (p0, d0, z2), + d0 = svclastb (p0, d0, z2)) + +/* +** clastb_d1_f64: +** fmov d0, d1 +** clastb d0, p0, d0, z2\.d +** ret +*/ +TEST_FOLD_LEFT_D (clastb_d1_f64, float64_t, svfloat64_t, + d0 = svclastb_n_f64 (p0, d1, z2), + d0 = svclastb (p0, d1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s16.c new file mode 100644 index 00000000000..37be2804028 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_s16_tied1: +** clastb z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_s16_tied1, svint16_t, + z0 = svclastb_s16 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_s16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_s16_tied2, svint16_t, + z0 = svclastb_s16 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_s16_untied: +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_s16_untied, svint16_t, + z0 = svclastb_s16 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_s16: +** clastb w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_s16, int16_t, svint16_t, + x0 = svclastb_n_s16 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_s16: +** mov w0, w1 +** clastb w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_s16, int16_t, svint16_t, + x0 = svclastb_n_s16 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s32.c new file mode 100644 index 00000000000..2e56c5a8f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_s32_tied1: +** clastb z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_s32_tied1, svint32_t, + z0 = svclastb_s32 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_s32_tied2, svint32_t, + z0 = svclastb_s32 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_s32_untied: +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_s32_untied, svint32_t, + z0 = svclastb_s32 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_s32: +** clastb w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_s32, int32_t, svint32_t, + x0 = svclastb_n_s32 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_s32: +** mov w0, w1 +** clastb w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_s32, int32_t, svint32_t, + x0 = svclastb_n_s32 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s64.c new file mode 100644 index 00000000000..9ce210aaec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_s64_tied1: +** clastb z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_s64_tied1, svint64_t, + z0 = svclastb_s64 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_s64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clastb_s64_tied2, svint64_t, + z0 = svclastb_s64 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_s64_untied: +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_s64_untied, svint64_t, + z0 = svclastb_s64 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_s64: +** clastb x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_s64, int64_t, svint64_t, + x0 = svclastb_n_s64 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_s64: +** mov x0, x1 +** clastb x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_s64, int64_t, svint64_t, + x0 = svclastb_n_s64 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s8.c new file mode 100644 index 00000000000..eb76c22cdb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_s8.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_s8_tied1: +** clastb z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_s8_tied1, svint8_t, + z0 = svclastb_s8 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_s8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_s8_tied2, svint8_t, + z0 = svclastb_s8 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_s8_untied: +** movprfx z0, z1 +** clastb z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_s8_untied, svint8_t, + z0 = svclastb_s8 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_s8: +** clastb w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_s8, int8_t, svint8_t, + x0 = svclastb_n_s8 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_s8: +** mov w0, w1 +** clastb w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_s8, int8_t, svint8_t, + x0 = svclastb_n_s8 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u16.c new file mode 100644 index 00000000000..5aea9c7bd01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_u16_tied1: +** clastb z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_u16_tied1, svuint16_t, + z0 = svclastb_u16 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_u16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_u16_tied2, svuint16_t, + z0 = svclastb_u16 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_u16_untied: +** movprfx z0, z1 +** clastb z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (clastb_u16_untied, svuint16_t, + z0 = svclastb_u16 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_u16: +** clastb w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_u16, uint16_t, svuint16_t, + x0 = svclastb_n_u16 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_u16: +** mov w0, w1 +** clastb w0, p0, w0, z0\.h +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_u16, uint16_t, svuint16_t, + x0 = svclastb_n_u16 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u32.c new file mode 100644 index 00000000000..47fcf4f27fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_u32_tied1: +** clastb z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_u32_tied1, svuint32_t, + z0 = svclastb_u32 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_u32_tied2, svuint32_t, + z0 = svclastb_u32 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_u32_untied: +** movprfx z0, z1 +** clastb z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (clastb_u32_untied, svuint32_t, + z0 = svclastb_u32 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_u32: +** clastb w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_u32, uint32_t, svuint32_t, + x0 = svclastb_n_u32 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_u32: +** mov w0, w1 +** clastb w0, p0, w0, z0\.s +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_u32, uint32_t, svuint32_t, + x0 = svclastb_n_u32 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u64.c new file mode 100644 index 00000000000..fb57afe8525 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_u64_tied1: +** clastb z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_u64_tied1, svuint64_t, + z0 = svclastb_u64 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_u64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (clastb_u64_tied2, svuint64_t, + z0 = svclastb_u64 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_u64_untied: +** movprfx z0, z1 +** clastb z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (clastb_u64_untied, svuint64_t, + z0 = svclastb_u64 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_u64: +** clastb x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_u64, uint64_t, svuint64_t, + x0 = svclastb_n_u64 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_u64: +** mov x0, x1 +** clastb x0, p0, x0, z0\.d +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_u64, uint64_t, svuint64_t, + x0 = svclastb_n_u64 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u8.c new file mode 100644 index 00000000000..f3ca8492007 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clastb_u8.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clastb_u8_tied1: +** clastb z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_u8_tied1, svuint8_t, + z0 = svclastb_u8 (p0, z0, z1), + z0 = svclastb (p0, z0, z1)) + +/* +** clastb_u8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clastb z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_u8_tied2, svuint8_t, + z0 = svclastb_u8 (p0, z1, z0), + z0 = svclastb (p0, z1, z0)) + +/* +** clastb_u8_untied: +** movprfx z0, z1 +** clastb z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (clastb_u8_untied, svuint8_t, + z0 = svclastb_u8 (p0, z1, z2), + z0 = svclastb (p0, z1, z2)) + +/* +** clastb_x0_u8: +** clastb w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x0_u8, uint8_t, svuint8_t, + x0 = svclastb_n_u8 (p0, x0, z0), + x0 = svclastb (p0, x0, z0)) + +/* +** clastb_x1_u8: +** mov w0, w1 +** clastb w0, p0, w0, z0\.b +** ret +*/ +TEST_FOLD_LEFT_X (clastb_x1_u8, uint8_t, svuint8_t, + x0 = svclastb_n_u8 (p0, x1, z0), + x0 = svclastb (p0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c new file mode 100644 index 00000000000..7af312397b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cls_s16_m_tied1: +** cls z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cls_s16_m_tied1, svuint16_t, svint16_t, + z0 = svcls_s16_m (z0, p0, z4), + z0 = svcls_m (z0, p0, z4)) + +/* +** cls_s16_m_untied: +** movprfx z0, z1 +** cls z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cls_s16_m_untied, svuint16_t, svint16_t, + z0 = svcls_s16_m (z1, p0, z4), + z0 = svcls_m (z1, p0, z4)) + +/* +** cls_s16_z: +** movprfx z0\.h, p0/z, z4\.h +** cls z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cls_s16_z, svuint16_t, svint16_t, + z0 = svcls_s16_z (p0, z4), + z0 = svcls_z (p0, z4)) + +/* +** cls_s16_x: +** cls z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cls_s16_x, svuint16_t, svint16_t, + z0 = svcls_s16_x (p0, z4), + z0 = svcls_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c new file mode 100644 index 00000000000..813876f6877 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cls_s32_m_tied1: +** cls z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cls_s32_m_tied1, svuint32_t, svint32_t, + z0 = svcls_s32_m (z0, p0, z4), + z0 = svcls_m (z0, p0, z4)) + +/* +** cls_s32_m_untied: +** movprfx z0, z1 +** cls z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cls_s32_m_untied, svuint32_t, svint32_t, + z0 = svcls_s32_m (z1, p0, z4), + z0 = svcls_m (z1, p0, z4)) + +/* +** cls_s32_z: +** movprfx z0\.s, p0/z, z4\.s +** cls z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cls_s32_z, svuint32_t, svint32_t, + z0 = svcls_s32_z (p0, z4), + z0 = svcls_z (p0, z4)) + +/* +** cls_s32_x: +** cls z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cls_s32_x, svuint32_t, svint32_t, + z0 = svcls_s32_x (p0, z4), + z0 = svcls_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c new file mode 100644 index 00000000000..660a20556c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cls_s64_m_tied1: +** cls z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cls_s64_m_tied1, svuint64_t, svint64_t, + z0 = svcls_s64_m (z0, p0, z4), + z0 = svcls_m (z0, p0, z4)) + +/* +** cls_s64_m_untied: +** movprfx z0, z1 +** cls z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cls_s64_m_untied, svuint64_t, svint64_t, + z0 = svcls_s64_m (z1, p0, z4), + z0 = svcls_m (z1, p0, z4)) + +/* +** cls_s64_z: +** movprfx z0\.d, p0/z, z4\.d +** cls z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cls_s64_z, svuint64_t, svint64_t, + z0 = svcls_s64_z (p0, z4), + z0 = svcls_z (p0, z4)) + +/* +** cls_s64_x: +** cls z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cls_s64_x, svuint64_t, svint64_t, + z0 = svcls_s64_x (p0, z4), + z0 = svcls_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c new file mode 100644 index 00000000000..56f5c26086f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cls_s8_m_tied1: +** cls z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cls_s8_m_tied1, svuint8_t, svint8_t, + z0 = svcls_s8_m (z0, p0, z4), + z0 = svcls_m (z0, p0, z4)) + +/* +** cls_s8_m_untied: +** movprfx z0, z1 +** cls z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cls_s8_m_untied, svuint8_t, svint8_t, + z0 = svcls_s8_m (z1, p0, z4), + z0 = svcls_m (z1, p0, z4)) + +/* +** cls_s8_z: +** movprfx z0\.b, p0/z, z4\.b +** cls z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cls_s8_z, svuint8_t, svint8_t, + z0 = svcls_s8_z (p0, z4), + z0 = svcls_z (p0, z4)) + +/* +** cls_s8_x: +** cls z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cls_s8_x, svuint8_t, svint8_t, + z0 = svcls_s8_x (p0, z4), + z0 = svcls_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c new file mode 100644 index 00000000000..58f89005cd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_s16_m_tied1: +** clz z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (clz_s16_m_tied1, svuint16_t, svint16_t, + z0 = svclz_s16_m (z0, p0, z4), + z0 = svclz_m (z0, p0, z4)) + +/* +** clz_s16_m_untied: +** movprfx z0, z1 +** clz z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (clz_s16_m_untied, svuint16_t, svint16_t, + z0 = svclz_s16_m (z1, p0, z4), + z0 = svclz_m (z1, p0, z4)) + +/* +** clz_s16_z: +** movprfx z0\.h, p0/z, z4\.h +** clz z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (clz_s16_z, svuint16_t, svint16_t, + z0 = svclz_s16_z (p0, z4), + z0 = svclz_z (p0, z4)) + +/* +** clz_s16_x: +** clz z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (clz_s16_x, svuint16_t, svint16_t, + z0 = svclz_s16_x (p0, z4), + z0 = svclz_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c new file mode 100644 index 00000000000..a9198070b58 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_s32_m_tied1: +** clz z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (clz_s32_m_tied1, svuint32_t, svint32_t, + z0 = svclz_s32_m (z0, p0, z4), + z0 = svclz_m (z0, p0, z4)) + +/* +** clz_s32_m_untied: +** movprfx z0, z1 +** clz z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (clz_s32_m_untied, svuint32_t, svint32_t, + z0 = svclz_s32_m (z1, p0, z4), + z0 = svclz_m (z1, p0, z4)) + +/* +** clz_s32_z: +** movprfx z0\.s, p0/z, z4\.s +** clz z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (clz_s32_z, svuint32_t, svint32_t, + z0 = svclz_s32_z (p0, z4), + z0 = svclz_z (p0, z4)) + +/* +** clz_s32_x: +** clz z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (clz_s32_x, svuint32_t, svint32_t, + z0 = svclz_s32_x (p0, z4), + z0 = svclz_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c new file mode 100644 index 00000000000..02c0c993e0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_s64_m_tied1: +** clz z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (clz_s64_m_tied1, svuint64_t, svint64_t, + z0 = svclz_s64_m (z0, p0, z4), + z0 = svclz_m (z0, p0, z4)) + +/* +** clz_s64_m_untied: +** movprfx z0, z1 +** clz z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (clz_s64_m_untied, svuint64_t, svint64_t, + z0 = svclz_s64_m (z1, p0, z4), + z0 = svclz_m (z1, p0, z4)) + +/* +** clz_s64_z: +** movprfx z0\.d, p0/z, z4\.d +** clz z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (clz_s64_z, svuint64_t, svint64_t, + z0 = svclz_s64_z (p0, z4), + z0 = svclz_z (p0, z4)) + +/* +** clz_s64_x: +** clz z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (clz_s64_x, svuint64_t, svint64_t, + z0 = svclz_s64_x (p0, z4), + z0 = svclz_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c new file mode 100644 index 00000000000..642d298c8ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_s8_m_tied1: +** clz z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (clz_s8_m_tied1, svuint8_t, svint8_t, + z0 = svclz_s8_m (z0, p0, z4), + z0 = svclz_m (z0, p0, z4)) + +/* +** clz_s8_m_untied: +** movprfx z0, z1 +** clz z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (clz_s8_m_untied, svuint8_t, svint8_t, + z0 = svclz_s8_m (z1, p0, z4), + z0 = svclz_m (z1, p0, z4)) + +/* +** clz_s8_z: +** movprfx z0\.b, p0/z, z4\.b +** clz z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (clz_s8_z, svuint8_t, svint8_t, + z0 = svclz_s8_z (p0, z4), + z0 = svclz_z (p0, z4)) + +/* +** clz_s8_x: +** clz z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (clz_s8_x, svuint8_t, svint8_t, + z0 = svclz_s8_x (p0, z4), + z0 = svclz_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c new file mode 100644 index 00000000000..f0872301759 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_u16_m_tied12: +** clz z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_m_tied12, svuint16_t, + z0 = svclz_u16_m (z0, p0, z0), + z0 = svclz_m (z0, p0, z0)) + +/* +** clz_u16_m_tied1: +** clz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_m_tied1, svuint16_t, + z0 = svclz_u16_m (z0, p0, z1), + z0 = svclz_m (z0, p0, z1)) + +/* +** clz_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clz z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_m_tied2, svuint16_t, + z0 = svclz_u16_m (z1, p0, z0), + z0 = svclz_m (z1, p0, z0)) + +/* +** clz_u16_m_untied: +** movprfx z0, z2 +** clz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_m_untied, svuint16_t, + z0 = svclz_u16_m (z2, p0, z1), + z0 = svclz_m (z2, p0, z1)) + +/* +** clz_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** clz z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_z_tied1, svuint16_t, + z0 = svclz_u16_z (p0, z0), + z0 = svclz_z (p0, z0)) + +/* +** clz_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** clz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_z_untied, svuint16_t, + z0 = svclz_u16_z (p0, z1), + z0 = svclz_z (p0, z1)) + +/* +** clz_u16_x_tied1: +** clz z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_x_tied1, svuint16_t, + z0 = svclz_u16_x (p0, z0), + z0 = svclz_x (p0, z0)) + +/* +** clz_u16_x_untied: +** clz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (clz_u16_x_untied, svuint16_t, + z0 = svclz_u16_x (p0, z1), + z0 = svclz_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c new file mode 100644 index 00000000000..e0042413162 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_u32_m_tied12: +** clz z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_m_tied12, svuint32_t, + z0 = svclz_u32_m (z0, p0, z0), + z0 = svclz_m (z0, p0, z0)) + +/* +** clz_u32_m_tied1: +** clz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_m_tied1, svuint32_t, + z0 = svclz_u32_m (z0, p0, z1), + z0 = svclz_m (z0, p0, z1)) + +/* +** clz_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clz z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_m_tied2, svuint32_t, + z0 = svclz_u32_m (z1, p0, z0), + z0 = svclz_m (z1, p0, z0)) + +/* +** clz_u32_m_untied: +** movprfx z0, z2 +** clz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_m_untied, svuint32_t, + z0 = svclz_u32_m (z2, p0, z1), + z0 = svclz_m (z2, p0, z1)) + +/* +** clz_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** clz z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_z_tied1, svuint32_t, + z0 = svclz_u32_z (p0, z0), + z0 = svclz_z (p0, z0)) + +/* +** clz_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** clz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_z_untied, svuint32_t, + z0 = svclz_u32_z (p0, z1), + z0 = svclz_z (p0, z1)) + +/* +** clz_u32_x_tied1: +** clz z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_x_tied1, svuint32_t, + z0 = svclz_u32_x (p0, z0), + z0 = svclz_x (p0, z0)) + +/* +** clz_u32_x_untied: +** clz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (clz_u32_x_untied, svuint32_t, + z0 = svclz_u32_x (p0, z1), + z0 = svclz_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c new file mode 100644 index 00000000000..e879e1b9a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_u64_m_tied12: +** clz z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_m_tied12, svuint64_t, + z0 = svclz_u64_m (z0, p0, z0), + z0 = svclz_m (z0, p0, z0)) + +/* +** clz_u64_m_tied1: +** clz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_m_tied1, svuint64_t, + z0 = svclz_u64_m (z0, p0, z1), + z0 = svclz_m (z0, p0, z1)) + +/* +** clz_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** clz z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (clz_u64_m_tied2, svuint64_t, + z0 = svclz_u64_m (z1, p0, z0), + z0 = svclz_m (z1, p0, z0)) + +/* +** clz_u64_m_untied: +** movprfx z0, z2 +** clz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_m_untied, svuint64_t, + z0 = svclz_u64_m (z2, p0, z1), + z0 = svclz_m (z2, p0, z1)) + +/* +** clz_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** clz z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (clz_u64_z_tied1, svuint64_t, + z0 = svclz_u64_z (p0, z0), + z0 = svclz_z (p0, z0)) + +/* +** clz_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** clz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_z_untied, svuint64_t, + z0 = svclz_u64_z (p0, z1), + z0 = svclz_z (p0, z1)) + +/* +** clz_u64_x_tied1: +** clz z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_x_tied1, svuint64_t, + z0 = svclz_u64_x (p0, z0), + z0 = svclz_x (p0, z0)) + +/* +** clz_u64_x_untied: +** clz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (clz_u64_x_untied, svuint64_t, + z0 = svclz_u64_x (p0, z1), + z0 = svclz_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c new file mode 100644 index 00000000000..ce6cb8f4517 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** clz_u8_m_tied12: +** clz z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_m_tied12, svuint8_t, + z0 = svclz_u8_m (z0, p0, z0), + z0 = svclz_m (z0, p0, z0)) + +/* +** clz_u8_m_tied1: +** clz z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_m_tied1, svuint8_t, + z0 = svclz_u8_m (z0, p0, z1), + z0 = svclz_m (z0, p0, z1)) + +/* +** clz_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** clz z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_m_tied2, svuint8_t, + z0 = svclz_u8_m (z1, p0, z0), + z0 = svclz_m (z1, p0, z0)) + +/* +** clz_u8_m_untied: +** movprfx z0, z2 +** clz z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_m_untied, svuint8_t, + z0 = svclz_u8_m (z2, p0, z1), + z0 = svclz_m (z2, p0, z1)) + +/* +** clz_u8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** clz z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_z_tied1, svuint8_t, + z0 = svclz_u8_z (p0, z0), + z0 = svclz_z (p0, z0)) + +/* +** clz_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** clz z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_z_untied, svuint8_t, + z0 = svclz_u8_z (p0, z1), + z0 = svclz_z (p0, z1)) + +/* +** clz_u8_x_tied1: +** clz z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_x_tied1, svuint8_t, + z0 = svclz_u8_x (p0, z0), + z0 = svclz_x (p0, z0)) + +/* +** clz_u8_x_untied: +** clz z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (clz_u8_x_untied, svuint8_t, + z0 = svclz_u8_x (p0, z1), + z0 = svclz_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f16.c new file mode 100644 index 00000000000..3bf44a59f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f16.c @@ -0,0 +1,675 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmla_0_f16_m_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_m_tied1, svfloat16_t, + z0 = svcmla_f16_m (p0, z0, z1, z2, 0), + z0 = svcmla_m (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_m_tied2, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z0, z2, 0), + z0 = svcmla_m (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_m_tied3, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z0, 0), + z0 = svcmla_m (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f16_m_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_m_untied, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z3, 0), + z0 = svcmla_m (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f16_m_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_m_tied1, svfloat16_t, + z0 = svcmla_f16_m (p0, z0, z1, z2, 90), + z0 = svcmla_m (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_m_tied2, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z0, z2, 90), + z0 = svcmla_m (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_m_tied3, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z0, 90), + z0 = svcmla_m (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f16_m_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_m_untied, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z3, 90), + z0 = svcmla_m (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f16_m_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_m_tied1, svfloat16_t, + z0 = svcmla_f16_m (p0, z0, z1, z2, 180), + z0 = svcmla_m (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_m_tied2, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z0, z2, 180), + z0 = svcmla_m (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_m_tied3, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z0, 180), + z0 = svcmla_m (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f16_m_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_m_untied, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z3, 180), + z0 = svcmla_m (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f16_m_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_m_tied1, svfloat16_t, + z0 = svcmla_f16_m (p0, z0, z1, z2, 270), + z0 = svcmla_m (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_m_tied2, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z0, z2, 270), + z0 = svcmla_m (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_m_tied3, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z0, 270), + z0 = svcmla_m (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f16_m_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_m_untied, svfloat16_t, + z0 = svcmla_f16_m (p0, z1, z2, z3, 270), + z0 = svcmla_m (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_z_tied1, svfloat16_t, + z0 = svcmla_f16_z (p0, z0, z1, z2, 0), + z0 = svcmla_z (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_z_tied2, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z0, z2, 0), + z0 = svcmla_z (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f16_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_z_tied3, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z0, 0), + z0 = svcmla_z (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_z_untied, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z3, 0), + z0 = svcmla_z (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_z_tied1, svfloat16_t, + z0 = svcmla_f16_z (p0, z0, z1, z2, 90), + z0 = svcmla_z (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_z_tied2, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z0, z2, 90), + z0 = svcmla_z (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f16_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_z_tied3, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z0, 90), + z0 = svcmla_z (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_z_untied, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z3, 90), + z0 = svcmla_z (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_z_tied1, svfloat16_t, + z0 = svcmla_f16_z (p0, z0, z1, z2, 180), + z0 = svcmla_z (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_z_tied2, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z0, z2, 180), + z0 = svcmla_z (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f16_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_z_tied3, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z0, 180), + z0 = svcmla_z (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_z_untied, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z3, 180), + z0 = svcmla_z (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_z_tied1, svfloat16_t, + z0 = svcmla_f16_z (p0, z0, z1, z2, 270), + z0 = svcmla_z (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_z_tied2, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z0, z2, 270), + z0 = svcmla_z (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f16_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_z_tied3, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z0, 270), + z0 = svcmla_z (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_z_untied, svfloat16_t, + z0 = svcmla_f16_z (p0, z1, z2, z3, 270), + z0 = svcmla_z (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f16_x_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (p0, z0, z1, z2, 0), + z0 = svcmla_x (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z0, z2, 0), + z0 = svcmla_x (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f16_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z0, 0), + z0 = svcmla_x (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f16_x_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z3, 0), + z0 = svcmla_x (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f16_x_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (p0, z0, z1, z2, 90), + z0 = svcmla_x (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z0, z2, 90), + z0 = svcmla_x (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f16_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z0, 90), + z0 = svcmla_x (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f16_x_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z3, 90), + z0 = svcmla_x (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f16_x_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (p0, z0, z1, z2, 180), + z0 = svcmla_x (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z0, z2, 180), + z0 = svcmla_x (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f16_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z0, 180), + z0 = svcmla_x (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f16_x_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z3, 180), + z0 = svcmla_x (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f16_x_tied1: +** fcmla z0\.h, p0/m, z1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (p0, z0, z1, z2, 270), + z0 = svcmla_x (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, \1\.h, z2\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z0, z2, 270), + z0 = svcmla_x (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f16_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, \1\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z0, 270), + z0 = svcmla_x (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f16_x_untied: +** movprfx z0, z1 +** fcmla z0\.h, p0/m, z2\.h, z3\.h, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (p0, z1, z2, z3, 270), + z0 = svcmla_x (p0, z1, z2, z3, 270)) + +/* +** ptrue_cmla_0_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z0, z1, z2, 0), + z0 = svcmla_x (svptrue_b16 (), z0, z1, z2, 0)) + +/* +** ptrue_cmla_0_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z0, z2, 0), + z0 = svcmla_x (svptrue_b16 (), z1, z0, z2, 0)) + +/* +** ptrue_cmla_0_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z0, 0), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z0, 0)) + +/* +** ptrue_cmla_0_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z3, 0), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z3, 0)) + +/* +** ptrue_cmla_90_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z0, z1, z2, 90), + z0 = svcmla_x (svptrue_b16 (), z0, z1, z2, 90)) + +/* +** ptrue_cmla_90_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z0, z2, 90), + z0 = svcmla_x (svptrue_b16 (), z1, z0, z2, 90)) + +/* +** ptrue_cmla_90_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z0, 90), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z0, 90)) + +/* +** ptrue_cmla_90_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z3, 90), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z3, 90)) + +/* +** ptrue_cmla_180_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z0, z1, z2, 180), + z0 = svcmla_x (svptrue_b16 (), z0, z1, z2, 180)) + +/* +** ptrue_cmla_180_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z0, z2, 180), + z0 = svcmla_x (svptrue_b16 (), z1, z0, z2, 180)) + +/* +** ptrue_cmla_180_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z0, 180), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z0, 180)) + +/* +** ptrue_cmla_180_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z3, 180), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z3, 180)) + +/* +** ptrue_cmla_270_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f16_x_tied1, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z0, z1, z2, 270), + z0 = svcmla_x (svptrue_b16 (), z0, z1, z2, 270)) + +/* +** ptrue_cmla_270_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f16_x_tied2, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z0, z2, 270), + z0 = svcmla_x (svptrue_b16 (), z1, z0, z2, 270)) + +/* +** ptrue_cmla_270_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f16_x_tied3, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z0, 270), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z0, 270)) + +/* +** ptrue_cmla_270_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f16_x_untied, svfloat16_t, + z0 = svcmla_f16_x (svptrue_b16 (), z1, z2, z3, 270), + z0 = svcmla_x (svptrue_b16 (), z1, z2, z3, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f32.c new file mode 100644 index 00000000000..b266738b248 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f32.c @@ -0,0 +1,675 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmla_0_f32_m_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_m_tied1, svfloat32_t, + z0 = svcmla_f32_m (p0, z0, z1, z2, 0), + z0 = svcmla_m (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_m_tied2, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z0, z2, 0), + z0 = svcmla_m (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_m_tied3, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z0, 0), + z0 = svcmla_m (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f32_m_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_m_untied, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z3, 0), + z0 = svcmla_m (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f32_m_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_m_tied1, svfloat32_t, + z0 = svcmla_f32_m (p0, z0, z1, z2, 90), + z0 = svcmla_m (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_m_tied2, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z0, z2, 90), + z0 = svcmla_m (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_m_tied3, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z0, 90), + z0 = svcmla_m (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f32_m_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_m_untied, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z3, 90), + z0 = svcmla_m (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f32_m_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_m_tied1, svfloat32_t, + z0 = svcmla_f32_m (p0, z0, z1, z2, 180), + z0 = svcmla_m (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_m_tied2, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z0, z2, 180), + z0 = svcmla_m (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_m_tied3, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z0, 180), + z0 = svcmla_m (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f32_m_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_m_untied, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z3, 180), + z0 = svcmla_m (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f32_m_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_m_tied1, svfloat32_t, + z0 = svcmla_f32_m (p0, z0, z1, z2, 270), + z0 = svcmla_m (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_m_tied2, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z0, z2, 270), + z0 = svcmla_m (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_m_tied3, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z0, 270), + z0 = svcmla_m (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f32_m_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_m_untied, svfloat32_t, + z0 = svcmla_f32_m (p0, z1, z2, z3, 270), + z0 = svcmla_m (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_z_tied1, svfloat32_t, + z0 = svcmla_f32_z (p0, z0, z1, z2, 0), + z0 = svcmla_z (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_z_tied2, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z0, z2, 0), + z0 = svcmla_z (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f32_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_z_tied3, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z0, 0), + z0 = svcmla_z (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_z_untied, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z3, 0), + z0 = svcmla_z (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_z_tied1, svfloat32_t, + z0 = svcmla_f32_z (p0, z0, z1, z2, 90), + z0 = svcmla_z (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_z_tied2, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z0, z2, 90), + z0 = svcmla_z (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f32_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_z_tied3, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z0, 90), + z0 = svcmla_z (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_z_untied, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z3, 90), + z0 = svcmla_z (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_z_tied1, svfloat32_t, + z0 = svcmla_f32_z (p0, z0, z1, z2, 180), + z0 = svcmla_z (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_z_tied2, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z0, z2, 180), + z0 = svcmla_z (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f32_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_z_tied3, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z0, 180), + z0 = svcmla_z (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_z_untied, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z3, 180), + z0 = svcmla_z (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_z_tied1, svfloat32_t, + z0 = svcmla_f32_z (p0, z0, z1, z2, 270), + z0 = svcmla_z (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_z_tied2, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z0, z2, 270), + z0 = svcmla_z (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f32_z_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_z_tied3, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z0, 270), + z0 = svcmla_z (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_z_untied, svfloat32_t, + z0 = svcmla_f32_z (p0, z1, z2, z3, 270), + z0 = svcmla_z (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f32_x_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (p0, z0, z1, z2, 0), + z0 = svcmla_x (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z0, z2, 0), + z0 = svcmla_x (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f32_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z0, 0), + z0 = svcmla_x (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f32_x_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z3, 0), + z0 = svcmla_x (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f32_x_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (p0, z0, z1, z2, 90), + z0 = svcmla_x (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z0, z2, 90), + z0 = svcmla_x (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f32_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z0, 90), + z0 = svcmla_x (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f32_x_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z3, 90), + z0 = svcmla_x (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f32_x_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (p0, z0, z1, z2, 180), + z0 = svcmla_x (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z0, z2, 180), + z0 = svcmla_x (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f32_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z0, 180), + z0 = svcmla_x (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f32_x_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z3, 180), + z0 = svcmla_x (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f32_x_tied1: +** fcmla z0\.s, p0/m, z1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (p0, z0, z1, z2, 270), + z0 = svcmla_x (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, \1\.s, z2\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z0, z2, 270), + z0 = svcmla_x (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f32_x_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, \1\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z0, 270), + z0 = svcmla_x (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f32_x_untied: +** movprfx z0, z1 +** fcmla z0\.s, p0/m, z2\.s, z3\.s, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (p0, z1, z2, z3, 270), + z0 = svcmla_x (p0, z1, z2, z3, 270)) + +/* +** ptrue_cmla_0_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z0, z1, z2, 0), + z0 = svcmla_x (svptrue_b32 (), z0, z1, z2, 0)) + +/* +** ptrue_cmla_0_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z0, z2, 0), + z0 = svcmla_x (svptrue_b32 (), z1, z0, z2, 0)) + +/* +** ptrue_cmla_0_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z0, 0), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z0, 0)) + +/* +** ptrue_cmla_0_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z3, 0), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z3, 0)) + +/* +** ptrue_cmla_90_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z0, z1, z2, 90), + z0 = svcmla_x (svptrue_b32 (), z0, z1, z2, 90)) + +/* +** ptrue_cmla_90_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z0, z2, 90), + z0 = svcmla_x (svptrue_b32 (), z1, z0, z2, 90)) + +/* +** ptrue_cmla_90_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z0, 90), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z0, 90)) + +/* +** ptrue_cmla_90_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z3, 90), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z3, 90)) + +/* +** ptrue_cmla_180_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z0, z1, z2, 180), + z0 = svcmla_x (svptrue_b32 (), z0, z1, z2, 180)) + +/* +** ptrue_cmla_180_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z0, z2, 180), + z0 = svcmla_x (svptrue_b32 (), z1, z0, z2, 180)) + +/* +** ptrue_cmla_180_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z0, 180), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z0, 180)) + +/* +** ptrue_cmla_180_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z3, 180), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z3, 180)) + +/* +** ptrue_cmla_270_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f32_x_tied1, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z0, z1, z2, 270), + z0 = svcmla_x (svptrue_b32 (), z0, z1, z2, 270)) + +/* +** ptrue_cmla_270_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f32_x_tied2, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z0, z2, 270), + z0 = svcmla_x (svptrue_b32 (), z1, z0, z2, 270)) + +/* +** ptrue_cmla_270_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f32_x_tied3, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z0, 270), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z0, 270)) + +/* +** ptrue_cmla_270_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f32_x_untied, svfloat32_t, + z0 = svcmla_f32_x (svptrue_b32 (), z1, z2, z3, 270), + z0 = svcmla_x (svptrue_b32 (), z1, z2, z3, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f64.c new file mode 100644 index 00000000000..024ae5ce3ad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_f64.c @@ -0,0 +1,675 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmla_0_f64_m_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_m_tied1, svfloat64_t, + z0 = svcmla_f64_m (p0, z0, z1, z2, 0), + z0 = svcmla_m (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_m_tied2, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z0, z2, 0), + z0 = svcmla_m (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_m_tied3, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z0, 0), + z0 = svcmla_m (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f64_m_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_m_untied, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z3, 0), + z0 = svcmla_m (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f64_m_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_m_tied1, svfloat64_t, + z0 = svcmla_f64_m (p0, z0, z1, z2, 90), + z0 = svcmla_m (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_m_tied2, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z0, z2, 90), + z0 = svcmla_m (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_m_tied3, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z0, 90), + z0 = svcmla_m (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f64_m_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_m_untied, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z3, 90), + z0 = svcmla_m (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f64_m_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_m_tied1, svfloat64_t, + z0 = svcmla_f64_m (p0, z0, z1, z2, 180), + z0 = svcmla_m (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_m_tied2, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z0, z2, 180), + z0 = svcmla_m (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_m_tied3, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z0, 180), + z0 = svcmla_m (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f64_m_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_m_untied, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z3, 180), + z0 = svcmla_m (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f64_m_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_m_tied1, svfloat64_t, + z0 = svcmla_f64_m (p0, z0, z1, z2, 270), + z0 = svcmla_m (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_m_tied2, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z0, z2, 270), + z0 = svcmla_m (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_m_tied3, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z0, 270), + z0 = svcmla_m (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f64_m_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_m_untied, svfloat64_t, + z0 = svcmla_f64_m (p0, z1, z2, z3, 270), + z0 = svcmla_m (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_z_tied1, svfloat64_t, + z0 = svcmla_f64_z (p0, z0, z1, z2, 0), + z0 = svcmla_z (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, \1, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_z_tied2, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z0, z2, 0), + z0 = svcmla_z (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f64_z_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, \1, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_z_tied3, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z0, 0), + z0 = svcmla_z (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_z_untied, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z3, 0), + z0 = svcmla_z (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_z_tied1, svfloat64_t, + z0 = svcmla_f64_z (p0, z0, z1, z2, 90), + z0 = svcmla_z (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, \1, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_z_tied2, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z0, z2, 90), + z0 = svcmla_z (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f64_z_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_z_tied3, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z0, 90), + z0 = svcmla_z (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_z_untied, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z3, 90), + z0 = svcmla_z (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_z_tied1, svfloat64_t, + z0 = svcmla_f64_z (p0, z0, z1, z2, 180), + z0 = svcmla_z (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, \1, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_z_tied2, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z0, z2, 180), + z0 = svcmla_z (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f64_z_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, \1, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_z_tied3, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z0, 180), + z0 = svcmla_z (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_z_untied, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z3, 180), + z0 = svcmla_z (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_z_tied1, svfloat64_t, + z0 = svcmla_f64_z (p0, z0, z1, z2, 270), + z0 = svcmla_z (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, \1, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_z_tied2, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z0, z2, 270), + z0 = svcmla_z (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f64_z_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_z_tied3, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z0, 270), + z0 = svcmla_z (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_z_untied, svfloat64_t, + z0 = svcmla_f64_z (p0, z1, z2, z3, 270), + z0 = svcmla_z (p0, z1, z2, z3, 270)) + +/* +** cmla_0_f64_x_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (p0, z0, z1, z2, 0), + z0 = svcmla_x (p0, z0, z1, z2, 0)) + +/* +** cmla_0_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z0, z2, 0), + z0 = svcmla_x (p0, z1, z0, z2, 0)) + +/* +** cmla_0_f64_x_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z0, 0), + z0 = svcmla_x (p0, z1, z2, z0, 0)) + +/* +** cmla_0_f64_x_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_0_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z3, 0), + z0 = svcmla_x (p0, z1, z2, z3, 0)) + +/* +** cmla_90_f64_x_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (p0, z0, z1, z2, 90), + z0 = svcmla_x (p0, z0, z1, z2, 90)) + +/* +** cmla_90_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z0, z2, 90), + z0 = svcmla_x (p0, z1, z0, z2, 90)) + +/* +** cmla_90_f64_x_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z0, 90), + z0 = svcmla_x (p0, z1, z2, z0, 90)) + +/* +** cmla_90_f64_x_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_90_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z3, 90), + z0 = svcmla_x (p0, z1, z2, z3, 90)) + +/* +** cmla_180_f64_x_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (p0, z0, z1, z2, 180), + z0 = svcmla_x (p0, z0, z1, z2, 180)) + +/* +** cmla_180_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z0, z2, 180), + z0 = svcmla_x (p0, z1, z0, z2, 180)) + +/* +** cmla_180_f64_x_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z0, 180), + z0 = svcmla_x (p0, z1, z2, z0, 180)) + +/* +** cmla_180_f64_x_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_180_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z3, 180), + z0 = svcmla_x (p0, z1, z2, z3, 180)) + +/* +** cmla_270_f64_x_tied1: +** fcmla z0\.d, p0/m, z1\.d, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (p0, z0, z1, z2, 270), + z0 = svcmla_x (p0, z0, z1, z2, 270)) + +/* +** cmla_270_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, \1, z2\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z0, z2, 270), + z0 = svcmla_x (p0, z1, z0, z2, 270)) + +/* +** cmla_270_f64_x_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, \1, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z0, 270), + z0 = svcmla_x (p0, z1, z2, z0, 270)) + +/* +** cmla_270_f64_x_untied: +** movprfx z0, z1 +** fcmla z0\.d, p0/m, z2\.d, z3\.d, #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_270_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (p0, z1, z2, z3, 270), + z0 = svcmla_x (p0, z1, z2, z3, 270)) + +/* +** ptrue_cmla_0_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z0, z1, z2, 0), + z0 = svcmla_x (svptrue_b64 (), z0, z1, z2, 0)) + +/* +** ptrue_cmla_0_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z0, z2, 0), + z0 = svcmla_x (svptrue_b64 (), z1, z0, z2, 0)) + +/* +** ptrue_cmla_0_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z0, 0), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z0, 0)) + +/* +** ptrue_cmla_0_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_0_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z3, 0), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z3, 0)) + +/* +** ptrue_cmla_90_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z0, z1, z2, 90), + z0 = svcmla_x (svptrue_b64 (), z0, z1, z2, 90)) + +/* +** ptrue_cmla_90_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z0, z2, 90), + z0 = svcmla_x (svptrue_b64 (), z1, z0, z2, 90)) + +/* +** ptrue_cmla_90_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z0, 90), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z0, 90)) + +/* +** ptrue_cmla_90_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_90_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z3, 90), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z3, 90)) + +/* +** ptrue_cmla_180_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z0, z1, z2, 180), + z0 = svcmla_x (svptrue_b64 (), z0, z1, z2, 180)) + +/* +** ptrue_cmla_180_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z0, z2, 180), + z0 = svcmla_x (svptrue_b64 (), z1, z0, z2, 180)) + +/* +** ptrue_cmla_180_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z0, 180), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z0, 180)) + +/* +** ptrue_cmla_180_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_180_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z3, 180), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z3, 180)) + +/* +** ptrue_cmla_270_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f64_x_tied1, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z0, z1, z2, 270), + z0 = svcmla_x (svptrue_b64 (), z0, z1, z2, 270)) + +/* +** ptrue_cmla_270_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f64_x_tied2, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z0, z2, 270), + z0 = svcmla_x (svptrue_b64 (), z1, z0, z2, 270)) + +/* +** ptrue_cmla_270_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f64_x_tied3, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z0, 270), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z0, 270)) + +/* +** ptrue_cmla_270_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_cmla_270_f64_x_untied, svfloat64_t, + z0 = svcmla_f64_x (svptrue_b64 (), z1, z2, z3, 270), + z0 = svcmla_x (svptrue_b64 (), z1, z2, z3, 270)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f16.c new file mode 100644 index 00000000000..16f1b77ad3c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f16.c @@ -0,0 +1,194 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmla_lane_0_0_f16_tied1: +** fcmla z0\.h, z1\.h, z2\.h\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f16_tied1, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 0, 0), + z0 = svcmla_lane (z0, z1, z2, 0, 0)) + +/* +** cmla_lane_0_0_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, \1\.h, z2\.h\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f16_tied2, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z0, z2, 0, 0), + z0 = svcmla_lane (z1, z0, z2, 0, 0)) + +/* +** cmla_lane_0_0_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, \1\.h\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f16_tied3, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z0, 0, 0), + z0 = svcmla_lane (z1, z2, z0, 0, 0)) + +/* +** cmla_lane_0_0_f16_untied: +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, z3\.h\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f16_untied, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z3, 0, 0), + z0 = svcmla_lane (z1, z2, z3, 0, 0)) + +/* +** cmla_lane_0_90_f16_tied1: +** fcmla z0\.h, z1\.h, z2\.h\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f16_tied1, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 0, 90), + z0 = svcmla_lane (z0, z1, z2, 0, 90)) + +/* +** cmla_lane_0_90_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, \1\.h, z2\.h\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f16_tied2, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z0, z2, 0, 90), + z0 = svcmla_lane (z1, z0, z2, 0, 90)) + +/* +** cmla_lane_0_90_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, \1\.h\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f16_tied3, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z0, 0, 90), + z0 = svcmla_lane (z1, z2, z0, 0, 90)) + +/* +** cmla_lane_0_90_f16_untied: +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, z3\.h\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f16_untied, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z3, 0, 90), + z0 = svcmla_lane (z1, z2, z3, 0, 90)) + +/* +** cmla_lane_0_180_f16_tied1: +** fcmla z0\.h, z1\.h, z2\.h\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f16_tied1, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 0, 180), + z0 = svcmla_lane (z0, z1, z2, 0, 180)) + +/* +** cmla_lane_0_180_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, \1\.h, z2\.h\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f16_tied2, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z0, z2, 0, 180), + z0 = svcmla_lane (z1, z0, z2, 0, 180)) + +/* +** cmla_lane_0_180_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, \1\.h\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f16_tied3, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z0, 0, 180), + z0 = svcmla_lane (z1, z2, z0, 0, 180)) + +/* +** cmla_lane_0_180_f16_untied: +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, z3\.h\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f16_untied, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z3, 0, 180), + z0 = svcmla_lane (z1, z2, z3, 0, 180)) + +/* +** cmla_lane_0_270_f16_tied1: +** fcmla z0\.h, z1\.h, z2\.h\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f16_tied1, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 0, 270), + z0 = svcmla_lane (z0, z1, z2, 0, 270)) + +/* +** cmla_lane_0_270_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, \1\.h, z2\.h\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f16_tied2, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z0, z2, 0, 270), + z0 = svcmla_lane (z1, z0, z2, 0, 270)) + +/* +** cmla_lane_0_270_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, \1\.h\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f16_tied3, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z0, 0, 270), + z0 = svcmla_lane (z1, z2, z0, 0, 270)) + +/* +** cmla_lane_0_270_f16_untied: +** movprfx z0, z1 +** fcmla z0\.h, z2\.h, z3\.h\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f16_untied, svfloat16_t, + z0 = svcmla_lane_f16 (z1, z2, z3, 0, 270), + z0 = svcmla_lane (z1, z2, z3, 0, 270)) + +/* +** cmla_lane_1_f16: +** fcmla z0\.h, z1\.h, z2\.h\[1\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_1_f16, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 1, 0), + z0 = svcmla_lane (z0, z1, z2, 1, 0)) + +/* +** cmla_lane_2_f16: +** fcmla z0\.h, z1\.h, z2\.h\[2\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_2_f16, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 2, 0), + z0 = svcmla_lane (z0, z1, z2, 2, 0)) + +/* +** cmla_lane_3_f16: +** fcmla z0\.h, z1\.h, z2\.h\[3\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_3_f16, svfloat16_t, + z0 = svcmla_lane_f16 (z0, z1, z2, 3, 0), + z0 = svcmla_lane (z0, z1, z2, 3, 0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f32.c new file mode 100644 index 00000000000..85bff68fd8d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmla_lane_f32.c @@ -0,0 +1,176 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmla_lane_0_0_f32_tied1: +** fcmla z0\.s, z1\.s, z2\.s\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f32_tied1, svfloat32_t, + z0 = svcmla_lane_f32 (z0, z1, z2, 0, 0), + z0 = svcmla_lane (z0, z1, z2, 0, 0)) + +/* +** cmla_lane_0_0_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, \1\.s, z2\.s\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f32_tied2, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z0, z2, 0, 0), + z0 = svcmla_lane (z1, z0, z2, 0, 0)) + +/* +** cmla_lane_0_0_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, \1\.s\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f32_tied3, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z0, 0, 0), + z0 = svcmla_lane (z1, z2, z0, 0, 0)) + +/* +** cmla_lane_0_0_f32_untied: +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, z3\.s\[0\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_0_f32_untied, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z3, 0, 0), + z0 = svcmla_lane (z1, z2, z3, 0, 0)) + +/* +** cmla_lane_0_90_f32_tied1: +** fcmla z0\.s, z1\.s, z2\.s\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f32_tied1, svfloat32_t, + z0 = svcmla_lane_f32 (z0, z1, z2, 0, 90), + z0 = svcmla_lane (z0, z1, z2, 0, 90)) + +/* +** cmla_lane_0_90_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, \1\.s, z2\.s\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f32_tied2, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z0, z2, 0, 90), + z0 = svcmla_lane (z1, z0, z2, 0, 90)) + +/* +** cmla_lane_0_90_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, \1\.s\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f32_tied3, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z0, 0, 90), + z0 = svcmla_lane (z1, z2, z0, 0, 90)) + +/* +** cmla_lane_0_90_f32_untied: +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, z3\.s\[0\], #90 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_90_f32_untied, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z3, 0, 90), + z0 = svcmla_lane (z1, z2, z3, 0, 90)) + +/* +** cmla_lane_0_180_f32_tied1: +** fcmla z0\.s, z1\.s, z2\.s\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f32_tied1, svfloat32_t, + z0 = svcmla_lane_f32 (z0, z1, z2, 0, 180), + z0 = svcmla_lane (z0, z1, z2, 0, 180)) + +/* +** cmla_lane_0_180_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, \1\.s, z2\.s\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f32_tied2, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z0, z2, 0, 180), + z0 = svcmla_lane (z1, z0, z2, 0, 180)) + +/* +** cmla_lane_0_180_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, \1\.s\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f32_tied3, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z0, 0, 180), + z0 = svcmla_lane (z1, z2, z0, 0, 180)) + +/* +** cmla_lane_0_180_f32_untied: +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, z3\.s\[0\], #180 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_180_f32_untied, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z3, 0, 180), + z0 = svcmla_lane (z1, z2, z3, 0, 180)) + +/* +** cmla_lane_0_270_f32_tied1: +** fcmla z0\.s, z1\.s, z2\.s\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f32_tied1, svfloat32_t, + z0 = svcmla_lane_f32 (z0, z1, z2, 0, 270), + z0 = svcmla_lane (z0, z1, z2, 0, 270)) + +/* +** cmla_lane_0_270_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, \1\.s, z2\.s\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f32_tied2, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z0, z2, 0, 270), + z0 = svcmla_lane (z1, z0, z2, 0, 270)) + +/* +** cmla_lane_0_270_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, \1\.s\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f32_tied3, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z0, 0, 270), + z0 = svcmla_lane (z1, z2, z0, 0, 270)) + +/* +** cmla_lane_0_270_f32_untied: +** movprfx z0, z1 +** fcmla z0\.s, z2\.s, z3\.s\[0\], #270 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_0_270_f32_untied, svfloat32_t, + z0 = svcmla_lane_f32 (z1, z2, z3, 0, 270), + z0 = svcmla_lane (z1, z2, z3, 0, 270)) + +/* +** cmla_lane_1_f32: +** fcmla z0\.s, z1\.s, z2\.s\[1\], #0 +** ret +*/ +TEST_UNIFORM_Z (cmla_lane_1_f32, svfloat32_t, + z0 = svcmla_lane_f32 (z0, z1, z2, 1, 0), + z0 = svcmla_lane (z0, z1, z2, 1, 0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f16.c new file mode 100644 index 00000000000..7149ad3004a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f16.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_f16_tied: +** fcmeq p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f16_tied, svfloat16_t, + p0 = svcmpeq_f16 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_f16_untied: +** fcmeq p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f16_untied, svfloat16_t, + p0 = svcmpeq_f16 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_h4_f16: +** mov (z[0-9]+\.h), h4 +** fcmeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZD (cmpeq_h4_f16, svfloat16_t, float16_t, + p0 = svcmpeq_n_f16 (p1, z0, d4), + p0 = svcmpeq (p1, z0, d4)) + +/* +** cmpeq_0_f16: +** fcmeq p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_f16, svfloat16_t, + p0 = svcmpeq_n_f16 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fcmeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_f16, svfloat16_t, + p0 = svcmpeq_n_f16 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f32.c new file mode 100644 index 00000000000..05910bc50f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f32.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_f32_tied: +** fcmeq p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f32_tied, svfloat32_t, + p0 = svcmpeq_f32 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_f32_untied: +** fcmeq p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f32_untied, svfloat32_t, + p0 = svcmpeq_f32 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_s4_f32: +** mov (z[0-9]+\.s), s4 +** fcmeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZD (cmpeq_s4_f32, svfloat32_t, float32_t, + p0 = svcmpeq_n_f32 (p1, z0, d4), + p0 = svcmpeq (p1, z0, d4)) + +/* +** cmpeq_0_f32: +** fcmeq p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_f32, svfloat32_t, + p0 = svcmpeq_n_f32 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fcmeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_f32, svfloat32_t, + p0 = svcmpeq_n_f32 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f64.c new file mode 100644 index 00000000000..f94bdfe2755 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_f64.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_f64_tied: +** fcmeq p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f64_tied, svfloat64_t, + p0 = svcmpeq_f64 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_f64_untied: +** fcmeq p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_f64_untied, svfloat64_t, + p0 = svcmpeq_f64 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_d4_f64: +** mov (z[0-9]+\.d), d4 +** fcmeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZD (cmpeq_d4_f64, svfloat64_t, float64_t, + p0 = svcmpeq_n_f64 (p1, z0, d4), + p0 = svcmpeq (p1, z0, d4)) + +/* +** cmpeq_0_f64: +** fcmeq p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_f64, svfloat64_t, + p0 = svcmpeq_n_f64 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fcmeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_f64, svfloat64_t, + p0 = svcmpeq_n_f64 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s16.c new file mode 100644 index 00000000000..b0befcb7795 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_s16_tied: +** cmpeq p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s16_tied, svint16_t, + p0 = svcmpeq_s16 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_s16_untied: +** cmpeq p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s16_untied, svint16_t, + p0 = svcmpeq_s16 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_s16: +** mov (z[0-9]+\.h), w0 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_s16, svint16_t, int16_t, + p0 = svcmpeq_n_s16 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_s16: +** cmpeq p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_s16: +** cmpeq p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_s16: +** cmpeq p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_s16: +** mov (z[0-9]+\.h), #16 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_s16: +** cmpeq p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_s16: +** cmpeq p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_s16: +** mov (z[0-9]+\.h), #-17 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_s16, svint16_t, + p0 = svcmpeq_n_s16 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s32.c new file mode 100644 index 00000000000..de48a2c386c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_s32_tied: +** cmpeq p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s32_tied, svint32_t, + p0 = svcmpeq_s32 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_s32_untied: +** cmpeq p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s32_untied, svint32_t, + p0 = svcmpeq_s32 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_s32: +** mov (z[0-9]+\.s), w0 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_s32, svint32_t, int32_t, + p0 = svcmpeq_n_s32 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_s32: +** cmpeq p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_s32: +** cmpeq p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_s32: +** cmpeq p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_s32: +** mov (z[0-9]+\.s), #16 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_s32: +** cmpeq p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_s32: +** cmpeq p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_s32: +** mov (z[0-9]+\.s), #-17 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_s32, svint32_t, + p0 = svcmpeq_n_s32 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s64.c new file mode 100644 index 00000000000..ff976712a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s64.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_s64_tied: +** cmpeq p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s64_tied, svint64_t, + p0 = svcmpeq_s64 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_s64_untied: +** cmpeq p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s64_untied, svint64_t, + p0 = svcmpeq_s64 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_x0_s64: +** mov (z[0-9]+\.d), x0 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_x0_s64, svint64_t, int64_t, + p0 = svcmpeq_n_s64 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_s64: +** cmpeq p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_s64: +** cmpeq p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_s64: +** cmpeq p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_s64: +** mov (z[0-9]+\.d), #16 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_s64: +** cmpeq p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_s64: +** cmpeq p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_s64: +** mov (z[0-9]+\.d), #-17 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_s64, svint64_t, + p0 = svcmpeq_n_s64 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s8.c new file mode 100644 index 00000000000..1325755a8f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_s8_tied: +** cmpeq p0\.b, p0/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s8_tied, svint8_t, + p0 = svcmpeq_s8 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_s8_untied: +** cmpeq p0\.b, p1/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_s8_untied, svint8_t, + p0 = svcmpeq_s8 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_s8: +** mov (z[0-9]+\.b), w0 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_s8, svint8_t, int8_t, + p0 = svcmpeq_n_s8 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_s8: +** cmpeq p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_s8: +** cmpeq p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_s8: +** cmpeq p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_s8: +** mov (z[0-9]+\.b), #16 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_s8: +** cmpeq p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_s8: +** cmpeq p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_s8: +** mov (z[0-9]+\.b), #-17 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_s8, svint8_t, + p0 = svcmpeq_n_s8 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u16.c new file mode 100644 index 00000000000..91004692cde --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_u16_tied: +** cmpeq p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u16_tied, svuint16_t, + p0 = svcmpeq_u16 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_u16_untied: +** cmpeq p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u16_untied, svuint16_t, + p0 = svcmpeq_u16 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_u16: +** mov (z[0-9]+\.h), w0 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_u16, svuint16_t, uint16_t, + p0 = svcmpeq_n_u16 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_u16: +** cmpeq p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_u16: +** cmpeq p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_u16: +** cmpeq p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_u16: +** mov (z[0-9]+\.h), #16 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_u16: +** cmpeq p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_u16: +** cmpeq p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_u16: +** mov (z[0-9]+\.h), #-17 +** cmpeq p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_u16, svuint16_t, + p0 = svcmpeq_n_u16 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u32.c new file mode 100644 index 00000000000..2cff56eb6ce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_u32_tied: +** cmpeq p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u32_tied, svuint32_t, + p0 = svcmpeq_u32 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_u32_untied: +** cmpeq p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u32_untied, svuint32_t, + p0 = svcmpeq_u32 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_u32: +** mov (z[0-9]+\.s), w0 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_u32, svuint32_t, uint32_t, + p0 = svcmpeq_n_u32 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_u32: +** cmpeq p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_u32: +** cmpeq p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_u32: +** cmpeq p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_u32: +** mov (z[0-9]+\.s), #16 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_u32: +** cmpeq p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_u32: +** cmpeq p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_u32: +** mov (z[0-9]+\.s), #-17 +** cmpeq p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_u32, svuint32_t, + p0 = svcmpeq_n_u32 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u64.c new file mode 100644 index 00000000000..0f02c99880a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u64.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_u64_tied: +** cmpeq p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u64_tied, svuint64_t, + p0 = svcmpeq_u64 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_u64_untied: +** cmpeq p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u64_untied, svuint64_t, + p0 = svcmpeq_u64 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_x0_u64: +** mov (z[0-9]+\.d), x0 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_x0_u64, svuint64_t, uint64_t, + p0 = svcmpeq_n_u64 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_u64: +** cmpeq p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_u64: +** cmpeq p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_u64: +** cmpeq p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_u64: +** mov (z[0-9]+\.d), #16 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_u64: +** cmpeq p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_u64: +** cmpeq p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_u64: +** mov (z[0-9]+\.d), #-17 +** cmpeq p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_u64, svuint64_t, + p0 = svcmpeq_n_u64 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u8.c new file mode 100644 index 00000000000..ccd9a61c60b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_u8_tied: +** cmpeq p0\.b, p0/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u8_tied, svuint8_t, + p0 = svcmpeq_u8 (p0, z0, z1), + p0 = svcmpeq (p0, z0, z1)) + +/* +** cmpeq_u8_untied: +** cmpeq p0\.b, p1/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_u8_untied, svuint8_t, + p0 = svcmpeq_u8 (p1, z0, z1), + p0 = svcmpeq (p1, z0, z1)) + +/* +** cmpeq_w0_u8: +** mov (z[0-9]+\.b), w0 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_ZX (cmpeq_w0_u8, svuint8_t, uint8_t, + p0 = svcmpeq_n_u8 (p1, z0, x0), + p0 = svcmpeq (p1, z0, x0)) + +/* +** cmpeq_0_u8: +** cmpeq p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_0_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, 0), + p0 = svcmpeq (p1, z0, 0)) + +/* +** cmpeq_1_u8: +** cmpeq p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_1_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, 1), + p0 = svcmpeq (p1, z0, 1)) + +/* +** cmpeq_15_u8: +** cmpeq p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_15_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, 15), + p0 = svcmpeq (p1, z0, 15)) + +/* +** cmpeq_16_u8: +** mov (z[0-9]+\.b), #16 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_16_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, 16), + p0 = svcmpeq (p1, z0, 16)) + +/* +** cmpeq_m1_u8: +** cmpeq p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m1_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, -1), + p0 = svcmpeq (p1, z0, -1)) + +/* +** cmpeq_m16_u8: +** cmpeq p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_m16_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, -16), + p0 = svcmpeq (p1, z0, -16)) + +/* +** cmpeq_m17_u8: +** mov (z[0-9]+\.b), #-17 +** cmpeq p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpeq_m17_u8, svuint8_t, + p0 = svcmpeq_n_u8 (p1, z0, -17), + p0 = svcmpeq (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s16.c new file mode 100644 index 00000000000..c9712b3b459 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_wide_s16_tied: +** cmpeq p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmpeq_wide_s16 (p0, z0, z1), + p0 = svcmpeq_wide (p0, z0, z1)) + +/* +** cmpeq_wide_s16_untied: +** cmpeq p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmpeq_wide_s16 (p1, z0, z1), + p0 = svcmpeq_wide (p1, z0, z1)) + +/* +** cmpeq_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmpeq p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpeq_wide_x0_s16, svint16_t, int64_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, x0), + p0 = svcmpeq_wide (p1, z0, x0)) + +/* +** cmpeq_wide_0_s16: +** cmpeq p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_0_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, 0), + p0 = svcmpeq_wide (p1, z0, 0)) + +/* +** cmpeq_wide_1_s16: +** cmpeq p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_1_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, 1), + p0 = svcmpeq_wide (p1, z0, 1)) + +/* +** cmpeq_wide_15_s16: +** cmpeq p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_15_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, 15), + p0 = svcmpeq_wide (p1, z0, 15)) + +/* +** cmpeq_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmpeq p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_16_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, 16), + p0 = svcmpeq_wide (p1, z0, 16)) + +/* +** cmpeq_wide_m1_s16: +** cmpeq p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m1_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, -1), + p0 = svcmpeq_wide (p1, z0, -1)) + +/* +** cmpeq_wide_m16_s16: +** cmpeq p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m16_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, -16), + p0 = svcmpeq_wide (p1, z0, -16)) + +/* +** cmpeq_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmpeq p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m17_s16, svint16_t, + p0 = svcmpeq_wide_n_s16 (p1, z0, -17), + p0 = svcmpeq_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s32.c new file mode 100644 index 00000000000..22bd99f57da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_wide_s32_tied: +** cmpeq p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmpeq_wide_s32 (p0, z0, z1), + p0 = svcmpeq_wide (p0, z0, z1)) + +/* +** cmpeq_wide_s32_untied: +** cmpeq p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmpeq_wide_s32 (p1, z0, z1), + p0 = svcmpeq_wide (p1, z0, z1)) + +/* +** cmpeq_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmpeq p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpeq_wide_x0_s32, svint32_t, int64_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, x0), + p0 = svcmpeq_wide (p1, z0, x0)) + +/* +** cmpeq_wide_0_s32: +** cmpeq p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_0_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, 0), + p0 = svcmpeq_wide (p1, z0, 0)) + +/* +** cmpeq_wide_1_s32: +** cmpeq p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_1_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, 1), + p0 = svcmpeq_wide (p1, z0, 1)) + +/* +** cmpeq_wide_15_s32: +** cmpeq p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_15_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, 15), + p0 = svcmpeq_wide (p1, z0, 15)) + +/* +** cmpeq_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmpeq p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_16_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, 16), + p0 = svcmpeq_wide (p1, z0, 16)) + +/* +** cmpeq_wide_m1_s32: +** cmpeq p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m1_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, -1), + p0 = svcmpeq_wide (p1, z0, -1)) + +/* +** cmpeq_wide_m16_s32: +** cmpeq p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m16_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, -16), + p0 = svcmpeq_wide (p1, z0, -16)) + +/* +** cmpeq_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmpeq p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m17_s32, svint32_t, + p0 = svcmpeq_wide_n_s32 (p1, z0, -17), + p0 = svcmpeq_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s8.c new file mode 100644 index 00000000000..a9e9a0bf53b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpeq_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpeq_wide_s8_tied: +** cmpeq p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmpeq_wide_s8 (p0, z0, z1), + p0 = svcmpeq_wide (p0, z0, z1)) + +/* +** cmpeq_wide_s8_untied: +** cmpeq p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpeq_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmpeq_wide_s8 (p1, z0, z1), + p0 = svcmpeq_wide (p1, z0, z1)) + +/* +** cmpeq_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmpeq p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpeq_wide_x0_s8, svint8_t, int64_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, x0), + p0 = svcmpeq_wide (p1, z0, x0)) + +/* +** cmpeq_wide_0_s8: +** cmpeq p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_0_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, 0), + p0 = svcmpeq_wide (p1, z0, 0)) + +/* +** cmpeq_wide_1_s8: +** cmpeq p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_1_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, 1), + p0 = svcmpeq_wide (p1, z0, 1)) + +/* +** cmpeq_wide_15_s8: +** cmpeq p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_15_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, 15), + p0 = svcmpeq_wide (p1, z0, 15)) + +/* +** cmpeq_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmpeq p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_16_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, 16), + p0 = svcmpeq_wide (p1, z0, 16)) + +/* +** cmpeq_wide_m1_s8: +** cmpeq p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m1_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, -1), + p0 = svcmpeq_wide (p1, z0, -1)) + +/* +** cmpeq_wide_m16_s8: +** cmpeq p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m16_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, -16), + p0 = svcmpeq_wide (p1, z0, -16)) + +/* +** cmpeq_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmpeq p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpeq_wide_m17_s8, svint8_t, + p0 = svcmpeq_wide_n_s8 (p1, z0, -17), + p0 = svcmpeq_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f16.c new file mode 100644 index 00000000000..a6db8c16a84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f16.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_f16_tied: +** ( +** fcmge p0\.h, p0/z, z0\.h, z1\.h +** | +** fcmle p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f16_tied, svfloat16_t, + p0 = svcmpge_f16 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_f16_untied: +** ( +** fcmge p0\.h, p1/z, z0\.h, z1\.h +** | +** fcmle p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f16_untied, svfloat16_t, + p0 = svcmpge_f16 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** fcmge p0\.h, p1/z, z0\.h, \1 +** | +** fcmle p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpge_h4_f16, svfloat16_t, float16_t, + p0 = svcmpge_n_f16 (p1, z0, d4), + p0 = svcmpge (p1, z0, d4)) + +/* +** cmpge_0_f16: +** fcmge p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_f16, svfloat16_t, + p0 = svcmpge_n_f16 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** fcmge p0\.h, p1/z, z0\.h, \1 +** | +** fcmle p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_1_f16, svfloat16_t, + p0 = svcmpge_n_f16 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f32.c new file mode 100644 index 00000000000..ee2976e5824 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f32.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_f32_tied: +** ( +** fcmge p0\.s, p0/z, z0\.s, z1\.s +** | +** fcmle p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f32_tied, svfloat32_t, + p0 = svcmpge_f32 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_f32_untied: +** ( +** fcmge p0\.s, p1/z, z0\.s, z1\.s +** | +** fcmle p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f32_untied, svfloat32_t, + p0 = svcmpge_f32 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** fcmge p0\.s, p1/z, z0\.s, \1 +** | +** fcmle p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpge_s4_f32, svfloat32_t, float32_t, + p0 = svcmpge_n_f32 (p1, z0, d4), + p0 = svcmpge (p1, z0, d4)) + +/* +** cmpge_0_f32: +** fcmge p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_f32, svfloat32_t, + p0 = svcmpge_n_f32 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** fcmge p0\.s, p1/z, z0\.s, \1 +** | +** fcmle p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_1_f32, svfloat32_t, + p0 = svcmpge_n_f32 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f64.c new file mode 100644 index 00000000000..ceea0afe3ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_f64.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_f64_tied: +** ( +** fcmge p0\.d, p0/z, z0\.d, z1\.d +** | +** fcmle p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f64_tied, svfloat64_t, + p0 = svcmpge_f64 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_f64_untied: +** ( +** fcmge p0\.d, p1/z, z0\.d, z1\.d +** | +** fcmle p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_f64_untied, svfloat64_t, + p0 = svcmpge_f64 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** fcmge p0\.d, p1/z, z0\.d, \1 +** | +** fcmle p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpge_d4_f64, svfloat64_t, float64_t, + p0 = svcmpge_n_f64 (p1, z0, d4), + p0 = svcmpge (p1, z0, d4)) + +/* +** cmpge_0_f64: +** fcmge p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_f64, svfloat64_t, + p0 = svcmpge_n_f64 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** fcmge p0\.d, p1/z, z0\.d, \1 +** | +** fcmle p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_1_f64, svfloat64_t, + p0 = svcmpge_n_f64 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s16.c new file mode 100644 index 00000000000..de9180b8463 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_s16_tied: +** ( +** cmpge p0\.h, p0/z, z0\.h, z1\.h +** | +** cmple p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s16_tied, svint16_t, + p0 = svcmpge_s16 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_s16_untied: +** ( +** cmpge p0\.h, p1/z, z0\.h, z1\.h +** | +** cmple p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s16_untied, svint16_t, + p0 = svcmpge_s16 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_s16: +** mov (z[0-9]+\.h), w0 +** ( +** cmpge p0\.h, p1/z, z0\.h, \1 +** | +** cmple p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_s16, svint16_t, int16_t, + p0 = svcmpge_n_s16 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_s16: +** cmpge p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_s16: +** cmpge p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_s16: +** cmpge p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_s16: +** mov (z[0-9]+\.h), #16 +** ( +** cmpge p0\.h, p1/z, z0\.h, \1 +** | +** cmple p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_16_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_m1_s16: +** cmpge p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) + +/* +** cmpge_m16_s16: +** cmpge p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_m16_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, -16), + p0 = svcmpge (p1, z0, -16)) + +/* +** cmpge_m17_s16: +** mov (z[0-9]+\.h), #-17 +** ( +** cmpge p0\.h, p1/z, z0\.h, \1 +** | +** cmple p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m17_s16, svint16_t, + p0 = svcmpge_n_s16 (p1, z0, -17), + p0 = svcmpge (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s32.c new file mode 100644 index 00000000000..67286b1fe32 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_s32_tied: +** ( +** cmpge p0\.s, p0/z, z0\.s, z1\.s +** | +** cmple p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s32_tied, svint32_t, + p0 = svcmpge_s32 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_s32_untied: +** ( +** cmpge p0\.s, p1/z, z0\.s, z1\.s +** | +** cmple p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s32_untied, svint32_t, + p0 = svcmpge_s32 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_s32: +** mov (z[0-9]+\.s), w0 +** ( +** cmpge p0\.s, p1/z, z0\.s, \1 +** | +** cmple p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_s32, svint32_t, int32_t, + p0 = svcmpge_n_s32 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_s32: +** cmpge p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_s32: +** cmpge p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_s32: +** cmpge p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_s32: +** mov (z[0-9]+\.s), #16 +** ( +** cmpge p0\.s, p1/z, z0\.s, \1 +** | +** cmple p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_16_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_m1_s32: +** cmpge p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) + +/* +** cmpge_m16_s32: +** cmpge p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_m16_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, -16), + p0 = svcmpge (p1, z0, -16)) + +/* +** cmpge_m17_s32: +** mov (z[0-9]+\.s), #-17 +** ( +** cmpge p0\.s, p1/z, z0\.s, \1 +** | +** cmple p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m17_s32, svint32_t, + p0 = svcmpge_n_s32 (p1, z0, -17), + p0 = svcmpge (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s64.c new file mode 100644 index 00000000000..02e3ac07a50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_s64_tied: +** ( +** cmpge p0\.d, p0/z, z0\.d, z1\.d +** | +** cmple p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s64_tied, svint64_t, + p0 = svcmpge_s64 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_s64_untied: +** ( +** cmpge p0\.d, p1/z, z0\.d, z1\.d +** | +** cmple p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s64_untied, svint64_t, + p0 = svcmpge_s64 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_x0_s64: +** mov (z[0-9]+\.d), x0 +** ( +** cmpge p0\.d, p1/z, z0\.d, \1 +** | +** cmple p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_x0_s64, svint64_t, int64_t, + p0 = svcmpge_n_s64 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_s64: +** cmpge p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_s64: +** cmpge p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_s64: +** cmpge p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_s64: +** mov (z[0-9]+\.d), #16 +** ( +** cmpge p0\.d, p1/z, z0\.d, \1 +** | +** cmple p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_16_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_m1_s64: +** cmpge p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) + +/* +** cmpge_m16_s64: +** cmpge p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_m16_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, -16), + p0 = svcmpge (p1, z0, -16)) + +/* +** cmpge_m17_s64: +** mov (z[0-9]+\.d), #-17 +** ( +** cmpge p0\.d, p1/z, z0\.d, \1 +** | +** cmple p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m17_s64, svint64_t, + p0 = svcmpge_n_s64 (p1, z0, -17), + p0 = svcmpge (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s8.c new file mode 100644 index 00000000000..45c9c5f1031 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_s8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_s8_tied: +** ( +** cmpge p0\.b, p0/z, z0\.b, z1\.b +** | +** cmple p0\.b, p0/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s8_tied, svint8_t, + p0 = svcmpge_s8 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_s8_untied: +** ( +** cmpge p0\.b, p1/z, z0\.b, z1\.b +** | +** cmple p0\.b, p1/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_s8_untied, svint8_t, + p0 = svcmpge_s8 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_s8: +** mov (z[0-9]+\.b), w0 +** ( +** cmpge p0\.b, p1/z, z0\.b, \1 +** | +** cmple p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_s8, svint8_t, int8_t, + p0 = svcmpge_n_s8 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_s8: +** cmpge p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_s8: +** cmpge p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_s8: +** cmpge p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_s8: +** mov (z[0-9]+\.b), #16 +** ( +** cmpge p0\.b, p1/z, z0\.b, \1 +** | +** cmple p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_16_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_m1_s8: +** cmpge p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) + +/* +** cmpge_m16_s8: +** cmpge p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_m16_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, -16), + p0 = svcmpge (p1, z0, -16)) + +/* +** cmpge_m17_s8: +** mov (z[0-9]+\.b), #-17 +** ( +** cmpge p0\.b, p1/z, z0\.b, \1 +** | +** cmple p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m17_s8, svint8_t, + p0 = svcmpge_n_s8 (p1, z0, -17), + p0 = svcmpge (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u16.c new file mode 100644 index 00000000000..7c7d2b30743 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_u16_tied: +** ( +** cmphs p0\.h, p0/z, z0\.h, z1\.h +** | +** cmpls p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u16_tied, svuint16_t, + p0 = svcmpge_u16 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_u16_untied: +** ( +** cmphs p0\.h, p1/z, z0\.h, z1\.h +** | +** cmpls p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u16_untied, svuint16_t, + p0 = svcmpge_u16 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_u16: +** mov (z[0-9]+\.h), w0 +** ( +** cmphs p0\.h, p1/z, z0\.h, \1 +** | +** cmpls p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_u16, svuint16_t, uint16_t, + p0 = svcmpge_n_u16 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_u16: +** cmphs p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_u16: +** cmphs p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_u16: +** cmphs p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_u16: +** cmphs p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_16_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_127_u16: +** cmphs p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_127_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 127), + p0 = svcmpge (p1, z0, 127)) + +/* +** cmpge_128_u16: +** mov (z[0-9]+\.h), #128 +** ( +** cmphs p0\.h, p1/z, z0\.h, \1 +** | +** cmpls p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_128_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, 128), + p0 = svcmpge (p1, z0, 128)) + +/* +** cmpge_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.h, p1/z, z0\.h, \1\.h +** | +** cmpls p0\.h, p1/z, \1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_u16, svuint16_t, + p0 = svcmpge_n_u16 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u32.c new file mode 100644 index 00000000000..a2021ef50d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_u32_tied: +** ( +** cmphs p0\.s, p0/z, z0\.s, z1\.s +** | +** cmpls p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u32_tied, svuint32_t, + p0 = svcmpge_u32 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_u32_untied: +** ( +** cmphs p0\.s, p1/z, z0\.s, z1\.s +** | +** cmpls p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u32_untied, svuint32_t, + p0 = svcmpge_u32 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_u32: +** mov (z[0-9]+\.s), w0 +** ( +** cmphs p0\.s, p1/z, z0\.s, \1 +** | +** cmpls p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_u32, svuint32_t, uint32_t, + p0 = svcmpge_n_u32 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_u32: +** cmphs p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_u32: +** cmphs p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_u32: +** cmphs p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_u32: +** cmphs p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_16_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_127_u32: +** cmphs p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_127_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 127), + p0 = svcmpge (p1, z0, 127)) + +/* +** cmpge_128_u32: +** mov (z[0-9]+\.s), #128 +** ( +** cmphs p0\.s, p1/z, z0\.s, \1 +** | +** cmpls p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_128_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, 128), + p0 = svcmpge (p1, z0, 128)) + +/* +** cmpge_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.s, p1/z, z0\.s, \1\.s +** | +** cmpls p0\.s, p1/z, \1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_u32, svuint32_t, + p0 = svcmpge_n_u32 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u64.c new file mode 100644 index 00000000000..0f915959029 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_u64_tied: +** ( +** cmphs p0\.d, p0/z, z0\.d, z1\.d +** | +** cmpls p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u64_tied, svuint64_t, + p0 = svcmpge_u64 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_u64_untied: +** ( +** cmphs p0\.d, p1/z, z0\.d, z1\.d +** | +** cmpls p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u64_untied, svuint64_t, + p0 = svcmpge_u64 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_x0_u64: +** mov (z[0-9]+\.d), x0 +** ( +** cmphs p0\.d, p1/z, z0\.d, \1 +** | +** cmpls p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_x0_u64, svuint64_t, uint64_t, + p0 = svcmpge_n_u64 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_u64: +** cmphs p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_u64: +** cmphs p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_u64: +** cmphs p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_u64: +** cmphs p0\.d, p1/z, z0\.d, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_16_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_127_u64: +** cmphs p0\.d, p1/z, z0\.d, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_127_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 127), + p0 = svcmpge (p1, z0, 127)) + +/* +** cmpge_128_u64: +** mov (z[0-9]+\.d), #128 +** ( +** cmphs p0\.d, p1/z, z0\.d, \1 +** | +** cmpls p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_128_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, 128), + p0 = svcmpge (p1, z0, 128)) + +/* +** cmpge_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.d, p1/z, z0\.d, \1\.d +** | +** cmpls p0\.d, p1/z, \1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_u64, svuint64_t, + p0 = svcmpge_n_u64 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u8.c new file mode 100644 index 00000000000..39f988d01da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_u8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_u8_tied: +** ( +** cmphs p0\.b, p0/z, z0\.b, z1\.b +** | +** cmpls p0\.b, p0/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u8_tied, svuint8_t, + p0 = svcmpge_u8 (p0, z0, z1), + p0 = svcmpge (p0, z0, z1)) + +/* +** cmpge_u8_untied: +** ( +** cmphs p0\.b, p1/z, z0\.b, z1\.b +** | +** cmpls p0\.b, p1/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_u8_untied, svuint8_t, + p0 = svcmpge_u8 (p1, z0, z1), + p0 = svcmpge (p1, z0, z1)) + +/* +** cmpge_w0_u8: +** mov (z[0-9]+\.b), w0 +** ( +** cmphs p0\.b, p1/z, z0\.b, \1 +** | +** cmpls p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpge_w0_u8, svuint8_t, uint8_t, + p0 = svcmpge_n_u8 (p1, z0, x0), + p0 = svcmpge (p1, z0, x0)) + +/* +** cmpge_0_u8: +** cmphs p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_0_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 0), + p0 = svcmpge (p1, z0, 0)) + +/* +** cmpge_1_u8: +** cmphs p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_1_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 1), + p0 = svcmpge (p1, z0, 1)) + +/* +** cmpge_15_u8: +** cmphs p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_15_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 15), + p0 = svcmpge (p1, z0, 15)) + +/* +** cmpge_16_u8: +** cmphs p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_16_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 16), + p0 = svcmpge (p1, z0, 16)) + +/* +** cmpge_127_u8: +** cmphs p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_127_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 127), + p0 = svcmpge (p1, z0, 127)) + +/* +** cmpge_128_u8: +** mov (z[0-9]+\.b), #-128 +** ( +** cmphs p0\.b, p1/z, z0\.b, \1 +** | +** cmpls p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_128_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, 128), + p0 = svcmpge (p1, z0, 128)) + +/* +** cmpge_m1_u8: +** mov (z[0-9]+\.b), #-1 +** ( +** cmphs p0\.b, p1/z, z0\.b, \1 +** | +** cmpls p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpge_m1_u8, svuint8_t, + p0 = svcmpge_n_u8 (p1, z0, -1), + p0 = svcmpge (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s16.c new file mode 100644 index 00000000000..0400d787107 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_s16_tied: +** cmpge p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmpge_wide_s16 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_s16_untied: +** cmpge p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmpge_wide_s16 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmpge p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_s16, svint16_t, int64_t, + p0 = svcmpge_wide_n_s16 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_s16: +** cmpge p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_s16: +** cmpge p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_s16: +** cmpge p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmpge p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_m1_s16: +** cmpge p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) + +/* +** cmpge_wide_m16_s16: +** cmpge p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m16_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, -16), + p0 = svcmpge_wide (p1, z0, -16)) + +/* +** cmpge_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmpge p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m17_s16, svint16_t, + p0 = svcmpge_wide_n_s16 (p1, z0, -17), + p0 = svcmpge_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s32.c new file mode 100644 index 00000000000..ad7b9c55bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_s32_tied: +** cmpge p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmpge_wide_s32 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_s32_untied: +** cmpge p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmpge_wide_s32 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmpge p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_s32, svint32_t, int64_t, + p0 = svcmpge_wide_n_s32 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_s32: +** cmpge p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_s32: +** cmpge p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_s32: +** cmpge p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmpge p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_m1_s32: +** cmpge p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) + +/* +** cmpge_wide_m16_s32: +** cmpge p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m16_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, -16), + p0 = svcmpge_wide (p1, z0, -16)) + +/* +** cmpge_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmpge p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m17_s32, svint32_t, + p0 = svcmpge_wide_n_s32 (p1, z0, -17), + p0 = svcmpge_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s8.c new file mode 100644 index 00000000000..b03a4248890 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_s8_tied: +** cmpge p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmpge_wide_s8 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_s8_untied: +** cmpge p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmpge_wide_s8 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmpge p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_s8, svint8_t, int64_t, + p0 = svcmpge_wide_n_s8 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_s8: +** cmpge p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_s8: +** cmpge p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_s8: +** cmpge p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmpge p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_m1_s8: +** cmpge p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) + +/* +** cmpge_wide_m16_s8: +** cmpge p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m16_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, -16), + p0 = svcmpge_wide (p1, z0, -16)) + +/* +** cmpge_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmpge p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m17_s8, svint8_t, + p0 = svcmpge_wide_n_s8 (p1, z0, -17), + p0 = svcmpge_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u16.c new file mode 100644 index 00000000000..966b1e554be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_u16_tied: +** cmphs p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u16_tied, svuint16_t, svuint64_t, + p0 = svcmpge_wide_u16 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_u16_untied: +** cmphs p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u16_untied, svuint16_t, svuint64_t, + p0 = svcmpge_wide_u16 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_u16: +** mov (z[0-9]+\.d), x0 +** cmphs p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_u16, svuint16_t, uint64_t, + p0 = svcmpge_wide_n_u16 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_u16: +** cmphs p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_u16: +** cmphs p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_u16: +** cmphs p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_u16: +** cmphs p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_127_u16: +** cmphs p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_127_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 127), + p0 = svcmpge_wide (p1, z0, 127)) + +/* +** cmpge_wide_128_u16: +** mov (z[0-9]+\.d), #128 +** cmphs p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_128_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, 128), + p0 = svcmpge_wide (p1, z0, 128)) + +/* +** cmpge_wide_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** cmphs p0\.h, p1/z, z0\.h, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_u16, svuint16_t, + p0 = svcmpge_wide_n_u16 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u32.c new file mode 100644 index 00000000000..fdeb53a4659 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_u32_tied: +** cmphs p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u32_tied, svuint32_t, svuint64_t, + p0 = svcmpge_wide_u32 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_u32_untied: +** cmphs p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u32_untied, svuint32_t, svuint64_t, + p0 = svcmpge_wide_u32 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_u32: +** mov (z[0-9]+\.d), x0 +** cmphs p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_u32, svuint32_t, uint64_t, + p0 = svcmpge_wide_n_u32 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_u32: +** cmphs p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_u32: +** cmphs p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_u32: +** cmphs p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_u32: +** cmphs p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_127_u32: +** cmphs p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_127_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 127), + p0 = svcmpge_wide (p1, z0, 127)) + +/* +** cmpge_wide_128_u32: +** mov (z[0-9]+\.d), #128 +** cmphs p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_128_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, 128), + p0 = svcmpge_wide (p1, z0, 128)) + +/* +** cmpge_wide_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** cmphs p0\.s, p1/z, z0\.s, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_u32, svuint32_t, + p0 = svcmpge_wide_n_u32 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u8.c new file mode 100644 index 00000000000..56509312027 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpge_wide_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpge_wide_u8_tied: +** cmphs p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u8_tied, svuint8_t, svuint64_t, + p0 = svcmpge_wide_u8 (p0, z0, z1), + p0 = svcmpge_wide (p0, z0, z1)) + +/* +** cmpge_wide_u8_untied: +** cmphs p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpge_wide_u8_untied, svuint8_t, svuint64_t, + p0 = svcmpge_wide_u8 (p1, z0, z1), + p0 = svcmpge_wide (p1, z0, z1)) + +/* +** cmpge_wide_x0_u8: +** mov (z[0-9]+\.d), x0 +** cmphs p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpge_wide_x0_u8, svuint8_t, uint64_t, + p0 = svcmpge_wide_n_u8 (p1, z0, x0), + p0 = svcmpge_wide (p1, z0, x0)) + +/* +** cmpge_wide_0_u8: +** cmphs p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_0_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 0), + p0 = svcmpge_wide (p1, z0, 0)) + +/* +** cmpge_wide_1_u8: +** cmphs p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_1_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 1), + p0 = svcmpge_wide (p1, z0, 1)) + +/* +** cmpge_wide_15_u8: +** cmphs p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_15_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 15), + p0 = svcmpge_wide (p1, z0, 15)) + +/* +** cmpge_wide_16_u8: +** cmphs p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_16_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 16), + p0 = svcmpge_wide (p1, z0, 16)) + +/* +** cmpge_wide_127_u8: +** cmphs p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_127_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 127), + p0 = svcmpge_wide (p1, z0, 127)) + +/* +** cmpge_wide_128_u8: +** mov (z[0-9]+\.d), #128 +** cmphs p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_128_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, 128), + p0 = svcmpge_wide (p1, z0, 128)) + +/* +** cmpge_wide_m1_u8: +** mov (z[0-9]+)\.b, #-1 +** cmphs p0\.b, p1/z, z0\.b, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpge_wide_m1_u8, svuint8_t, + p0 = svcmpge_wide_n_u8 (p1, z0, -1), + p0 = svcmpge_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f16.c new file mode 100644 index 00000000000..69b01579470 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f16.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_f16_tied: +** ( +** fcmgt p0\.h, p0/z, z0\.h, z1\.h +** | +** fcmlt p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f16_tied, svfloat16_t, + p0 = svcmpgt_f16 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_f16_untied: +** ( +** fcmgt p0\.h, p1/z, z0\.h, z1\.h +** | +** fcmlt p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f16_untied, svfloat16_t, + p0 = svcmpgt_f16 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** fcmgt p0\.h, p1/z, z0\.h, \1 +** | +** fcmlt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpgt_h4_f16, svfloat16_t, float16_t, + p0 = svcmpgt_n_f16 (p1, z0, d4), + p0 = svcmpgt (p1, z0, d4)) + +/* +** cmpgt_0_f16: +** fcmgt p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_f16, svfloat16_t, + p0 = svcmpgt_n_f16 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.h, p1/z, z0\.h, \1 +** | +** fcmlt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_f16, svfloat16_t, + p0 = svcmpgt_n_f16 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f32.c new file mode 100644 index 00000000000..7d66b67c365 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f32.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_f32_tied: +** ( +** fcmgt p0\.s, p0/z, z0\.s, z1\.s +** | +** fcmlt p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f32_tied, svfloat32_t, + p0 = svcmpgt_f32 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_f32_untied: +** ( +** fcmgt p0\.s, p1/z, z0\.s, z1\.s +** | +** fcmlt p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f32_untied, svfloat32_t, + p0 = svcmpgt_f32 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** fcmgt p0\.s, p1/z, z0\.s, \1 +** | +** fcmlt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpgt_s4_f32, svfloat32_t, float32_t, + p0 = svcmpgt_n_f32 (p1, z0, d4), + p0 = svcmpgt (p1, z0, d4)) + +/* +** cmpgt_0_f32: +** fcmgt p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_f32, svfloat32_t, + p0 = svcmpgt_n_f32 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.s, p1/z, z0\.s, \1 +** | +** fcmlt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_f32, svfloat32_t, + p0 = svcmpgt_n_f32 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f64.c new file mode 100644 index 00000000000..f3a155476c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_f64.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_f64_tied: +** ( +** fcmgt p0\.d, p0/z, z0\.d, z1\.d +** | +** fcmlt p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f64_tied, svfloat64_t, + p0 = svcmpgt_f64 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_f64_untied: +** ( +** fcmgt p0\.d, p1/z, z0\.d, z1\.d +** | +** fcmlt p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_f64_untied, svfloat64_t, + p0 = svcmpgt_f64 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** fcmgt p0\.d, p1/z, z0\.d, \1 +** | +** fcmlt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZD (cmpgt_d4_f64, svfloat64_t, float64_t, + p0 = svcmpgt_n_f64 (p1, z0, d4), + p0 = svcmpgt (p1, z0, d4)) + +/* +** cmpgt_0_f64: +** fcmgt p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_f64, svfloat64_t, + p0 = svcmpgt_n_f64 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.d, p1/z, z0\.d, \1 +** | +** fcmlt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_f64, svfloat64_t, + p0 = svcmpgt_n_f64 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s16.c new file mode 100644 index 00000000000..cc86c0c00a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_s16_tied: +** ( +** cmpgt p0\.h, p0/z, z0\.h, z1\.h +** | +** cmplt p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s16_tied, svint16_t, + p0 = svcmpgt_s16 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_s16_untied: +** ( +** cmpgt p0\.h, p1/z, z0\.h, z1\.h +** | +** cmplt p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s16_untied, svint16_t, + p0 = svcmpgt_s16 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_s16: +** mov (z[0-9]+\.h), w0 +** ( +** cmpgt p0\.h, p1/z, z0\.h, \1 +** | +** cmplt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_s16, svint16_t, int16_t, + p0 = svcmpgt_n_s16 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_s16: +** cmpgt p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_s16: +** cmpgt p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_s16: +** cmpgt p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_s16: +** mov (z[0-9]+\.h), #16 +** ( +** cmpgt p0\.h, p1/z, z0\.h, \1 +** | +** cmplt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_m1_s16: +** cmpgt p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) + +/* +** cmpgt_m16_s16: +** cmpgt p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m16_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, -16), + p0 = svcmpgt (p1, z0, -16)) + +/* +** cmpgt_m17_s16: +** mov (z[0-9]+\.h), #-17 +** ( +** cmpgt p0\.h, p1/z, z0\.h, \1 +** | +** cmplt p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m17_s16, svint16_t, + p0 = svcmpgt_n_s16 (p1, z0, -17), + p0 = svcmpgt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s32.c new file mode 100644 index 00000000000..75f0cc73709 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_s32_tied: +** ( +** cmpgt p0\.s, p0/z, z0\.s, z1\.s +** | +** cmplt p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s32_tied, svint32_t, + p0 = svcmpgt_s32 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_s32_untied: +** ( +** cmpgt p0\.s, p1/z, z0\.s, z1\.s +** | +** cmplt p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s32_untied, svint32_t, + p0 = svcmpgt_s32 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_s32: +** mov (z[0-9]+\.s), w0 +** ( +** cmpgt p0\.s, p1/z, z0\.s, \1 +** | +** cmplt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_s32, svint32_t, int32_t, + p0 = svcmpgt_n_s32 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_s32: +** cmpgt p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_s32: +** cmpgt p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_s32: +** cmpgt p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_s32: +** mov (z[0-9]+\.s), #16 +** ( +** cmpgt p0\.s, p1/z, z0\.s, \1 +** | +** cmplt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_m1_s32: +** cmpgt p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) + +/* +** cmpgt_m16_s32: +** cmpgt p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m16_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, -16), + p0 = svcmpgt (p1, z0, -16)) + +/* +** cmpgt_m17_s32: +** mov (z[0-9]+\.s), #-17 +** ( +** cmpgt p0\.s, p1/z, z0\.s, \1 +** | +** cmplt p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m17_s32, svint32_t, + p0 = svcmpgt_n_s32 (p1, z0, -17), + p0 = svcmpgt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s64.c new file mode 100644 index 00000000000..dbfd55e6fc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_s64_tied: +** ( +** cmpgt p0\.d, p0/z, z0\.d, z1\.d +** | +** cmplt p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s64_tied, svint64_t, + p0 = svcmpgt_s64 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_s64_untied: +** ( +** cmpgt p0\.d, p1/z, z0\.d, z1\.d +** | +** cmplt p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s64_untied, svint64_t, + p0 = svcmpgt_s64 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_x0_s64: +** mov (z[0-9]+\.d), x0 +** ( +** cmpgt p0\.d, p1/z, z0\.d, \1 +** | +** cmplt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_x0_s64, svint64_t, int64_t, + p0 = svcmpgt_n_s64 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_s64: +** cmpgt p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_s64: +** cmpgt p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_s64: +** cmpgt p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_s64: +** mov (z[0-9]+\.d), #16 +** ( +** cmpgt p0\.d, p1/z, z0\.d, \1 +** | +** cmplt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_m1_s64: +** cmpgt p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) + +/* +** cmpgt_m16_s64: +** cmpgt p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m16_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, -16), + p0 = svcmpgt (p1, z0, -16)) + +/* +** cmpgt_m17_s64: +** mov (z[0-9]+\.d), #-17 +** ( +** cmpgt p0\.d, p1/z, z0\.d, \1 +** | +** cmplt p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m17_s64, svint64_t, + p0 = svcmpgt_n_s64 (p1, z0, -17), + p0 = svcmpgt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s8.c new file mode 100644 index 00000000000..710c2e602b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_s8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_s8_tied: +** ( +** cmpgt p0\.b, p0/z, z0\.b, z1\.b +** | +** cmplt p0\.b, p0/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s8_tied, svint8_t, + p0 = svcmpgt_s8 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_s8_untied: +** ( +** cmpgt p0\.b, p1/z, z0\.b, z1\.b +** | +** cmplt p0\.b, p1/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_s8_untied, svint8_t, + p0 = svcmpgt_s8 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_s8: +** mov (z[0-9]+\.b), w0 +** ( +** cmpgt p0\.b, p1/z, z0\.b, \1 +** | +** cmplt p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_s8, svint8_t, int8_t, + p0 = svcmpgt_n_s8 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_s8: +** cmpgt p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_s8: +** cmpgt p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_s8: +** cmpgt p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_s8: +** mov (z[0-9]+\.b), #16 +** ( +** cmpgt p0\.b, p1/z, z0\.b, \1 +** | +** cmplt p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_m1_s8: +** cmpgt p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) + +/* +** cmpgt_m16_s8: +** cmpgt p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_m16_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, -16), + p0 = svcmpgt (p1, z0, -16)) + +/* +** cmpgt_m17_s8: +** mov (z[0-9]+\.b), #-17 +** ( +** cmpgt p0\.b, p1/z, z0\.b, \1 +** | +** cmplt p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m17_s8, svint8_t, + p0 = svcmpgt_n_s8 (p1, z0, -17), + p0 = svcmpgt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u16.c new file mode 100644 index 00000000000..48e99c72c83 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_u16_tied: +** ( +** cmphi p0\.h, p0/z, z0\.h, z1\.h +** | +** cmplo p0\.h, p0/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u16_tied, svuint16_t, + p0 = svcmpgt_u16 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_u16_untied: +** ( +** cmphi p0\.h, p1/z, z0\.h, z1\.h +** | +** cmplo p0\.h, p1/z, z1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u16_untied, svuint16_t, + p0 = svcmpgt_u16 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_u16: +** mov (z[0-9]+\.h), w0 +** ( +** cmphi p0\.h, p1/z, z0\.h, \1 +** | +** cmplo p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_u16, svuint16_t, uint16_t, + p0 = svcmpgt_n_u16 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_u16: +** cmphi p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_u16: +** cmphi p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_u16: +** cmphi p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_u16: +** cmphi p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_127_u16: +** cmphi p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_127_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 127), + p0 = svcmpgt (p1, z0, 127)) + +/* +** cmpgt_128_u16: +** mov (z[0-9]+\.h), #128 +** ( +** cmphi p0\.h, p1/z, z0\.h, \1 +** | +** cmplo p0\.h, p1/z, \1, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_128_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, 128), + p0 = svcmpgt (p1, z0, 128)) + +/* +** cmpgt_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.h, p1/z, z0\.h, \1\.h +** | +** cmplo p0\.h, p1/z, \1\.h, z0\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_u16, svuint16_t, + p0 = svcmpgt_n_u16 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u32.c new file mode 100644 index 00000000000..408037d720c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_u32_tied: +** ( +** cmphi p0\.s, p0/z, z0\.s, z1\.s +** | +** cmplo p0\.s, p0/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u32_tied, svuint32_t, + p0 = svcmpgt_u32 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_u32_untied: +** ( +** cmphi p0\.s, p1/z, z0\.s, z1\.s +** | +** cmplo p0\.s, p1/z, z1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u32_untied, svuint32_t, + p0 = svcmpgt_u32 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_u32: +** mov (z[0-9]+\.s), w0 +** ( +** cmphi p0\.s, p1/z, z0\.s, \1 +** | +** cmplo p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_u32, svuint32_t, uint32_t, + p0 = svcmpgt_n_u32 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_u32: +** cmphi p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_u32: +** cmphi p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_u32: +** cmphi p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_u32: +** cmphi p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_127_u32: +** cmphi p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_127_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 127), + p0 = svcmpgt (p1, z0, 127)) + +/* +** cmpgt_128_u32: +** mov (z[0-9]+\.s), #128 +** ( +** cmphi p0\.s, p1/z, z0\.s, \1 +** | +** cmplo p0\.s, p1/z, \1, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_128_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, 128), + p0 = svcmpgt (p1, z0, 128)) + +/* +** cmpgt_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.s, p1/z, z0\.s, \1\.s +** | +** cmplo p0\.s, p1/z, \1\.s, z0\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_u32, svuint32_t, + p0 = svcmpgt_n_u32 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u64.c new file mode 100644 index 00000000000..f76a23e491b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_u64_tied: +** ( +** cmphi p0\.d, p0/z, z0\.d, z1\.d +** | +** cmplo p0\.d, p0/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u64_tied, svuint64_t, + p0 = svcmpgt_u64 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_u64_untied: +** ( +** cmphi p0\.d, p1/z, z0\.d, z1\.d +** | +** cmplo p0\.d, p1/z, z1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u64_untied, svuint64_t, + p0 = svcmpgt_u64 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_x0_u64: +** mov (z[0-9]+\.d), x0 +** ( +** cmphi p0\.d, p1/z, z0\.d, \1 +** | +** cmplo p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_x0_u64, svuint64_t, uint64_t, + p0 = svcmpgt_n_u64 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_u64: +** cmphi p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_u64: +** cmphi p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_u64: +** cmphi p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_u64: +** cmphi p0\.d, p1/z, z0\.d, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_127_u64: +** cmphi p0\.d, p1/z, z0\.d, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_127_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 127), + p0 = svcmpgt (p1, z0, 127)) + +/* +** cmpgt_128_u64: +** mov (z[0-9]+\.d), #128 +** ( +** cmphi p0\.d, p1/z, z0\.d, \1 +** | +** cmplo p0\.d, p1/z, \1, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_128_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, 128), + p0 = svcmpgt (p1, z0, 128)) + +/* +** cmpgt_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.d, p1/z, z0\.d, \1\.d +** | +** cmplo p0\.d, p1/z, \1\.d, z0\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_u64, svuint64_t, + p0 = svcmpgt_n_u64 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u8.c new file mode 100644 index 00000000000..4f28331f9e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_u8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_u8_tied: +** ( +** cmphi p0\.b, p0/z, z0\.b, z1\.b +** | +** cmplo p0\.b, p0/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u8_tied, svuint8_t, + p0 = svcmpgt_u8 (p0, z0, z1), + p0 = svcmpgt (p0, z0, z1)) + +/* +** cmpgt_u8_untied: +** ( +** cmphi p0\.b, p1/z, z0\.b, z1\.b +** | +** cmplo p0\.b, p1/z, z1\.b, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_u8_untied, svuint8_t, + p0 = svcmpgt_u8 (p1, z0, z1), + p0 = svcmpgt (p1, z0, z1)) + +/* +** cmpgt_w0_u8: +** mov (z[0-9]+\.b), w0 +** ( +** cmphi p0\.b, p1/z, z0\.b, \1 +** | +** cmplo p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_ZX (cmpgt_w0_u8, svuint8_t, uint8_t, + p0 = svcmpgt_n_u8 (p1, z0, x0), + p0 = svcmpgt (p1, z0, x0)) + +/* +** cmpgt_0_u8: +** cmphi p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_0_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 0), + p0 = svcmpgt (p1, z0, 0)) + +/* +** cmpgt_1_u8: +** cmphi p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_1_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 1), + p0 = svcmpgt (p1, z0, 1)) + +/* +** cmpgt_15_u8: +** cmphi p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_15_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 15), + p0 = svcmpgt (p1, z0, 15)) + +/* +** cmpgt_16_u8: +** cmphi p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_16_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 16), + p0 = svcmpgt (p1, z0, 16)) + +/* +** cmpgt_127_u8: +** cmphi p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_127_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 127), + p0 = svcmpgt (p1, z0, 127)) + +/* +** cmpgt_128_u8: +** mov (z[0-9]+\.b), #-128 +** ( +** cmphi p0\.b, p1/z, z0\.b, \1 +** | +** cmplo p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_128_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, 128), + p0 = svcmpgt (p1, z0, 128)) + +/* +** cmpgt_m1_u8: +** mov (z[0-9]+\.b), #-1 +** ( +** cmphi p0\.b, p1/z, z0\.b, \1 +** | +** cmplo p0\.b, p1/z, \1, z0\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmpgt_m1_u8, svuint8_t, + p0 = svcmpgt_n_u8 (p1, z0, -1), + p0 = svcmpgt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s16.c new file mode 100644 index 00000000000..07d3bbbd90e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_s16_tied: +** cmpgt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmpgt_wide_s16 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_s16_untied: +** cmpgt p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmpgt_wide_s16 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmpgt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_s16, svint16_t, int64_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_s16: +** cmpgt p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_s16: +** cmpgt p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_s16: +** cmpgt p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmpgt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_m1_s16: +** cmpgt p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) + +/* +** cmpgt_wide_m16_s16: +** cmpgt p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m16_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, -16), + p0 = svcmpgt_wide (p1, z0, -16)) + +/* +** cmpgt_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmpgt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m17_s16, svint16_t, + p0 = svcmpgt_wide_n_s16 (p1, z0, -17), + p0 = svcmpgt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s32.c new file mode 100644 index 00000000000..f984362e68b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_s32_tied: +** cmpgt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmpgt_wide_s32 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_s32_untied: +** cmpgt p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmpgt_wide_s32 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmpgt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_s32, svint32_t, int64_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_s32: +** cmpgt p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_s32: +** cmpgt p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_s32: +** cmpgt p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmpgt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_m1_s32: +** cmpgt p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) + +/* +** cmpgt_wide_m16_s32: +** cmpgt p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m16_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, -16), + p0 = svcmpgt_wide (p1, z0, -16)) + +/* +** cmpgt_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmpgt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m17_s32, svint32_t, + p0 = svcmpgt_wide_n_s32 (p1, z0, -17), + p0 = svcmpgt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s8.c new file mode 100644 index 00000000000..07047a315f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_s8_tied: +** cmpgt p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmpgt_wide_s8 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_s8_untied: +** cmpgt p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmpgt_wide_s8 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmpgt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_s8, svint8_t, int64_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_s8: +** cmpgt p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_s8: +** cmpgt p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_s8: +** cmpgt p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmpgt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_m1_s8: +** cmpgt p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) + +/* +** cmpgt_wide_m16_s8: +** cmpgt p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m16_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, -16), + p0 = svcmpgt_wide (p1, z0, -16)) + +/* +** cmpgt_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmpgt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m17_s8, svint8_t, + p0 = svcmpgt_wide_n_s8 (p1, z0, -17), + p0 = svcmpgt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u16.c new file mode 100644 index 00000000000..bcffb88c096 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_u16_tied: +** cmphi p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u16_tied, svuint16_t, svuint64_t, + p0 = svcmpgt_wide_u16 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_u16_untied: +** cmphi p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u16_untied, svuint16_t, svuint64_t, + p0 = svcmpgt_wide_u16 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_u16: +** mov (z[0-9]+\.d), x0 +** cmphi p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_u16, svuint16_t, uint64_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_u16: +** cmphi p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_u16: +** cmphi p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_u16: +** cmphi p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_u16: +** cmphi p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_127_u16: +** cmphi p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_127_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 127), + p0 = svcmpgt_wide (p1, z0, 127)) + +/* +** cmpgt_wide_128_u16: +** mov (z[0-9]+\.d), #128 +** cmphi p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_128_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, 128), + p0 = svcmpgt_wide (p1, z0, 128)) + +/* +** cmpgt_wide_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** cmphi p0\.h, p1/z, z0\.h, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_u16, svuint16_t, + p0 = svcmpgt_wide_n_u16 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u32.c new file mode 100644 index 00000000000..65c0231e592 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_u32_tied: +** cmphi p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u32_tied, svuint32_t, svuint64_t, + p0 = svcmpgt_wide_u32 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_u32_untied: +** cmphi p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u32_untied, svuint32_t, svuint64_t, + p0 = svcmpgt_wide_u32 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_u32: +** mov (z[0-9]+\.d), x0 +** cmphi p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_u32, svuint32_t, uint64_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_u32: +** cmphi p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_u32: +** cmphi p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_u32: +** cmphi p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_u32: +** cmphi p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_127_u32: +** cmphi p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_127_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 127), + p0 = svcmpgt_wide (p1, z0, 127)) + +/* +** cmpgt_wide_128_u32: +** mov (z[0-9]+\.d), #128 +** cmphi p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_128_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, 128), + p0 = svcmpgt_wide (p1, z0, 128)) + +/* +** cmpgt_wide_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** cmphi p0\.s, p1/z, z0\.s, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_u32, svuint32_t, + p0 = svcmpgt_wide_n_u32 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u8.c new file mode 100644 index 00000000000..0d1142f27a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpgt_wide_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpgt_wide_u8_tied: +** cmphi p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u8_tied, svuint8_t, svuint64_t, + p0 = svcmpgt_wide_u8 (p0, z0, z1), + p0 = svcmpgt_wide (p0, z0, z1)) + +/* +** cmpgt_wide_u8_untied: +** cmphi p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpgt_wide_u8_untied, svuint8_t, svuint64_t, + p0 = svcmpgt_wide_u8 (p1, z0, z1), + p0 = svcmpgt_wide (p1, z0, z1)) + +/* +** cmpgt_wide_x0_u8: +** mov (z[0-9]+\.d), x0 +** cmphi p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpgt_wide_x0_u8, svuint8_t, uint64_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, x0), + p0 = svcmpgt_wide (p1, z0, x0)) + +/* +** cmpgt_wide_0_u8: +** cmphi p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_0_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 0), + p0 = svcmpgt_wide (p1, z0, 0)) + +/* +** cmpgt_wide_1_u8: +** cmphi p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_1_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 1), + p0 = svcmpgt_wide (p1, z0, 1)) + +/* +** cmpgt_wide_15_u8: +** cmphi p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_15_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 15), + p0 = svcmpgt_wide (p1, z0, 15)) + +/* +** cmpgt_wide_16_u8: +** cmphi p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_16_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 16), + p0 = svcmpgt_wide (p1, z0, 16)) + +/* +** cmpgt_wide_127_u8: +** cmphi p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_127_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 127), + p0 = svcmpgt_wide (p1, z0, 127)) + +/* +** cmpgt_wide_128_u8: +** mov (z[0-9]+\.d), #128 +** cmphi p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_128_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, 128), + p0 = svcmpgt_wide (p1, z0, 128)) + +/* +** cmpgt_wide_m1_u8: +** mov (z[0-9]+)\.b, #-1 +** cmphi p0\.b, p1/z, z0\.b, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmpgt_wide_m1_u8, svuint8_t, + p0 = svcmpgt_wide_n_u8 (p1, z0, -1), + p0 = svcmpgt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f16.c new file mode 100644 index 00000000000..7d500590f1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f16.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_f16_tied: +** ( +** fcmge p0\.h, p0/z, z1\.h, z0\.h +** | +** fcmle p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f16_tied, svfloat16_t, + p0 = svcmple_f16 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_f16_untied: +** ( +** fcmge p0\.h, p1/z, z1\.h, z0\.h +** | +** fcmle p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f16_untied, svfloat16_t, + p0 = svcmple_f16 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** fcmge p0\.h, p1/z, \1, z0\.h +** | +** fcmle p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmple_h4_f16, svfloat16_t, float16_t, + p0 = svcmple_n_f16 (p1, z0, d4), + p0 = svcmple (p1, z0, d4)) + +/* +** cmple_0_f16: +** fcmle p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_f16, svfloat16_t, + p0 = svcmple_n_f16 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** fcmge p0\.h, p1/z, \1, z0\.h +** | +** fcmle p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_1_f16, svfloat16_t, + p0 = svcmple_n_f16 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f32.c new file mode 100644 index 00000000000..3df63fef762 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f32.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_f32_tied: +** ( +** fcmge p0\.s, p0/z, z1\.s, z0\.s +** | +** fcmle p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f32_tied, svfloat32_t, + p0 = svcmple_f32 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_f32_untied: +** ( +** fcmge p0\.s, p1/z, z1\.s, z0\.s +** | +** fcmle p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f32_untied, svfloat32_t, + p0 = svcmple_f32 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** fcmge p0\.s, p1/z, \1, z0\.s +** | +** fcmle p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmple_s4_f32, svfloat32_t, float32_t, + p0 = svcmple_n_f32 (p1, z0, d4), + p0 = svcmple (p1, z0, d4)) + +/* +** cmple_0_f32: +** fcmle p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_f32, svfloat32_t, + p0 = svcmple_n_f32 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** fcmge p0\.s, p1/z, \1, z0\.s +** | +** fcmle p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_1_f32, svfloat32_t, + p0 = svcmple_n_f32 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f64.c new file mode 100644 index 00000000000..5946a1b3ac2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_f64.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_f64_tied: +** ( +** fcmge p0\.d, p0/z, z1\.d, z0\.d +** | +** fcmle p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f64_tied, svfloat64_t, + p0 = svcmple_f64 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_f64_untied: +** ( +** fcmge p0\.d, p1/z, z1\.d, z0\.d +** | +** fcmle p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_f64_untied, svfloat64_t, + p0 = svcmple_f64 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** fcmge p0\.d, p1/z, \1, z0\.d +** | +** fcmle p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmple_d4_f64, svfloat64_t, float64_t, + p0 = svcmple_n_f64 (p1, z0, d4), + p0 = svcmple (p1, z0, d4)) + +/* +** cmple_0_f64: +** fcmle p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_f64, svfloat64_t, + p0 = svcmple_n_f64 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** fcmge p0\.d, p1/z, \1, z0\.d +** | +** fcmle p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_1_f64, svfloat64_t, + p0 = svcmple_n_f64 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s16.c new file mode 100644 index 00000000000..9b221bb4c20 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_s16_tied: +** ( +** cmpge p0\.h, p0/z, z1\.h, z0\.h +** | +** cmple p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s16_tied, svint16_t, + p0 = svcmple_s16 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_s16_untied: +** ( +** cmpge p0\.h, p1/z, z1\.h, z0\.h +** | +** cmple p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s16_untied, svint16_t, + p0 = svcmple_s16 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_s16: +** mov (z[0-9]+\.h), w0 +** ( +** cmpge p0\.h, p1/z, \1, z0\.h +** | +** cmple p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_s16, svint16_t, int16_t, + p0 = svcmple_n_s16 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_s16: +** cmple p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_s16: +** cmple p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_s16: +** cmple p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_s16: +** mov (z[0-9]+\.h), #16 +** ( +** cmpge p0\.h, p1/z, \1, z0\.h +** | +** cmple p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_16_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_m1_s16: +** cmple p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_m1_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) + +/* +** cmple_m16_s16: +** cmple p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_m16_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, -16), + p0 = svcmple (p1, z0, -16)) + +/* +** cmple_m17_s16: +** mov (z[0-9]+\.h), #-17 +** ( +** cmpge p0\.h, p1/z, \1, z0\.h +** | +** cmple p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m17_s16, svint16_t, + p0 = svcmple_n_s16 (p1, z0, -17), + p0 = svcmple (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s32.c new file mode 100644 index 00000000000..b0c8367e24e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_s32_tied: +** ( +** cmpge p0\.s, p0/z, z1\.s, z0\.s +** | +** cmple p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s32_tied, svint32_t, + p0 = svcmple_s32 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_s32_untied: +** ( +** cmpge p0\.s, p1/z, z1\.s, z0\.s +** | +** cmple p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s32_untied, svint32_t, + p0 = svcmple_s32 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_s32: +** mov (z[0-9]+\.s), w0 +** ( +** cmpge p0\.s, p1/z, \1, z0\.s +** | +** cmple p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_s32, svint32_t, int32_t, + p0 = svcmple_n_s32 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_s32: +** cmple p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_s32: +** cmple p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_s32: +** cmple p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_s32: +** mov (z[0-9]+\.s), #16 +** ( +** cmpge p0\.s, p1/z, \1, z0\.s +** | +** cmple p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_16_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_m1_s32: +** cmple p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_m1_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) + +/* +** cmple_m16_s32: +** cmple p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_m16_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, -16), + p0 = svcmple (p1, z0, -16)) + +/* +** cmple_m17_s32: +** mov (z[0-9]+\.s), #-17 +** ( +** cmpge p0\.s, p1/z, \1, z0\.s +** | +** cmple p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m17_s32, svint32_t, + p0 = svcmple_n_s32 (p1, z0, -17), + p0 = svcmple (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s64.c new file mode 100644 index 00000000000..faaa8761427 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_s64_tied: +** ( +** cmpge p0\.d, p0/z, z1\.d, z0\.d +** | +** cmple p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s64_tied, svint64_t, + p0 = svcmple_s64 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_s64_untied: +** ( +** cmpge p0\.d, p1/z, z1\.d, z0\.d +** | +** cmple p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s64_untied, svint64_t, + p0 = svcmple_s64 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_x0_s64: +** mov (z[0-9]+\.d), x0 +** ( +** cmpge p0\.d, p1/z, \1, z0\.d +** | +** cmple p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_x0_s64, svint64_t, int64_t, + p0 = svcmple_n_s64 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_s64: +** cmple p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_s64: +** cmple p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_s64: +** cmple p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_s64: +** mov (z[0-9]+\.d), #16 +** ( +** cmpge p0\.d, p1/z, \1, z0\.d +** | +** cmple p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_16_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_m1_s64: +** cmple p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_m1_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) + +/* +** cmple_m16_s64: +** cmple p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_m16_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, -16), + p0 = svcmple (p1, z0, -16)) + +/* +** cmple_m17_s64: +** mov (z[0-9]+\.d), #-17 +** ( +** cmpge p0\.d, p1/z, \1, z0\.d +** | +** cmple p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m17_s64, svint64_t, + p0 = svcmple_n_s64 (p1, z0, -17), + p0 = svcmple (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s8.c new file mode 100644 index 00000000000..222487d75cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_s8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_s8_tied: +** ( +** cmpge p0\.b, p0/z, z1\.b, z0\.b +** | +** cmple p0\.b, p0/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s8_tied, svint8_t, + p0 = svcmple_s8 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_s8_untied: +** ( +** cmpge p0\.b, p1/z, z1\.b, z0\.b +** | +** cmple p0\.b, p1/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_s8_untied, svint8_t, + p0 = svcmple_s8 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_s8: +** mov (z[0-9]+\.b), w0 +** ( +** cmpge p0\.b, p1/z, \1, z0\.b +** | +** cmple p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_s8, svint8_t, int8_t, + p0 = svcmple_n_s8 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_s8: +** cmple p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_s8: +** cmple p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_s8: +** cmple p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_s8: +** mov (z[0-9]+\.b), #16 +** ( +** cmpge p0\.b, p1/z, \1, z0\.b +** | +** cmple p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_16_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_m1_s8: +** cmple p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_m1_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) + +/* +** cmple_m16_s8: +** cmple p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_m16_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, -16), + p0 = svcmple (p1, z0, -16)) + +/* +** cmple_m17_s8: +** mov (z[0-9]+\.b), #-17 +** ( +** cmpge p0\.b, p1/z, \1, z0\.b +** | +** cmple p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m17_s8, svint8_t, + p0 = svcmple_n_s8 (p1, z0, -17), + p0 = svcmple (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u16.c new file mode 100644 index 00000000000..26af06e5285 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_u16_tied: +** ( +** cmphs p0\.h, p0/z, z1\.h, z0\.h +** | +** cmpls p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u16_tied, svuint16_t, + p0 = svcmple_u16 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_u16_untied: +** ( +** cmphs p0\.h, p1/z, z1\.h, z0\.h +** | +** cmpls p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u16_untied, svuint16_t, + p0 = svcmple_u16 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_u16: +** mov (z[0-9]+\.h), w0 +** ( +** cmphs p0\.h, p1/z, \1, z0\.h +** | +** cmpls p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_u16, svuint16_t, uint16_t, + p0 = svcmple_n_u16 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_u16: +** cmpls p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_u16: +** cmpls p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_u16: +** cmpls p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_u16: +** cmpls p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_16_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_127_u16: +** cmpls p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_127_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 127), + p0 = svcmple (p1, z0, 127)) + +/* +** cmple_128_u16: +** mov (z[0-9]+\.h), #128 +** ( +** cmphs p0\.h, p1/z, \1, z0\.h +** | +** cmpls p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_128_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, 128), + p0 = svcmple (p1, z0, 128)) + +/* +** cmple_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.h, p1/z, \1\.h, z0\.h +** | +** cmpls p0\.h, p1/z, z0\.h, \1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m1_u16, svuint16_t, + p0 = svcmple_n_u16 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u32.c new file mode 100644 index 00000000000..cee2d14c8ea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_u32_tied: +** ( +** cmphs p0\.s, p0/z, z1\.s, z0\.s +** | +** cmpls p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u32_tied, svuint32_t, + p0 = svcmple_u32 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_u32_untied: +** ( +** cmphs p0\.s, p1/z, z1\.s, z0\.s +** | +** cmpls p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u32_untied, svuint32_t, + p0 = svcmple_u32 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_u32: +** mov (z[0-9]+\.s), w0 +** ( +** cmphs p0\.s, p1/z, \1, z0\.s +** | +** cmpls p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_u32, svuint32_t, uint32_t, + p0 = svcmple_n_u32 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_u32: +** cmpls p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_u32: +** cmpls p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_u32: +** cmpls p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_u32: +** cmpls p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_16_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_127_u32: +** cmpls p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_127_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 127), + p0 = svcmple (p1, z0, 127)) + +/* +** cmple_128_u32: +** mov (z[0-9]+\.s), #128 +** ( +** cmphs p0\.s, p1/z, \1, z0\.s +** | +** cmpls p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_128_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, 128), + p0 = svcmple (p1, z0, 128)) + +/* +** cmple_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.s, p1/z, \1\.s, z0\.s +** | +** cmpls p0\.s, p1/z, z0\.s, \1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m1_u32, svuint32_t, + p0 = svcmple_n_u32 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u64.c new file mode 100644 index 00000000000..b8388bca865 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_u64_tied: +** ( +** cmphs p0\.d, p0/z, z1\.d, z0\.d +** | +** cmpls p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u64_tied, svuint64_t, + p0 = svcmple_u64 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_u64_untied: +** ( +** cmphs p0\.d, p1/z, z1\.d, z0\.d +** | +** cmpls p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u64_untied, svuint64_t, + p0 = svcmple_u64 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_x0_u64: +** mov (z[0-9]+\.d), x0 +** ( +** cmphs p0\.d, p1/z, \1, z0\.d +** | +** cmpls p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_x0_u64, svuint64_t, uint64_t, + p0 = svcmple_n_u64 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_u64: +** cmpls p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_u64: +** cmpls p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_u64: +** cmpls p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_u64: +** cmpls p0\.d, p1/z, z0\.d, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_16_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_127_u64: +** cmpls p0\.d, p1/z, z0\.d, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_127_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 127), + p0 = svcmple (p1, z0, 127)) + +/* +** cmple_128_u64: +** mov (z[0-9]+\.d), #128 +** ( +** cmphs p0\.d, p1/z, \1, z0\.d +** | +** cmpls p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_128_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, 128), + p0 = svcmple (p1, z0, 128)) + +/* +** cmple_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphs p0\.d, p1/z, \1\.d, z0\.d +** | +** cmpls p0\.d, p1/z, z0\.d, \1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m1_u64, svuint64_t, + p0 = svcmple_n_u64 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u8.c new file mode 100644 index 00000000000..55a8d4f40b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_u8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_u8_tied: +** ( +** cmphs p0\.b, p0/z, z1\.b, z0\.b +** | +** cmpls p0\.b, p0/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u8_tied, svuint8_t, + p0 = svcmple_u8 (p0, z0, z1), + p0 = svcmple (p0, z0, z1)) + +/* +** cmple_u8_untied: +** ( +** cmphs p0\.b, p1/z, z1\.b, z0\.b +** | +** cmpls p0\.b, p1/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_u8_untied, svuint8_t, + p0 = svcmple_u8 (p1, z0, z1), + p0 = svcmple (p1, z0, z1)) + +/* +** cmple_w0_u8: +** mov (z[0-9]+\.b), w0 +** ( +** cmphs p0\.b, p1/z, \1, z0\.b +** | +** cmpls p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmple_w0_u8, svuint8_t, uint8_t, + p0 = svcmple_n_u8 (p1, z0, x0), + p0 = svcmple (p1, z0, x0)) + +/* +** cmple_0_u8: +** cmpls p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_0_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 0), + p0 = svcmple (p1, z0, 0)) + +/* +** cmple_1_u8: +** cmpls p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_1_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 1), + p0 = svcmple (p1, z0, 1)) + +/* +** cmple_15_u8: +** cmpls p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_15_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 15), + p0 = svcmple (p1, z0, 15)) + +/* +** cmple_16_u8: +** cmpls p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_16_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 16), + p0 = svcmple (p1, z0, 16)) + +/* +** cmple_127_u8: +** cmpls p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_127_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 127), + p0 = svcmple (p1, z0, 127)) + +/* +** cmple_128_u8: +** mov (z[0-9]+\.b), #-128 +** ( +** cmphs p0\.b, p1/z, \1, z0\.b +** | +** cmpls p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_128_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, 128), + p0 = svcmple (p1, z0, 128)) + +/* +** cmple_m1_u8: +** mov (z[0-9]+\.b), #-1 +** ( +** cmphs p0\.b, p1/z, \1, z0\.b +** | +** cmpls p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmple_m1_u8, svuint8_t, + p0 = svcmple_n_u8 (p1, z0, -1), + p0 = svcmple (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s16.c new file mode 100644 index 00000000000..f1f0b2ed620 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_s16_tied: +** cmple p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmple_wide_s16 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_s16_untied: +** cmple p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmple_wide_s16 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmple p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_s16, svint16_t, int64_t, + p0 = svcmple_wide_n_s16 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_s16: +** cmple p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_s16: +** cmple p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_s16: +** cmple p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmple p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_m1_s16: +** cmple p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) + +/* +** cmple_wide_m16_s16: +** cmple p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m16_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, -16), + p0 = svcmple_wide (p1, z0, -16)) + +/* +** cmple_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmple p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m17_s16, svint16_t, + p0 = svcmple_wide_n_s16 (p1, z0, -17), + p0 = svcmple_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s32.c new file mode 100644 index 00000000000..edc5513b67b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_s32_tied: +** cmple p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmple_wide_s32 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_s32_untied: +** cmple p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmple_wide_s32 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmple p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_s32, svint32_t, int64_t, + p0 = svcmple_wide_n_s32 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_s32: +** cmple p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_s32: +** cmple p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_s32: +** cmple p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmple p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_m1_s32: +** cmple p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) + +/* +** cmple_wide_m16_s32: +** cmple p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m16_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, -16), + p0 = svcmple_wide (p1, z0, -16)) + +/* +** cmple_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmple p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m17_s32, svint32_t, + p0 = svcmple_wide_n_s32 (p1, z0, -17), + p0 = svcmple_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s8.c new file mode 100644 index 00000000000..984044460ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_s8_tied: +** cmple p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmple_wide_s8 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_s8_untied: +** cmple p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmple_wide_s8 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmple p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_s8, svint8_t, int64_t, + p0 = svcmple_wide_n_s8 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_s8: +** cmple p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_s8: +** cmple p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_s8: +** cmple p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmple p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_m1_s8: +** cmple p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) + +/* +** cmple_wide_m16_s8: +** cmple p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m16_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, -16), + p0 = svcmple_wide (p1, z0, -16)) + +/* +** cmple_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmple p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m17_s8, svint8_t, + p0 = svcmple_wide_n_s8 (p1, z0, -17), + p0 = svcmple_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u16.c new file mode 100644 index 00000000000..a39a1aad5c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_u16_tied: +** cmpls p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u16_tied, svuint16_t, svuint64_t, + p0 = svcmple_wide_u16 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_u16_untied: +** cmpls p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u16_untied, svuint16_t, svuint64_t, + p0 = svcmple_wide_u16 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_u16: +** mov (z[0-9]+\.d), x0 +** cmpls p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_u16, svuint16_t, uint64_t, + p0 = svcmple_wide_n_u16 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_u16: +** cmpls p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_u16: +** cmpls p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_u16: +** cmpls p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_u16: +** cmpls p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_127_u16: +** cmpls p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_127_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 127), + p0 = svcmple_wide (p1, z0, 127)) + +/* +** cmple_wide_128_u16: +** mov (z[0-9]+\.d), #128 +** cmpls p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_128_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, 128), + p0 = svcmple_wide (p1, z0, 128)) + +/* +** cmple_wide_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** cmpls p0\.h, p1/z, z0\.h, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_u16, svuint16_t, + p0 = svcmple_wide_n_u16 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u32.c new file mode 100644 index 00000000000..fe682c9e827 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_u32_tied: +** cmpls p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u32_tied, svuint32_t, svuint64_t, + p0 = svcmple_wide_u32 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_u32_untied: +** cmpls p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u32_untied, svuint32_t, svuint64_t, + p0 = svcmple_wide_u32 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_u32: +** mov (z[0-9]+\.d), x0 +** cmpls p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_u32, svuint32_t, uint64_t, + p0 = svcmple_wide_n_u32 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_u32: +** cmpls p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_u32: +** cmpls p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_u32: +** cmpls p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_u32: +** cmpls p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_127_u32: +** cmpls p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_127_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 127), + p0 = svcmple_wide (p1, z0, 127)) + +/* +** cmple_wide_128_u32: +** mov (z[0-9]+\.d), #128 +** cmpls p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_128_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, 128), + p0 = svcmple_wide (p1, z0, 128)) + +/* +** cmple_wide_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** cmpls p0\.s, p1/z, z0\.s, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_u32, svuint32_t, + p0 = svcmple_wide_n_u32 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u8.c new file mode 100644 index 00000000000..893dfa62738 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmple_wide_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmple_wide_u8_tied: +** cmpls p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u8_tied, svuint8_t, svuint64_t, + p0 = svcmple_wide_u8 (p0, z0, z1), + p0 = svcmple_wide (p0, z0, z1)) + +/* +** cmple_wide_u8_untied: +** cmpls p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmple_wide_u8_untied, svuint8_t, svuint64_t, + p0 = svcmple_wide_u8 (p1, z0, z1), + p0 = svcmple_wide (p1, z0, z1)) + +/* +** cmple_wide_x0_u8: +** mov (z[0-9]+\.d), x0 +** cmpls p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmple_wide_x0_u8, svuint8_t, uint64_t, + p0 = svcmple_wide_n_u8 (p1, z0, x0), + p0 = svcmple_wide (p1, z0, x0)) + +/* +** cmple_wide_0_u8: +** cmpls p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_0_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 0), + p0 = svcmple_wide (p1, z0, 0)) + +/* +** cmple_wide_1_u8: +** cmpls p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_1_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 1), + p0 = svcmple_wide (p1, z0, 1)) + +/* +** cmple_wide_15_u8: +** cmpls p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_15_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 15), + p0 = svcmple_wide (p1, z0, 15)) + +/* +** cmple_wide_16_u8: +** cmpls p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_16_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 16), + p0 = svcmple_wide (p1, z0, 16)) + +/* +** cmple_wide_127_u8: +** cmpls p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_127_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 127), + p0 = svcmple_wide (p1, z0, 127)) + +/* +** cmple_wide_128_u8: +** mov (z[0-9]+\.d), #128 +** cmpls p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmple_wide_128_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, 128), + p0 = svcmple_wide (p1, z0, 128)) + +/* +** cmple_wide_m1_u8: +** mov (z[0-9]+)\.b, #-1 +** cmpls p0\.b, p1/z, z0\.b, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmple_wide_m1_u8, svuint8_t, + p0 = svcmple_wide_n_u8 (p1, z0, -1), + p0 = svcmple_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f16.c new file mode 100644 index 00000000000..598f673a815 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f16.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_f16_tied: +** ( +** fcmgt p0\.h, p0/z, z1\.h, z0\.h +** | +** fcmlt p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f16_tied, svfloat16_t, + p0 = svcmplt_f16 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_f16_untied: +** ( +** fcmgt p0\.h, p1/z, z1\.h, z0\.h +** | +** fcmlt p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f16_untied, svfloat16_t, + p0 = svcmplt_f16 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_h4_f16: +** mov (z[0-9]+\.h), h4 +** ( +** fcmgt p0\.h, p1/z, \1, z0\.h +** | +** fcmlt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmplt_h4_f16, svfloat16_t, float16_t, + p0 = svcmplt_n_f16 (p1, z0, d4), + p0 = svcmplt (p1, z0, d4)) + +/* +** cmplt_0_f16: +** fcmlt p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_f16, svfloat16_t, + p0 = svcmplt_n_f16 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.h, p1/z, \1, z0\.h +** | +** fcmlt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_1_f16, svfloat16_t, + p0 = svcmplt_n_f16 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f32.c new file mode 100644 index 00000000000..f9dea3665de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f32.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_f32_tied: +** ( +** fcmgt p0\.s, p0/z, z1\.s, z0\.s +** | +** fcmlt p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f32_tied, svfloat32_t, + p0 = svcmplt_f32 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_f32_untied: +** ( +** fcmgt p0\.s, p1/z, z1\.s, z0\.s +** | +** fcmlt p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f32_untied, svfloat32_t, + p0 = svcmplt_f32 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_s4_f32: +** mov (z[0-9]+\.s), s4 +** ( +** fcmgt p0\.s, p1/z, \1, z0\.s +** | +** fcmlt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmplt_s4_f32, svfloat32_t, float32_t, + p0 = svcmplt_n_f32 (p1, z0, d4), + p0 = svcmplt (p1, z0, d4)) + +/* +** cmplt_0_f32: +** fcmlt p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_f32, svfloat32_t, + p0 = svcmplt_n_f32 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.s, p1/z, \1, z0\.s +** | +** fcmlt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_1_f32, svfloat32_t, + p0 = svcmplt_n_f32 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f64.c new file mode 100644 index 00000000000..6f251db4f38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_f64.c @@ -0,0 +1,66 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_f64_tied: +** ( +** fcmgt p0\.d, p0/z, z1\.d, z0\.d +** | +** fcmlt p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f64_tied, svfloat64_t, + p0 = svcmplt_f64 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_f64_untied: +** ( +** fcmgt p0\.d, p1/z, z1\.d, z0\.d +** | +** fcmlt p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_f64_untied, svfloat64_t, + p0 = svcmplt_f64 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_d4_f64: +** mov (z[0-9]+\.d), d4 +** ( +** fcmgt p0\.d, p1/z, \1, z0\.d +** | +** fcmlt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZD (cmplt_d4_f64, svfloat64_t, float64_t, + p0 = svcmplt_n_f64 (p1, z0, d4), + p0 = svcmplt (p1, z0, d4)) + +/* +** cmplt_0_f64: +** fcmlt p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_f64, svfloat64_t, + p0 = svcmplt_n_f64 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** fcmgt p0\.d, p1/z, \1, z0\.d +** | +** fcmlt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_1_f64, svfloat64_t, + p0 = svcmplt_n_f64 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s16.c new file mode 100644 index 00000000000..1e2bf9dde4e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_s16_tied: +** ( +** cmpgt p0\.h, p0/z, z1\.h, z0\.h +** | +** cmplt p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s16_tied, svint16_t, + p0 = svcmplt_s16 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_s16_untied: +** ( +** cmpgt p0\.h, p1/z, z1\.h, z0\.h +** | +** cmplt p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s16_untied, svint16_t, + p0 = svcmplt_s16 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_s16: +** mov (z[0-9]+\.h), w0 +** ( +** cmpgt p0\.h, p1/z, \1, z0\.h +** | +** cmplt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_s16, svint16_t, int16_t, + p0 = svcmplt_n_s16 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_s16: +** cmplt p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_s16: +** cmplt p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_s16: +** cmplt p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_s16: +** mov (z[0-9]+\.h), #16 +** ( +** cmpgt p0\.h, p1/z, \1, z0\.h +** | +** cmplt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_16_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_m1_s16: +** cmplt p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) + +/* +** cmplt_m16_s16: +** cmplt p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_m16_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, -16), + p0 = svcmplt (p1, z0, -16)) + +/* +** cmplt_m17_s16: +** mov (z[0-9]+\.h), #-17 +** ( +** cmpgt p0\.h, p1/z, \1, z0\.h +** | +** cmplt p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m17_s16, svint16_t, + p0 = svcmplt_n_s16 (p1, z0, -17), + p0 = svcmplt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s32.c new file mode 100644 index 00000000000..8e2c02c4df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_s32_tied: +** ( +** cmpgt p0\.s, p0/z, z1\.s, z0\.s +** | +** cmplt p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s32_tied, svint32_t, + p0 = svcmplt_s32 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_s32_untied: +** ( +** cmpgt p0\.s, p1/z, z1\.s, z0\.s +** | +** cmplt p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s32_untied, svint32_t, + p0 = svcmplt_s32 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_s32: +** mov (z[0-9]+\.s), w0 +** ( +** cmpgt p0\.s, p1/z, \1, z0\.s +** | +** cmplt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_s32, svint32_t, int32_t, + p0 = svcmplt_n_s32 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_s32: +** cmplt p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_s32: +** cmplt p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_s32: +** cmplt p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_s32: +** mov (z[0-9]+\.s), #16 +** ( +** cmpgt p0\.s, p1/z, \1, z0\.s +** | +** cmplt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_16_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_m1_s32: +** cmplt p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) + +/* +** cmplt_m16_s32: +** cmplt p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_m16_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, -16), + p0 = svcmplt (p1, z0, -16)) + +/* +** cmplt_m17_s32: +** mov (z[0-9]+\.s), #-17 +** ( +** cmpgt p0\.s, p1/z, \1, z0\.s +** | +** cmplt p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m17_s32, svint32_t, + p0 = svcmplt_n_s32 (p1, z0, -17), + p0 = svcmplt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s64.c new file mode 100644 index 00000000000..818c9fba92b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_s64_tied: +** ( +** cmpgt p0\.d, p0/z, z1\.d, z0\.d +** | +** cmplt p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s64_tied, svint64_t, + p0 = svcmplt_s64 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_s64_untied: +** ( +** cmpgt p0\.d, p1/z, z1\.d, z0\.d +** | +** cmplt p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s64_untied, svint64_t, + p0 = svcmplt_s64 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_x0_s64: +** mov (z[0-9]+\.d), x0 +** ( +** cmpgt p0\.d, p1/z, \1, z0\.d +** | +** cmplt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_x0_s64, svint64_t, int64_t, + p0 = svcmplt_n_s64 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_s64: +** cmplt p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_s64: +** cmplt p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_s64: +** cmplt p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_s64: +** mov (z[0-9]+\.d), #16 +** ( +** cmpgt p0\.d, p1/z, \1, z0\.d +** | +** cmplt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_16_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_m1_s64: +** cmplt p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) + +/* +** cmplt_m16_s64: +** cmplt p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_m16_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, -16), + p0 = svcmplt (p1, z0, -16)) + +/* +** cmplt_m17_s64: +** mov (z[0-9]+\.d), #-17 +** ( +** cmpgt p0\.d, p1/z, \1, z0\.d +** | +** cmplt p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m17_s64, svint64_t, + p0 = svcmplt_n_s64 (p1, z0, -17), + p0 = svcmplt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s8.c new file mode 100644 index 00000000000..54b8dc40882 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_s8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_s8_tied: +** ( +** cmpgt p0\.b, p0/z, z1\.b, z0\.b +** | +** cmplt p0\.b, p0/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s8_tied, svint8_t, + p0 = svcmplt_s8 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_s8_untied: +** ( +** cmpgt p0\.b, p1/z, z1\.b, z0\.b +** | +** cmplt p0\.b, p1/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_s8_untied, svint8_t, + p0 = svcmplt_s8 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_s8: +** mov (z[0-9]+\.b), w0 +** ( +** cmpgt p0\.b, p1/z, \1, z0\.b +** | +** cmplt p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_s8, svint8_t, int8_t, + p0 = svcmplt_n_s8 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_s8: +** cmplt p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_s8: +** cmplt p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_s8: +** cmplt p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_s8: +** mov (z[0-9]+\.b), #16 +** ( +** cmpgt p0\.b, p1/z, \1, z0\.b +** | +** cmplt p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_16_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_m1_s8: +** cmplt p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) + +/* +** cmplt_m16_s8: +** cmplt p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_m16_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, -16), + p0 = svcmplt (p1, z0, -16)) + +/* +** cmplt_m17_s8: +** mov (z[0-9]+\.b), #-17 +** ( +** cmpgt p0\.b, p1/z, \1, z0\.b +** | +** cmplt p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m17_s8, svint8_t, + p0 = svcmplt_n_s8 (p1, z0, -17), + p0 = svcmplt (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u16.c new file mode 100644 index 00000000000..c0f2a05508e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u16.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_u16_tied: +** ( +** cmphi p0\.h, p0/z, z1\.h, z0\.h +** | +** cmplo p0\.h, p0/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u16_tied, svuint16_t, + p0 = svcmplt_u16 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_u16_untied: +** ( +** cmphi p0\.h, p1/z, z1\.h, z0\.h +** | +** cmplo p0\.h, p1/z, z0\.h, z1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u16_untied, svuint16_t, + p0 = svcmplt_u16 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_u16: +** mov (z[0-9]+\.h), w0 +** ( +** cmphi p0\.h, p1/z, \1, z0\.h +** | +** cmplo p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_u16, svuint16_t, uint16_t, + p0 = svcmplt_n_u16 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_u16: +** cmplo p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_u16: +** cmplo p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_u16: +** cmplo p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_u16: +** cmplo p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_16_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_127_u16: +** cmplo p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_127_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 127), + p0 = svcmplt (p1, z0, 127)) + +/* +** cmplt_128_u16: +** mov (z[0-9]+\.h), #128 +** ( +** cmphi p0\.h, p1/z, \1, z0\.h +** | +** cmplo p0\.h, p1/z, z0\.h, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_128_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, 128), + p0 = svcmplt (p1, z0, 128)) + +/* +** cmplt_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.h, p1/z, \1\.h, z0\.h +** | +** cmplo p0\.h, p1/z, z0\.h, \1\.h +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_u16, svuint16_t, + p0 = svcmplt_n_u16 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u32.c new file mode 100644 index 00000000000..3bb0b1464b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u32.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_u32_tied: +** ( +** cmphi p0\.s, p0/z, z1\.s, z0\.s +** | +** cmplo p0\.s, p0/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u32_tied, svuint32_t, + p0 = svcmplt_u32 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_u32_untied: +** ( +** cmphi p0\.s, p1/z, z1\.s, z0\.s +** | +** cmplo p0\.s, p1/z, z0\.s, z1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u32_untied, svuint32_t, + p0 = svcmplt_u32 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_u32: +** mov (z[0-9]+\.s), w0 +** ( +** cmphi p0\.s, p1/z, \1, z0\.s +** | +** cmplo p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_u32, svuint32_t, uint32_t, + p0 = svcmplt_n_u32 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_u32: +** cmplo p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_u32: +** cmplo p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_u32: +** cmplo p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_u32: +** cmplo p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_16_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_127_u32: +** cmplo p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_127_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 127), + p0 = svcmplt (p1, z0, 127)) + +/* +** cmplt_128_u32: +** mov (z[0-9]+\.s), #128 +** ( +** cmphi p0\.s, p1/z, \1, z0\.s +** | +** cmplo p0\.s, p1/z, z0\.s, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_128_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, 128), + p0 = svcmplt (p1, z0, 128)) + +/* +** cmplt_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.s, p1/z, \1\.s, z0\.s +** | +** cmplo p0\.s, p1/z, z0\.s, \1\.s +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_u32, svuint32_t, + p0 = svcmplt_n_u32 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u64.c new file mode 100644 index 00000000000..d9de5add2bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u64.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_u64_tied: +** ( +** cmphi p0\.d, p0/z, z1\.d, z0\.d +** | +** cmplo p0\.d, p0/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u64_tied, svuint64_t, + p0 = svcmplt_u64 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_u64_untied: +** ( +** cmphi p0\.d, p1/z, z1\.d, z0\.d +** | +** cmplo p0\.d, p1/z, z0\.d, z1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u64_untied, svuint64_t, + p0 = svcmplt_u64 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_x0_u64: +** mov (z[0-9]+\.d), x0 +** ( +** cmphi p0\.d, p1/z, \1, z0\.d +** | +** cmplo p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_x0_u64, svuint64_t, uint64_t, + p0 = svcmplt_n_u64 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_u64: +** cmplo p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_u64: +** cmplo p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_u64: +** cmplo p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_u64: +** cmplo p0\.d, p1/z, z0\.d, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_16_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_127_u64: +** cmplo p0\.d, p1/z, z0\.d, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_127_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 127), + p0 = svcmplt (p1, z0, 127)) + +/* +** cmplt_128_u64: +** mov (z[0-9]+\.d), #128 +** ( +** cmphi p0\.d, p1/z, \1, z0\.d +** | +** cmplo p0\.d, p1/z, z0\.d, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_128_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, 128), + p0 = svcmplt (p1, z0, 128)) + +/* +** cmplt_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** ( +** cmphi p0\.d, p1/z, \1\.d, z0\.d +** | +** cmplo p0\.d, p1/z, z0\.d, \1\.d +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_u64, svuint64_t, + p0 = svcmplt_n_u64 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u8.c new file mode 100644 index 00000000000..42d5ad86894 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_u8.c @@ -0,0 +1,116 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_u8_tied: +** ( +** cmphi p0\.b, p0/z, z1\.b, z0\.b +** | +** cmplo p0\.b, p0/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u8_tied, svuint8_t, + p0 = svcmplt_u8 (p0, z0, z1), + p0 = svcmplt (p0, z0, z1)) + +/* +** cmplt_u8_untied: +** ( +** cmphi p0\.b, p1/z, z1\.b, z0\.b +** | +** cmplo p0\.b, p1/z, z0\.b, z1\.b +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_u8_untied, svuint8_t, + p0 = svcmplt_u8 (p1, z0, z1), + p0 = svcmplt (p1, z0, z1)) + +/* +** cmplt_w0_u8: +** mov (z[0-9]+\.b), w0 +** ( +** cmphi p0\.b, p1/z, \1, z0\.b +** | +** cmplo p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_ZX (cmplt_w0_u8, svuint8_t, uint8_t, + p0 = svcmplt_n_u8 (p1, z0, x0), + p0 = svcmplt (p1, z0, x0)) + +/* +** cmplt_0_u8: +** cmplo p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_0_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 0), + p0 = svcmplt (p1, z0, 0)) + +/* +** cmplt_1_u8: +** cmplo p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_1_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 1), + p0 = svcmplt (p1, z0, 1)) + +/* +** cmplt_15_u8: +** cmplo p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_15_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 15), + p0 = svcmplt (p1, z0, 15)) + +/* +** cmplt_16_u8: +** cmplo p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_16_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 16), + p0 = svcmplt (p1, z0, 16)) + +/* +** cmplt_127_u8: +** cmplo p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_127_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 127), + p0 = svcmplt (p1, z0, 127)) + +/* +** cmplt_128_u8: +** mov (z[0-9]+\.b), #-128 +** ( +** cmphi p0\.b, p1/z, \1, z0\.b +** | +** cmplo p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_128_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, 128), + p0 = svcmplt (p1, z0, 128)) + +/* +** cmplt_m1_u8: +** mov (z[0-9]+\.b), #-1 +** ( +** cmphi p0\.b, p1/z, \1, z0\.b +** | +** cmplo p0\.b, p1/z, z0\.b, \1 +** ) +** ret +*/ +TEST_COMPARE_Z (cmplt_m1_u8, svuint8_t, + p0 = svcmplt_n_u8 (p1, z0, -1), + p0 = svcmplt (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s16.c new file mode 100644 index 00000000000..a3c8942ba8d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_s16_tied: +** cmplt p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmplt_wide_s16 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_s16_untied: +** cmplt p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmplt_wide_s16 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmplt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_s16, svint16_t, int64_t, + p0 = svcmplt_wide_n_s16 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_s16: +** cmplt p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_s16: +** cmplt p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_s16: +** cmplt p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmplt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_m1_s16: +** cmplt p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) + +/* +** cmplt_wide_m16_s16: +** cmplt p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m16_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, -16), + p0 = svcmplt_wide (p1, z0, -16)) + +/* +** cmplt_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmplt p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m17_s16, svint16_t, + p0 = svcmplt_wide_n_s16 (p1, z0, -17), + p0 = svcmplt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s32.c new file mode 100644 index 00000000000..b2cad6773e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_s32_tied: +** cmplt p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmplt_wide_s32 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_s32_untied: +** cmplt p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmplt_wide_s32 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmplt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_s32, svint32_t, int64_t, + p0 = svcmplt_wide_n_s32 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_s32: +** cmplt p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_s32: +** cmplt p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_s32: +** cmplt p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmplt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_m1_s32: +** cmplt p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) + +/* +** cmplt_wide_m16_s32: +** cmplt p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m16_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, -16), + p0 = svcmplt_wide (p1, z0, -16)) + +/* +** cmplt_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmplt p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m17_s32, svint32_t, + p0 = svcmplt_wide_n_s32 (p1, z0, -17), + p0 = svcmplt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s8.c new file mode 100644 index 00000000000..1015fe3093a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_s8_tied: +** cmplt p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmplt_wide_s8 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_s8_untied: +** cmplt p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmplt_wide_s8 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmplt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_s8, svint8_t, int64_t, + p0 = svcmplt_wide_n_s8 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_s8: +** cmplt p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_s8: +** cmplt p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_s8: +** cmplt p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmplt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_m1_s8: +** cmplt p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) + +/* +** cmplt_wide_m16_s8: +** cmplt p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m16_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, -16), + p0 = svcmplt_wide (p1, z0, -16)) + +/* +** cmplt_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmplt p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m17_s8, svint8_t, + p0 = svcmplt_wide_n_s8 (p1, z0, -17), + p0 = svcmplt_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u16.c new file mode 100644 index 00000000000..851400d36b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_u16_tied: +** cmplo p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u16_tied, svuint16_t, svuint64_t, + p0 = svcmplt_wide_u16 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_u16_untied: +** cmplo p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u16_untied, svuint16_t, svuint64_t, + p0 = svcmplt_wide_u16 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_u16: +** mov (z[0-9]+\.d), x0 +** cmplo p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_u16, svuint16_t, uint64_t, + p0 = svcmplt_wide_n_u16 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_u16: +** cmplo p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_u16: +** cmplo p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_u16: +** cmplo p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_u16: +** cmplo p0\.h, p1/z, z0\.h, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_127_u16: +** cmplo p0\.h, p1/z, z0\.h, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_127_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 127), + p0 = svcmplt_wide (p1, z0, 127)) + +/* +** cmplt_wide_128_u16: +** mov (z[0-9]+\.d), #128 +** cmplo p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_128_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, 128), + p0 = svcmplt_wide (p1, z0, 128)) + +/* +** cmplt_wide_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** cmplo p0\.h, p1/z, z0\.h, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_u16, svuint16_t, + p0 = svcmplt_wide_n_u16 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u32.c new file mode 100644 index 00000000000..1f9652def17 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_u32_tied: +** cmplo p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u32_tied, svuint32_t, svuint64_t, + p0 = svcmplt_wide_u32 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_u32_untied: +** cmplo p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u32_untied, svuint32_t, svuint64_t, + p0 = svcmplt_wide_u32 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_u32: +** mov (z[0-9]+\.d), x0 +** cmplo p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_u32, svuint32_t, uint64_t, + p0 = svcmplt_wide_n_u32 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_u32: +** cmplo p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_u32: +** cmplo p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_u32: +** cmplo p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_u32: +** cmplo p0\.s, p1/z, z0\.s, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_127_u32: +** cmplo p0\.s, p1/z, z0\.s, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_127_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 127), + p0 = svcmplt_wide (p1, z0, 127)) + +/* +** cmplt_wide_128_u32: +** mov (z[0-9]+\.d), #128 +** cmplo p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_128_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, 128), + p0 = svcmplt_wide (p1, z0, 128)) + +/* +** cmplt_wide_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** cmplo p0\.s, p1/z, z0\.s, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_u32, svuint32_t, + p0 = svcmplt_wide_n_u32 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u8.c new file mode 100644 index 00000000000..95ef3cf16df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmplt_wide_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmplt_wide_u8_tied: +** cmplo p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u8_tied, svuint8_t, svuint64_t, + p0 = svcmplt_wide_u8 (p0, z0, z1), + p0 = svcmplt_wide (p0, z0, z1)) + +/* +** cmplt_wide_u8_untied: +** cmplo p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmplt_wide_u8_untied, svuint8_t, svuint64_t, + p0 = svcmplt_wide_u8 (p1, z0, z1), + p0 = svcmplt_wide (p1, z0, z1)) + +/* +** cmplt_wide_x0_u8: +** mov (z[0-9]+\.d), x0 +** cmplo p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmplt_wide_x0_u8, svuint8_t, uint64_t, + p0 = svcmplt_wide_n_u8 (p1, z0, x0), + p0 = svcmplt_wide (p1, z0, x0)) + +/* +** cmplt_wide_0_u8: +** cmplo p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_0_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 0), + p0 = svcmplt_wide (p1, z0, 0)) + +/* +** cmplt_wide_1_u8: +** cmplo p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_1_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 1), + p0 = svcmplt_wide (p1, z0, 1)) + +/* +** cmplt_wide_15_u8: +** cmplo p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_15_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 15), + p0 = svcmplt_wide (p1, z0, 15)) + +/* +** cmplt_wide_16_u8: +** cmplo p0\.b, p1/z, z0\.b, #16 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_16_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 16), + p0 = svcmplt_wide (p1, z0, 16)) + +/* +** cmplt_wide_127_u8: +** cmplo p0\.b, p1/z, z0\.b, #127 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_127_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 127), + p0 = svcmplt_wide (p1, z0, 127)) + +/* +** cmplt_wide_128_u8: +** mov (z[0-9]+\.d), #128 +** cmplo p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_128_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, 128), + p0 = svcmplt_wide (p1, z0, 128)) + +/* +** cmplt_wide_m1_u8: +** mov (z[0-9]+)\.b, #-1 +** cmplo p0\.b, p1/z, z0\.b, \1\.d +** ret +*/ +TEST_COMPARE_Z (cmplt_wide_m1_u8, svuint8_t, + p0 = svcmplt_wide_n_u8 (p1, z0, -1), + p0 = svcmplt_wide (p1, z0, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f16.c new file mode 100644 index 00000000000..63e203b0924 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f16.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_f16_tied: +** fcmne p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_f16_tied, svfloat16_t, + p0 = svcmpne_f16 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_f16_untied: +** fcmne p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_f16_untied, svfloat16_t, + p0 = svcmpne_f16 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_h4_f16: +** mov (z[0-9]+\.h), h4 +** fcmne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZD (cmpne_h4_f16, svfloat16_t, float16_t, + p0 = svcmpne_n_f16 (p1, z0, d4), + p0 = svcmpne (p1, z0, d4)) + +/* +** cmpne_0_f16: +** fcmne p0\.h, p1/z, z0\.h, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_f16, svfloat16_t, + p0 = svcmpne_n_f16 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fcmne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_1_f16, svfloat16_t, + p0 = svcmpne_n_f16 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f32.c new file mode 100644 index 00000000000..f81e2da511f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f32.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_f32_tied: +** fcmne p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_f32_tied, svfloat32_t, + p0 = svcmpne_f32 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_f32_untied: +** fcmne p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_f32_untied, svfloat32_t, + p0 = svcmpne_f32 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_s4_f32: +** mov (z[0-9]+\.s), s4 +** fcmne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZD (cmpne_s4_f32, svfloat32_t, float32_t, + p0 = svcmpne_n_f32 (p1, z0, d4), + p0 = svcmpne (p1, z0, d4)) + +/* +** cmpne_0_f32: +** fcmne p0\.s, p1/z, z0\.s, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_f32, svfloat32_t, + p0 = svcmpne_n_f32 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fcmne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_1_f32, svfloat32_t, + p0 = svcmpne_n_f32 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f64.c new file mode 100644 index 00000000000..22e4eeef481 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_f64.c @@ -0,0 +1,50 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_f64_tied: +** fcmne p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_f64_tied, svfloat64_t, + p0 = svcmpne_f64 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_f64_untied: +** fcmne p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_f64_untied, svfloat64_t, + p0 = svcmpne_f64 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_d4_f64: +** mov (z[0-9]+\.d), d4 +** fcmne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZD (cmpne_d4_f64, svfloat64_t, float64_t, + p0 = svcmpne_n_f64 (p1, z0, d4), + p0 = svcmpne (p1, z0, d4)) + +/* +** cmpne_0_f64: +** fcmne p0\.d, p1/z, z0\.d, #0\.0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_f64, svfloat64_t, + p0 = svcmpne_n_f64 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fcmne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_1_f64, svfloat64_t, + p0 = svcmpne_n_f64 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s16.c new file mode 100644 index 00000000000..d8c743f8b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_s16_tied: +** cmpne p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_s16_tied, svint16_t, + p0 = svcmpne_s16 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_s16_untied: +** cmpne p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_s16_untied, svint16_t, + p0 = svcmpne_s16 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_s16: +** mov (z[0-9]+\.h), w0 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_s16, svint16_t, int16_t, + p0 = svcmpne_n_s16 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_s16: +** cmpne p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_s16: +** cmpne p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_s16: +** cmpne p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_s16: +** mov (z[0-9]+\.h), #16 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_s16: +** cmpne p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_s16: +** cmpne p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_s16: +** mov (z[0-9]+\.h), #-17 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_s16, svint16_t, + p0 = svcmpne_n_s16 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s32.c new file mode 100644 index 00000000000..0d3c35111ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_s32_tied: +** cmpne p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_s32_tied, svint32_t, + p0 = svcmpne_s32 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_s32_untied: +** cmpne p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_s32_untied, svint32_t, + p0 = svcmpne_s32 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_s32: +** mov (z[0-9]+\.s), w0 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_s32, svint32_t, int32_t, + p0 = svcmpne_n_s32 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_s32: +** cmpne p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_s32: +** cmpne p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_s32: +** cmpne p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_s32: +** mov (z[0-9]+\.s), #16 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_s32: +** cmpne p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_s32: +** cmpne p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_s32: +** mov (z[0-9]+\.s), #-17 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_s32, svint32_t, + p0 = svcmpne_n_s32 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s64.c new file mode 100644 index 00000000000..4cf78f2dd3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s64.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_s64_tied: +** cmpne p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_s64_tied, svint64_t, + p0 = svcmpne_s64 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_s64_untied: +** cmpne p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_s64_untied, svint64_t, + p0 = svcmpne_s64 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_x0_s64: +** mov (z[0-9]+\.d), x0 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZX (cmpne_x0_s64, svint64_t, int64_t, + p0 = svcmpne_n_s64 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_s64: +** cmpne p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_s64: +** cmpne p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_s64: +** cmpne p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_s64: +** mov (z[0-9]+\.d), #16 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_s64: +** cmpne p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_s64: +** cmpne p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_s64: +** mov (z[0-9]+\.d), #-17 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_s64, svint64_t, + p0 = svcmpne_n_s64 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s8.c new file mode 100644 index 00000000000..6409ecdd42b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_s8_tied: +** cmpne p0\.b, p0/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_s8_tied, svint8_t, + p0 = svcmpne_s8 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_s8_untied: +** cmpne p0\.b, p1/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_s8_untied, svint8_t, + p0 = svcmpne_s8 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_s8: +** mov (z[0-9]+\.b), w0 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_s8, svint8_t, int8_t, + p0 = svcmpne_n_s8 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_s8: +** cmpne p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_s8: +** cmpne p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_s8: +** cmpne p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_s8: +** mov (z[0-9]+\.b), #16 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_s8: +** cmpne p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_s8: +** cmpne p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_s8: +** mov (z[0-9]+\.b), #-17 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_s8, svint8_t, + p0 = svcmpne_n_s8 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u16.c new file mode 100644 index 00000000000..4d22bc7d3f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_u16_tied: +** cmpne p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_u16_tied, svuint16_t, + p0 = svcmpne_u16 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_u16_untied: +** cmpne p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_u16_untied, svuint16_t, + p0 = svcmpne_u16 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_u16: +** mov (z[0-9]+\.h), w0 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_u16, svuint16_t, uint16_t, + p0 = svcmpne_n_u16 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_u16: +** cmpne p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_u16: +** cmpne p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_u16: +** cmpne p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_u16: +** mov (z[0-9]+\.h), #16 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_u16: +** cmpne p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_u16: +** cmpne p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_u16: +** mov (z[0-9]+\.h), #-17 +** cmpne p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_u16, svuint16_t, + p0 = svcmpne_n_u16 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u32.c new file mode 100644 index 00000000000..b7ca94a69e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_u32_tied: +** cmpne p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_u32_tied, svuint32_t, + p0 = svcmpne_u32 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_u32_untied: +** cmpne p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_u32_untied, svuint32_t, + p0 = svcmpne_u32 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_u32: +** mov (z[0-9]+\.s), w0 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_u32, svuint32_t, uint32_t, + p0 = svcmpne_n_u32 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_u32: +** cmpne p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_u32: +** cmpne p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_u32: +** cmpne p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_u32: +** mov (z[0-9]+\.s), #16 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_u32: +** cmpne p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_u32: +** cmpne p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_u32: +** mov (z[0-9]+\.s), #-17 +** cmpne p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_u32, svuint32_t, + p0 = svcmpne_n_u32 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u64.c new file mode 100644 index 00000000000..960ac85b1d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u64.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_u64_tied: +** cmpne p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_u64_tied, svuint64_t, + p0 = svcmpne_u64 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_u64_untied: +** cmpne p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_u64_untied, svuint64_t, + p0 = svcmpne_u64 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_x0_u64: +** mov (z[0-9]+\.d), x0 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZX (cmpne_x0_u64, svuint64_t, uint64_t, + p0 = svcmpne_n_u64 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_u64: +** cmpne p0\.d, p1/z, z0\.d, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_u64: +** cmpne p0\.d, p1/z, z0\.d, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_u64: +** cmpne p0\.d, p1/z, z0\.d, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_u64: +** mov (z[0-9]+\.d), #16 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_u64: +** cmpne p0\.d, p1/z, z0\.d, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_u64: +** cmpne p0\.d, p1/z, z0\.d, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_u64: +** mov (z[0-9]+\.d), #-17 +** cmpne p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_u64, svuint64_t, + p0 = svcmpne_n_u64 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u8.c new file mode 100644 index 00000000000..cb8496eabd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_u8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_u8_tied: +** cmpne p0\.b, p0/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_u8_tied, svuint8_t, + p0 = svcmpne_u8 (p0, z0, z1), + p0 = svcmpne (p0, z0, z1)) + +/* +** cmpne_u8_untied: +** cmpne p0\.b, p1/z, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_u8_untied, svuint8_t, + p0 = svcmpne_u8 (p1, z0, z1), + p0 = svcmpne (p1, z0, z1)) + +/* +** cmpne_w0_u8: +** mov (z[0-9]+\.b), w0 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_ZX (cmpne_w0_u8, svuint8_t, uint8_t, + p0 = svcmpne_n_u8 (p1, z0, x0), + p0 = svcmpne (p1, z0, x0)) + +/* +** cmpne_0_u8: +** cmpne p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_0_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, 0), + p0 = svcmpne (p1, z0, 0)) + +/* +** cmpne_1_u8: +** cmpne p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_1_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, 1), + p0 = svcmpne (p1, z0, 1)) + +/* +** cmpne_15_u8: +** cmpne p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_15_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, 15), + p0 = svcmpne (p1, z0, 15)) + +/* +** cmpne_16_u8: +** mov (z[0-9]+\.b), #16 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_16_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, 16), + p0 = svcmpne (p1, z0, 16)) + +/* +** cmpne_m1_u8: +** cmpne p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_m1_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, -1), + p0 = svcmpne (p1, z0, -1)) + +/* +** cmpne_m16_u8: +** cmpne p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_m16_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, -16), + p0 = svcmpne (p1, z0, -16)) + +/* +** cmpne_m17_u8: +** mov (z[0-9]+\.b), #-17 +** cmpne p0\.b, p1/z, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_COMPARE_Z (cmpne_m17_u8, svuint8_t, + p0 = svcmpne_n_u8 (p1, z0, -17), + p0 = svcmpne (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s16.c new file mode 100644 index 00000000000..4cb7586c9d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_wide_s16_tied: +** cmpne p0\.h, p0/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s16_tied, svint16_t, svint64_t, + p0 = svcmpne_wide_s16 (p0, z0, z1), + p0 = svcmpne_wide (p0, z0, z1)) + +/* +** cmpne_wide_s16_untied: +** cmpne p0\.h, p1/z, z0\.h, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s16_untied, svint16_t, svint64_t, + p0 = svcmpne_wide_s16 (p1, z0, z1), + p0 = svcmpne_wide (p1, z0, z1)) + +/* +** cmpne_wide_x0_s16: +** mov (z[0-9]+\.d), x0 +** cmpne p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpne_wide_x0_s16, svint16_t, int64_t, + p0 = svcmpne_wide_n_s16 (p1, z0, x0), + p0 = svcmpne_wide (p1, z0, x0)) + +/* +** cmpne_wide_0_s16: +** cmpne p0\.h, p1/z, z0\.h, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_0_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, 0), + p0 = svcmpne_wide (p1, z0, 0)) + +/* +** cmpne_wide_1_s16: +** cmpne p0\.h, p1/z, z0\.h, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_1_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, 1), + p0 = svcmpne_wide (p1, z0, 1)) + +/* +** cmpne_wide_15_s16: +** cmpne p0\.h, p1/z, z0\.h, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_15_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, 15), + p0 = svcmpne_wide (p1, z0, 15)) + +/* +** cmpne_wide_16_s16: +** mov (z[0-9]+\.d), #16 +** cmpne p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_16_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, 16), + p0 = svcmpne_wide (p1, z0, 16)) + +/* +** cmpne_wide_m1_s16: +** cmpne p0\.h, p1/z, z0\.h, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m1_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, -1), + p0 = svcmpne_wide (p1, z0, -1)) + +/* +** cmpne_wide_m16_s16: +** cmpne p0\.h, p1/z, z0\.h, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m16_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, -16), + p0 = svcmpne_wide (p1, z0, -16)) + +/* +** cmpne_wide_m17_s16: +** mov (z[0-9]+\.d), #-17 +** cmpne p0\.h, p1/z, z0\.h, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m17_s16, svint16_t, + p0 = svcmpne_wide_n_s16 (p1, z0, -17), + p0 = svcmpne_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s32.c new file mode 100644 index 00000000000..633994ed3f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_wide_s32_tied: +** cmpne p0\.s, p0/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s32_tied, svint32_t, svint64_t, + p0 = svcmpne_wide_s32 (p0, z0, z1), + p0 = svcmpne_wide (p0, z0, z1)) + +/* +** cmpne_wide_s32_untied: +** cmpne p0\.s, p1/z, z0\.s, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s32_untied, svint32_t, svint64_t, + p0 = svcmpne_wide_s32 (p1, z0, z1), + p0 = svcmpne_wide (p1, z0, z1)) + +/* +** cmpne_wide_x0_s32: +** mov (z[0-9]+\.d), x0 +** cmpne p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpne_wide_x0_s32, svint32_t, int64_t, + p0 = svcmpne_wide_n_s32 (p1, z0, x0), + p0 = svcmpne_wide (p1, z0, x0)) + +/* +** cmpne_wide_0_s32: +** cmpne p0\.s, p1/z, z0\.s, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_0_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, 0), + p0 = svcmpne_wide (p1, z0, 0)) + +/* +** cmpne_wide_1_s32: +** cmpne p0\.s, p1/z, z0\.s, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_1_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, 1), + p0 = svcmpne_wide (p1, z0, 1)) + +/* +** cmpne_wide_15_s32: +** cmpne p0\.s, p1/z, z0\.s, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_15_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, 15), + p0 = svcmpne_wide (p1, z0, 15)) + +/* +** cmpne_wide_16_s32: +** mov (z[0-9]+\.d), #16 +** cmpne p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_16_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, 16), + p0 = svcmpne_wide (p1, z0, 16)) + +/* +** cmpne_wide_m1_s32: +** cmpne p0\.s, p1/z, z0\.s, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m1_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, -1), + p0 = svcmpne_wide (p1, z0, -1)) + +/* +** cmpne_wide_m16_s32: +** cmpne p0\.s, p1/z, z0\.s, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m16_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, -16), + p0 = svcmpne_wide (p1, z0, -16)) + +/* +** cmpne_wide_m17_s32: +** mov (z[0-9]+\.d), #-17 +** cmpne p0\.s, p1/z, z0\.s, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m17_s32, svint32_t, + p0 = svcmpne_wide_n_s32 (p1, z0, -17), + p0 = svcmpne_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s8.c new file mode 100644 index 00000000000..de343f4cc69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpne_wide_s8.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpne_wide_s8_tied: +** cmpne p0\.b, p0/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s8_tied, svint8_t, svint64_t, + p0 = svcmpne_wide_s8 (p0, z0, z1), + p0 = svcmpne_wide (p0, z0, z1)) + +/* +** cmpne_wide_s8_untied: +** cmpne p0\.b, p1/z, z0\.b, z1\.d +** ret +*/ +TEST_COMPARE_DUAL_Z (cmpne_wide_s8_untied, svint8_t, svint64_t, + p0 = svcmpne_wide_s8 (p1, z0, z1), + p0 = svcmpne_wide (p1, z0, z1)) + +/* +** cmpne_wide_x0_s8: +** mov (z[0-9]+\.d), x0 +** cmpne p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_ZX (cmpne_wide_x0_s8, svint8_t, int64_t, + p0 = svcmpne_wide_n_s8 (p1, z0, x0), + p0 = svcmpne_wide (p1, z0, x0)) + +/* +** cmpne_wide_0_s8: +** cmpne p0\.b, p1/z, z0\.b, #0 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_0_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, 0), + p0 = svcmpne_wide (p1, z0, 0)) + +/* +** cmpne_wide_1_s8: +** cmpne p0\.b, p1/z, z0\.b, #1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_1_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, 1), + p0 = svcmpne_wide (p1, z0, 1)) + +/* +** cmpne_wide_15_s8: +** cmpne p0\.b, p1/z, z0\.b, #15 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_15_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, 15), + p0 = svcmpne_wide (p1, z0, 15)) + +/* +** cmpne_wide_16_s8: +** mov (z[0-9]+\.d), #16 +** cmpne p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_16_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, 16), + p0 = svcmpne_wide (p1, z0, 16)) + +/* +** cmpne_wide_m1_s8: +** cmpne p0\.b, p1/z, z0\.b, #-1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m1_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, -1), + p0 = svcmpne_wide (p1, z0, -1)) + +/* +** cmpne_wide_m16_s8: +** cmpne p0\.b, p1/z, z0\.b, #-16 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m16_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, -16), + p0 = svcmpne_wide (p1, z0, -16)) + +/* +** cmpne_wide_m17_s8: +** mov (z[0-9]+\.d), #-17 +** cmpne p0\.b, p1/z, z0\.b, \1 +** ret +*/ +TEST_COMPARE_Z (cmpne_wide_m17_s8, svint8_t, + p0 = svcmpne_wide_n_s8 (p1, z0, -17), + p0 = svcmpne_wide (p1, z0, -17)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c new file mode 100644 index 00000000000..8f702cddef8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f16.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpuo_f16_tied: +** fcmuo p0\.h, p0/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f16_tied, svfloat16_t, + p0 = svcmpuo_f16 (p0, z0, z1), + p0 = svcmpuo (p0, z0, z1)) + +/* +** cmpuo_f16_untied: +** fcmuo p0\.h, p1/z, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f16_untied, svfloat16_t, + p0 = svcmpuo_f16 (p1, z0, z1), + p0 = svcmpuo (p1, z0, z1)) + +/* +** cmpuo_h4_f16: +** mov (z[0-9]+\.h), h4 +** fcmuo p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_ZD (cmpuo_h4_f16, svfloat16_t, float16_t, + p0 = svcmpuo_n_f16 (p1, z0, d4), + p0 = svcmpuo (p1, z0, d4)) + +/* +** cmpuo_0_f16: +** mov (z[0-9]+\.h), #0 +** fcmuo p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpuo_0_f16, svfloat16_t, + p0 = svcmpuo_n_f16 (p1, z0, 0), + p0 = svcmpuo (p1, z0, 0)) + +/* +** cmpuo_1_f16: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fcmuo p0\.h, p1/z, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_COMPARE_Z (cmpuo_1_f16, svfloat16_t, + p0 = svcmpuo_n_f16 (p1, z0, 1), + p0 = svcmpuo (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c new file mode 100644 index 00000000000..8827604aa3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f32.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpuo_f32_tied: +** fcmuo p0\.s, p0/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f32_tied, svfloat32_t, + p0 = svcmpuo_f32 (p0, z0, z1), + p0 = svcmpuo (p0, z0, z1)) + +/* +** cmpuo_f32_untied: +** fcmuo p0\.s, p1/z, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f32_untied, svfloat32_t, + p0 = svcmpuo_f32 (p1, z0, z1), + p0 = svcmpuo (p1, z0, z1)) + +/* +** cmpuo_s4_f32: +** mov (z[0-9]+\.s), s4 +** fcmuo p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_ZD (cmpuo_s4_f32, svfloat32_t, float32_t, + p0 = svcmpuo_n_f32 (p1, z0, d4), + p0 = svcmpuo (p1, z0, d4)) + +/* +** cmpuo_0_f32: +** mov (z[0-9]+\.s), #0 +** fcmuo p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpuo_0_f32, svfloat32_t, + p0 = svcmpuo_n_f32 (p1, z0, 0), + p0 = svcmpuo (p1, z0, 0)) + +/* +** cmpuo_1_f32: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fcmuo p0\.s, p1/z, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_COMPARE_Z (cmpuo_1_f32, svfloat32_t, + p0 = svcmpuo_n_f32 (p1, z0, 1), + p0 = svcmpuo (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c new file mode 100644 index 00000000000..d7a71eca464 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cmpuo_f64.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cmpuo_f64_tied: +** fcmuo p0\.d, p0/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f64_tied, svfloat64_t, + p0 = svcmpuo_f64 (p0, z0, z1), + p0 = svcmpuo (p0, z0, z1)) + +/* +** cmpuo_f64_untied: +** fcmuo p0\.d, p1/z, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpuo_f64_untied, svfloat64_t, + p0 = svcmpuo_f64 (p1, z0, z1), + p0 = svcmpuo (p1, z0, z1)) + +/* +** cmpuo_d4_f64: +** mov (z[0-9]+\.d), d4 +** fcmuo p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_ZD (cmpuo_d4_f64, svfloat64_t, float64_t, + p0 = svcmpuo_n_f64 (p1, z0, d4), + p0 = svcmpuo (p1, z0, d4)) + +/* +** cmpuo_0_f64: +** mov (z[0-9]+\.d), #0 +** fcmuo p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpuo_0_f64, svfloat64_t, + p0 = svcmpuo_n_f64 (p1, z0, 0), + p0 = svcmpuo (p1, z0, 0)) + +/* +** cmpuo_1_f64: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fcmuo p0\.d, p1/z, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_COMPARE_Z (cmpuo_1_f64, svfloat64_t, + p0 = svcmpuo_n_f64 (p1, z0, 1), + p0 = svcmpuo (p1, z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c new file mode 100644 index 00000000000..19d46be68b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_s16_m_tied12: +** cnot z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_m_tied12, svint16_t, + z0 = svcnot_s16_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_s16_m_tied1: +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_m_tied1, svint16_t, + z0 = svcnot_s16_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_m_tied2, svint16_t, + z0 = svcnot_s16_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_s16_m_untied: +** movprfx z0, z2 +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_m_untied, svint16_t, + z0 = svcnot_s16_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** cnot z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_z_tied1, svint16_t, + z0 = svcnot_s16_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_z_untied, svint16_t, + z0 = svcnot_s16_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_s16_x_tied1: +** cnot z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_x_tied1, svint16_t, + z0 = svcnot_s16_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_s16_x_untied: +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_s16_x_untied, svint16_t, + z0 = svcnot_s16_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c new file mode 100644 index 00000000000..041b59a046c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_s32_m_tied12: +** cnot z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_m_tied12, svint32_t, + z0 = svcnot_s32_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_s32_m_tied1: +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_m_tied1, svint32_t, + z0 = svcnot_s32_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_m_tied2, svint32_t, + z0 = svcnot_s32_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_s32_m_untied: +** movprfx z0, z2 +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_m_untied, svint32_t, + z0 = svcnot_s32_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** cnot z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_z_tied1, svint32_t, + z0 = svcnot_s32_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_z_untied, svint32_t, + z0 = svcnot_s32_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_s32_x_tied1: +** cnot z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_x_tied1, svint32_t, + z0 = svcnot_s32_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_s32_x_untied: +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_s32_x_untied, svint32_t, + z0 = svcnot_s32_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c new file mode 100644 index 00000000000..c7135cb9568 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_s64_m_tied12: +** cnot z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_m_tied12, svint64_t, + z0 = svcnot_s64_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_s64_m_tied1: +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_m_tied1, svint64_t, + z0 = svcnot_s64_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** cnot z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_m_tied2, svint64_t, + z0 = svcnot_s64_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_s64_m_untied: +** movprfx z0, z2 +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_m_untied, svint64_t, + z0 = svcnot_s64_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** cnot z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_z_tied1, svint64_t, + z0 = svcnot_s64_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_z_untied, svint64_t, + z0 = svcnot_s64_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_s64_x_tied1: +** cnot z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_x_tied1, svint64_t, + z0 = svcnot_s64_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_s64_x_untied: +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_s64_x_untied, svint64_t, + z0 = svcnot_s64_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c new file mode 100644 index 00000000000..0560f97516b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_s8_m_tied12: +** cnot z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_m_tied12, svint8_t, + z0 = svcnot_s8_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_s8_m_tied1: +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_m_tied1, svint8_t, + z0 = svcnot_s8_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_m_tied2, svint8_t, + z0 = svcnot_s8_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_s8_m_untied: +** movprfx z0, z2 +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_m_untied, svint8_t, + z0 = svcnot_s8_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_s8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** cnot z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_z_tied1, svint8_t, + z0 = svcnot_s8_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_z_untied, svint8_t, + z0 = svcnot_s8_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_s8_x_tied1: +** cnot z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_x_tied1, svint8_t, + z0 = svcnot_s8_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_s8_x_untied: +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_s8_x_untied, svint8_t, + z0 = svcnot_s8_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c new file mode 100644 index 00000000000..7ea9ff71ded --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_u16_m_tied12: +** cnot z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_m_tied12, svuint16_t, + z0 = svcnot_u16_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_u16_m_tied1: +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_m_tied1, svuint16_t, + z0 = svcnot_u16_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_m_tied2, svuint16_t, + z0 = svcnot_u16_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_u16_m_untied: +** movprfx z0, z2 +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_m_untied, svuint16_t, + z0 = svcnot_u16_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** cnot z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_z_tied1, svuint16_t, + z0 = svcnot_u16_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_z_untied, svuint16_t, + z0 = svcnot_u16_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_u16_x_tied1: +** cnot z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_x_tied1, svuint16_t, + z0 = svcnot_u16_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_u16_x_untied: +** cnot z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnot_u16_x_untied, svuint16_t, + z0 = svcnot_u16_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c new file mode 100644 index 00000000000..972c7751eb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_u32_m_tied12: +** cnot z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_m_tied12, svuint32_t, + z0 = svcnot_u32_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_u32_m_tied1: +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_m_tied1, svuint32_t, + z0 = svcnot_u32_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_m_tied2, svuint32_t, + z0 = svcnot_u32_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_u32_m_untied: +** movprfx z0, z2 +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_m_untied, svuint32_t, + z0 = svcnot_u32_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** cnot z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_z_tied1, svuint32_t, + z0 = svcnot_u32_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_z_untied, svuint32_t, + z0 = svcnot_u32_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_u32_x_tied1: +** cnot z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_x_tied1, svuint32_t, + z0 = svcnot_u32_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_u32_x_untied: +** cnot z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnot_u32_x_untied, svuint32_t, + z0 = svcnot_u32_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c new file mode 100644 index 00000000000..f25e001c569 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_u64_m_tied12: +** cnot z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_m_tied12, svuint64_t, + z0 = svcnot_u64_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_u64_m_tied1: +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_m_tied1, svuint64_t, + z0 = svcnot_u64_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** cnot z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_m_tied2, svuint64_t, + z0 = svcnot_u64_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_u64_m_untied: +** movprfx z0, z2 +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_m_untied, svuint64_t, + z0 = svcnot_u64_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** cnot z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_z_tied1, svuint64_t, + z0 = svcnot_u64_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_z_untied, svuint64_t, + z0 = svcnot_u64_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_u64_x_tied1: +** cnot z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_x_tied1, svuint64_t, + z0 = svcnot_u64_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_u64_x_untied: +** cnot z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnot_u64_x_untied, svuint64_t, + z0 = svcnot_u64_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c new file mode 100644 index 00000000000..e135a72956a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnot_u8_m_tied12: +** cnot z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_m_tied12, svuint8_t, + z0 = svcnot_u8_m (z0, p0, z0), + z0 = svcnot_m (z0, p0, z0)) + +/* +** cnot_u8_m_tied1: +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_m_tied1, svuint8_t, + z0 = svcnot_u8_m (z0, p0, z1), + z0 = svcnot_m (z0, p0, z1)) + +/* +** cnot_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnot z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_m_tied2, svuint8_t, + z0 = svcnot_u8_m (z1, p0, z0), + z0 = svcnot_m (z1, p0, z0)) + +/* +** cnot_u8_m_untied: +** movprfx z0, z2 +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_m_untied, svuint8_t, + z0 = svcnot_u8_m (z2, p0, z1), + z0 = svcnot_m (z2, p0, z1)) + +/* +** cnot_u8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** cnot z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_z_tied1, svuint8_t, + z0 = svcnot_u8_z (p0, z0), + z0 = svcnot_z (p0, z0)) + +/* +** cnot_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_z_untied, svuint8_t, + z0 = svcnot_u8_z (p0, z1), + z0 = svcnot_z (p0, z1)) + +/* +** cnot_u8_x_tied1: +** cnot z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_x_tied1, svuint8_t, + z0 = svcnot_u8_x (p0, z0), + z0 = svcnot_x (p0, z0)) + +/* +** cnot_u8_x_untied: +** cnot z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnot_u8_x_untied, svuint8_t, + z0 = svcnot_u8_x (p0, z1), + z0 = svcnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c new file mode 100644 index 00000000000..b8061bb80dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_f16_m_tied1: +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_f16_m_tied1, svuint16_t, svfloat16_t, + z0 = svcnt_f16_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_f16_m_untied: +** movprfx z0, z1 +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_f16_m_untied, svuint16_t, svfloat16_t, + z0 = svcnt_f16_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_f16_z: +** movprfx z0\.h, p0/z, z4\.h +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_f16_z, svuint16_t, svfloat16_t, + z0 = svcnt_f16_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_f16_x: +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_f16_x, svuint16_t, svfloat16_t, + z0 = svcnt_f16_x (p0, z4), + z0 = svcnt_x (p0, z4)) + +/* +** ptrue_cnt_f16_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cnt_f16_x, svuint16_t, svfloat16_t, + z0 = svcnt_f16_x (svptrue_b16 (), z4), + z0 = svcnt_x (svptrue_b16 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c new file mode 100644 index 00000000000..b9292c97709 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_f32_m_tied1: +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_f32_m_tied1, svuint32_t, svfloat32_t, + z0 = svcnt_f32_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_f32_m_untied: +** movprfx z0, z1 +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_f32_m_untied, svuint32_t, svfloat32_t, + z0 = svcnt_f32_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_f32_z: +** movprfx z0\.s, p0/z, z4\.s +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_f32_z, svuint32_t, svfloat32_t, + z0 = svcnt_f32_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_f32_x: +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_f32_x, svuint32_t, svfloat32_t, + z0 = svcnt_f32_x (p0, z4), + z0 = svcnt_x (p0, z4)) + +/* +** ptrue_cnt_f32_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cnt_f32_x, svuint32_t, svfloat32_t, + z0 = svcnt_f32_x (svptrue_b32 (), z4), + z0 = svcnt_x (svptrue_b32 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c new file mode 100644 index 00000000000..4976ee467a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c @@ -0,0 +1,52 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_f64_m_tied1: +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_f64_m_tied1, svuint64_t, svfloat64_t, + z0 = svcnt_f64_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_f64_m_untied: +** movprfx z0, z1 +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_f64_m_untied, svuint64_t, svfloat64_t, + z0 = svcnt_f64_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_f64_z: +** movprfx z0\.d, p0/z, z4\.d +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_f64_z, svuint64_t, svfloat64_t, + z0 = svcnt_f64_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_f64_x: +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_f64_x, svuint64_t, svfloat64_t, + z0 = svcnt_f64_x (p0, z4), + z0 = svcnt_x (p0, z4)) + +/* +** ptrue_cnt_f64_x: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cnt_f64_x, svuint64_t, svfloat64_t, + z0 = svcnt_f64_x (svptrue_b64 (), z4), + z0 = svcnt_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c new file mode 100644 index 00000000000..a8ff8f3d2cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_s16_m_tied1: +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_s16_m_tied1, svuint16_t, svint16_t, + z0 = svcnt_s16_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_s16_m_untied: +** movprfx z0, z1 +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_s16_m_untied, svuint16_t, svint16_t, + z0 = svcnt_s16_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_s16_z: +** movprfx z0\.h, p0/z, z4\.h +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_s16_z, svuint16_t, svint16_t, + z0 = svcnt_s16_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_s16_x: +** cnt z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cnt_s16_x, svuint16_t, svint16_t, + z0 = svcnt_s16_x (p0, z4), + z0 = svcnt_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c new file mode 100644 index 00000000000..3d16041f24e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_s32_m_tied1: +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_s32_m_tied1, svuint32_t, svint32_t, + z0 = svcnt_s32_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_s32_m_untied: +** movprfx z0, z1 +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_s32_m_untied, svuint32_t, svint32_t, + z0 = svcnt_s32_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_s32_z: +** movprfx z0\.s, p0/z, z4\.s +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_s32_z, svuint32_t, svint32_t, + z0 = svcnt_s32_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_s32_x: +** cnt z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cnt_s32_x, svuint32_t, svint32_t, + z0 = svcnt_s32_x (p0, z4), + z0 = svcnt_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c new file mode 100644 index 00000000000..8c8871ba593 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_s64_m_tied1: +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_s64_m_tied1, svuint64_t, svint64_t, + z0 = svcnt_s64_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_s64_m_untied: +** movprfx z0, z1 +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_s64_m_untied, svuint64_t, svint64_t, + z0 = svcnt_s64_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_s64_z: +** movprfx z0\.d, p0/z, z4\.d +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_s64_z, svuint64_t, svint64_t, + z0 = svcnt_s64_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_s64_x: +** cnt z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cnt_s64_x, svuint64_t, svint64_t, + z0 = svcnt_s64_x (p0, z4), + z0 = svcnt_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c new file mode 100644 index 00000000000..8d85c8e5149 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_s8_m_tied1: +** cnt z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cnt_s8_m_tied1, svuint8_t, svint8_t, + z0 = svcnt_s8_m (z0, p0, z4), + z0 = svcnt_m (z0, p0, z4)) + +/* +** cnt_s8_m_untied: +** movprfx z0, z1 +** cnt z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cnt_s8_m_untied, svuint8_t, svint8_t, + z0 = svcnt_s8_m (z1, p0, z4), + z0 = svcnt_m (z1, p0, z4)) + +/* +** cnt_s8_z: +** movprfx z0\.b, p0/z, z4\.b +** cnt z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cnt_s8_z, svuint8_t, svint8_t, + z0 = svcnt_s8_z (p0, z4), + z0 = svcnt_z (p0, z4)) + +/* +** cnt_s8_x: +** cnt z0\.b, p0/m, z4\.b +** ret +*/ +TEST_DUAL_Z (cnt_s8_x, svuint8_t, svint8_t, + z0 = svcnt_s8_x (p0, z4), + z0 = svcnt_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c new file mode 100644 index 00000000000..f173d3108f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_u16_m_tied12: +** cnt z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_m_tied12, svuint16_t, + z0 = svcnt_u16_m (z0, p0, z0), + z0 = svcnt_m (z0, p0, z0)) + +/* +** cnt_u16_m_tied1: +** cnt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_m_tied1, svuint16_t, + z0 = svcnt_u16_m (z0, p0, z1), + z0 = svcnt_m (z0, p0, z1)) + +/* +** cnt_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnt z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_m_tied2, svuint16_t, + z0 = svcnt_u16_m (z1, p0, z0), + z0 = svcnt_m (z1, p0, z0)) + +/* +** cnt_u16_m_untied: +** movprfx z0, z2 +** cnt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_m_untied, svuint16_t, + z0 = svcnt_u16_m (z2, p0, z1), + z0 = svcnt_m (z2, p0, z1)) + +/* +** cnt_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** cnt z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_z_tied1, svuint16_t, + z0 = svcnt_u16_z (p0, z0), + z0 = svcnt_z (p0, z0)) + +/* +** cnt_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** cnt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_z_untied, svuint16_t, + z0 = svcnt_u16_z (p0, z1), + z0 = svcnt_z (p0, z1)) + +/* +** cnt_u16_x_tied1: +** cnt z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_x_tied1, svuint16_t, + z0 = svcnt_u16_x (p0, z0), + z0 = svcnt_x (p0, z0)) + +/* +** cnt_u16_x_untied: +** cnt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (cnt_u16_x_untied, svuint16_t, + z0 = svcnt_u16_x (p0, z1), + z0 = svcnt_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c new file mode 100644 index 00000000000..11969a6b6ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_u32_m_tied12: +** cnt z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_m_tied12, svuint32_t, + z0 = svcnt_u32_m (z0, p0, z0), + z0 = svcnt_m (z0, p0, z0)) + +/* +** cnt_u32_m_tied1: +** cnt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_m_tied1, svuint32_t, + z0 = svcnt_u32_m (z0, p0, z1), + z0 = svcnt_m (z0, p0, z1)) + +/* +** cnt_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnt z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_m_tied2, svuint32_t, + z0 = svcnt_u32_m (z1, p0, z0), + z0 = svcnt_m (z1, p0, z0)) + +/* +** cnt_u32_m_untied: +** movprfx z0, z2 +** cnt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_m_untied, svuint32_t, + z0 = svcnt_u32_m (z2, p0, z1), + z0 = svcnt_m (z2, p0, z1)) + +/* +** cnt_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** cnt z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_z_tied1, svuint32_t, + z0 = svcnt_u32_z (p0, z0), + z0 = svcnt_z (p0, z0)) + +/* +** cnt_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** cnt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_z_untied, svuint32_t, + z0 = svcnt_u32_z (p0, z1), + z0 = svcnt_z (p0, z1)) + +/* +** cnt_u32_x_tied1: +** cnt z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_x_tied1, svuint32_t, + z0 = svcnt_u32_x (p0, z0), + z0 = svcnt_x (p0, z0)) + +/* +** cnt_u32_x_untied: +** cnt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (cnt_u32_x_untied, svuint32_t, + z0 = svcnt_u32_x (p0, z1), + z0 = svcnt_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c new file mode 100644 index 00000000000..4eb69ea846e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_u64_m_tied12: +** cnt z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_m_tied12, svuint64_t, + z0 = svcnt_u64_m (z0, p0, z0), + z0 = svcnt_m (z0, p0, z0)) + +/* +** cnt_u64_m_tied1: +** cnt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_m_tied1, svuint64_t, + z0 = svcnt_u64_m (z0, p0, z1), + z0 = svcnt_m (z0, p0, z1)) + +/* +** cnt_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** cnt z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_m_tied2, svuint64_t, + z0 = svcnt_u64_m (z1, p0, z0), + z0 = svcnt_m (z1, p0, z0)) + +/* +** cnt_u64_m_untied: +** movprfx z0, z2 +** cnt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_m_untied, svuint64_t, + z0 = svcnt_u64_m (z2, p0, z1), + z0 = svcnt_m (z2, p0, z1)) + +/* +** cnt_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** cnt z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_z_tied1, svuint64_t, + z0 = svcnt_u64_z (p0, z0), + z0 = svcnt_z (p0, z0)) + +/* +** cnt_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** cnt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_z_untied, svuint64_t, + z0 = svcnt_u64_z (p0, z1), + z0 = svcnt_z (p0, z1)) + +/* +** cnt_u64_x_tied1: +** cnt z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_x_tied1, svuint64_t, + z0 = svcnt_u64_x (p0, z0), + z0 = svcnt_x (p0, z0)) + +/* +** cnt_u64_x_untied: +** cnt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (cnt_u64_x_untied, svuint64_t, + z0 = svcnt_u64_x (p0, z1), + z0 = svcnt_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c new file mode 100644 index 00000000000..30e79830219 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnt_u8_m_tied12: +** cnt z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_m_tied12, svuint8_t, + z0 = svcnt_u8_m (z0, p0, z0), + z0 = svcnt_m (z0, p0, z0)) + +/* +** cnt_u8_m_tied1: +** cnt z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_m_tied1, svuint8_t, + z0 = svcnt_u8_m (z0, p0, z1), + z0 = svcnt_m (z0, p0, z1)) + +/* +** cnt_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** cnt z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_m_tied2, svuint8_t, + z0 = svcnt_u8_m (z1, p0, z0), + z0 = svcnt_m (z1, p0, z0)) + +/* +** cnt_u8_m_untied: +** movprfx z0, z2 +** cnt z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_m_untied, svuint8_t, + z0 = svcnt_u8_m (z2, p0, z1), + z0 = svcnt_m (z2, p0, z1)) + +/* +** cnt_u8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** cnt z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_z_tied1, svuint8_t, + z0 = svcnt_u8_z (p0, z0), + z0 = svcnt_z (p0, z0)) + +/* +** cnt_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** cnt z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_z_untied, svuint8_t, + z0 = svcnt_u8_z (p0, z1), + z0 = svcnt_z (p0, z1)) + +/* +** cnt_u8_x_tied1: +** cnt z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_x_tied1, svuint8_t, + z0 = svcnt_u8_x (p0, z0), + z0 = svcnt_x (p0, z0)) + +/* +** cnt_u8_x_untied: +** cnt z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (cnt_u8_x_untied, svuint8_t, + z0 = svcnt_u8_x (p0, z1), + z0 = svcnt_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb.c new file mode 100644 index 00000000000..8b8fe8e4f2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb.c @@ -0,0 +1,280 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntb_1: +** cntb x0 +** ret +*/ +PROTO (cntb_1, uint64_t, ()) { return svcntb (); } + +/* +** cntb_2: +** cntb x0, all, mul #2 +** ret +*/ +PROTO (cntb_2, uint64_t, ()) { return svcntb () * 2; } + +/* +** cntb_3: +** cntb x0, all, mul #3 +** ret +*/ +PROTO (cntb_3, uint64_t, ()) { return svcntb () * 3; } + +/* +** cntb_4: +** cntb x0, all, mul #4 +** ret +*/ +PROTO (cntb_4, uint64_t, ()) { return svcntb () * 4; } + +/* +** cntb_8: +** cntb x0, all, mul #8 +** ret +*/ +PROTO (cntb_8, uint64_t, ()) { return svcntb () * 8; } + +/* +** cntb_15: +** cntb x0, all, mul #15 +** ret +*/ +PROTO (cntb_15, uint64_t, ()) { return svcntb () * 15; } + +/* +** cntb_16: +** cntb x0, all, mul #16 +** ret +*/ +PROTO (cntb_16, uint64_t, ()) { return svcntb () * 16; } + +/* Other sequences would be OK. */ +/* +** cntb_17: +** cntb x0, all, mul #16 +** incb x0 +** ret +*/ +PROTO (cntb_17, uint64_t, ()) { return svcntb () * 17; } + +/* +** cntb_32: +** cntd (x[0-9]+) +** lsl x0, \1, 8 +** ret +*/ +PROTO (cntb_32, uint64_t, ()) { return svcntb () * 32; } + +/* Other sequences would be OK. */ +/* +** cntb_33: +** cntb (x[0-9]+) +** lsl x0, \1, 5 +** incb x0 +** ret +*/ +PROTO (cntb_33, uint64_t, ()) { return svcntb () * 33; } + +/* +** cntb_64: +** cntd (x[0-9]+) +** lsl x0, \1, 9 +** ret +*/ +PROTO (cntb_64, uint64_t, ()) { return svcntb () * 64; } + +/* +** cntb_128: +** cntd (x[0-9]+) +** lsl x0, \1, 10 +** ret +*/ +PROTO (cntb_128, uint64_t, ()) { return svcntb () * 128; } + +/* Other sequences would be OK. */ +/* +** cntb_129: +** cntb (x[0-9]+) +** lsl x0, \1, 7 +** incb x0 +** ret +*/ +PROTO (cntb_129, uint64_t, ()) { return svcntb () * 129; } + +/* +** cntb_m1: +** cntb (x[0-9]+) +** neg x0, \1 +** ret +*/ +PROTO (cntb_m1, uint64_t, ()) { return -svcntb (); } + +/* +** cntb_m13: +** cntb (x[0-9]+), all, mul #13 +** neg x0, \1 +** ret +*/ +PROTO (cntb_m13, uint64_t, ()) { return -svcntb () * 13; } + +/* +** cntb_m15: +** cntb (x[0-9]+), all, mul #15 +** neg x0, \1 +** ret +*/ +PROTO (cntb_m15, uint64_t, ()) { return -svcntb () * 15; } + +/* +** cntb_m16: +** cntb (x[0-9]+), all, mul #16 +** neg x0, \1 +** ret +*/ +PROTO (cntb_m16, uint64_t, ()) { return -svcntb () * 16; } + +/* Other sequences would be OK. */ +/* +** cntb_m17: +** cntb x0, all, mul #16 +** incb x0 +** neg x0, x0 +** ret +*/ +PROTO (cntb_m17, uint64_t, ()) { return -svcntb () * 17; } + +/* +** incb_1: +** incb x0 +** ret +*/ +PROTO (incb_1, uint64_t, (uint64_t x0)) { return x0 + svcntb (); } + +/* +** incb_2: +** incb x0, all, mul #2 +** ret +*/ +PROTO (incb_2, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 2; } + +/* +** incb_3: +** incb x0, all, mul #3 +** ret +*/ +PROTO (incb_3, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 3; } + +/* +** incb_4: +** incb x0, all, mul #4 +** ret +*/ +PROTO (incb_4, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 4; } + +/* +** incb_8: +** incb x0, all, mul #8 +** ret +*/ +PROTO (incb_8, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 8; } + +/* +** incb_15: +** incb x0, all, mul #15 +** ret +*/ +PROTO (incb_15, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 15; } + +/* +** incb_16: +** incb x0, all, mul #16 +** ret +*/ +PROTO (incb_16, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 16; } + +/* +** incb_17: +** addvl x0, x0, #17 +** ret +*/ +PROTO (incb_17, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 17; } + +/* +** incb_31: +** addvl x0, x0, #31 +** ret +*/ +PROTO (incb_31, uint64_t, (uint64_t x0)) { return x0 + svcntb () * 31; } + +/* +** decb_1: +** decb x0 +** ret +*/ +PROTO (decb_1, uint64_t, (uint64_t x0)) { return x0 - svcntb (); } + +/* +** decb_2: +** decb x0, all, mul #2 +** ret +*/ +PROTO (decb_2, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 2; } + +/* +** decb_3: +** decb x0, all, mul #3 +** ret +*/ +PROTO (decb_3, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 3; } + +/* +** decb_4: +** decb x0, all, mul #4 +** ret +*/ +PROTO (decb_4, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 4; } + +/* +** decb_8: +** decb x0, all, mul #8 +** ret +*/ +PROTO (decb_8, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 8; } + +/* +** decb_15: +** decb x0, all, mul #15 +** ret +*/ +PROTO (decb_15, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 15; } + +/* +** decb_16: +** decb x0, all, mul #16 +** ret +*/ +PROTO (decb_16, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 16; } + +/* +** decb_17: +** addvl x0, x0, #-17 +** ret +*/ +PROTO (decb_17, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 17; } + +/* +** decb_31: +** addvl x0, x0, #-31 +** ret +*/ +PROTO (decb_31, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 31; } + +/* +** decb_32: +** addvl x0, x0, #-32 +** ret +*/ +PROTO (decb_32, uint64_t, (uint64_t x0)) { return x0 - svcntb () * 32; } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb_pat.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb_pat.c new file mode 100644 index 00000000000..effc5668dbe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntb_pat.c @@ -0,0 +1,432 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntb_pow2: +** cntb x0, pow2 +** ret +*/ +PROTO (cntb_pow2, uint64_t, ()) { return svcntb_pat (SV_POW2); } + +/* +** cntb_vl1: +** mov x0, #?1 +** ret +*/ +PROTO (cntb_vl1, uint64_t, ()) { return svcntb_pat (SV_VL1); } + +/* +** cntb_vl2: +** mov x0, #?2 +** ret +*/ +PROTO (cntb_vl2, uint64_t, ()) { return svcntb_pat (SV_VL2); } + +/* +** cntb_vl3: +** mov x0, #?3 +** ret +*/ +PROTO (cntb_vl3, uint64_t, ()) { return svcntb_pat (SV_VL3); } + +/* +** cntb_vl4: +** mov x0, #?4 +** ret +*/ +PROTO (cntb_vl4, uint64_t, ()) { return svcntb_pat (SV_VL4); } + +/* +** cntb_vl5: +** mov x0, #?5 +** ret +*/ +PROTO (cntb_vl5, uint64_t, ()) { return svcntb_pat (SV_VL5); } + +/* +** cntb_vl6: +** mov x0, #?6 +** ret +*/ +PROTO (cntb_vl6, uint64_t, ()) { return svcntb_pat (SV_VL6); } + +/* +** cntb_vl7: +** mov x0, #?7 +** ret +*/ +PROTO (cntb_vl7, uint64_t, ()) { return svcntb_pat (SV_VL7); } + +/* +** cntb_vl8: +** mov x0, #?8 +** ret +*/ +PROTO (cntb_vl8, uint64_t, ()) { return svcntb_pat (SV_VL8); } + +/* +** cntb_vl16: +** mov x0, #?16 +** ret +*/ +PROTO (cntb_vl16, uint64_t, ()) { return svcntb_pat (SV_VL16); } + +/* +** cntb_vl32: +** cntb x0, vl32 +** ret +*/ +PROTO (cntb_vl32, uint64_t, ()) { return svcntb_pat (SV_VL32); } + +/* +** cntb_vl64: +** cntb x0, vl64 +** ret +*/ +PROTO (cntb_vl64, uint64_t, ()) { return svcntb_pat (SV_VL64); } + +/* +** cntb_vl128: +** cntb x0, vl128 +** ret +*/ +PROTO (cntb_vl128, uint64_t, ()) { return svcntb_pat (SV_VL128); } + +/* +** cntb_vl256: +** cntb x0, vl256 +** ret +*/ +PROTO (cntb_vl256, uint64_t, ()) { return svcntb_pat (SV_VL256); } + +/* +** cntb_mul3: +** cntb x0, mul3 +** ret +*/ +PROTO (cntb_mul3, uint64_t, ()) { return svcntb_pat (SV_MUL3); } + +/* +** cntb_mul4: +** cntb x0, mul4 +** ret +*/ +PROTO (cntb_mul4, uint64_t, ()) { return svcntb_pat (SV_MUL4); } + +/* +** cntb_all: +** cntb x0 +** ret +*/ +PROTO (cntb_all, uint64_t, ()) { return svcntb_pat (SV_ALL); } + +/* +** incb_32_pow2: +** incb x0, pow2 +** ret +*/ +PROTO (incb_32_pow2, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_POW2); } + +/* +** incb_32_vl1: +** add w0, w0, #?1 +** ret +*/ +PROTO (incb_32_vl1, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL1); } + +/* +** incb_32_vl2: +** add w0, w0, #?2 +** ret +*/ +PROTO (incb_32_vl2, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL2); } + +/* +** incb_32_vl3: +** add w0, w0, #?3 +** ret +*/ +PROTO (incb_32_vl3, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL3); } + +/* +** incb_32_vl4: +** add w0, w0, #?4 +** ret +*/ +PROTO (incb_32_vl4, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL4); } + +/* +** incb_32_vl5: +** add w0, w0, #?5 +** ret +*/ +PROTO (incb_32_vl5, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL5); } + +/* +** incb_32_vl6: +** add w0, w0, #?6 +** ret +*/ +PROTO (incb_32_vl6, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL6); } + +/* +** incb_32_vl7: +** add w0, w0, #?7 +** ret +*/ +PROTO (incb_32_vl7, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL7); } + +/* +** incb_32_vl8: +** add w0, w0, #?8 +** ret +*/ +PROTO (incb_32_vl8, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL8); } + +/* +** incb_32_vl16: +** add w0, w0, #?16 +** ret +*/ +PROTO (incb_32_vl16, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL16); } + +/* +** incb_32_vl32: +** incb x0, vl32 +** ret +*/ +PROTO (incb_32_vl32, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL32); } + +/* +** incb_32_vl64: +** incb x0, vl64 +** ret +*/ +PROTO (incb_32_vl64, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL64); } + +/* +** incb_32_vl128: +** incb x0, vl128 +** ret +*/ +PROTO (incb_32_vl128, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL128); } + +/* +** incb_32_vl256: +** incb x0, vl256 +** ret +*/ +PROTO (incb_32_vl256, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_VL256); } + +/* +** incb_32_mul3: +** incb x0, mul3 +** ret +*/ +PROTO (incb_32_mul3, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_MUL3); } + +/* +** incb_32_mul4: +** incb x0, mul4 +** ret +*/ +PROTO (incb_32_mul4, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_MUL4); } + +/* +** incb_32_all: +** incb x0 +** ret +*/ +PROTO (incb_32_all, uint32_t, (uint32_t w0)) { return w0 + svcntb_pat (SV_ALL); } + +/* +** incb_64_pow2: +** incb x0, pow2 +** ret +*/ +PROTO (incb_64_pow2, uint64_t, (uint64_t x0)) { return x0 + svcntb_pat (SV_POW2); } + +/* +** incb_64_all: +** incb x0 +** ret +*/ +PROTO (incb_64_all, uint64_t, (uint64_t x0)) { return x0 + svcntb_pat (SV_ALL); } + +/* +** decb_32_pow2: +** decb x0, pow2 +** ret +*/ +PROTO (decb_32_pow2, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_POW2); } + +/* +** decb_32_vl1: +** sub w0, w0, #?1 +** ret +*/ +PROTO (decb_32_vl1, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL1); } + +/* +** decb_32_vl2: +** sub w0, w0, #?2 +** ret +*/ +PROTO (decb_32_vl2, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL2); } + +/* +** decb_32_vl3: +** sub w0, w0, #?3 +** ret +*/ +PROTO (decb_32_vl3, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL3); } + +/* +** decb_32_vl4: +** sub w0, w0, #?4 +** ret +*/ +PROTO (decb_32_vl4, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL4); } + +/* +** decb_32_vl5: +** sub w0, w0, #?5 +** ret +*/ +PROTO (decb_32_vl5, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL5); } + +/* +** decb_32_vl6: +** sub w0, w0, #?6 +** ret +*/ +PROTO (decb_32_vl6, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL6); } + +/* +** decb_32_vl7: +** sub w0, w0, #?7 +** ret +*/ +PROTO (decb_32_vl7, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL7); } + +/* +** decb_32_vl8: +** sub w0, w0, #?8 +** ret +*/ +PROTO (decb_32_vl8, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL8); } + +/* +** decb_32_vl16: +** sub w0, w0, #?16 +** ret +*/ +PROTO (decb_32_vl16, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL16); } + +/* +** decb_32_vl32: +** decb x0, vl32 +** ret +*/ +PROTO (decb_32_vl32, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL32); } + +/* +** decb_32_vl64: +** decb x0, vl64 +** ret +*/ +PROTO (decb_32_vl64, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL64); } + +/* +** decb_32_vl128: +** decb x0, vl128 +** ret +*/ +PROTO (decb_32_vl128, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL128); } + +/* +** decb_32_vl256: +** decb x0, vl256 +** ret +*/ +PROTO (decb_32_vl256, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_VL256); } + +/* +** decb_32_mul3: +** decb x0, mul3 +** ret +*/ +PROTO (decb_32_mul3, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_MUL3); } + +/* +** decb_32_mul4: +** decb x0, mul4 +** ret +*/ +PROTO (decb_32_mul4, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_MUL4); } + +/* +** decb_32_all: +** decb x0 +** ret +*/ +PROTO (decb_32_all, uint32_t, (uint32_t w0)) { return w0 - svcntb_pat (SV_ALL); } + +/* +** decb_64_pow2: +** decb x0, pow2 +** ret +*/ +PROTO (decb_64_pow2, uint64_t, (uint64_t x0)) { return x0 - svcntb_pat (SV_POW2); } + +/* +** decb_64_all: +** decb x0 +** ret +*/ +PROTO (decb_64_all, uint64_t, (uint64_t x0)) { return x0 - svcntb_pat (SV_ALL); } + +/* +** incb_s8_pow2_z0: +** cntb x([0-9]+), pow2 +** mov (z[0-9]+\.b), w\1 +** add z0\.b, (z0\.b, \2|\2, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (incb_s8_pow2_z0, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z0, svcntb_pat (SV_POW2)), + z0 = svadd_x (svptrue_b8 (), z0, svcntb_pat (SV_POW2))); + +/* +** incb_s8_pow2_z1: +** cntb x([0-9]+), pow2 +** mov (z[0-9]+\.b), w\1 +** add z0\.b, (z1\.b, \2|\2, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (incb_s8_pow2_z1, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z1, svcntb_pat (SV_POW2)), + z0 = svadd_x (svptrue_b8 (), z1, svcntb_pat (SV_POW2))); + +/* +** decb_s8_pow2_z0: +** cntb x([0-9]+), pow2 +** mov (z[0-9]+\.b), w\1 +** sub z0\.b, z0\.b, \2 +** ret +*/ +TEST_UNIFORM_Z (decb_s8_pow2_z0, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z0, svcntb_pat (SV_POW2)), + z0 = svsub_x (svptrue_b8 (), z0, svcntb_pat (SV_POW2))); + +/* +** decb_s8_pow2_z1: +** cntb x([0-9]+), pow2 +** mov (z[0-9]+\.b), w\1 +** sub z0\.b, z1\.b, \2 +** ret +*/ +TEST_UNIFORM_Z (decb_s8_pow2_z1, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z1, svcntb_pat (SV_POW2)), + z0 = svsub_x (svptrue_b8 (), z1, svcntb_pat (SV_POW2))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd.c new file mode 100644 index 00000000000..0d0ed4849f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd.c @@ -0,0 +1,278 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntd_1: +** cntd x0 +** ret +*/ +PROTO (cntd_1, uint64_t, ()) { return svcntd (); } + +/* +** cntd_2: +** cntw x0 +** ret +*/ +PROTO (cntd_2, uint64_t, ()) { return svcntd () * 2; } + +/* +** cntd_3: +** cntd x0, all, mul #3 +** ret +*/ +PROTO (cntd_3, uint64_t, ()) { return svcntd () * 3; } + +/* +** cntd_4: +** cnth x0 +** ret +*/ +PROTO (cntd_4, uint64_t, ()) { return svcntd () * 4; } + +/* +** cntd_8: +** cntb x0 +** ret +*/ +PROTO (cntd_8, uint64_t, ()) { return svcntd () * 8; } + +/* +** cntd_15: +** cntd x0, all, mul #15 +** ret +*/ +PROTO (cntd_15, uint64_t, ()) { return svcntd () * 15; } + +/* +** cntd_16: +** cntb x0, all, mul #2 +** ret +*/ +PROTO (cntd_16, uint64_t, ()) { return svcntd () * 16; } + +/* Other sequences would be OK. */ +/* +** cntd_17: +** cntb x0, all, mul #2 +** incd x0 +** ret +*/ +PROTO (cntd_17, uint64_t, ()) { return svcntd () * 17; } + +/* +** cntd_32: +** cntb x0, all, mul #4 +** ret +*/ +PROTO (cntd_32, uint64_t, ()) { return svcntd () * 32; } + +/* +** cntd_64: +** cntb x0, all, mul #8 +** ret +*/ +PROTO (cntd_64, uint64_t, ()) { return svcntd () * 64; } + +/* +** cntd_128: +** cntb x0, all, mul #16 +** ret +*/ +PROTO (cntd_128, uint64_t, ()) { return svcntd () * 128; } + +/* +** cntd_m1: +** cntd (x[0-9]+) +** neg x0, \1 +** ret +*/ +PROTO (cntd_m1, uint64_t, ()) { return -svcntd (); } + +/* +** cntd_m13: +** cntd (x[0-9]+), all, mul #13 +** neg x0, \1 +** ret +*/ +PROTO (cntd_m13, uint64_t, ()) { return -svcntd () * 13; } + +/* +** cntd_m15: +** cntd (x[0-9]+), all, mul #15 +** neg x0, \1 +** ret +*/ +PROTO (cntd_m15, uint64_t, ()) { return -svcntd () * 15; } + +/* +** cntd_m16: +** cntb (x[0-9]+), all, mul #2 +** neg x0, \1 +** ret +*/ +PROTO (cntd_m16, uint64_t, ()) { return -svcntd () * 16; } + +/* Other sequences would be OK. */ +/* +** cntd_m17: +** cntb x0, all, mul #2 +** incd x0 +** neg x0, x0 +** ret +*/ +PROTO (cntd_m17, uint64_t, ()) { return -svcntd () * 17; } + +/* +** incd_1: +** incd x0 +** ret +*/ +PROTO (incd_1, uint64_t, (uint64_t x0)) { return x0 + svcntd (); } + +/* +** incd_2: +** incw x0 +** ret +*/ +PROTO (incd_2, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 2; } + +/* +** incd_3: +** incd x0, all, mul #3 +** ret +*/ +PROTO (incd_3, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 3; } + +/* +** incd_4: +** inch x0 +** ret +*/ +PROTO (incd_4, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 4; } + +/* +** incd_7: +** incd x0, all, mul #7 +** ret +*/ +PROTO (incd_7, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 7; } + +/* +** incd_8: +** incb x0 +** ret +*/ +PROTO (incd_8, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 8; } + +/* +** incd_9: +** incd x0, all, mul #9 +** ret +*/ +PROTO (incd_9, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 9; } + +/* +** incd_15: +** incd x0, all, mul #15 +** ret +*/ +PROTO (incd_15, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 15; } + +/* +** incd_16: +** incb x0, all, mul #2 +** ret +*/ +PROTO (incd_16, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 16; } + +/* +** incd_18: +** incw x0, all, mul #9 +** ret +*/ +PROTO (incd_18, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 18; } + +/* +** incd_30: +** incw x0, all, mul #15 +** ret +*/ +PROTO (incd_30, uint64_t, (uint64_t x0)) { return x0 + svcntd () * 30; } + +/* +** decd_1: +** decd x0 +** ret +*/ +PROTO (decd_1, uint64_t, (uint64_t x0)) { return x0 - svcntd (); } + +/* +** decd_2: +** decw x0 +** ret +*/ +PROTO (decd_2, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 2; } + +/* +** decd_3: +** decd x0, all, mul #3 +** ret +*/ +PROTO (decd_3, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 3; } + +/* +** decd_4: +** dech x0 +** ret +*/ +PROTO (decd_4, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 4; } + +/* +** decd_7: +** decd x0, all, mul #7 +** ret +*/ +PROTO (decd_7, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 7; } + +/* +** decd_8: +** decb x0 +** ret +*/ +PROTO (decd_8, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 8; } + +/* +** decd_9: +** decd x0, all, mul #9 +** ret +*/ +PROTO (decd_9, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 9; } + +/* +** decd_15: +** decd x0, all, mul #15 +** ret +*/ +PROTO (decd_15, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 15; } + +/* +** decd_16: +** decb x0, all, mul #2 +** ret +*/ +PROTO (decd_16, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 16; } + +/* +** decd_18: +** decw x0, all, mul #9 +** ret +*/ +PROTO (decd_18, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 18; } + +/* +** decd_30: +** decw x0, all, mul #15 +** ret +*/ +PROTO (decd_30, uint64_t, (uint64_t x0)) { return x0 - svcntd () * 30; } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd_pat.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd_pat.c new file mode 100644 index 00000000000..31ecde7ae1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntd_pat.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntd_pow2: +** cntd x0, pow2 +** ret +*/ +PROTO (cntd_pow2, uint64_t, ()) { return svcntd_pat (SV_POW2); } + +/* +** cntd_vl1: +** mov x0, #?1 +** ret +*/ +PROTO (cntd_vl1, uint64_t, ()) { return svcntd_pat (SV_VL1); } + +/* +** cntd_vl2: +** mov x0, #?2 +** ret +*/ +PROTO (cntd_vl2, uint64_t, ()) { return svcntd_pat (SV_VL2); } + +/* +** cntd_vl3: +** cntd x0, vl3 +** ret +*/ +PROTO (cntd_vl3, uint64_t, ()) { return svcntd_pat (SV_VL3); } + +/* +** cntd_vl4: +** cntd x0, vl4 +** ret +*/ +PROTO (cntd_vl4, uint64_t, ()) { return svcntd_pat (SV_VL4); } + +/* +** cntd_vl5: +** cntd x0, vl5 +** ret +*/ +PROTO (cntd_vl5, uint64_t, ()) { return svcntd_pat (SV_VL5); } + +/* +** cntd_vl6: +** cntd x0, vl6 +** ret +*/ +PROTO (cntd_vl6, uint64_t, ()) { return svcntd_pat (SV_VL6); } + +/* +** cntd_vl7: +** cntd x0, vl7 +** ret +*/ +PROTO (cntd_vl7, uint64_t, ()) { return svcntd_pat (SV_VL7); } + +/* +** cntd_vl8: +** cntd x0, vl8 +** ret +*/ +PROTO (cntd_vl8, uint64_t, ()) { return svcntd_pat (SV_VL8); } + +/* +** cntd_vl16: +** cntd x0, vl16 +** ret +*/ +PROTO (cntd_vl16, uint64_t, ()) { return svcntd_pat (SV_VL16); } + +/* +** cntd_vl32: +** cntd x0, vl32 +** ret +*/ +PROTO (cntd_vl32, uint64_t, ()) { return svcntd_pat (SV_VL32); } + +/* +** cntd_vl64: +** cntd x0, vl64 +** ret +*/ +PROTO (cntd_vl64, uint64_t, ()) { return svcntd_pat (SV_VL64); } + +/* +** cntd_vl128: +** cntd x0, vl128 +** ret +*/ +PROTO (cntd_vl128, uint64_t, ()) { return svcntd_pat (SV_VL128); } + +/* +** cntd_vl256: +** cntd x0, vl256 +** ret +*/ +PROTO (cntd_vl256, uint64_t, ()) { return svcntd_pat (SV_VL256); } + +/* +** cntd_mul3: +** cntd x0, mul3 +** ret +*/ +PROTO (cntd_mul3, uint64_t, ()) { return svcntd_pat (SV_MUL3); } + +/* +** cntd_mul4: +** cntd x0, mul4 +** ret +*/ +PROTO (cntd_mul4, uint64_t, ()) { return svcntd_pat (SV_MUL4); } + +/* +** cntd_all: +** cntd x0 +** ret +*/ +PROTO (cntd_all, uint64_t, ()) { return svcntd_pat (SV_ALL); } + +/* +** incd_32_pow2: +** incd x0, pow2 +** ret +*/ +PROTO (incd_32_pow2, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_POW2); } + +/* +** incd_32_vl1: +** add w0, w0, #?1 +** ret +*/ +PROTO (incd_32_vl1, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL1); } + +/* +** incd_32_vl2: +** add w0, w0, #?2 +** ret +*/ +PROTO (incd_32_vl2, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL2); } + +/* +** incd_32_vl3: +** incd x0, vl3 +** ret +*/ +PROTO (incd_32_vl3, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL3); } + +/* +** incd_32_vl4: +** incd x0, vl4 +** ret +*/ +PROTO (incd_32_vl4, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL4); } + +/* +** incd_32_vl5: +** incd x0, vl5 +** ret +*/ +PROTO (incd_32_vl5, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL5); } + +/* +** incd_32_vl6: +** incd x0, vl6 +** ret +*/ +PROTO (incd_32_vl6, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL6); } + +/* +** incd_32_vl7: +** incd x0, vl7 +** ret +*/ +PROTO (incd_32_vl7, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL7); } + +/* +** incd_32_vl8: +** incd x0, vl8 +** ret +*/ +PROTO (incd_32_vl8, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL8); } + +/* +** incd_32_vl16: +** incd x0, vl16 +** ret +*/ +PROTO (incd_32_vl16, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL16); } + +/* +** incd_32_vl32: +** incd x0, vl32 +** ret +*/ +PROTO (incd_32_vl32, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL32); } + +/* +** incd_32_vl64: +** incd x0, vl64 +** ret +*/ +PROTO (incd_32_vl64, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL64); } + +/* +** incd_32_vl128: +** incd x0, vl128 +** ret +*/ +PROTO (incd_32_vl128, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL128); } + +/* +** incd_32_vl256: +** incd x0, vl256 +** ret +*/ +PROTO (incd_32_vl256, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_VL256); } + +/* +** incd_32_mul3: +** incd x0, mul3 +** ret +*/ +PROTO (incd_32_mul3, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_MUL3); } + +/* +** incd_32_mul4: +** incd x0, mul4 +** ret +*/ +PROTO (incd_32_mul4, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_MUL4); } + +/* +** incd_32_all: +** incd x0 +** ret +*/ +PROTO (incd_32_all, uint32_t, (uint32_t w0)) { return w0 + svcntd_pat (SV_ALL); } + +/* +** incd_64_pow2: +** incd x0, pow2 +** ret +*/ +PROTO (incd_64_pow2, uint64_t, (uint64_t x0)) { return x0 + svcntd_pat (SV_POW2); } + +/* +** incd_64_all: +** incd x0 +** ret +*/ +PROTO (incd_64_all, uint64_t, (uint64_t x0)) { return x0 + svcntd_pat (SV_ALL); } + +/* +** decd_32_pow2: +** decd x0, pow2 +** ret +*/ +PROTO (decd_32_pow2, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_POW2); } + +/* +** decd_32_vl1: +** sub w0, w0, #?1 +** ret +*/ +PROTO (decd_32_vl1, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL1); } + +/* +** decd_32_vl2: +** sub w0, w0, #?2 +** ret +*/ +PROTO (decd_32_vl2, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL2); } + +/* +** decd_32_vl3: +** decd x0, vl3 +** ret +*/ +PROTO (decd_32_vl3, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL3); } + +/* +** decd_32_vl4: +** decd x0, vl4 +** ret +*/ +PROTO (decd_32_vl4, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL4); } + +/* +** decd_32_vl5: +** decd x0, vl5 +** ret +*/ +PROTO (decd_32_vl5, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL5); } + +/* +** decd_32_vl6: +** decd x0, vl6 +** ret +*/ +PROTO (decd_32_vl6, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL6); } + +/* +** decd_32_vl7: +** decd x0, vl7 +** ret +*/ +PROTO (decd_32_vl7, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL7); } + +/* +** decd_32_vl8: +** decd x0, vl8 +** ret +*/ +PROTO (decd_32_vl8, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL8); } + +/* +** decd_32_vl16: +** decd x0, vl16 +** ret +*/ +PROTO (decd_32_vl16, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL16); } + +/* +** decd_32_vl32: +** decd x0, vl32 +** ret +*/ +PROTO (decd_32_vl32, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL32); } + +/* +** decd_32_vl64: +** decd x0, vl64 +** ret +*/ +PROTO (decd_32_vl64, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL64); } + +/* +** decd_32_vl128: +** decd x0, vl128 +** ret +*/ +PROTO (decd_32_vl128, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL128); } + +/* +** decd_32_vl256: +** decd x0, vl256 +** ret +*/ +PROTO (decd_32_vl256, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_VL256); } + +/* +** decd_32_mul3: +** decd x0, mul3 +** ret +*/ +PROTO (decd_32_mul3, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_MUL3); } + +/* +** decd_32_mul4: +** decd x0, mul4 +** ret +*/ +PROTO (decd_32_mul4, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_MUL4); } + +/* +** decd_32_all: +** decd x0 +** ret +*/ +PROTO (decd_32_all, uint32_t, (uint32_t w0)) { return w0 - svcntd_pat (SV_ALL); } + +/* +** decd_64_pow2: +** decd x0, pow2 +** ret +*/ +PROTO (decd_64_pow2, uint64_t, (uint64_t x0)) { return x0 - svcntd_pat (SV_POW2); } + +/* +** decd_64_all: +** decd x0 +** ret +*/ +PROTO (decd_64_all, uint64_t, (uint64_t x0)) { return x0 - svcntd_pat (SV_ALL); } + +/* +** incd_s64_pow2_z0: +** incd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (incd_s64_pow2_z0, svint64_t, + z0 = svadd_n_s64_x (svptrue_b64 (), z0, svcntd_pat (SV_POW2)), + z0 = svadd_x (svptrue_b64 (), z0, svcntd_pat (SV_POW2))); + +/* +** incd_s64_pow2_z1: +** movprfx z0, z1 +** incd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (incd_s64_pow2_z1, svint64_t, + z0 = svadd_n_s64_x (svptrue_b64 (), z1, svcntd_pat (SV_POW2)), + z0 = svadd_x (svptrue_b64 (), z1, svcntd_pat (SV_POW2))); + +/* +** decd_s64_pow2_z0: +** decd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (decd_s64_pow2_z0, svint64_t, + z0 = svsub_n_s64_x (svptrue_b64 (), z0, svcntd_pat (SV_POW2)), + z0 = svsub_x (svptrue_b64 (), z0, svcntd_pat (SV_POW2))); + +/* +** decd_s64_pow2_z1: +** movprfx z0, z1 +** decd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (decd_s64_pow2_z1, svint64_t, + z0 = svsub_n_s64_x (svptrue_b64 (), z1, svcntd_pat (SV_POW2)), + z0 = svsub_x (svptrue_b64 (), z1, svcntd_pat (SV_POW2))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth.c new file mode 100644 index 00000000000..c29930f1591 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth.c @@ -0,0 +1,280 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnth_1: +** cnth x0 +** ret +*/ +PROTO (cnth_1, uint64_t, ()) { return svcnth (); } + +/* +** cnth_2: +** cntb x0 +** ret +*/ +PROTO (cnth_2, uint64_t, ()) { return svcnth () * 2; } + +/* +** cnth_3: +** cnth x0, all, mul #3 +** ret +*/ +PROTO (cnth_3, uint64_t, ()) { return svcnth () * 3; } + +/* +** cnth_4: +** cntb x0, all, mul #2 +** ret +*/ +PROTO (cnth_4, uint64_t, ()) { return svcnth () * 4; } + +/* +** cnth_8: +** cntb x0, all, mul #4 +** ret +*/ +PROTO (cnth_8, uint64_t, ()) { return svcnth () * 8; } + +/* +** cnth_15: +** cnth x0, all, mul #15 +** ret +*/ +PROTO (cnth_15, uint64_t, ()) { return svcnth () * 15; } + +/* +** cnth_16: +** cntb x0, all, mul #8 +** ret +*/ +PROTO (cnth_16, uint64_t, ()) { return svcnth () * 16; } + +/* Other sequences would be OK. */ +/* +** cnth_17: +** cntb x0, all, mul #8 +** inch x0 +** ret +*/ +PROTO (cnth_17, uint64_t, ()) { return svcnth () * 17; } + +/* +** cnth_32: +** cntb x0, all, mul #16 +** ret +*/ +PROTO (cnth_32, uint64_t, ()) { return svcnth () * 32; } + +/* +** cnth_64: +** cntd (x[0-9]+) +** lsl x0, \1, 8 +** ret +*/ +PROTO (cnth_64, uint64_t, ()) { return svcnth () * 64; } + +/* +** cnth_128: +** cntd (x[0-9]+) +** lsl x0, \1, 9 +** ret +*/ +PROTO (cnth_128, uint64_t, ()) { return svcnth () * 128; } + +/* +** cnth_m1: +** cnth (x[0-9]+) +** neg x0, \1 +** ret +*/ +PROTO (cnth_m1, uint64_t, ()) { return -svcnth (); } + +/* +** cnth_m13: +** cnth (x[0-9]+), all, mul #13 +** neg x0, \1 +** ret +*/ +PROTO (cnth_m13, uint64_t, ()) { return -svcnth () * 13; } + +/* +** cnth_m15: +** cnth (x[0-9]+), all, mul #15 +** neg x0, \1 +** ret +*/ +PROTO (cnth_m15, uint64_t, ()) { return -svcnth () * 15; } + +/* +** cnth_m16: +** cntb (x[0-9]+), all, mul #8 +** neg x0, \1 +** ret +*/ +PROTO (cnth_m16, uint64_t, ()) { return -svcnth () * 16; } + +/* Other sequences would be OK. */ +/* +** cnth_m17: +** cntb x0, all, mul #8 +** inch x0 +** neg x0, x0 +** ret +*/ +PROTO (cnth_m17, uint64_t, ()) { return -svcnth () * 17; } + +/* +** inch_1: +** inch x0 +** ret +*/ +PROTO (inch_1, uint64_t, (uint64_t x0)) { return x0 + svcnth (); } + +/* +** inch_2: +** incb x0 +** ret +*/ +PROTO (inch_2, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 2; } + +/* +** inch_3: +** inch x0, all, mul #3 +** ret +*/ +PROTO (inch_3, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 3; } + +/* +** inch_4: +** incb x0, all, mul #2 +** ret +*/ +PROTO (inch_4, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 4; } + +/* +** inch_7: +** inch x0, all, mul #7 +** ret +*/ +PROTO (inch_7, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 7; } + +/* +** inch_8: +** incb x0, all, mul #4 +** ret +*/ +PROTO (inch_8, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 8; } + +/* +** inch_9: +** inch x0, all, mul #9 +** ret +*/ +PROTO (inch_9, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 9; } + +/* +** inch_15: +** inch x0, all, mul #15 +** ret +*/ +PROTO (inch_15, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 15; } + +/* +** inch_16: +** incb x0, all, mul #8 +** ret +*/ +PROTO (inch_16, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 16; } + +/* +** inch_18: +** incb x0, all, mul #9 +** ret +*/ +PROTO (inch_18, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 18; } + +/* +** inch_30: +** incb x0, all, mul #15 +** ret +*/ +PROTO (inch_30, uint64_t, (uint64_t x0)) { return x0 + svcnth () * 30; } + +/* +** dech_1: +** dech x0 +** ret +*/ +PROTO (dech_1, uint64_t, (uint64_t x0)) { return x0 - svcnth (); } + +/* +** dech_2: +** decb x0 +** ret +*/ +PROTO (dech_2, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 2; } + +/* +** dech_3: +** dech x0, all, mul #3 +** ret +*/ +PROTO (dech_3, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 3; } + +/* +** dech_4: +** decb x0, all, mul #2 +** ret +*/ +PROTO (dech_4, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 4; } + +/* +** dech_7: +** dech x0, all, mul #7 +** ret +*/ +PROTO (dech_7, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 7; } + +/* +** dech_8: +** decb x0, all, mul #4 +** ret +*/ +PROTO (dech_8, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 8; } + +/* +** dech_9: +** dech x0, all, mul #9 +** ret +*/ +PROTO (dech_9, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 9; } + +/* +** dech_15: +** dech x0, all, mul #15 +** ret +*/ +PROTO (dech_15, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 15; } + +/* +** dech_16: +** decb x0, all, mul #8 +** ret +*/ +PROTO (dech_16, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 16; } + +/* +** dech_18: +** decb x0, all, mul #9 +** ret +*/ +PROTO (dech_18, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 18; } + +/* +** dech_30: +** decb x0, all, mul #15 +** ret +*/ +PROTO (dech_30, uint64_t, (uint64_t x0)) { return x0 - svcnth () * 30; } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth_pat.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth_pat.c new file mode 100644 index 00000000000..7a42e7ad963 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnth_pat.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cnth_pow2: +** cnth x0, pow2 +** ret +*/ +PROTO (cnth_pow2, uint64_t, ()) { return svcnth_pat (SV_POW2); } + +/* +** cnth_vl1: +** mov x0, #?1 +** ret +*/ +PROTO (cnth_vl1, uint64_t, ()) { return svcnth_pat (SV_VL1); } + +/* +** cnth_vl2: +** mov x0, #?2 +** ret +*/ +PROTO (cnth_vl2, uint64_t, ()) { return svcnth_pat (SV_VL2); } + +/* +** cnth_vl3: +** mov x0, #?3 +** ret +*/ +PROTO (cnth_vl3, uint64_t, ()) { return svcnth_pat (SV_VL3); } + +/* +** cnth_vl4: +** mov x0, #?4 +** ret +*/ +PROTO (cnth_vl4, uint64_t, ()) { return svcnth_pat (SV_VL4); } + +/* +** cnth_vl5: +** mov x0, #?5 +** ret +*/ +PROTO (cnth_vl5, uint64_t, ()) { return svcnth_pat (SV_VL5); } + +/* +** cnth_vl6: +** mov x0, #?6 +** ret +*/ +PROTO (cnth_vl6, uint64_t, ()) { return svcnth_pat (SV_VL6); } + +/* +** cnth_vl7: +** mov x0, #?7 +** ret +*/ +PROTO (cnth_vl7, uint64_t, ()) { return svcnth_pat (SV_VL7); } + +/* +** cnth_vl8: +** mov x0, #?8 +** ret +*/ +PROTO (cnth_vl8, uint64_t, ()) { return svcnth_pat (SV_VL8); } + +/* +** cnth_vl16: +** cnth x0, vl16 +** ret +*/ +PROTO (cnth_vl16, uint64_t, ()) { return svcnth_pat (SV_VL16); } + +/* +** cnth_vl32: +** cnth x0, vl32 +** ret +*/ +PROTO (cnth_vl32, uint64_t, ()) { return svcnth_pat (SV_VL32); } + +/* +** cnth_vl64: +** cnth x0, vl64 +** ret +*/ +PROTO (cnth_vl64, uint64_t, ()) { return svcnth_pat (SV_VL64); } + +/* +** cnth_vl128: +** cnth x0, vl128 +** ret +*/ +PROTO (cnth_vl128, uint64_t, ()) { return svcnth_pat (SV_VL128); } + +/* +** cnth_vl256: +** cnth x0, vl256 +** ret +*/ +PROTO (cnth_vl256, uint64_t, ()) { return svcnth_pat (SV_VL256); } + +/* +** cnth_mul3: +** cnth x0, mul3 +** ret +*/ +PROTO (cnth_mul3, uint64_t, ()) { return svcnth_pat (SV_MUL3); } + +/* +** cnth_mul4: +** cnth x0, mul4 +** ret +*/ +PROTO (cnth_mul4, uint64_t, ()) { return svcnth_pat (SV_MUL4); } + +/* +** cnth_all: +** cnth x0 +** ret +*/ +PROTO (cnth_all, uint64_t, ()) { return svcnth_pat (SV_ALL); } + +/* +** inch_32_pow2: +** inch x0, pow2 +** ret +*/ +PROTO (inch_32_pow2, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_POW2); } + +/* +** inch_32_vl1: +** add w0, w0, #?1 +** ret +*/ +PROTO (inch_32_vl1, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL1); } + +/* +** inch_32_vl2: +** add w0, w0, #?2 +** ret +*/ +PROTO (inch_32_vl2, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL2); } + +/* +** inch_32_vl3: +** add w0, w0, #?3 +** ret +*/ +PROTO (inch_32_vl3, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL3); } + +/* +** inch_32_vl4: +** add w0, w0, #?4 +** ret +*/ +PROTO (inch_32_vl4, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL4); } + +/* +** inch_32_vl5: +** add w0, w0, #?5 +** ret +*/ +PROTO (inch_32_vl5, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL5); } + +/* +** inch_32_vl6: +** add w0, w0, #?6 +** ret +*/ +PROTO (inch_32_vl6, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL6); } + +/* +** inch_32_vl7: +** add w0, w0, #?7 +** ret +*/ +PROTO (inch_32_vl7, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL7); } + +/* +** inch_32_vl8: +** add w0, w0, #?8 +** ret +*/ +PROTO (inch_32_vl8, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL8); } + +/* +** inch_32_vl16: +** inch x0, vl16 +** ret +*/ +PROTO (inch_32_vl16, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL16); } + +/* +** inch_32_vl32: +** inch x0, vl32 +** ret +*/ +PROTO (inch_32_vl32, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL32); } + +/* +** inch_32_vl64: +** inch x0, vl64 +** ret +*/ +PROTO (inch_32_vl64, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL64); } + +/* +** inch_32_vl128: +** inch x0, vl128 +** ret +*/ +PROTO (inch_32_vl128, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL128); } + +/* +** inch_32_vl256: +** inch x0, vl256 +** ret +*/ +PROTO (inch_32_vl256, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_VL256); } + +/* +** inch_32_mul3: +** inch x0, mul3 +** ret +*/ +PROTO (inch_32_mul3, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_MUL3); } + +/* +** inch_32_mul4: +** inch x0, mul4 +** ret +*/ +PROTO (inch_32_mul4, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_MUL4); } + +/* +** inch_32_all: +** inch x0 +** ret +*/ +PROTO (inch_32_all, uint32_t, (uint32_t w0)) { return w0 + svcnth_pat (SV_ALL); } + +/* +** inch_64_pow2: +** inch x0, pow2 +** ret +*/ +PROTO (inch_64_pow2, uint64_t, (uint64_t x0)) { return x0 + svcnth_pat (SV_POW2); } + +/* +** inch_64_all: +** inch x0 +** ret +*/ +PROTO (inch_64_all, uint64_t, (uint64_t x0)) { return x0 + svcnth_pat (SV_ALL); } + +/* +** dech_32_pow2: +** dech x0, pow2 +** ret +*/ +PROTO (dech_32_pow2, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_POW2); } + +/* +** dech_32_vl1: +** sub w0, w0, #?1 +** ret +*/ +PROTO (dech_32_vl1, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL1); } + +/* +** dech_32_vl2: +** sub w0, w0, #?2 +** ret +*/ +PROTO (dech_32_vl2, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL2); } + +/* +** dech_32_vl3: +** sub w0, w0, #?3 +** ret +*/ +PROTO (dech_32_vl3, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL3); } + +/* +** dech_32_vl4: +** sub w0, w0, #?4 +** ret +*/ +PROTO (dech_32_vl4, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL4); } + +/* +** dech_32_vl5: +** sub w0, w0, #?5 +** ret +*/ +PROTO (dech_32_vl5, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL5); } + +/* +** dech_32_vl6: +** sub w0, w0, #?6 +** ret +*/ +PROTO (dech_32_vl6, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL6); } + +/* +** dech_32_vl7: +** sub w0, w0, #?7 +** ret +*/ +PROTO (dech_32_vl7, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL7); } + +/* +** dech_32_vl8: +** sub w0, w0, #?8 +** ret +*/ +PROTO (dech_32_vl8, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL8); } + +/* +** dech_32_vl16: +** dech x0, vl16 +** ret +*/ +PROTO (dech_32_vl16, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL16); } + +/* +** dech_32_vl32: +** dech x0, vl32 +** ret +*/ +PROTO (dech_32_vl32, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL32); } + +/* +** dech_32_vl64: +** dech x0, vl64 +** ret +*/ +PROTO (dech_32_vl64, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL64); } + +/* +** dech_32_vl128: +** dech x0, vl128 +** ret +*/ +PROTO (dech_32_vl128, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL128); } + +/* +** dech_32_vl256: +** dech x0, vl256 +** ret +*/ +PROTO (dech_32_vl256, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_VL256); } + +/* +** dech_32_mul3: +** dech x0, mul3 +** ret +*/ +PROTO (dech_32_mul3, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_MUL3); } + +/* +** dech_32_mul4: +** dech x0, mul4 +** ret +*/ +PROTO (dech_32_mul4, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_MUL4); } + +/* +** dech_32_all: +** dech x0 +** ret +*/ +PROTO (dech_32_all, uint32_t, (uint32_t w0)) { return w0 - svcnth_pat (SV_ALL); } + +/* +** dech_64_pow2: +** dech x0, pow2 +** ret +*/ +PROTO (dech_64_pow2, uint64_t, (uint64_t x0)) { return x0 - svcnth_pat (SV_POW2); } + +/* +** dech_64_all: +** dech x0 +** ret +*/ +PROTO (dech_64_all, uint64_t, (uint64_t x0)) { return x0 - svcnth_pat (SV_ALL); } + +/* +** inch_s16_pow2_z0: +** inch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (inch_s16_pow2_z0, svint16_t, + z0 = svadd_n_s16_x (svptrue_b16 (), z0, svcnth_pat (SV_POW2)), + z0 = svadd_x (svptrue_b16 (), z0, svcnth_pat (SV_POW2))); + +/* +** inch_s16_pow2_z1: +** movprfx z0, z1 +** inch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (inch_s16_pow2_z1, svint16_t, + z0 = svadd_n_s16_x (svptrue_b16 (), z1, svcnth_pat (SV_POW2)), + z0 = svadd_x (svptrue_b16 (), z1, svcnth_pat (SV_POW2))); + +/* +** dech_s16_pow2_z0: +** dech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (dech_s16_pow2_z0, svint16_t, + z0 = svsub_n_s16_x (svptrue_b16 (), z0, svcnth_pat (SV_POW2)), + z0 = svsub_x (svptrue_b16 (), z0, svcnth_pat (SV_POW2))); + +/* +** dech_s16_pow2_z1: +** movprfx z0, z1 +** dech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (dech_s16_pow2_z1, svint16_t, + z0 = svsub_n_s16_x (svptrue_b16 (), z1, svcnth_pat (SV_POW2)), + z0 = svsub_x (svptrue_b16 (), z1, svcnth_pat (SV_POW2))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b16.c new file mode 100644 index 00000000000..d88b9e5f32c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b16.c @@ -0,0 +1,243 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** cnt_b16_32: +** cntp x0, p0, p1\.h +** ret +*/ +TEST_PTEST (cnt_b16_32, uint32_t, + x0 = svcntp_b16 (p0, p1)); + +/* +** cnt_b16_64: +** cntp x0, p0, p1\.h +** ret +*/ +TEST_PTEST (cnt_b16_64, uint64_t, + x0 = svcntp_b16 (p0, p1)); + +/* +** inc_b16_32_general_x0: +** cntp x([0-9]+), p0, p1\.h +** add w0, (w0, w\1|w\1, w0) +** ret +*/ +TEST_PTEST (inc_b16_32_general_x0, uint32_t, + x0 += svcntp_b16 (p0, p1)); + +/* +** inc_b16_32_general_x1: +** cntp x([0-9]+), p0, p1\.h +** add w0, (w1, w\1|w\1, w1) +** ret +*/ +TEST_PTEST (inc_b16_32_general_x1, uint32_t, + x0 = x1 + svcntp_b16 (p0, p1)); + +/* +** inc_b16_32_ptrue_x0: +** incp x0, p1\.h +** ret +*/ +TEST_PTEST (inc_b16_32_ptrue_x0, uint32_t, + x0 += svcntp_b16 (svptrue_b16 (), p1)); + +/* +** inc_b16_32_ptrue_x1: +** mov w0, w1 +** incp x0, p1\.h +** ret +*/ +TEST_PTEST (inc_b16_32_ptrue_x1, uint32_t, + x0 = x1 + svcntp_b16 (svptrue_b16 (), p1)); + +/* +** inc_b16_64_general_x0: +** cntp (x[0-9]+), p0, p1\.h +** add x0, (x0, \1|\1, x0) +** ret +*/ +TEST_PTEST (inc_b16_64_general_x0, uint64_t, + x0 += svcntp_b16 (p0, p1)); + +/* +** inc_b16_64_general_x1: +** cntp (x[0-9]+), p0, p1\.h +** add x0, (x1, \1|\1, x1) +** ret +*/ +TEST_PTEST (inc_b16_64_general_x1, uint64_t, + x0 = x1 + svcntp_b16 (p0, p1)); + +/* +** inc_b16_64_ptrue_x0: +** incp x0, p1\.h +** ret +*/ +TEST_PTEST (inc_b16_64_ptrue_x0, uint64_t, + x0 += svcntp_b16 (svptrue_b16 (), p1)); + +/* +** inc_b16_64_ptrue_x1: +** mov x0, x1 +** incp x0, p1\.h +** ret +*/ +TEST_PTEST (inc_b16_64_ptrue_x1, uint64_t, + x0 = x1 + svcntp_b16 (svptrue_b16 (), p1)); + +/* +** dec_b16_32_general_x0: +** cntp x([0-9]+), p0, p1\.h +** sub w0, w0, w\1 +** ret +*/ +TEST_PTEST (dec_b16_32_general_x0, uint32_t, + x0 -= svcntp_b16 (p0, p1)); + +/* +** dec_b16_32_general_x1: +** cntp x([0-9]+), p0, p1\.h +** sub w0, w1, w\1 +** ret +*/ +TEST_PTEST (dec_b16_32_general_x1, uint32_t, + x0 = x1 - svcntp_b16 (p0, p1)); + +/* +** dec_b16_32_ptrue_x0: +** decp x0, p1\.h +** ret +*/ +TEST_PTEST (dec_b16_32_ptrue_x0, uint32_t, + x0 -= svcntp_b16 (svptrue_b16 (), p1)); + +/* +** dec_b16_32_ptrue_x1: +** mov w0, w1 +** decp x0, p1\.h +** ret +*/ +TEST_PTEST (dec_b16_32_ptrue_x1, uint32_t, + x0 = x1 - svcntp_b16 (svptrue_b16 (), p1)); + +/* +** dec_b16_64_general_x0: +** cntp (x[0-9]+), p0, p1\.h +** sub x0, x0, \1 +** ret +*/ +TEST_PTEST (dec_b16_64_general_x0, uint64_t, + x0 -= svcntp_b16 (p0, p1)); + +/* +** dec_b16_64_general_x1: +** cntp (x[0-9]+), p0, p1\.h +** sub x0, x1, \1 +** ret +*/ +TEST_PTEST (dec_b16_64_general_x1, uint64_t, + x0 = x1 - svcntp_b16 (p0, p1)); + +/* +** dec_b16_64_ptrue_x0: +** decp x0, p1\.h +** ret +*/ +TEST_PTEST (dec_b16_64_ptrue_x0, uint64_t, + x0 -= svcntp_b16 (svptrue_b16 (), p1)); + +/* +** dec_b16_64_ptrue_x1: +** mov x0, x1 +** decp x0, p1\.h +** ret +*/ +TEST_PTEST (dec_b16_64_ptrue_x1, uint64_t, + x0 = x1 - svcntp_b16 (svptrue_b16 (), p1)); + +/* +** inc_b16_u16_general_z0: +** cntp x([0-9]+), p0, p1\.h +** mov (z[0-9]+\.h), w\1 +** add z0\.h, (z0\.h, \2|\2, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (inc_b16_u16_general_z0, svuint16_t, + z0 = svadd_n_u16_x (svptrue_b16 (), z0, svcntp_b16 (p0, p1)), + z0 = svadd_x (svptrue_b16 (), z0, svcntp_b16 (p0, p1))); + +/* +** inc_b16_u16_general_z1: +** cntp x([0-9]+), p0, p1\.h +** mov (z[0-9]+\.h), w\1 +** add z0\.h, (z1\.h, \2|\2, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (inc_b16_u16_general_z1, svuint16_t, + z0 = svadd_n_u16_x (svptrue_b16 (), z1, svcntp_b16 (p0, p1)), + z0 = svadd_x (svptrue_b16 (), z1, svcntp_b16 (p0, p1))); + +/* +** inc_b16_u16_ptrue_z0: +** incp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b16_u16_ptrue_z0, svuint16_t, + z0 = svadd_n_u16_x (svptrue_b16 (), z0, svcntp_b16 (svptrue_b16 (), p0)), + z0 = svadd_x (svptrue_b16 (), z0, svcntp_b16 (svptrue_b16 (), p0))); + +/* +** inc_b16_u16_ptrue_z1: +** movprfx z0, z1 +** incp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b16_u16_ptrue_z1, svuint16_t, + z0 = svadd_n_u16_x (svptrue_b16 (), z1, svcntp_b16 (svptrue_b16 (), p0)), + z0 = svadd_x (svptrue_b16 (), z1, svcntp_b16 (svptrue_b16 (), p0))); + +/* +** dec_b16_u16_general_z0: +** cntp x([0-9]+), p0, p1\.h +** mov (z[0-9]+\.h), w\1 +** sub z0\.h, z0\.h, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b16_u16_general_z0, svuint16_t, + z0 = svsub_n_u16_x (svptrue_b16 (), z0, svcntp_b16 (p0, p1)), + z0 = svsub_x (svptrue_b16 (), z0, svcntp_b16 (p0, p1))); + +/* +** dec_b16_u16_general_z1: +** cntp x([0-9]+), p0, p1\.h +** mov (z[0-9]+\.h), w\1 +** sub z0\.h, z1\.h, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b16_u16_general_z1, svuint16_t, + z0 = svsub_n_u16_x (svptrue_b16 (), z1, svcntp_b16 (p0, p1)), + z0 = svsub_x (svptrue_b16 (), z1, svcntp_b16 (p0, p1))); + +/* +** dec_b16_u16_ptrue_z0: +** decp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b16_u16_ptrue_z0, svuint16_t, + z0 = svsub_n_u16_x (svptrue_b16 (), z0, svcntp_b16 (svptrue_b16 (), p0)), + z0 = svsub_x (svptrue_b16 (), z0, svcntp_b16 (svptrue_b16 (), p0))); + +/* +** dec_b16_u16_ptrue_z1: +** movprfx z0, z1 +** decp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b16_u16_ptrue_z1, svuint16_t, + z0 = svsub_n_u16_x (svptrue_b16 (), z1, svcntp_b16 (svptrue_b16 (), p0)), + z0 = svsub_x (svptrue_b16 (), z1, svcntp_b16 (svptrue_b16 (), p0))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b32.c new file mode 100644 index 00000000000..0da81889528 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b32.c @@ -0,0 +1,243 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** cnt_b32_32: +** cntp x0, p0, p1\.s +** ret +*/ +TEST_PTEST (cnt_b32_32, uint32_t, + x0 = svcntp_b32 (p0, p1)); + +/* +** cnt_b32_64: +** cntp x0, p0, p1\.s +** ret +*/ +TEST_PTEST (cnt_b32_64, uint64_t, + x0 = svcntp_b32 (p0, p1)); + +/* +** inc_b32_32_general_x0: +** cntp x([0-9]+), p0, p1\.s +** add w0, (w0, w\1|w\1, w0) +** ret +*/ +TEST_PTEST (inc_b32_32_general_x0, uint32_t, + x0 += svcntp_b32 (p0, p1)); + +/* +** inc_b32_32_general_x1: +** cntp x([0-9]+), p0, p1\.s +** add w0, (w1, w\1|w\1, w1) +** ret +*/ +TEST_PTEST (inc_b32_32_general_x1, uint32_t, + x0 = x1 + svcntp_b32 (p0, p1)); + +/* +** inc_b32_32_ptrue_x0: +** incp x0, p1\.s +** ret +*/ +TEST_PTEST (inc_b32_32_ptrue_x0, uint32_t, + x0 += svcntp_b32 (svptrue_b32 (), p1)); + +/* +** inc_b32_32_ptrue_x1: +** mov w0, w1 +** incp x0, p1\.s +** ret +*/ +TEST_PTEST (inc_b32_32_ptrue_x1, uint32_t, + x0 = x1 + svcntp_b32 (svptrue_b32 (), p1)); + +/* +** inc_b32_64_general_x0: +** cntp (x[0-9]+), p0, p1\.s +** add x0, (x0, \1|\1, x0) +** ret +*/ +TEST_PTEST (inc_b32_64_general_x0, uint64_t, + x0 += svcntp_b32 (p0, p1)); + +/* +** inc_b32_64_general_x1: +** cntp (x[0-9]+), p0, p1\.s +** add x0, (x1, \1|\1, x1) +** ret +*/ +TEST_PTEST (inc_b32_64_general_x1, uint64_t, + x0 = x1 + svcntp_b32 (p0, p1)); + +/* +** inc_b32_64_ptrue_x0: +** incp x0, p1\.s +** ret +*/ +TEST_PTEST (inc_b32_64_ptrue_x0, uint64_t, + x0 += svcntp_b32 (svptrue_b32 (), p1)); + +/* +** inc_b32_64_ptrue_x1: +** mov x0, x1 +** incp x0, p1\.s +** ret +*/ +TEST_PTEST (inc_b32_64_ptrue_x1, uint64_t, + x0 = x1 + svcntp_b32 (svptrue_b32 (), p1)); + +/* +** dec_b32_32_general_x0: +** cntp x([0-9]+), p0, p1\.s +** sub w0, w0, w\1 +** ret +*/ +TEST_PTEST (dec_b32_32_general_x0, uint32_t, + x0 -= svcntp_b32 (p0, p1)); + +/* +** dec_b32_32_general_x1: +** cntp x([0-9]+), p0, p1\.s +** sub w0, w1, w\1 +** ret +*/ +TEST_PTEST (dec_b32_32_general_x1, uint32_t, + x0 = x1 - svcntp_b32 (p0, p1)); + +/* +** dec_b32_32_ptrue_x0: +** decp x0, p1\.s +** ret +*/ +TEST_PTEST (dec_b32_32_ptrue_x0, uint32_t, + x0 -= svcntp_b32 (svptrue_b32 (), p1)); + +/* +** dec_b32_32_ptrue_x1: +** mov w0, w1 +** decp x0, p1\.s +** ret +*/ +TEST_PTEST (dec_b32_32_ptrue_x1, uint32_t, + x0 = x1 - svcntp_b32 (svptrue_b32 (), p1)); + +/* +** dec_b32_64_general_x0: +** cntp (x[0-9]+), p0, p1\.s +** sub x0, x0, \1 +** ret +*/ +TEST_PTEST (dec_b32_64_general_x0, uint64_t, + x0 -= svcntp_b32 (p0, p1)); + +/* +** dec_b32_64_general_x1: +** cntp (x[0-9]+), p0, p1\.s +** sub x0, x1, \1 +** ret +*/ +TEST_PTEST (dec_b32_64_general_x1, uint64_t, + x0 = x1 - svcntp_b32 (p0, p1)); + +/* +** dec_b32_64_ptrue_x0: +** decp x0, p1\.s +** ret +*/ +TEST_PTEST (dec_b32_64_ptrue_x0, uint64_t, + x0 -= svcntp_b32 (svptrue_b32 (), p1)); + +/* +** dec_b32_64_ptrue_x1: +** mov x0, x1 +** decp x0, p1\.s +** ret +*/ +TEST_PTEST (dec_b32_64_ptrue_x1, uint64_t, + x0 = x1 - svcntp_b32 (svptrue_b32 (), p1)); + +/* +** inc_b32_s32_general_z0: +** cntp x([0-9]+), p0, p1\.s +** mov (z[0-9]+\.s), w\1 +** add z0\.s, (z0\.s, \2|\2, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (inc_b32_s32_general_z0, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z0, svcntp_b32 (p0, p1)), + z0 = svadd_x (svptrue_b32 (), z0, svcntp_b32 (p0, p1))); + +/* +** inc_b32_s32_general_z1: +** cntp x([0-9]+), p0, p1\.s +** mov (z[0-9]+\.s), w\1 +** add z0\.s, (z1\.s, \2|\2, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (inc_b32_s32_general_z1, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z1, svcntp_b32 (p0, p1)), + z0 = svadd_x (svptrue_b32 (), z1, svcntp_b32 (p0, p1))); + +/* +** inc_b32_s32_ptrue_z0: +** incp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b32_s32_ptrue_z0, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z0, svcntp_b32 (svptrue_b32 (), p0)), + z0 = svadd_x (svptrue_b32 (), z0, svcntp_b32 (svptrue_b32 (), p0))); + +/* +** inc_b32_s32_ptrue_z1: +** movprfx z0, z1 +** incp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b32_s32_ptrue_z1, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z1, svcntp_b32 (svptrue_b32 (), p0)), + z0 = svadd_x (svptrue_b32 (), z1, svcntp_b32 (svptrue_b32 (), p0))); + +/* +** dec_b32_s32_general_z0: +** cntp x([0-9]+), p0, p1\.s +** mov (z[0-9]+\.s), w\1 +** sub z0\.s, z0\.s, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b32_s32_general_z0, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z0, svcntp_b32 (p0, p1)), + z0 = svsub_x (svptrue_b32 (), z0, svcntp_b32 (p0, p1))); + +/* +** dec_b32_s32_general_z1: +** cntp x([0-9]+), p0, p1\.s +** mov (z[0-9]+\.s), w\1 +** sub z0\.s, z1\.s, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b32_s32_general_z1, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z1, svcntp_b32 (p0, p1)), + z0 = svsub_x (svptrue_b32 (), z1, svcntp_b32 (p0, p1))); + +/* +** dec_b32_s32_ptrue_z0: +** decp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b32_s32_ptrue_z0, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z0, svcntp_b32 (svptrue_b32 (), p0)), + z0 = svsub_x (svptrue_b32 (), z0, svcntp_b32 (svptrue_b32 (), p0))); + +/* +** dec_b32_s32_ptrue_z1: +** movprfx z0, z1 +** decp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b32_s32_ptrue_z1, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z1, svcntp_b32 (svptrue_b32 (), p0)), + z0 = svsub_x (svptrue_b32 (), z1, svcntp_b32 (svptrue_b32 (), p0))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b64.c new file mode 100644 index 00000000000..6ddbaef5af1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b64.c @@ -0,0 +1,243 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** cnt_b64_32: +** cntp x0, p0, p1\.d +** ret +*/ +TEST_PTEST (cnt_b64_32, uint32_t, + x0 = svcntp_b64 (p0, p1)); + +/* +** cnt_b64_64: +** cntp x0, p0, p1\.d +** ret +*/ +TEST_PTEST (cnt_b64_64, uint64_t, + x0 = svcntp_b64 (p0, p1)); + +/* +** inc_b64_32_general_x0: +** cntp x([0-9]+), p0, p1\.d +** add w0, (w0, w\1|w\1, w0) +** ret +*/ +TEST_PTEST (inc_b64_32_general_x0, uint32_t, + x0 += svcntp_b64 (p0, p1)); + +/* +** inc_b64_32_general_x1: +** cntp x([0-9]+), p0, p1\.d +** add w0, (w1, w\1|w\1, w1) +** ret +*/ +TEST_PTEST (inc_b64_32_general_x1, uint32_t, + x0 = x1 + svcntp_b64 (p0, p1)); + +/* +** inc_b64_32_ptrue_x0: +** incp x0, p1\.d +** ret +*/ +TEST_PTEST (inc_b64_32_ptrue_x0, uint32_t, + x0 += svcntp_b64 (svptrue_b64 (), p1)); + +/* +** inc_b64_32_ptrue_x1: +** mov w0, w1 +** incp x0, p1\.d +** ret +*/ +TEST_PTEST (inc_b64_32_ptrue_x1, uint32_t, + x0 = x1 + svcntp_b64 (svptrue_b64 (), p1)); + +/* +** inc_b64_64_general_x0: +** cntp (x[0-9]+), p0, p1\.d +** add x0, (x0, \1|\1, x0) +** ret +*/ +TEST_PTEST (inc_b64_64_general_x0, uint64_t, + x0 += svcntp_b64 (p0, p1)); + +/* +** inc_b64_64_general_x1: +** cntp (x[0-9]+), p0, p1\.d +** add x0, (x1, \1|\1, x1) +** ret +*/ +TEST_PTEST (inc_b64_64_general_x1, uint64_t, + x0 = x1 + svcntp_b64 (p0, p1)); + +/* +** inc_b64_64_ptrue_x0: +** incp x0, p1\.d +** ret +*/ +TEST_PTEST (inc_b64_64_ptrue_x0, uint64_t, + x0 += svcntp_b64 (svptrue_b64 (), p1)); + +/* +** inc_b64_64_ptrue_x1: +** mov x0, x1 +** incp x0, p1\.d +** ret +*/ +TEST_PTEST (inc_b64_64_ptrue_x1, uint64_t, + x0 = x1 + svcntp_b64 (svptrue_b64 (), p1)); + +/* +** dec_b64_32_general_x0: +** cntp x([0-9]+), p0, p1\.d +** sub w0, w0, w\1 +** ret +*/ +TEST_PTEST (dec_b64_32_general_x0, uint32_t, + x0 -= svcntp_b64 (p0, p1)); + +/* +** dec_b64_32_general_x1: +** cntp x([0-9]+), p0, p1\.d +** sub w0, w1, w\1 +** ret +*/ +TEST_PTEST (dec_b64_32_general_x1, uint32_t, + x0 = x1 - svcntp_b64 (p0, p1)); + +/* +** dec_b64_32_ptrue_x0: +** decp x0, p1\.d +** ret +*/ +TEST_PTEST (dec_b64_32_ptrue_x0, uint32_t, + x0 -= svcntp_b64 (svptrue_b64 (), p1)); + +/* +** dec_b64_32_ptrue_x1: +** mov w0, w1 +** decp x0, p1\.d +** ret +*/ +TEST_PTEST (dec_b64_32_ptrue_x1, uint32_t, + x0 = x1 - svcntp_b64 (svptrue_b64 (), p1)); + +/* +** dec_b64_64_general_x0: +** cntp (x[0-9]+), p0, p1\.d +** sub x0, x0, \1 +** ret +*/ +TEST_PTEST (dec_b64_64_general_x0, uint64_t, + x0 -= svcntp_b64 (p0, p1)); + +/* +** dec_b64_64_general_x1: +** cntp (x[0-9]+), p0, p1\.d +** sub x0, x1, \1 +** ret +*/ +TEST_PTEST (dec_b64_64_general_x1, uint64_t, + x0 = x1 - svcntp_b64 (p0, p1)); + +/* +** dec_b64_64_ptrue_x0: +** decp x0, p1\.d +** ret +*/ +TEST_PTEST (dec_b64_64_ptrue_x0, uint64_t, + x0 -= svcntp_b64 (svptrue_b64 (), p1)); + +/* +** dec_b64_64_ptrue_x1: +** mov x0, x1 +** decp x0, p1\.d +** ret +*/ +TEST_PTEST (dec_b64_64_ptrue_x1, uint64_t, + x0 = x1 - svcntp_b64 (svptrue_b64 (), p1)); + +/* +** inc_b64_u64_general_z0: +** cntp (x[0-9]+), p0, p1\.d +** mov (z[0-9]+\.d), \1 +** add z0\.d, (z0\.d, \2|\2, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (inc_b64_u64_general_z0, svuint64_t, + z0 = svadd_n_u64_x (svptrue_b64 (), z0, svcntp_b64 (p0, p1)), + z0 = svadd_x (svptrue_b64 (), z0, svcntp_b64 (p0, p1))); + +/* +** inc_b64_u64_general_z1: +** cntp (x[0-9]+), p0, p1\.d +** mov (z[0-9]+\.d), \1 +** add z0\.d, (z1\.d, \2|\2, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (inc_b64_u64_general_z1, svuint64_t, + z0 = svadd_n_u64_x (svptrue_b64 (), z1, svcntp_b64 (p0, p1)), + z0 = svadd_x (svptrue_b64 (), z1, svcntp_b64 (p0, p1))); + +/* +** inc_b64_u64_ptrue_z0: +** incp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b64_u64_ptrue_z0, svuint64_t, + z0 = svadd_n_u64_x (svptrue_b64 (), z0, svcntp_b64 (svptrue_b64 (), p0)), + z0 = svadd_x (svptrue_b64 (), z0, svcntp_b64 (svptrue_b64 (), p0))); + +/* +** inc_b64_u64_ptrue_z1: +** movprfx z0, z1 +** incp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (inc_b64_u64_ptrue_z1, svuint64_t, + z0 = svadd_n_u64_x (svptrue_b64 (), z1, svcntp_b64 (svptrue_b64 (), p0)), + z0 = svadd_x (svptrue_b64 (), z1, svcntp_b64 (svptrue_b64 (), p0))); + +/* +** dec_b64_u64_general_z0: +** cntp (x[0-9]+), p0, p1\.d +** mov (z[0-9]+\.d), \1 +** sub z0\.d, z0\.d, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b64_u64_general_z0, svuint64_t, + z0 = svsub_n_u64_x (svptrue_b64 (), z0, svcntp_b64 (p0, p1)), + z0 = svsub_x (svptrue_b64 (), z0, svcntp_b64 (p0, p1))); + +/* +** dec_b64_u64_general_z1: +** cntp (x[0-9]+), p0, p1\.d +** mov (z[0-9]+\.d), \1 +** sub z0\.d, z1\.d, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b64_u64_general_z1, svuint64_t, + z0 = svsub_n_u64_x (svptrue_b64 (), z1, svcntp_b64 (p0, p1)), + z0 = svsub_x (svptrue_b64 (), z1, svcntp_b64 (p0, p1))); + +/* +** dec_b64_u64_ptrue_z0: +** decp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b64_u64_ptrue_z0, svuint64_t, + z0 = svsub_n_u64_x (svptrue_b64 (), z0, svcntp_b64 (svptrue_b64 (), p0)), + z0 = svsub_x (svptrue_b64 (), z0, svcntp_b64 (svptrue_b64 (), p0))); + +/* +** dec_b64_u64_ptrue_z1: +** movprfx z0, z1 +** decp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (dec_b64_u64_ptrue_z1, svuint64_t, + z0 = svsub_n_u64_x (svptrue_b64 (), z1, svcntp_b64 (svptrue_b64 (), p0)), + z0 = svsub_x (svptrue_b64 (), z1, svcntp_b64 (svptrue_b64 (), p0))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b8.c new file mode 100644 index 00000000000..e02c02cd695 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntp_b8.c @@ -0,0 +1,253 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** cnt_b8_32: +** cntp x0, p0, p1\.b +** ret +*/ +TEST_PTEST (cnt_b8_32, uint32_t, + x0 = svcntp_b8 (p0, p1)); + +/* +** cnt_b8_64: +** cntp x0, p0, p1\.b +** ret +*/ +TEST_PTEST (cnt_b8_64, uint64_t, + x0 = svcntp_b8 (p0, p1)); + +/* +** inc_b8_32_general_x0: +** cntp x([0-9]+), p0, p1\.b +** add w0, (w0, w\1|w\1, w0) +** ret +*/ +TEST_PTEST (inc_b8_32_general_x0, uint32_t, + x0 += svcntp_b8 (p0, p1)); + +/* +** inc_b8_32_general_x1: +** cntp x([0-9]+), p0, p1\.b +** add w0, (w1, w\1|w\1, w1) +** ret +*/ +TEST_PTEST (inc_b8_32_general_x1, uint32_t, + x0 = x1 + svcntp_b8 (p0, p1)); + +/* +** inc_b8_32_ptrue_x0: +** incp x0, p1\.b +** ret +*/ +TEST_PTEST (inc_b8_32_ptrue_x0, uint32_t, + x0 += svcntp_b8 (svptrue_b8 (), p1)); + +/* +** inc_b8_32_ptrue_x1: +** mov w0, w1 +** incp x0, p1\.b +** ret +*/ +TEST_PTEST (inc_b8_32_ptrue_x1, uint32_t, + x0 = x1 + svcntp_b8 (svptrue_b8 (), p1)); + +/* +** inc_b8_64_general_x0: +** cntp (x[0-9]+), p0, p1\.b +** add x0, (x0, \1|\1, x0) +** ret +*/ +TEST_PTEST (inc_b8_64_general_x0, uint64_t, + x0 += svcntp_b8 (p0, p1)); + +/* +** inc_b8_64_general_x1: +** cntp (x[0-9]+), p0, p1\.b +** add x0, (x1, \1|\1, x1) +** ret +*/ +TEST_PTEST (inc_b8_64_general_x1, uint64_t, + x0 = x1 + svcntp_b8 (p0, p1)); + +/* +** inc_b8_64_ptrue_x0: +** incp x0, p1\.b +** ret +*/ +TEST_PTEST (inc_b8_64_ptrue_x0, uint64_t, + x0 += svcntp_b8 (svptrue_b8 (), p1)); + +/* +** inc_b8_64_ptrue_x1: +** mov x0, x1 +** incp x0, p1\.b +** ret +*/ +TEST_PTEST (inc_b8_64_ptrue_x1, uint64_t, + x0 = x1 + svcntp_b8 (svptrue_b8 (), p1)); + +/* +** dec_b8_32_general_x0: +** cntp x([0-9]+), p0, p1\.b +** sub w0, w0, w\1 +** ret +*/ +TEST_PTEST (dec_b8_32_general_x0, uint32_t, + x0 -= svcntp_b8 (p0, p1)); + +/* +** dec_b8_32_general_x1: +** cntp x([0-9]+), p0, p1\.b +** sub w0, w1, w\1 +** ret +*/ +TEST_PTEST (dec_b8_32_general_x1, uint32_t, + x0 = x1 - svcntp_b8 (p0, p1)); + +/* +** dec_b8_32_ptrue_x0: +** decp x0, p1\.b +** ret +*/ +TEST_PTEST (dec_b8_32_ptrue_x0, uint32_t, + x0 -= svcntp_b8 (svptrue_b8 (), p1)); + +/* +** dec_b8_32_ptrue_x1: +** mov w0, w1 +** decp x0, p1\.b +** ret +*/ +TEST_PTEST (dec_b8_32_ptrue_x1, uint32_t, + x0 = x1 - svcntp_b8 (svptrue_b8 (), p1)); + +/* +** dec_b8_64_general_x0: +** cntp (x[0-9]+), p0, p1\.b +** sub x0, x0, \1 +** ret +*/ +TEST_PTEST (dec_b8_64_general_x0, uint64_t, + x0 -= svcntp_b8 (p0, p1)); + +/* +** dec_b8_64_general_x1: +** cntp (x[0-9]+), p0, p1\.b +** sub x0, x1, \1 +** ret +*/ +TEST_PTEST (dec_b8_64_general_x1, uint64_t, + x0 = x1 - svcntp_b8 (p0, p1)); + +/* +** dec_b8_64_ptrue_x0: +** decp x0, p1\.b +** ret +*/ +TEST_PTEST (dec_b8_64_ptrue_x0, uint64_t, + x0 -= svcntp_b8 (svptrue_b8 (), p1)); + +/* +** dec_b8_64_ptrue_x1: +** mov x0, x1 +** decp x0, p1\.b +** ret +*/ +TEST_PTEST (dec_b8_64_ptrue_x1, uint64_t, + x0 = x1 - svcntp_b8 (svptrue_b8 (), p1)); + +/* +** inc_b8_s8_general_z0: +** cntp x([0-9]+), p0, p1\.b +** mov (z[0-9]+\.b), w\1 +** add z0\.b, (z0\.b, \2|\2, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (inc_b8_s8_general_z0, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z0, svcntp_b8 (p0, p1)), + z0 = svadd_x (svptrue_b8 (), z0, svcntp_b8 (p0, p1))); + +/* +** inc_b8_s8_general_z1: +** cntp x([0-9]+), p0, p1\.b +** mov (z[0-9]+\.b), w\1 +** add z0\.b, (z1\.b, \2|\2, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (inc_b8_s8_general_z1, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z1, svcntp_b8 (p0, p1)), + z0 = svadd_x (svptrue_b8 (), z1, svcntp_b8 (p0, p1))); + +/* +** inc_b8_s8_ptrue_z0: +** ptrue (p[0-7])\.b, all +** cntp x([0-9]+), \1, p0\.b +** mov (z[0-9]+\.b), w\2 +** add z0\.b, (z0\.b, \3|\3, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (inc_b8_s8_ptrue_z0, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z0, svcntp_b8 (svptrue_b8 (), p0)), + z0 = svadd_x (svptrue_b8 (), z0, svcntp_b8 (svptrue_b8 (), p0))); + +/* +** inc_b8_s8_ptrue_z1: +** ptrue (p[0-7])\.b, all +** cntp x([0-9]+), \1, p0\.b +** mov (z[0-9]+\.b), w\2 +** add z0\.b, (z1\.b, \3|\3, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (inc_b8_s8_ptrue_z1, svint8_t, + z0 = svadd_n_s8_x (svptrue_b8 (), z1, svcntp_b8 (svptrue_b8 (), p0)), + z0 = svadd_x (svptrue_b8 (), z1, svcntp_b8 (svptrue_b8 (), p0))); + +/* +** dec_b8_s8_general_z0: +** cntp x([0-9]+), p0, p1\.b +** mov (z[0-9]+\.b), w\1 +** sub z0\.b, z0\.b, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b8_s8_general_z0, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z0, svcntp_b8 (p0, p1)), + z0 = svsub_x (svptrue_b8 (), z0, svcntp_b8 (p0, p1))); + +/* +** dec_b8_s8_general_z1: +** cntp x([0-9]+), p0, p1\.b +** mov (z[0-9]+\.b), w\1 +** sub z0\.b, z1\.b, \2 +** ret +*/ +TEST_UNIFORM_Z (dec_b8_s8_general_z1, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z1, svcntp_b8 (p0, p1)), + z0 = svsub_x (svptrue_b8 (), z1, svcntp_b8 (p0, p1))); + +/* +** dec_b8_s8_ptrue_z0: +** ptrue (p[0-7])\.b, all +** cntp x([0-9]+), \1, p0\.b +** mov (z[0-9]+\.b), w\2 +** sub z0\.b, z0\.b, \3 +** ret +*/ +TEST_UNIFORM_Z (dec_b8_s8_ptrue_z0, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z0, svcntp_b8 (svptrue_b8 (), p0)), + z0 = svsub_x (svptrue_b8 (), z0, svcntp_b8 (svptrue_b8 (), p0))); + +/* +** dec_b8_s8_ptrue_z1: +** ptrue (p[0-7])\.b, all +** cntp x([0-9]+), \1, p0\.b +** mov (z[0-9]+\.b), w\2 +** sub z0\.b, z1\.b, \3 +** ret +*/ +TEST_UNIFORM_Z (dec_b8_s8_ptrue_z1, svint8_t, + z0 = svsub_n_s8_x (svptrue_b8 (), z1, svcntp_b8 (svptrue_b8 (), p0)), + z0 = svsub_x (svptrue_b8 (), z1, svcntp_b8 (svptrue_b8 (), p0))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw.c new file mode 100644 index 00000000000..e26cc67a467 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw.c @@ -0,0 +1,279 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntw_1: +** cntw x0 +** ret +*/ +PROTO (cntw_1, uint64_t, ()) { return svcntw (); } + +/* +** cntw_2: +** cnth x0 +** ret +*/ +PROTO (cntw_2, uint64_t, ()) { return svcntw () * 2; } + +/* +** cntw_3: +** cntw x0, all, mul #3 +** ret +*/ +PROTO (cntw_3, uint64_t, ()) { return svcntw () * 3; } + +/* +** cntw_4: +** cntb x0 +** ret +*/ +PROTO (cntw_4, uint64_t, ()) { return svcntw () * 4; } + +/* +** cntw_8: +** cntb x0, all, mul #2 +** ret +*/ +PROTO (cntw_8, uint64_t, ()) { return svcntw () * 8; } + +/* +** cntw_15: +** cntw x0, all, mul #15 +** ret +*/ +PROTO (cntw_15, uint64_t, ()) { return svcntw () * 15; } + +/* +** cntw_16: +** cntb x0, all, mul #4 +** ret +*/ +PROTO (cntw_16, uint64_t, ()) { return svcntw () * 16; } + +/* Other sequences would be OK. */ +/* +** cntw_17: +** cntb x0, all, mul #4 +** incw x0 +** ret +*/ +PROTO (cntw_17, uint64_t, ()) { return svcntw () * 17; } + +/* +** cntw_32: +** cntb x0, all, mul #8 +** ret +*/ +PROTO (cntw_32, uint64_t, ()) { return svcntw () * 32; } + +/* +** cntw_64: +** cntb x0, all, mul #16 +** ret +*/ +PROTO (cntw_64, uint64_t, ()) { return svcntw () * 64; } + +/* +** cntw_128: +** cntd (x[0-9]+) +** lsl x0, \1, 8 +** ret +*/ +PROTO (cntw_128, uint64_t, ()) { return svcntw () * 128; } + +/* +** cntw_m1: +** cntw (x[0-9]+) +** neg x0, \1 +** ret +*/ +PROTO (cntw_m1, uint64_t, ()) { return -svcntw (); } + +/* +** cntw_m13: +** cntw (x[0-9]+), all, mul #13 +** neg x0, \1 +** ret +*/ +PROTO (cntw_m13, uint64_t, ()) { return -svcntw () * 13; } + +/* +** cntw_m15: +** cntw (x[0-9]+), all, mul #15 +** neg x0, \1 +** ret +*/ +PROTO (cntw_m15, uint64_t, ()) { return -svcntw () * 15; } + +/* +** cntw_m16: +** cntb (x[0-9]+), all, mul #4 +** neg x0, \1 +** ret +*/ +PROTO (cntw_m16, uint64_t, ()) { return -svcntw () * 16; } + +/* Other sequences would be OK. */ +/* +** cntw_m17: +** cntb x0, all, mul #4 +** incw x0 +** neg x0, x0 +** ret +*/ +PROTO (cntw_m17, uint64_t, ()) { return -svcntw () * 17; } + +/* +** incw_1: +** incw x0 +** ret +*/ +PROTO (incw_1, uint64_t, (uint64_t x0)) { return x0 + svcntw (); } + +/* +** incw_2: +** inch x0 +** ret +*/ +PROTO (incw_2, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 2; } + +/* +** incw_3: +** incw x0, all, mul #3 +** ret +*/ +PROTO (incw_3, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 3; } + +/* +** incw_4: +** incb x0 +** ret +*/ +PROTO (incw_4, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 4; } + +/* +** incw_7: +** incw x0, all, mul #7 +** ret +*/ +PROTO (incw_7, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 7; } + +/* +** incw_8: +** incb x0, all, mul #2 +** ret +*/ +PROTO (incw_8, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 8; } + +/* +** incw_9: +** incw x0, all, mul #9 +** ret +*/ +PROTO (incw_9, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 9; } + +/* +** incw_15: +** incw x0, all, mul #15 +** ret +*/ +PROTO (incw_15, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 15; } + +/* +** incw_16: +** incb x0, all, mul #4 +** ret +*/ +PROTO (incw_16, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 16; } + +/* +** incw_18: +** inch x0, all, mul #9 +** ret +*/ +PROTO (incw_18, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 18; } + +/* +** incw_30: +** inch x0, all, mul #15 +** ret +*/ +PROTO (incw_30, uint64_t, (uint64_t x0)) { return x0 + svcntw () * 30; } + +/* +** decw_1: +** decw x0 +** ret +*/ +PROTO (decw_1, uint64_t, (uint64_t x0)) { return x0 - svcntw (); } + +/* +** decw_2: +** dech x0 +** ret +*/ +PROTO (decw_2, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 2; } + +/* +** decw_3: +** decw x0, all, mul #3 +** ret +*/ +PROTO (decw_3, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 3; } + +/* +** decw_4: +** decb x0 +** ret +*/ +PROTO (decw_4, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 4; } + +/* +** decw_7: +** decw x0, all, mul #7 +** ret +*/ +PROTO (decw_7, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 7; } + +/* +** decw_8: +** decb x0, all, mul #2 +** ret +*/ +PROTO (decw_8, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 8; } + +/* +** decw_9: +** decw x0, all, mul #9 +** ret +*/ +PROTO (decw_9, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 9; } + +/* +** decw_15: +** decw x0, all, mul #15 +** ret +*/ +PROTO (decw_15, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 15; } + +/* +** decw_16: +** decb x0, all, mul #4 +** ret +*/ +PROTO (decw_16, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 16; } + +/* +** decw_18: +** dech x0, all, mul #9 +** ret +*/ +PROTO (decw_18, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 18; } + +/* +** decw_30: +** dech x0, all, mul #15 +** ret +*/ +PROTO (decw_30, uint64_t, (uint64_t x0)) { return x0 - svcntw () * 30; } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw_pat.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw_pat.c new file mode 100644 index 00000000000..ff6b7d882b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cntw_pat.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cntw_pow2: +** cntw x0, pow2 +** ret +*/ +PROTO (cntw_pow2, uint64_t, ()) { return svcntw_pat (SV_POW2); } + +/* +** cntw_vl1: +** mov x0, #?1 +** ret +*/ +PROTO (cntw_vl1, uint64_t, ()) { return svcntw_pat (SV_VL1); } + +/* +** cntw_vl2: +** mov x0, #?2 +** ret +*/ +PROTO (cntw_vl2, uint64_t, ()) { return svcntw_pat (SV_VL2); } + +/* +** cntw_vl3: +** mov x0, #?3 +** ret +*/ +PROTO (cntw_vl3, uint64_t, ()) { return svcntw_pat (SV_VL3); } + +/* +** cntw_vl4: +** mov x0, #?4 +** ret +*/ +PROTO (cntw_vl4, uint64_t, ()) { return svcntw_pat (SV_VL4); } + +/* +** cntw_vl5: +** cntw x0, vl5 +** ret +*/ +PROTO (cntw_vl5, uint64_t, ()) { return svcntw_pat (SV_VL5); } + +/* +** cntw_vl6: +** cntw x0, vl6 +** ret +*/ +PROTO (cntw_vl6, uint64_t, ()) { return svcntw_pat (SV_VL6); } + +/* +** cntw_vl7: +** cntw x0, vl7 +** ret +*/ +PROTO (cntw_vl7, uint64_t, ()) { return svcntw_pat (SV_VL7); } + +/* +** cntw_vl8: +** cntw x0, vl8 +** ret +*/ +PROTO (cntw_vl8, uint64_t, ()) { return svcntw_pat (SV_VL8); } + +/* +** cntw_vl16: +** cntw x0, vl16 +** ret +*/ +PROTO (cntw_vl16, uint64_t, ()) { return svcntw_pat (SV_VL16); } + +/* +** cntw_vl32: +** cntw x0, vl32 +** ret +*/ +PROTO (cntw_vl32, uint64_t, ()) { return svcntw_pat (SV_VL32); } + +/* +** cntw_vl64: +** cntw x0, vl64 +** ret +*/ +PROTO (cntw_vl64, uint64_t, ()) { return svcntw_pat (SV_VL64); } + +/* +** cntw_vl128: +** cntw x0, vl128 +** ret +*/ +PROTO (cntw_vl128, uint64_t, ()) { return svcntw_pat (SV_VL128); } + +/* +** cntw_vl256: +** cntw x0, vl256 +** ret +*/ +PROTO (cntw_vl256, uint64_t, ()) { return svcntw_pat (SV_VL256); } + +/* +** cntw_mul3: +** cntw x0, mul3 +** ret +*/ +PROTO (cntw_mul3, uint64_t, ()) { return svcntw_pat (SV_MUL3); } + +/* +** cntw_mul4: +** cntw x0, mul4 +** ret +*/ +PROTO (cntw_mul4, uint64_t, ()) { return svcntw_pat (SV_MUL4); } + +/* +** cntw_all: +** cntw x0 +** ret +*/ +PROTO (cntw_all, uint64_t, ()) { return svcntw_pat (SV_ALL); } + +/* +** incw_32_pow2: +** incw x0, pow2 +** ret +*/ +PROTO (incw_32_pow2, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_POW2); } + +/* +** incw_32_vl1: +** add w0, w0, #?1 +** ret +*/ +PROTO (incw_32_vl1, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL1); } + +/* +** incw_32_vl2: +** add w0, w0, #?2 +** ret +*/ +PROTO (incw_32_vl2, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL2); } + +/* +** incw_32_vl3: +** add w0, w0, #?3 +** ret +*/ +PROTO (incw_32_vl3, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL3); } + +/* +** incw_32_vl4: +** add w0, w0, #?4 +** ret +*/ +PROTO (incw_32_vl4, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL4); } + +/* +** incw_32_vl5: +** incw x0, vl5 +** ret +*/ +PROTO (incw_32_vl5, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL5); } + +/* +** incw_32_vl6: +** incw x0, vl6 +** ret +*/ +PROTO (incw_32_vl6, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL6); } + +/* +** incw_32_vl7: +** incw x0, vl7 +** ret +*/ +PROTO (incw_32_vl7, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL7); } + +/* +** incw_32_vl8: +** incw x0, vl8 +** ret +*/ +PROTO (incw_32_vl8, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL8); } + +/* +** incw_32_vl16: +** incw x0, vl16 +** ret +*/ +PROTO (incw_32_vl16, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL16); } + +/* +** incw_32_vl32: +** incw x0, vl32 +** ret +*/ +PROTO (incw_32_vl32, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL32); } + +/* +** incw_32_vl64: +** incw x0, vl64 +** ret +*/ +PROTO (incw_32_vl64, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL64); } + +/* +** incw_32_vl128: +** incw x0, vl128 +** ret +*/ +PROTO (incw_32_vl128, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL128); } + +/* +** incw_32_vl256: +** incw x0, vl256 +** ret +*/ +PROTO (incw_32_vl256, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_VL256); } + +/* +** incw_32_mul3: +** incw x0, mul3 +** ret +*/ +PROTO (incw_32_mul3, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_MUL3); } + +/* +** incw_32_mul4: +** incw x0, mul4 +** ret +*/ +PROTO (incw_32_mul4, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_MUL4); } + +/* +** incw_32_all: +** incw x0 +** ret +*/ +PROTO (incw_32_all, uint32_t, (uint32_t w0)) { return w0 + svcntw_pat (SV_ALL); } + +/* +** incw_64_pow2: +** incw x0, pow2 +** ret +*/ +PROTO (incw_64_pow2, uint64_t, (uint64_t x0)) { return x0 + svcntw_pat (SV_POW2); } + +/* +** incw_64_all: +** incw x0 +** ret +*/ +PROTO (incw_64_all, uint64_t, (uint64_t x0)) { return x0 + svcntw_pat (SV_ALL); } + +/* +** decw_32_pow2: +** decw x0, pow2 +** ret +*/ +PROTO (decw_32_pow2, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_POW2); } + +/* +** decw_32_vl1: +** sub w0, w0, #?1 +** ret +*/ +PROTO (decw_32_vl1, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL1); } + +/* +** decw_32_vl2: +** sub w0, w0, #?2 +** ret +*/ +PROTO (decw_32_vl2, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL2); } + +/* +** decw_32_vl3: +** sub w0, w0, #?3 +** ret +*/ +PROTO (decw_32_vl3, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL3); } + +/* +** decw_32_vl4: +** sub w0, w0, #?4 +** ret +*/ +PROTO (decw_32_vl4, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL4); } + +/* +** decw_32_vl5: +** decw x0, vl5 +** ret +*/ +PROTO (decw_32_vl5, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL5); } + +/* +** decw_32_vl6: +** decw x0, vl6 +** ret +*/ +PROTO (decw_32_vl6, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL6); } + +/* +** decw_32_vl7: +** decw x0, vl7 +** ret +*/ +PROTO (decw_32_vl7, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL7); } + +/* +** decw_32_vl8: +** decw x0, vl8 +** ret +*/ +PROTO (decw_32_vl8, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL8); } + +/* +** decw_32_vl16: +** decw x0, vl16 +** ret +*/ +PROTO (decw_32_vl16, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL16); } + +/* +** decw_32_vl32: +** decw x0, vl32 +** ret +*/ +PROTO (decw_32_vl32, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL32); } + +/* +** decw_32_vl64: +** decw x0, vl64 +** ret +*/ +PROTO (decw_32_vl64, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL64); } + +/* +** decw_32_vl128: +** decw x0, vl128 +** ret +*/ +PROTO (decw_32_vl128, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL128); } + +/* +** decw_32_vl256: +** decw x0, vl256 +** ret +*/ +PROTO (decw_32_vl256, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_VL256); } + +/* +** decw_32_mul3: +** decw x0, mul3 +** ret +*/ +PROTO (decw_32_mul3, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_MUL3); } + +/* +** decw_32_mul4: +** decw x0, mul4 +** ret +*/ +PROTO (decw_32_mul4, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_MUL4); } + +/* +** decw_32_all: +** decw x0 +** ret +*/ +PROTO (decw_32_all, uint32_t, (uint32_t w0)) { return w0 - svcntw_pat (SV_ALL); } + +/* +** decw_64_pow2: +** decw x0, pow2 +** ret +*/ +PROTO (decw_64_pow2, uint64_t, (uint64_t x0)) { return x0 - svcntw_pat (SV_POW2); } + +/* +** decw_64_all: +** decw x0 +** ret +*/ +PROTO (decw_64_all, uint64_t, (uint64_t x0)) { return x0 - svcntw_pat (SV_ALL); } + +/* +** incw_s32_pow2_z0: +** incw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (incw_s32_pow2_z0, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z0, svcntw_pat (SV_POW2)), + z0 = svadd_x (svptrue_b32 (), z0, svcntw_pat (SV_POW2))); + +/* +** incw_s32_pow2_z1: +** movprfx z0, z1 +** incw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (incw_s32_pow2_z1, svint32_t, + z0 = svadd_n_s32_x (svptrue_b32 (), z1, svcntw_pat (SV_POW2)), + z0 = svadd_x (svptrue_b32 (), z1, svcntw_pat (SV_POW2))); + +/* +** decw_s32_pow2_z0: +** decw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (decw_s32_pow2_z0, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z0, svcntw_pat (SV_POW2)), + z0 = svsub_x (svptrue_b32 (), z0, svcntw_pat (SV_POW2))); + +/* +** decw_s32_pow2_z1: +** movprfx z0, z1 +** decw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (decw_s32_pow2_z1, svint32_t, + z0 = svsub_n_s32_x (svptrue_b32 (), z1, svcntw_pat (SV_POW2)), + z0 = svsub_x (svptrue_b32 (), z1, svcntw_pat (SV_POW2))); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f32.c new file mode 100644 index 00000000000..2e80d6830ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_f32_tied1: +** compact z0\.s, p0, z0\.s +** ret +*/ +TEST_UNIFORM_Z (compact_f32_tied1, svfloat32_t, + z0 = svcompact_f32 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_f32_untied: +** compact z0\.s, p0, z1\.s +** ret +*/ +TEST_UNIFORM_Z (compact_f32_untied, svfloat32_t, + z0 = svcompact_f32 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f64.c new file mode 100644 index 00000000000..e0bc33efec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_f64_tied1: +** compact z0\.d, p0, z0\.d +** ret +*/ +TEST_UNIFORM_Z (compact_f64_tied1, svfloat64_t, + z0 = svcompact_f64 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_f64_untied: +** compact z0\.d, p0, z1\.d +** ret +*/ +TEST_UNIFORM_Z (compact_f64_untied, svfloat64_t, + z0 = svcompact_f64 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s32.c new file mode 100644 index 00000000000..e4634982bf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_s32_tied1: +** compact z0\.s, p0, z0\.s +** ret +*/ +TEST_UNIFORM_Z (compact_s32_tied1, svint32_t, + z0 = svcompact_s32 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_s32_untied: +** compact z0\.s, p0, z1\.s +** ret +*/ +TEST_UNIFORM_Z (compact_s32_untied, svint32_t, + z0 = svcompact_s32 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s64.c new file mode 100644 index 00000000000..71cb97b8a2a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_s64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_s64_tied1: +** compact z0\.d, p0, z0\.d +** ret +*/ +TEST_UNIFORM_Z (compact_s64_tied1, svint64_t, + z0 = svcompact_s64 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_s64_untied: +** compact z0\.d, p0, z1\.d +** ret +*/ +TEST_UNIFORM_Z (compact_s64_untied, svint64_t, + z0 = svcompact_s64 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u32.c new file mode 100644 index 00000000000..954329a0b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_u32_tied1: +** compact z0\.s, p0, z0\.s +** ret +*/ +TEST_UNIFORM_Z (compact_u32_tied1, svuint32_t, + z0 = svcompact_u32 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_u32_untied: +** compact z0\.s, p0, z1\.s +** ret +*/ +TEST_UNIFORM_Z (compact_u32_untied, svuint32_t, + z0 = svcompact_u32 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u64.c new file mode 100644 index 00000000000..ec664845f4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/compact_u64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** compact_u64_tied1: +** compact z0\.d, p0, z0\.d +** ret +*/ +TEST_UNIFORM_Z (compact_u64_tied1, svuint64_t, + z0 = svcompact_u64 (p0, z0), + z0 = svcompact (p0, z0)) + +/* +** compact_u64_untied: +** compact z0\.d, p0, z1\.d +** ret +*/ +TEST_UNIFORM_Z (compact_u64_untied, svuint64_t, + z0 = svcompact_u64 (p0, z1), + z0 = svcompact (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create2_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create2_1.c new file mode 100644 index 00000000000..b09e6ab1793 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create2_1.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** create2_s8: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** ret +*/ +TEST_CREATE (create2_s8, svint8x2_t, svint8_t, + z0 = svcreate2_s8 (z6, z4), + z0 = svcreate2 (z6, z4)) + +/* +** create2_u8: +** mov z0\.d, z4\.d +** mov z1\.d, z6\.d +** ret +*/ +TEST_CREATE (create2_u8, svuint8x2_t, svuint8_t, + z0 = svcreate2_u8 (z4, z6), + z0 = svcreate2 (z4, z6)) + +/* +** create2_s16: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** ret +*/ +TEST_CREATE (create2_s16, svint16x2_t, svint16_t, + z0 = svcreate2_s16 (z6, z4), + z0 = svcreate2 (z6, z4)) + +/* +** create2_u16: +** mov z0\.d, z6\.d +** mov z1\.d, z5\.d +** ret +*/ +TEST_CREATE (create2_u16, svuint16x2_t, svuint16_t, + z0 = svcreate2_u16 (z6, z5), + z0 = svcreate2 (z6, z5)) + +/* +** create2_f16: +** mov z0\.d, z4\.d +** mov z1\.d, z5\.d +** ret +*/ +TEST_CREATE (create2_f16, svfloat16x2_t, svfloat16_t, + z0 = svcreate2_f16 (z4, z5), + z0 = svcreate2 (z4, z5)) + +/* +** create2_s32: +** mov z0\.d, z6\.d +** mov z1\.d, z7\.d +** ret +*/ +TEST_CREATE (create2_s32, svint32x2_t, svint32_t, + z0 = svcreate2_s32 (z6, z7), + z0 = svcreate2 (z6, z7)) + +/* +** create2_u32: +** mov z0\.d, z7\.d +** mov z1\.d, z5\.d +** ret +*/ +TEST_CREATE (create2_u32, svuint32x2_t, svuint32_t, + z0 = svcreate2_u32 (z7, z5), + z0 = svcreate2 (z7, z5)) + +/* +** create2_f32: +** mov z0\.d, z7\.d +** mov z1\.d, z4\.d +** ret +*/ +TEST_CREATE (create2_f32, svfloat32x2_t, svfloat32_t, + z0 = svcreate2_f32 (z7, z4), + z0 = svcreate2 (z7, z4)) + +/* +** create2_s64: +** mov z0\.d, z5\.d +** mov z1\.d, z7\.d +** ret +*/ +TEST_CREATE (create2_s64, svint64x2_t, svint64_t, + z0 = svcreate2_s64 (z5, z7), + z0 = svcreate2 (z5, z7)) + +/* +** create2_u64: +** mov z0\.d, z7\.d +** mov z1\.d, z6\.d +** ret +*/ +TEST_CREATE (create2_u64, svuint64x2_t, svuint64_t, + z0 = svcreate2_u64 (z7, z6), + z0 = svcreate2 (z7, z6)) + +/* +** create2_f64: +** mov z0\.d, z5\.d +** mov z1\.d, z4\.d +** ret +*/ +TEST_CREATE (create2_f64, svfloat64x2_t, svfloat64_t, + z0 = svcreate2_f64 (z5, z4), + z0 = svcreate2 (z5, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create3_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create3_1.c new file mode 100644 index 00000000000..6b71bf38d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create3_1.c @@ -0,0 +1,124 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** create3_s8: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** mov z2\.d, z7\.d +** ret +*/ +TEST_CREATE (create3_s8, svint8x3_t, svint8_t, + z0 = svcreate3_s8 (z6, z4, z7), + z0 = svcreate3 (z6, z4, z7)) + +/* +** create3_u8: +** mov z0\.d, z4\.d +** mov z1\.d, z6\.d +** mov z2\.d, z5\.d +** ret +*/ +TEST_CREATE (create3_u8, svuint8x3_t, svuint8_t, + z0 = svcreate3_u8 (z4, z6, z5), + z0 = svcreate3 (z4, z6, z5)) + +/* +** create3_s16: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** mov z2\.d, z5\.d +** ret +*/ +TEST_CREATE (create3_s16, svint16x3_t, svint16_t, + z0 = svcreate3_s16 (z6, z4, z5), + z0 = svcreate3 (z6, z4, z5)) + +/* +** create3_u16: +** mov z0\.d, z6\.d +** mov z1\.d, z5\.d +** mov z2\.d, z4\.d +** ret +*/ +TEST_CREATE (create3_u16, svuint16x3_t, svuint16_t, + z0 = svcreate3_u16 (z6, z5, z4), + z0 = svcreate3 (z6, z5, z4)) + +/* +** create3_f16: +** mov z0\.d, z4\.d +** mov z1\.d, z5\.d +** mov z2\.d, z6\.d +** ret +*/ +TEST_CREATE (create3_f16, svfloat16x3_t, svfloat16_t, + z0 = svcreate3_f16 (z4, z5, z6), + z0 = svcreate3 (z4, z5, z6)) + +/* +** create3_s32: +** mov z0\.d, z6\.d +** mov z1\.d, z7\.d +** mov z2\.d, z4\.d +** ret +*/ +TEST_CREATE (create3_s32, svint32x3_t, svint32_t, + z0 = svcreate3_s32 (z6, z7, z4), + z0 = svcreate3 (z6, z7, z4)) + +/* +** create3_u32: +** mov z0\.d, z7\.d +** mov z1\.d, z5\.d +** mov z2\.d, z6\.d +** ret +*/ +TEST_CREATE (create3_u32, svuint32x3_t, svuint32_t, + z0 = svcreate3_u32 (z7, z5, z6), + z0 = svcreate3 (z7, z5, z6)) + +/* +** create3_f32: +** mov z0\.d, z7\.d +** mov z1\.d, z4\.d +** mov z2\.d, z6\.d +** ret +*/ +TEST_CREATE (create3_f32, svfloat32x3_t, svfloat32_t, + z0 = svcreate3_f32 (z7, z4, z6), + z0 = svcreate3 (z7, z4, z6)) + +/* +** create3_s64: +** mov z0\.d, z5\.d +** mov z1\.d, z7\.d +** mov z2\.d, z6\.d +** ret +*/ +TEST_CREATE (create3_s64, svint64x3_t, svint64_t, + z0 = svcreate3_s64 (z5, z7, z6), + z0 = svcreate3 (z5, z7, z6)) + +/* +** create3_u64: +** mov z0\.d, z7\.d +** mov z1\.d, z6\.d +** mov z2\.d, z4\.d +** ret +*/ +TEST_CREATE (create3_u64, svuint64x3_t, svuint64_t, + z0 = svcreate3_u64 (z7, z6, z4), + z0 = svcreate3 (z7, z6, z4)) + +/* +** create3_f64: +** mov z0\.d, z5\.d +** mov z1\.d, z4\.d +** mov z2\.d, z7\.d +** ret +*/ +TEST_CREATE (create3_f64, svfloat64x3_t, svfloat64_t, + z0 = svcreate3_f64 (z5, z4, z7), + z0 = svcreate3 (z5, z4, z7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create4_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create4_1.c new file mode 100644 index 00000000000..03b22d3c1ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/create4_1.c @@ -0,0 +1,135 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** create4_s8: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** mov z2\.d, z7\.d +** mov z3\.d, z5\.d +** ret +*/ +TEST_CREATE (create4_s8, svint8x4_t, svint8_t, + z0 = svcreate4_s8 (z6, z4, z7, z5), + z0 = svcreate4 (z6, z4, z7, z5)) + +/* +** create4_u8: +** mov z0\.d, z4\.d +** mov z1\.d, z6\.d +** mov z2\.d, z5\.d +** mov z3\.d, z7\.d +** ret +*/ +TEST_CREATE (create4_u8, svuint8x4_t, svuint8_t, + z0 = svcreate4_u8 (z4, z6, z5, z7), + z0 = svcreate4 (z4, z6, z5, z7)) + +/* +** create4_s16: +** mov z0\.d, z6\.d +** mov z1\.d, z4\.d +** mov z2\.d, z5\.d +** mov z3\.d, z7\.d +** ret +*/ +TEST_CREATE (create4_s16, svint16x4_t, svint16_t, + z0 = svcreate4_s16 (z6, z4, z5, z7), + z0 = svcreate4 (z6, z4, z5, z7)) + +/* +** create4_u16: +** mov z0\.d, z6\.d +** mov z1\.d, z5\.d +** mov z2\.d, z4\.d +** mov z3\.d, z7\.d +** ret +*/ +TEST_CREATE (create4_u16, svuint16x4_t, svuint16_t, + z0 = svcreate4_u16 (z6, z5, z4, z7), + z0 = svcreate4 (z6, z5, z4, z7)) + +/* +** create4_f16: +** mov z0\.d, z4\.d +** mov z1\.d, z5\.d +** mov z2\.d, z6\.d +** mov z3\.d, z7\.d +** ret +*/ +TEST_CREATE (create4_f16, svfloat16x4_t, svfloat16_t, + z0 = svcreate4_f16 (z4, z5, z6, z7), + z0 = svcreate4 (z4, z5, z6, z7)) + +/* +** create4_s32: +** mov z0\.d, z6\.d +** mov z1\.d, z7\.d +** mov z2\.d, z4\.d +** mov z3\.d, z5\.d +** ret +*/ +TEST_CREATE (create4_s32, svint32x4_t, svint32_t, + z0 = svcreate4_s32 (z6, z7, z4, z5), + z0 = svcreate4 (z6, z7, z4, z5)) + +/* +** create4_u32: +** mov z0\.d, z7\.d +** mov z1\.d, z5\.d +** mov z2\.d, z6\.d +** mov z3\.d, z7\.d +** ret +*/ +TEST_CREATE (create4_u32, svuint32x4_t, svuint32_t, + z0 = svcreate4_u32 (z7, z5, z6, z7), + z0 = svcreate4 (z7, z5, z6, z7)) + +/* +** create4_f32: +** mov z0\.d, z7\.d +** mov z1\.d, z4\.d +** mov z2\.d, z6\.d +** mov z3\.d, z4\.d +** ret +*/ +TEST_CREATE (create4_f32, svfloat32x4_t, svfloat32_t, + z0 = svcreate4_f32 (z7, z4, z6, z4), + z0 = svcreate4 (z7, z4, z6, z4)) + +/* +** create4_s64: +** mov z0\.d, z5\.d +** mov z1\.d, z7\.d +** mov z2\.d, z6\.d +** mov z3\.d, z6\.d +** ret +*/ +TEST_CREATE (create4_s64, svint64x4_t, svint64_t, + z0 = svcreate4_s64 (z5, z7, z6, z6), + z0 = svcreate4 (z5, z7, z6, z6)) + +/* +** create4_u64: +** mov z0\.d, z7\.d +** mov z1\.d, z6\.d +** mov z2\.d, z4\.d +** mov z3\.d, z5\.d +** ret +*/ +TEST_CREATE (create4_u64, svuint64x4_t, svuint64_t, + z0 = svcreate4_u64 (z7, z6, z4, z5), + z0 = svcreate4 (z7, z6, z4, z5)) + +/* +** create4_f64: +** mov z0\.d, z5\.d +** mov z1\.d, z4\.d +** mov z2\.d, z7\.d +** mov z3\.d, z6\.d +** ret +*/ +TEST_CREATE (create4_f64, svfloat64x4_t, svfloat64_t, + z0 = svcreate4_f64 (z5, z4, z7, z6), + z0 = svcreate4 (z5, z4, z7, z6)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c new file mode 100644 index 00000000000..5dcd480464b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c @@ -0,0 +1,731 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_f16_f32_m_tied1: +** fcvt z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_f32_m_tied1, svfloat16_t, svfloat32_t, + z0 = svcvt_f16_f32_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvt z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f32_m_tied2, svfloat16_t, svfloat32_t, + z0_res = svcvt_f16_f32_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_f32_m_untied: +** movprfx z0, z1 +** fcvt z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_f32_m_untied, svfloat16_t, svfloat32_t, + z0 = svcvt_f16_f32_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_f64_m_tied1: +** fcvt z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_f64_m_tied1, svfloat16_t, svfloat64_t, + z0 = svcvt_f16_f64_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvt z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f64_m_tied2, svfloat16_t, svfloat64_t, + z0_res = svcvt_f16_f64_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_f64_m_untied: +** movprfx z0, z1 +** fcvt z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_f64_m_untied, svfloat16_t, svfloat64_t, + z0 = svcvt_f16_f64_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_s16_m_tied1: +** scvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_s16_m_tied1, svfloat16_t, svint16_t, + z0 = svcvt_f16_s16_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** scvtf z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s16_m_tied2, svfloat16_t, svint16_t, + z0_res = svcvt_f16_s16_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_s16_m_untied: +** movprfx z0, z1 +** scvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_s16_m_untied, svfloat16_t, svint16_t, + z0 = svcvt_f16_s16_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_s32_m_tied1: +** scvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_s32_m_tied1, svfloat16_t, svint32_t, + z0 = svcvt_f16_s32_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** scvtf z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s32_m_tied2, svfloat16_t, svint32_t, + z0_res = svcvt_f16_s32_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_s32_m_untied: +** movprfx z0, z1 +** scvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_s32_m_untied, svfloat16_t, svint32_t, + z0 = svcvt_f16_s32_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_s64_m_tied1: +** scvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_s64_m_tied1, svfloat16_t, svint64_t, + z0 = svcvt_f16_s64_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** scvtf z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s64_m_tied2, svfloat16_t, svint64_t, + z0_res = svcvt_f16_s64_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_s64_m_untied: +** movprfx z0, z1 +** scvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_s64_m_untied, svfloat16_t, svint64_t, + z0 = svcvt_f16_s64_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_u16_m_tied1: +** ucvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_u16_m_tied1, svfloat16_t, svuint16_t, + z0 = svcvt_f16_u16_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** ucvtf z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u16_m_tied2, svfloat16_t, svuint16_t, + z0_res = svcvt_f16_u16_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_u16_m_untied: +** movprfx z0, z1 +** ucvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_u16_m_untied, svfloat16_t, svuint16_t, + z0 = svcvt_f16_u16_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_u32_m_tied1: +** ucvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_u32_m_tied1, svfloat16_t, svuint32_t, + z0 = svcvt_f16_u32_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** ucvtf z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u32_m_tied2, svfloat16_t, svuint32_t, + z0_res = svcvt_f16_u32_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_u32_m_untied: +** movprfx z0, z1 +** ucvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_u32_m_untied, svfloat16_t, svuint32_t, + z0 = svcvt_f16_u32_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_u64_m_tied1: +** ucvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_u64_m_tied1, svfloat16_t, svuint64_t, + z0 = svcvt_f16_u64_m (z0, p0, z4), + z0 = svcvt_f16_m (z0, p0, z4)) + +/* +** cvt_f16_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** ucvtf z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u64_m_tied2, svfloat16_t, svuint64_t, + z0_res = svcvt_f16_u64_m (z4, p0, z0), + z0_res = svcvt_f16_m (z4, p0, z0)) + +/* +** cvt_f16_u64_m_untied: +** movprfx z0, z1 +** ucvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_u64_m_untied, svfloat16_t, svuint64_t, + z0 = svcvt_f16_u64_m (z1, p0, z4), + z0 = svcvt_f16_m (z1, p0, z4)) + +/* +** cvt_f16_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvt z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f32_z_tied1, svfloat16_t, svfloat32_t, + z0_res = svcvt_f16_f32_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_f32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvt z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_f32_z_untied, svfloat16_t, svfloat32_t, + z0 = svcvt_f16_f32_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvt z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f64_z_tied1, svfloat16_t, svfloat64_t, + z0_res = svcvt_f16_f64_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvt z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_f64_z_untied, svfloat16_t, svfloat64_t, + z0 = svcvt_f16_f64_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** scvtf z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s16_z_tied1, svfloat16_t, svint16_t, + z0_res = svcvt_f16_s16_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_s16_z_untied: +** movprfx z0\.h, p0/z, z4\.h +** scvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_s16_z_untied, svfloat16_t, svint16_t, + z0 = svcvt_f16_s16_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** scvtf z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s32_z_tied1, svfloat16_t, svint32_t, + z0_res = svcvt_f16_s32_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_s32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** scvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_s32_z_untied, svfloat16_t, svint32_t, + z0 = svcvt_f16_s32_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** scvtf z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s64_z_tied1, svfloat16_t, svint64_t, + z0_res = svcvt_f16_s64_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_s64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** scvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_s64_z_untied, svfloat16_t, svint64_t, + z0 = svcvt_f16_s64_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** ucvtf z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u16_z_tied1, svfloat16_t, svuint16_t, + z0_res = svcvt_f16_u16_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_u16_z_untied: +** movprfx z0\.h, p0/z, z4\.h +** ucvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_u16_z_untied, svfloat16_t, svuint16_t, + z0 = svcvt_f16_u16_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** ucvtf z0\.h, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u32_z_tied1, svfloat16_t, svuint32_t, + z0_res = svcvt_f16_u32_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_u32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** ucvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_u32_z_untied, svfloat16_t, svuint32_t, + z0 = svcvt_f16_u32_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** ucvtf z0\.h, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u64_z_tied1, svfloat16_t, svuint64_t, + z0_res = svcvt_f16_u64_z (p0, z0), + z0_res = svcvt_f16_z (p0, z0)) + +/* +** cvt_f16_u64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** ucvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_u64_z_untied, svfloat16_t, svuint64_t, + z0 = svcvt_f16_u64_z (p0, z4), + z0 = svcvt_f16_z (p0, z4)) + +/* +** cvt_f16_f32_x_tied1: +** fcvt z0\.h, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f32_x_tied1, svfloat16_t, svfloat32_t, + z0_res = svcvt_f16_f32_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_f32_x_untied: +** fcvt z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_f32_x_untied, svfloat16_t, svfloat32_t, + z0 = svcvt_f16_f32_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_f64_x_tied1: +** fcvt z0\.h, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_f64_x_tied1, svfloat16_t, svfloat64_t, + z0_res = svcvt_f16_f64_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_f64_x_untied: +** fcvt z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_f64_x_untied, svfloat16_t, svfloat64_t, + z0 = svcvt_f16_f64_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_s16_x_tied1: +** scvtf z0\.h, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s16_x_tied1, svfloat16_t, svint16_t, + z0_res = svcvt_f16_s16_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_s16_x_untied: +** scvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_s16_x_untied, svfloat16_t, svint16_t, + z0 = svcvt_f16_s16_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_s32_x_tied1: +** scvtf z0\.h, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s32_x_tied1, svfloat16_t, svint32_t, + z0_res = svcvt_f16_s32_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_s32_x_untied: +** scvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_s32_x_untied, svfloat16_t, svint32_t, + z0 = svcvt_f16_s32_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_s64_x_tied1: +** scvtf z0\.h, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_s64_x_tied1, svfloat16_t, svint64_t, + z0_res = svcvt_f16_s64_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_s64_x_untied: +** scvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_s64_x_untied, svfloat16_t, svint64_t, + z0 = svcvt_f16_s64_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_u16_x_tied1: +** ucvtf z0\.h, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u16_x_tied1, svfloat16_t, svuint16_t, + z0_res = svcvt_f16_u16_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_u16_x_untied: +** ucvtf z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f16_u16_x_untied, svfloat16_t, svuint16_t, + z0 = svcvt_f16_u16_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_u32_x_tied1: +** ucvtf z0\.h, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u32_x_tied1, svfloat16_t, svuint32_t, + z0_res = svcvt_f16_u32_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_u32_x_untied: +** ucvtf z0\.h, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f16_u32_x_untied, svfloat16_t, svuint32_t, + z0 = svcvt_f16_u32_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** cvt_f16_u64_x_tied1: +** ucvtf z0\.h, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f16_u64_x_tied1, svfloat16_t, svuint64_t, + z0_res = svcvt_f16_u64_x (p0, z0), + z0_res = svcvt_f16_x (p0, z0)) + +/* +** cvt_f16_u64_x_untied: +** ucvtf z0\.h, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f16_u64_x_untied, svfloat16_t, svuint64_t, + z0 = svcvt_f16_u64_x (p0, z4), + z0 = svcvt_f16_x (p0, z4)) + +/* +** ptrue_cvt_f16_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_f32_x_tied1, svfloat16_t, svfloat32_t, + z0_res = svcvt_f16_f32_x (svptrue_b32 (), z0), + z0_res = svcvt_f16_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f16_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_f32_x_untied, svfloat16_t, svfloat32_t, + z0 = svcvt_f16_f32_x (svptrue_b32 (), z4), + z0 = svcvt_f16_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f16_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_f64_x_tied1, svfloat16_t, svfloat64_t, + z0_res = svcvt_f16_f64_x (svptrue_b64 (), z0), + z0_res = svcvt_f16_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f16_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_f64_x_untied, svfloat16_t, svfloat64_t, + z0 = svcvt_f16_f64_x (svptrue_b64 (), z4), + z0 = svcvt_f16_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f16_s16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_s16_x_tied1, svfloat16_t, svint16_t, + z0_res = svcvt_f16_s16_x (svptrue_b16 (), z0), + z0_res = svcvt_f16_x (svptrue_b16 (), z0)) + +/* +** ptrue_cvt_f16_s16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_s16_x_untied, svfloat16_t, svint16_t, + z0 = svcvt_f16_s16_x (svptrue_b16 (), z4), + z0 = svcvt_f16_x (svptrue_b16 (), z4)) + +/* +** ptrue_cvt_f16_s32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_s32_x_tied1, svfloat16_t, svint32_t, + z0_res = svcvt_f16_s32_x (svptrue_b32 (), z0), + z0_res = svcvt_f16_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f16_s32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_s32_x_untied, svfloat16_t, svint32_t, + z0 = svcvt_f16_s32_x (svptrue_b32 (), z4), + z0 = svcvt_f16_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f16_s64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_s64_x_tied1, svfloat16_t, svint64_t, + z0_res = svcvt_f16_s64_x (svptrue_b64 (), z0), + z0_res = svcvt_f16_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f16_s64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_s64_x_untied, svfloat16_t, svint64_t, + z0 = svcvt_f16_s64_x (svptrue_b64 (), z4), + z0 = svcvt_f16_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f16_u16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_u16_x_tied1, svfloat16_t, svuint16_t, + z0_res = svcvt_f16_u16_x (svptrue_b16 (), z0), + z0_res = svcvt_f16_x (svptrue_b16 (), z0)) + +/* +** ptrue_cvt_f16_u16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_u16_x_untied, svfloat16_t, svuint16_t, + z0 = svcvt_f16_u16_x (svptrue_b16 (), z4), + z0 = svcvt_f16_x (svptrue_b16 (), z4)) + +/* +** ptrue_cvt_f16_u32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_u32_x_tied1, svfloat16_t, svuint32_t, + z0_res = svcvt_f16_u32_x (svptrue_b32 (), z0), + z0_res = svcvt_f16_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f16_u32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_u32_x_untied, svfloat16_t, svuint32_t, + z0 = svcvt_f16_u32_x (svptrue_b32 (), z4), + z0 = svcvt_f16_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f16_u64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f16_u64_x_tied1, svfloat16_t, svuint64_t, + z0_res = svcvt_f16_u64_x (svptrue_b64 (), z0), + z0_res = svcvt_f16_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f16_u64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f16_u64_x_untied, svfloat16_t, svuint64_t, + z0 = svcvt_f16_u64_x (svptrue_b64 (), z4), + z0 = svcvt_f16_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c new file mode 100644 index 00000000000..c1646993996 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c @@ -0,0 +1,549 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_f32_f16_m_tied1: +** fcvt z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f32_f16_m_tied1, svfloat32_t, svfloat16_t, + z0 = svcvt_f32_f16_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvt z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f16_m_tied2, svfloat32_t, svfloat16_t, + z0_res = svcvt_f32_f16_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_f16_m_untied: +** movprfx z0, z1 +** fcvt z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f32_f16_m_untied, svfloat32_t, svfloat16_t, + z0 = svcvt_f32_f16_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_f64_m_tied1: +** fcvt z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_f64_m_tied1, svfloat32_t, svfloat64_t, + z0 = svcvt_f32_f64_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvt z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f64_m_tied2, svfloat32_t, svfloat64_t, + z0_res = svcvt_f32_f64_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_f64_m_untied: +** movprfx z0, z1 +** fcvt z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_f64_m_untied, svfloat32_t, svfloat64_t, + z0 = svcvt_f32_f64_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_s32_m_tied1: +** scvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_s32_m_tied1, svfloat32_t, svint32_t, + z0 = svcvt_f32_s32_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** scvtf z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s32_m_tied2, svfloat32_t, svint32_t, + z0_res = svcvt_f32_s32_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_s32_m_untied: +** movprfx z0, z1 +** scvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_s32_m_untied, svfloat32_t, svint32_t, + z0 = svcvt_f32_s32_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_s64_m_tied1: +** scvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_s64_m_tied1, svfloat32_t, svint64_t, + z0 = svcvt_f32_s64_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** scvtf z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s64_m_tied2, svfloat32_t, svint64_t, + z0_res = svcvt_f32_s64_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_s64_m_untied: +** movprfx z0, z1 +** scvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_s64_m_untied, svfloat32_t, svint64_t, + z0 = svcvt_f32_s64_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_u32_m_tied1: +** ucvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_u32_m_tied1, svfloat32_t, svuint32_t, + z0 = svcvt_f32_u32_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** ucvtf z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u32_m_tied2, svfloat32_t, svuint32_t, + z0_res = svcvt_f32_u32_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_u32_m_untied: +** movprfx z0, z1 +** ucvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_u32_m_untied, svfloat32_t, svuint32_t, + z0 = svcvt_f32_u32_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_u64_m_tied1: +** ucvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_u64_m_tied1, svfloat32_t, svuint64_t, + z0 = svcvt_f32_u64_m (z0, p0, z4), + z0 = svcvt_f32_m (z0, p0, z4)) + +/* +** cvt_f32_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** ucvtf z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u64_m_tied2, svfloat32_t, svuint64_t, + z0_res = svcvt_f32_u64_m (z4, p0, z0), + z0_res = svcvt_f32_m (z4, p0, z0)) + +/* +** cvt_f32_u64_m_untied: +** movprfx z0, z1 +** ucvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_u64_m_untied, svfloat32_t, svuint64_t, + z0 = svcvt_f32_u64_m (z1, p0, z4), + z0 = svcvt_f32_m (z1, p0, z4)) + +/* +** cvt_f32_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvt z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f16_z_tied1, svfloat32_t, svfloat16_t, + z0_res = svcvt_f32_f16_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_f16_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvt z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f32_f16_z_untied, svfloat32_t, svfloat16_t, + z0 = svcvt_f32_f16_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvt z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f64_z_tied1, svfloat32_t, svfloat64_t, + z0_res = svcvt_f32_f64_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvt z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_f64_z_untied, svfloat32_t, svfloat64_t, + z0 = svcvt_f32_f64_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** scvtf z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s32_z_tied1, svfloat32_t, svint32_t, + z0_res = svcvt_f32_s32_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_s32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** scvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_s32_z_untied, svfloat32_t, svint32_t, + z0 = svcvt_f32_s32_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** scvtf z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s64_z_tied1, svfloat32_t, svint64_t, + z0_res = svcvt_f32_s64_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_s64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** scvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_s64_z_untied, svfloat32_t, svint64_t, + z0 = svcvt_f32_s64_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** ucvtf z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u32_z_tied1, svfloat32_t, svuint32_t, + z0_res = svcvt_f32_u32_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_u32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** ucvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_u32_z_untied, svfloat32_t, svuint32_t, + z0 = svcvt_f32_u32_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** ucvtf z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u64_z_tied1, svfloat32_t, svuint64_t, + z0_res = svcvt_f32_u64_z (p0, z0), + z0_res = svcvt_f32_z (p0, z0)) + +/* +** cvt_f32_u64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** ucvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_u64_z_untied, svfloat32_t, svuint64_t, + z0 = svcvt_f32_u64_z (p0, z4), + z0 = svcvt_f32_z (p0, z4)) + +/* +** cvt_f32_f16_x_tied1: +** fcvt z0\.s, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f16_x_tied1, svfloat32_t, svfloat16_t, + z0_res = svcvt_f32_f16_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_f16_x_untied: +** fcvt z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f32_f16_x_untied, svfloat32_t, svfloat16_t, + z0 = svcvt_f32_f16_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** cvt_f32_f64_x_tied1: +** fcvt z0\.s, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_f64_x_tied1, svfloat32_t, svfloat64_t, + z0_res = svcvt_f32_f64_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_f64_x_untied: +** fcvt z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_f64_x_untied, svfloat32_t, svfloat64_t, + z0 = svcvt_f32_f64_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** cvt_f32_s32_x_tied1: +** scvtf z0\.s, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s32_x_tied1, svfloat32_t, svint32_t, + z0_res = svcvt_f32_s32_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_s32_x_untied: +** scvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_s32_x_untied, svfloat32_t, svint32_t, + z0 = svcvt_f32_s32_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** cvt_f32_s64_x_tied1: +** scvtf z0\.s, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_s64_x_tied1, svfloat32_t, svint64_t, + z0_res = svcvt_f32_s64_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_s64_x_untied: +** scvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_s64_x_untied, svfloat32_t, svint64_t, + z0 = svcvt_f32_s64_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** cvt_f32_u32_x_tied1: +** ucvtf z0\.s, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u32_x_tied1, svfloat32_t, svuint32_t, + z0_res = svcvt_f32_u32_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_u32_x_untied: +** ucvtf z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f32_u32_x_untied, svfloat32_t, svuint32_t, + z0 = svcvt_f32_u32_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** cvt_f32_u64_x_tied1: +** ucvtf z0\.s, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f32_u64_x_tied1, svfloat32_t, svuint64_t, + z0_res = svcvt_f32_u64_x (p0, z0), + z0_res = svcvt_f32_x (p0, z0)) + +/* +** cvt_f32_u64_x_untied: +** ucvtf z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f32_u64_x_untied, svfloat32_t, svuint64_t, + z0 = svcvt_f32_u64_x (p0, z4), + z0 = svcvt_f32_x (p0, z4)) + +/* +** ptrue_cvt_f32_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_f16_x_tied1, svfloat32_t, svfloat16_t, + z0_res = svcvt_f32_f16_x (svptrue_b32 (), z0), + z0_res = svcvt_f32_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f32_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_f16_x_untied, svfloat32_t, svfloat16_t, + z0 = svcvt_f32_f16_x (svptrue_b32 (), z4), + z0 = svcvt_f32_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f32_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_f64_x_tied1, svfloat32_t, svfloat64_t, + z0_res = svcvt_f32_f64_x (svptrue_b64 (), z0), + z0_res = svcvt_f32_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f32_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_f64_x_untied, svfloat32_t, svfloat64_t, + z0 = svcvt_f32_f64_x (svptrue_b64 (), z4), + z0 = svcvt_f32_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f32_s32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_s32_x_tied1, svfloat32_t, svint32_t, + z0_res = svcvt_f32_s32_x (svptrue_b32 (), z0), + z0_res = svcvt_f32_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f32_s32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_s32_x_untied, svfloat32_t, svint32_t, + z0 = svcvt_f32_s32_x (svptrue_b32 (), z4), + z0 = svcvt_f32_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f32_s64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_s64_x_tied1, svfloat32_t, svint64_t, + z0_res = svcvt_f32_s64_x (svptrue_b64 (), z0), + z0_res = svcvt_f32_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f32_s64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_s64_x_untied, svfloat32_t, svint64_t, + z0 = svcvt_f32_s64_x (svptrue_b64 (), z4), + z0 = svcvt_f32_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f32_u32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_u32_x_tied1, svfloat32_t, svuint32_t, + z0_res = svcvt_f32_u32_x (svptrue_b32 (), z0), + z0_res = svcvt_f32_x (svptrue_b32 (), z0)) + +/* +** ptrue_cvt_f32_u32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_u32_x_untied, svfloat32_t, svuint32_t, + z0 = svcvt_f32_u32_x (svptrue_b32 (), z4), + z0 = svcvt_f32_x (svptrue_b32 (), z4)) + +/* +** ptrue_cvt_f32_u64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f32_u64_x_tied1, svfloat32_t, svuint64_t, + z0_res = svcvt_f32_u64_x (svptrue_b64 (), z0), + z0_res = svcvt_f32_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f32_u64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f32_u64_x_untied, svfloat32_t, svuint64_t, + z0 = svcvt_f32_u64_x (svptrue_b64 (), z4), + z0 = svcvt_f32_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c new file mode 100644 index 00000000000..1d08e6ec503 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c @@ -0,0 +1,549 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_f64_f16_m_tied1: +** fcvt z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f64_f16_m_tied1, svfloat64_t, svfloat16_t, + z0 = svcvt_f64_f16_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvt z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f16_m_tied2, svfloat64_t, svfloat16_t, + z0_res = svcvt_f64_f16_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_f16_m_untied: +** movprfx z0, z1 +** fcvt z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f64_f16_m_untied, svfloat64_t, svfloat16_t, + z0 = svcvt_f64_f16_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_f32_m_tied1: +** fcvt z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_f32_m_tied1, svfloat64_t, svfloat32_t, + z0 = svcvt_f64_f32_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvt z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f32_m_tied2, svfloat64_t, svfloat32_t, + z0_res = svcvt_f64_f32_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_f32_m_untied: +** movprfx z0, z1 +** fcvt z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_f32_m_untied, svfloat64_t, svfloat32_t, + z0 = svcvt_f64_f32_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_s32_m_tied1: +** scvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_s32_m_tied1, svfloat64_t, svint32_t, + z0 = svcvt_f64_s32_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** scvtf z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s32_m_tied2, svfloat64_t, svint32_t, + z0_res = svcvt_f64_s32_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_s32_m_untied: +** movprfx z0, z1 +** scvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_s32_m_untied, svfloat64_t, svint32_t, + z0 = svcvt_f64_s32_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_s64_m_tied1: +** scvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_s64_m_tied1, svfloat64_t, svint64_t, + z0 = svcvt_f64_s64_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** scvtf z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s64_m_tied2, svfloat64_t, svint64_t, + z0_res = svcvt_f64_s64_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_s64_m_untied: +** movprfx z0, z1 +** scvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_s64_m_untied, svfloat64_t, svint64_t, + z0 = svcvt_f64_s64_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_u32_m_tied1: +** ucvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_u32_m_tied1, svfloat64_t, svuint32_t, + z0 = svcvt_f64_u32_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** ucvtf z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u32_m_tied2, svfloat64_t, svuint32_t, + z0_res = svcvt_f64_u32_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_u32_m_untied: +** movprfx z0, z1 +** ucvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_u32_m_untied, svfloat64_t, svuint32_t, + z0 = svcvt_f64_u32_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_u64_m_tied1: +** ucvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_u64_m_tied1, svfloat64_t, svuint64_t, + z0 = svcvt_f64_u64_m (z0, p0, z4), + z0 = svcvt_f64_m (z0, p0, z4)) + +/* +** cvt_f64_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** ucvtf z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u64_m_tied2, svfloat64_t, svuint64_t, + z0_res = svcvt_f64_u64_m (z4, p0, z0), + z0_res = svcvt_f64_m (z4, p0, z0)) + +/* +** cvt_f64_u64_m_untied: +** movprfx z0, z1 +** ucvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_u64_m_untied, svfloat64_t, svuint64_t, + z0 = svcvt_f64_u64_m (z1, p0, z4), + z0 = svcvt_f64_m (z1, p0, z4)) + +/* +** cvt_f64_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvt z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f16_z_tied1, svfloat64_t, svfloat16_t, + z0_res = svcvt_f64_f16_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_f16_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvt z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f64_f16_z_untied, svfloat64_t, svfloat16_t, + z0 = svcvt_f64_f16_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvt z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f32_z_tied1, svfloat64_t, svfloat32_t, + z0_res = svcvt_f64_f32_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_f32_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvt z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_f32_z_untied, svfloat64_t, svfloat32_t, + z0 = svcvt_f64_f32_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** scvtf z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s32_z_tied1, svfloat64_t, svint32_t, + z0_res = svcvt_f64_s32_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_s32_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** scvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_s32_z_untied, svfloat64_t, svint32_t, + z0 = svcvt_f64_s32_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** scvtf z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s64_z_tied1, svfloat64_t, svint64_t, + z0_res = svcvt_f64_s64_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_s64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** scvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_s64_z_untied, svfloat64_t, svint64_t, + z0 = svcvt_f64_s64_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** ucvtf z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u32_z_tied1, svfloat64_t, svuint32_t, + z0_res = svcvt_f64_u32_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_u32_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** ucvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_u32_z_untied, svfloat64_t, svuint32_t, + z0 = svcvt_f64_u32_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** ucvtf z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u64_z_tied1, svfloat64_t, svuint64_t, + z0_res = svcvt_f64_u64_z (p0, z0), + z0_res = svcvt_f64_z (p0, z0)) + +/* +** cvt_f64_u64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** ucvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_u64_z_untied, svfloat64_t, svuint64_t, + z0 = svcvt_f64_u64_z (p0, z4), + z0 = svcvt_f64_z (p0, z4)) + +/* +** cvt_f64_f16_x_tied1: +** fcvt z0\.d, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f16_x_tied1, svfloat64_t, svfloat16_t, + z0_res = svcvt_f64_f16_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_f16_x_untied: +** fcvt z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_f64_f16_x_untied, svfloat64_t, svfloat16_t, + z0 = svcvt_f64_f16_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** cvt_f64_f32_x_tied1: +** fcvt z0\.d, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_f32_x_tied1, svfloat64_t, svfloat32_t, + z0_res = svcvt_f64_f32_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_f32_x_untied: +** fcvt z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_f32_x_untied, svfloat64_t, svfloat32_t, + z0 = svcvt_f64_f32_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** cvt_f64_s32_x_tied1: +** scvtf z0\.d, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s32_x_tied1, svfloat64_t, svint32_t, + z0_res = svcvt_f64_s32_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_s32_x_untied: +** scvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_s32_x_untied, svfloat64_t, svint32_t, + z0 = svcvt_f64_s32_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** cvt_f64_s64_x_tied1: +** scvtf z0\.d, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_s64_x_tied1, svfloat64_t, svint64_t, + z0_res = svcvt_f64_s64_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_s64_x_untied: +** scvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_s64_x_untied, svfloat64_t, svint64_t, + z0 = svcvt_f64_s64_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** cvt_f64_u32_x_tied1: +** ucvtf z0\.d, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u32_x_tied1, svfloat64_t, svuint32_t, + z0_res = svcvt_f64_u32_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_u32_x_untied: +** ucvtf z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_f64_u32_x_untied, svfloat64_t, svuint32_t, + z0 = svcvt_f64_u32_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** cvt_f64_u64_x_tied1: +** ucvtf z0\.d, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_f64_u64_x_tied1, svfloat64_t, svuint64_t, + z0_res = svcvt_f64_u64_x (p0, z0), + z0_res = svcvt_f64_x (p0, z0)) + +/* +** cvt_f64_u64_x_untied: +** ucvtf z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_f64_u64_x_untied, svfloat64_t, svuint64_t, + z0 = svcvt_f64_u64_x (p0, z4), + z0 = svcvt_f64_x (p0, z4)) + +/* +** ptrue_cvt_f64_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_f16_x_tied1, svfloat64_t, svfloat16_t, + z0_res = svcvt_f64_f16_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_f16_x_untied, svfloat64_t, svfloat16_t, + z0 = svcvt_f64_f16_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f64_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_f32_x_tied1, svfloat64_t, svfloat32_t, + z0_res = svcvt_f64_f32_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_f32_x_untied, svfloat64_t, svfloat32_t, + z0 = svcvt_f64_f32_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f64_s32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_s32_x_tied1, svfloat64_t, svint32_t, + z0_res = svcvt_f64_s32_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_s32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_s32_x_untied, svfloat64_t, svint32_t, + z0 = svcvt_f64_s32_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f64_s64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_s64_x_tied1, svfloat64_t, svint64_t, + z0_res = svcvt_f64_s64_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_s64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_s64_x_untied, svfloat64_t, svint64_t, + z0 = svcvt_f64_s64_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f64_u32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_u32_x_tied1, svfloat64_t, svuint32_t, + z0_res = svcvt_f64_u32_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_u32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_u32_x_untied, svfloat64_t, svuint32_t, + z0 = svcvt_f64_u32_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) + +/* +** ptrue_cvt_f64_u64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_cvt_f64_u64_x_tied1, svfloat64_t, svuint64_t, + z0_res = svcvt_f64_u64_x (svptrue_b64 (), z0), + z0_res = svcvt_f64_x (svptrue_b64 (), z0)) + +/* +** ptrue_cvt_f64_u64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_cvt_f64_u64_x_untied, svfloat64_t, svuint64_t, + z0 = svcvt_f64_u64_x (svptrue_b64 (), z4), + z0 = svcvt_f64_x (svptrue_b64 (), z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c new file mode 100644 index 00000000000..81761ab092c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c @@ -0,0 +1,72 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_s16_f16_m_tied1: +** fcvtzs z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s16_f16_m_tied1, svint16_t, svfloat16_t, + z0 = svcvt_s16_f16_m (z0, p0, z4), + z0 = svcvt_s16_m (z0, p0, z4)) + +/* +** cvt_s16_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s16_f16_m_tied2, svint16_t, svfloat16_t, + z0_res = svcvt_s16_f16_m (z4, p0, z0), + z0_res = svcvt_s16_m (z4, p0, z0)) + +/* +** cvt_s16_f16_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s16_f16_m_untied, svint16_t, svfloat16_t, + z0 = svcvt_s16_f16_m (z1, p0, z4), + z0 = svcvt_s16_m (z1, p0, z4)) + +/* +** cvt_s16_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** fcvtzs z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s16_f16_z_tied1, svint16_t, svfloat16_t, + z0_res = svcvt_s16_f16_z (p0, z0), + z0_res = svcvt_s16_z (p0, z0)) + +/* +** cvt_s16_f16_z_untied: +** movprfx z0\.h, p0/z, z4\.h +** fcvtzs z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s16_f16_z_untied, svint16_t, svfloat16_t, + z0 = svcvt_s16_f16_z (p0, z4), + z0 = svcvt_s16_z (p0, z4)) + +/* +** cvt_s16_f16_x_tied1: +** fcvtzs z0\.h, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s16_f16_x_tied1, svint16_t, svfloat16_t, + z0_res = svcvt_s16_f16_x (p0, z0), + z0_res = svcvt_s16_x (p0, z0)) + +/* +** cvt_s16_f16_x_untied: +** fcvtzs z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s16_f16_x_untied, svint16_t, svfloat16_t, + z0 = svcvt_s16_f16_x (p0, z4), + z0 = svcvt_s16_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c new file mode 100644 index 00000000000..d30da5cc53a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c @@ -0,0 +1,210 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_s32_f16_m_tied1: +** fcvtzs z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s32_f16_m_tied1, svint32_t, svfloat16_t, + z0 = svcvt_s32_f16_m (z0, p0, z4), + z0 = svcvt_s32_m (z0, p0, z4)) + +/* +** cvt_s32_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzs z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f16_m_tied2, svint32_t, svfloat16_t, + z0_res = svcvt_s32_f16_m (z4, p0, z0), + z0_res = svcvt_s32_m (z4, p0, z0)) + +/* +** cvt_s32_f16_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s32_f16_m_untied, svint32_t, svfloat16_t, + z0 = svcvt_s32_f16_m (z1, p0, z4), + z0 = svcvt_s32_m (z1, p0, z4)) + +/* +** cvt_s32_f32_m_tied1: +** fcvtzs z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s32_f32_m_tied1, svint32_t, svfloat32_t, + z0 = svcvt_s32_f32_m (z0, p0, z4), + z0 = svcvt_s32_m (z0, p0, z4)) + +/* +** cvt_s32_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f32_m_tied2, svint32_t, svfloat32_t, + z0_res = svcvt_s32_f32_m (z4, p0, z0), + z0_res = svcvt_s32_m (z4, p0, z0)) + +/* +** cvt_s32_f32_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s32_f32_m_untied, svint32_t, svfloat32_t, + z0 = svcvt_s32_f32_m (z1, p0, z4), + z0 = svcvt_s32_m (z1, p0, z4)) + +/* +** cvt_s32_f64_m_tied1: +** fcvtzs z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s32_f64_m_tied1, svint32_t, svfloat64_t, + z0 = svcvt_s32_f64_m (z0, p0, z4), + z0 = svcvt_s32_m (z0, p0, z4)) + +/* +** cvt_s32_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvtzs z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f64_m_tied2, svint32_t, svfloat64_t, + z0_res = svcvt_s32_f64_m (z4, p0, z0), + z0_res = svcvt_s32_m (z4, p0, z0)) + +/* +** cvt_s32_f64_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s32_f64_m_untied, svint32_t, svfloat64_t, + z0 = svcvt_s32_f64_m (z1, p0, z4), + z0 = svcvt_s32_m (z1, p0, z4)) + +/* +** cvt_s32_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvtzs z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f16_z_tied1, svint32_t, svfloat16_t, + z0_res = svcvt_s32_f16_z (p0, z0), + z0_res = svcvt_s32_z (p0, z0)) + +/* +** cvt_s32_f16_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvtzs z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s32_f16_z_untied, svint32_t, svfloat16_t, + z0 = svcvt_s32_f16_z (p0, z4), + z0 = svcvt_s32_z (p0, z4)) + +/* +** cvt_s32_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvtzs z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f32_z_tied1, svint32_t, svfloat32_t, + z0_res = svcvt_s32_f32_z (p0, z0), + z0_res = svcvt_s32_z (p0, z0)) + +/* +** cvt_s32_f32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvtzs z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s32_f32_z_untied, svint32_t, svfloat32_t, + z0 = svcvt_s32_f32_z (p0, z4), + z0 = svcvt_s32_z (p0, z4)) + +/* +** cvt_s32_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvtzs z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f64_z_tied1, svint32_t, svfloat64_t, + z0_res = svcvt_s32_f64_z (p0, z0), + z0_res = svcvt_s32_z (p0, z0)) + +/* +** cvt_s32_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzs z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s32_f64_z_untied, svint32_t, svfloat64_t, + z0 = svcvt_s32_f64_z (p0, z4), + z0 = svcvt_s32_z (p0, z4)) + +/* +** cvt_s32_f16_x_tied1: +** fcvtzs z0\.s, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f16_x_tied1, svint32_t, svfloat16_t, + z0_res = svcvt_s32_f16_x (p0, z0), + z0_res = svcvt_s32_x (p0, z0)) + +/* +** cvt_s32_f16_x_untied: +** fcvtzs z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s32_f16_x_untied, svint32_t, svfloat16_t, + z0 = svcvt_s32_f16_x (p0, z4), + z0 = svcvt_s32_x (p0, z4)) + +/* +** cvt_s32_f32_x_tied1: +** fcvtzs z0\.s, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f32_x_tied1, svint32_t, svfloat32_t, + z0_res = svcvt_s32_f32_x (p0, z0), + z0_res = svcvt_s32_x (p0, z0)) + +/* +** cvt_s32_f32_x_untied: +** fcvtzs z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s32_f32_x_untied, svint32_t, svfloat32_t, + z0 = svcvt_s32_f32_x (p0, z4), + z0 = svcvt_s32_x (p0, z4)) + +/* +** cvt_s32_f64_x_tied1: +** fcvtzs z0\.s, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_s32_f64_x_tied1, svint32_t, svfloat64_t, + z0_res = svcvt_s32_f64_x (p0, z0), + z0_res = svcvt_s32_x (p0, z0)) + +/* +** cvt_s32_f64_x_untied: +** fcvtzs z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s32_f64_x_untied, svint32_t, svfloat64_t, + z0 = svcvt_s32_f64_x (p0, z4), + z0 = svcvt_s32_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c new file mode 100644 index 00000000000..68cd80784de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c @@ -0,0 +1,210 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_s64_f16_m_tied1: +** fcvtzs z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s64_f16_m_tied1, svint64_t, svfloat16_t, + z0 = svcvt_s64_f16_m (z0, p0, z4), + z0 = svcvt_s64_m (z0, p0, z4)) + +/* +** cvt_s64_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzs z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f16_m_tied2, svint64_t, svfloat16_t, + z0_res = svcvt_s64_f16_m (z4, p0, z0), + z0_res = svcvt_s64_m (z4, p0, z0)) + +/* +** cvt_s64_f16_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s64_f16_m_untied, svint64_t, svfloat16_t, + z0 = svcvt_s64_f16_m (z1, p0, z4), + z0 = svcvt_s64_m (z1, p0, z4)) + +/* +** cvt_s64_f32_m_tied1: +** fcvtzs z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s64_f32_m_tied1, svint64_t, svfloat32_t, + z0 = svcvt_s64_f32_m (z0, p0, z4), + z0 = svcvt_s64_m (z0, p0, z4)) + +/* +** cvt_s64_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzs z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f32_m_tied2, svint64_t, svfloat32_t, + z0_res = svcvt_s64_f32_m (z4, p0, z0), + z0_res = svcvt_s64_m (z4, p0, z0)) + +/* +** cvt_s64_f32_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s64_f32_m_untied, svint64_t, svfloat32_t, + z0 = svcvt_s64_f32_m (z1, p0, z4), + z0 = svcvt_s64_m (z1, p0, z4)) + +/* +** cvt_s64_f64_m_tied1: +** fcvtzs z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s64_f64_m_tied1, svint64_t, svfloat64_t, + z0 = svcvt_s64_f64_m (z0, p0, z4), + z0 = svcvt_s64_m (z0, p0, z4)) + +/* +** cvt_s64_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvtzs z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f64_m_tied2, svint64_t, svfloat64_t, + z0_res = svcvt_s64_f64_m (z4, p0, z0), + z0_res = svcvt_s64_m (z4, p0, z0)) + +/* +** cvt_s64_f64_m_untied: +** movprfx z0, z1 +** fcvtzs z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s64_f64_m_untied, svint64_t, svfloat64_t, + z0 = svcvt_s64_f64_m (z1, p0, z4), + z0 = svcvt_s64_m (z1, p0, z4)) + +/* +** cvt_s64_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvtzs z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f16_z_tied1, svint64_t, svfloat16_t, + z0_res = svcvt_s64_f16_z (p0, z0), + z0_res = svcvt_s64_z (p0, z0)) + +/* +** cvt_s64_f16_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzs z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s64_f16_z_untied, svint64_t, svfloat16_t, + z0 = svcvt_s64_f16_z (p0, z4), + z0 = svcvt_s64_z (p0, z4)) + +/* +** cvt_s64_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvtzs z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f32_z_tied1, svint64_t, svfloat32_t, + z0_res = svcvt_s64_f32_z (p0, z0), + z0_res = svcvt_s64_z (p0, z0)) + +/* +** cvt_s64_f32_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzs z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s64_f32_z_untied, svint64_t, svfloat32_t, + z0 = svcvt_s64_f32_z (p0, z4), + z0 = svcvt_s64_z (p0, z4)) + +/* +** cvt_s64_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvtzs z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f64_z_tied1, svint64_t, svfloat64_t, + z0_res = svcvt_s64_f64_z (p0, z0), + z0_res = svcvt_s64_z (p0, z0)) + +/* +** cvt_s64_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzs z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s64_f64_z_untied, svint64_t, svfloat64_t, + z0 = svcvt_s64_f64_z (p0, z4), + z0 = svcvt_s64_z (p0, z4)) + +/* +** cvt_s64_f16_x_tied1: +** fcvtzs z0\.d, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f16_x_tied1, svint64_t, svfloat16_t, + z0_res = svcvt_s64_f16_x (p0, z0), + z0_res = svcvt_s64_x (p0, z0)) + +/* +** cvt_s64_f16_x_untied: +** fcvtzs z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_s64_f16_x_untied, svint64_t, svfloat16_t, + z0 = svcvt_s64_f16_x (p0, z4), + z0 = svcvt_s64_x (p0, z4)) + +/* +** cvt_s64_f32_x_tied1: +** fcvtzs z0\.d, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f32_x_tied1, svint64_t, svfloat32_t, + z0_res = svcvt_s64_f32_x (p0, z0), + z0_res = svcvt_s64_x (p0, z0)) + +/* +** cvt_s64_f32_x_untied: +** fcvtzs z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_s64_f32_x_untied, svint64_t, svfloat32_t, + z0 = svcvt_s64_f32_x (p0, z4), + z0 = svcvt_s64_x (p0, z4)) + +/* +** cvt_s64_f64_x_tied1: +** fcvtzs z0\.d, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_s64_f64_x_tied1, svint64_t, svfloat64_t, + z0_res = svcvt_s64_f64_x (p0, z0), + z0_res = svcvt_s64_x (p0, z0)) + +/* +** cvt_s64_f64_x_untied: +** fcvtzs z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_s64_f64_x_untied, svint64_t, svfloat64_t, + z0 = svcvt_s64_f64_x (p0, z4), + z0 = svcvt_s64_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c new file mode 100644 index 00000000000..4db0dffdd97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c @@ -0,0 +1,72 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_u16_f16_m_tied1: +** fcvtzu z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u16_f16_m_tied1, svuint16_t, svfloat16_t, + z0 = svcvt_u16_f16_m (z0, p0, z4), + z0 = svcvt_u16_m (z0, p0, z4)) + +/* +** cvt_u16_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzu z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u16_f16_m_tied2, svuint16_t, svfloat16_t, + z0_res = svcvt_u16_f16_m (z4, p0, z0), + z0_res = svcvt_u16_m (z4, p0, z0)) + +/* +** cvt_u16_f16_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u16_f16_m_untied, svuint16_t, svfloat16_t, + z0 = svcvt_u16_f16_m (z1, p0, z4), + z0 = svcvt_u16_m (z1, p0, z4)) + +/* +** cvt_u16_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** fcvtzu z0\.h, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u16_f16_z_tied1, svuint16_t, svfloat16_t, + z0_res = svcvt_u16_f16_z (p0, z0), + z0_res = svcvt_u16_z (p0, z0)) + +/* +** cvt_u16_f16_z_untied: +** movprfx z0\.h, p0/z, z4\.h +** fcvtzu z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u16_f16_z_untied, svuint16_t, svfloat16_t, + z0 = svcvt_u16_f16_z (p0, z4), + z0 = svcvt_u16_z (p0, z4)) + +/* +** cvt_u16_f16_x_tied1: +** fcvtzu z0\.h, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u16_f16_x_tied1, svuint16_t, svfloat16_t, + z0_res = svcvt_u16_f16_x (p0, z0), + z0_res = svcvt_u16_x (p0, z0)) + +/* +** cvt_u16_f16_x_untied: +** fcvtzu z0\.h, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u16_f16_x_untied, svuint16_t, svfloat16_t, + z0 = svcvt_u16_f16_x (p0, z4), + z0 = svcvt_u16_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c new file mode 100644 index 00000000000..52ef49fcf09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c @@ -0,0 +1,210 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_u32_f16_m_tied1: +** fcvtzu z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u32_f16_m_tied1, svuint32_t, svfloat16_t, + z0 = svcvt_u32_f16_m (z0, p0, z4), + z0 = svcvt_u32_m (z0, p0, z4)) + +/* +** cvt_u32_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzu z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f16_m_tied2, svuint32_t, svfloat16_t, + z0_res = svcvt_u32_f16_m (z4, p0, z0), + z0_res = svcvt_u32_m (z4, p0, z0)) + +/* +** cvt_u32_f16_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u32_f16_m_untied, svuint32_t, svfloat16_t, + z0 = svcvt_u32_f16_m (z1, p0, z4), + z0 = svcvt_u32_m (z1, p0, z4)) + +/* +** cvt_u32_f32_m_tied1: +** fcvtzu z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u32_f32_m_tied1, svuint32_t, svfloat32_t, + z0 = svcvt_u32_f32_m (z0, p0, z4), + z0 = svcvt_u32_m (z0, p0, z4)) + +/* +** cvt_u32_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzu z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f32_m_tied2, svuint32_t, svfloat32_t, + z0_res = svcvt_u32_f32_m (z4, p0, z0), + z0_res = svcvt_u32_m (z4, p0, z0)) + +/* +** cvt_u32_f32_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u32_f32_m_untied, svuint32_t, svfloat32_t, + z0 = svcvt_u32_f32_m (z1, p0, z4), + z0 = svcvt_u32_m (z1, p0, z4)) + +/* +** cvt_u32_f64_m_tied1: +** fcvtzu z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u32_f64_m_tied1, svuint32_t, svfloat64_t, + z0 = svcvt_u32_f64_m (z0, p0, z4), + z0 = svcvt_u32_m (z0, p0, z4)) + +/* +** cvt_u32_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvtzu z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f64_m_tied2, svuint32_t, svfloat64_t, + z0_res = svcvt_u32_f64_m (z4, p0, z0), + z0_res = svcvt_u32_m (z4, p0, z0)) + +/* +** cvt_u32_f64_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u32_f64_m_untied, svuint32_t, svfloat64_t, + z0 = svcvt_u32_f64_m (z1, p0, z4), + z0 = svcvt_u32_m (z1, p0, z4)) + +/* +** cvt_u32_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvtzu z0\.s, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f16_z_tied1, svuint32_t, svfloat16_t, + z0_res = svcvt_u32_f16_z (p0, z0), + z0_res = svcvt_u32_z (p0, z0)) + +/* +** cvt_u32_f16_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvtzu z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u32_f16_z_untied, svuint32_t, svfloat16_t, + z0 = svcvt_u32_f16_z (p0, z4), + z0 = svcvt_u32_z (p0, z4)) + +/* +** cvt_u32_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fcvtzu z0\.s, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f32_z_tied1, svuint32_t, svfloat32_t, + z0_res = svcvt_u32_f32_z (p0, z0), + z0_res = svcvt_u32_z (p0, z0)) + +/* +** cvt_u32_f32_z_untied: +** movprfx z0\.s, p0/z, z4\.s +** fcvtzu z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u32_f32_z_untied, svuint32_t, svfloat32_t, + z0 = svcvt_u32_f32_z (p0, z4), + z0 = svcvt_u32_z (p0, z4)) + +/* +** cvt_u32_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvtzu z0\.s, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f64_z_tied1, svuint32_t, svfloat64_t, + z0_res = svcvt_u32_f64_z (p0, z0), + z0_res = svcvt_u32_z (p0, z0)) + +/* +** cvt_u32_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzu z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u32_f64_z_untied, svuint32_t, svfloat64_t, + z0 = svcvt_u32_f64_z (p0, z4), + z0 = svcvt_u32_z (p0, z4)) + +/* +** cvt_u32_f16_x_tied1: +** fcvtzu z0\.s, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f16_x_tied1, svuint32_t, svfloat16_t, + z0_res = svcvt_u32_f16_x (p0, z0), + z0_res = svcvt_u32_x (p0, z0)) + +/* +** cvt_u32_f16_x_untied: +** fcvtzu z0\.s, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u32_f16_x_untied, svuint32_t, svfloat16_t, + z0 = svcvt_u32_f16_x (p0, z4), + z0 = svcvt_u32_x (p0, z4)) + +/* +** cvt_u32_f32_x_tied1: +** fcvtzu z0\.s, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f32_x_tied1, svuint32_t, svfloat32_t, + z0_res = svcvt_u32_f32_x (p0, z0), + z0_res = svcvt_u32_x (p0, z0)) + +/* +** cvt_u32_f32_x_untied: +** fcvtzu z0\.s, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u32_f32_x_untied, svuint32_t, svfloat32_t, + z0 = svcvt_u32_f32_x (p0, z4), + z0 = svcvt_u32_x (p0, z4)) + +/* +** cvt_u32_f64_x_tied1: +** fcvtzu z0\.s, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_u32_f64_x_tied1, svuint32_t, svfloat64_t, + z0_res = svcvt_u32_f64_x (p0, z0), + z0_res = svcvt_u32_x (p0, z0)) + +/* +** cvt_u32_f64_x_untied: +** fcvtzu z0\.s, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u32_f64_x_untied, svuint32_t, svfloat64_t, + z0 = svcvt_u32_f64_x (p0, z4), + z0 = svcvt_u32_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c new file mode 100644 index 00000000000..0c43758aeb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c @@ -0,0 +1,210 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** cvt_u64_f16_m_tied1: +** fcvtzu z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u64_f16_m_tied1, svuint64_t, svfloat16_t, + z0 = svcvt_u64_f16_m (z0, p0, z4), + z0 = svcvt_u64_m (z0, p0, z4)) + +/* +** cvt_u64_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzu z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f16_m_tied2, svuint64_t, svfloat16_t, + z0_res = svcvt_u64_f16_m (z4, p0, z0), + z0_res = svcvt_u64_m (z4, p0, z0)) + +/* +** cvt_u64_f16_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u64_f16_m_untied, svuint64_t, svfloat16_t, + z0 = svcvt_u64_f16_m (z1, p0, z4), + z0 = svcvt_u64_m (z1, p0, z4)) + +/* +** cvt_u64_f32_m_tied1: +** fcvtzu z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u64_f32_m_tied1, svuint64_t, svfloat32_t, + z0 = svcvt_u64_f32_m (z0, p0, z4), + z0 = svcvt_u64_m (z0, p0, z4)) + +/* +** cvt_u64_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fcvtzu z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f32_m_tied2, svuint64_t, svfloat32_t, + z0_res = svcvt_u64_f32_m (z4, p0, z0), + z0_res = svcvt_u64_m (z4, p0, z0)) + +/* +** cvt_u64_f32_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u64_f32_m_untied, svuint64_t, svfloat32_t, + z0 = svcvt_u64_f32_m (z1, p0, z4), + z0 = svcvt_u64_m (z1, p0, z4)) + +/* +** cvt_u64_f64_m_tied1: +** fcvtzu z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u64_f64_m_tied1, svuint64_t, svfloat64_t, + z0 = svcvt_u64_f64_m (z0, p0, z4), + z0 = svcvt_u64_m (z0, p0, z4)) + +/* +** cvt_u64_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fcvtzu z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f64_m_tied2, svuint64_t, svfloat64_t, + z0_res = svcvt_u64_f64_m (z4, p0, z0), + z0_res = svcvt_u64_m (z4, p0, z0)) + +/* +** cvt_u64_f64_m_untied: +** movprfx z0, z1 +** fcvtzu z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u64_f64_m_untied, svuint64_t, svfloat64_t, + z0 = svcvt_u64_f64_m (z1, p0, z4), + z0 = svcvt_u64_m (z1, p0, z4)) + +/* +** cvt_u64_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvtzu z0\.d, p0/m, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f16_z_tied1, svuint64_t, svfloat16_t, + z0_res = svcvt_u64_f16_z (p0, z0), + z0_res = svcvt_u64_z (p0, z0)) + +/* +** cvt_u64_f16_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzu z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u64_f16_z_untied, svuint64_t, svfloat16_t, + z0 = svcvt_u64_f16_z (p0, z4), + z0 = svcvt_u64_z (p0, z4)) + +/* +** cvt_u64_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.d, p0/z, \1\.d +** fcvtzu z0\.d, p0/m, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f32_z_tied1, svuint64_t, svfloat32_t, + z0_res = svcvt_u64_f32_z (p0, z0), + z0_res = svcvt_u64_z (p0, z0)) + +/* +** cvt_u64_f32_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzu z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u64_f32_z_untied, svuint64_t, svfloat32_t, + z0 = svcvt_u64_f32_z (p0, z4), + z0 = svcvt_u64_z (p0, z4)) + +/* +** cvt_u64_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fcvtzu z0\.d, p0/m, \1 +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f64_z_tied1, svuint64_t, svfloat64_t, + z0_res = svcvt_u64_f64_z (p0, z0), + z0_res = svcvt_u64_z (p0, z0)) + +/* +** cvt_u64_f64_z_untied: +** movprfx z0\.d, p0/z, z4\.d +** fcvtzu z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u64_f64_z_untied, svuint64_t, svfloat64_t, + z0 = svcvt_u64_f64_z (p0, z4), + z0 = svcvt_u64_z (p0, z4)) + +/* +** cvt_u64_f16_x_tied1: +** fcvtzu z0\.d, p0/m, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f16_x_tied1, svuint64_t, svfloat16_t, + z0_res = svcvt_u64_f16_x (p0, z0), + z0_res = svcvt_u64_x (p0, z0)) + +/* +** cvt_u64_f16_x_untied: +** fcvtzu z0\.d, p0/m, z4\.h +** ret +*/ +TEST_DUAL_Z (cvt_u64_f16_x_untied, svuint64_t, svfloat16_t, + z0 = svcvt_u64_f16_x (p0, z4), + z0 = svcvt_u64_x (p0, z4)) + +/* +** cvt_u64_f32_x_tied1: +** fcvtzu z0\.d, p0/m, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f32_x_tied1, svuint64_t, svfloat32_t, + z0_res = svcvt_u64_f32_x (p0, z0), + z0_res = svcvt_u64_x (p0, z0)) + +/* +** cvt_u64_f32_x_untied: +** fcvtzu z0\.d, p0/m, z4\.s +** ret +*/ +TEST_DUAL_Z (cvt_u64_f32_x_untied, svuint64_t, svfloat32_t, + z0 = svcvt_u64_f32_x (p0, z4), + z0 = svcvt_u64_x (p0, z4)) + +/* +** cvt_u64_f64_x_tied1: +** fcvtzu z0\.d, p0/m, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (cvt_u64_f64_x_tied1, svuint64_t, svfloat64_t, + z0_res = svcvt_u64_f64_x (p0, z0), + z0_res = svcvt_u64_x (p0, z0)) + +/* +** cvt_u64_f64_x_untied: +** fcvtzu z0\.d, p0/m, z4\.d +** ret +*/ +TEST_DUAL_Z (cvt_u64_f64_x_untied, svuint64_t, svfloat64_t, + z0 = svcvt_u64_f64_x (p0, z4), + z0 = svcvt_u64_x (p0, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f16.c new file mode 100644 index 00000000000..35f5c158911 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f16.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_f16_m_tied1: +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_m_tied1, svfloat16_t, + z0 = svdiv_f16_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fdiv z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_m_tied2, svfloat16_t, + z0 = svdiv_f16_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_f16_m_untied: +** movprfx z0, z1 +** fdiv z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_m_untied, svfloat16_t, + z0 = svdiv_f16_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svdiv_n_f16_m (p0, z0, d4), + z0 = svdiv_m (p0, z0, d4)) + +/* +** div_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svdiv_n_f16_m (p0, z1, d4), + z0 = svdiv_m (p0, z1, d4)) + +/* +** div_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_m_tied1, svfloat16_t, + z0 = svdiv_n_f16_m (p0, z0, 1), + z0 = svdiv_m (p0, z0, 1)) + +/* +** div_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_m_untied, svfloat16_t, + z0 = svdiv_n_f16_m (p0, z1, 1), + z0 = svdiv_m (p0, z1, 1)) + +/* +** div_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_z_tied1, svfloat16_t, + z0 = svdiv_f16_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_z_tied2, svfloat16_t, + z0 = svdiv_f16_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdiv z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f16_z_untied, svfloat16_t, + z0 = svdiv_f16_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svdiv_n_f16_z (p0, z0, d4), + z0 = svdiv_z (p0, z0, d4)) + +/* +** div_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdiv z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svdiv_n_f16_z (p0, z1, d4), + z0 = svdiv_z (p0, z1, d4)) + +/* +** div_1_f16_z_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_z_tied1, svfloat16_t, + z0 = svdiv_n_f16_z (p0, z0, 1), + z0 = svdiv_z (p0, z0, 1)) + +/* +** div_1_f16_z_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdiv z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_z_untied, svfloat16_t, + z0 = svdiv_n_f16_z (p0, z1, 1), + z0 = svdiv_z (p0, z1, 1)) + +/* +** div_0p5_f16_z: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0\.h, p0/z, z0\.h +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (div_0p5_f16_z, svfloat16_t, + z0 = svdiv_n_f16_z (p0, z0, 0.5), + z0 = svdiv_z (p0, z0, 0.5)) + +/* +** div_f16_x_tied1: +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_x_tied1, svfloat16_t, + z0 = svdiv_f16_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_f16_x_tied2: +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_f16_x_tied2, svfloat16_t, + z0 = svdiv_f16_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_f16_x_untied: +** ( +** movprfx z0, z1 +** fdiv z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f16_x_untied, svfloat16_t, + z0 = svdiv_f16_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svdiv_n_f16_x (p0, z0, d4), + z0 = svdiv_x (p0, z0, d4)) + +/* +** div_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (div_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svdiv_n_f16_x (p0, z1, d4), + z0 = svdiv_x (p0, z1, d4)) + +/* +** div_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fdiv z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_x_tied1, svfloat16_t, + z0 = svdiv_n_f16_x (p0, z0, 1), + z0 = svdiv_x (p0, z0, 1)) + +/* +** div_1_f16_x_untied: +** fmov z0\.h, #1\.0(?:e\+0)? +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (div_1_f16_x_untied, svfloat16_t, + z0 = svdiv_n_f16_x (p0, z1, 1), + z0 = svdiv_x (p0, z1, 1)) + +/* +** ptrue_div_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f16_x_tied1, svfloat16_t, + z0 = svdiv_f16_x (svptrue_b16 (), z0, z1), + z0 = svdiv_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_div_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f16_x_tied2, svfloat16_t, + z0 = svdiv_f16_x (svptrue_b16 (), z1, z0), + z0 = svdiv_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_div_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f16_x_untied, svfloat16_t, + z0 = svdiv_f16_x (svptrue_b16 (), z1, z2), + z0 = svdiv_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_div_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f16_x_tied1, svfloat16_t, + z0 = svdiv_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svdiv_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_div_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f16_x_untied, svfloat16_t, + z0 = svdiv_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svdiv_x (svptrue_b16 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f32.c new file mode 100644 index 00000000000..40cc203da67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f32.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_f32_m_tied1: +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_m_tied1, svfloat32_t, + z0 = svdiv_f32_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fdiv z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_m_tied2, svfloat32_t, + z0 = svdiv_f32_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_f32_m_untied: +** movprfx z0, z1 +** fdiv z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_m_untied, svfloat32_t, + z0 = svdiv_f32_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_m_tied1, svfloat32_t, float, + z0 = svdiv_n_f32_m (p0, z0, d4), + z0 = svdiv_m (p0, z0, d4)) + +/* +** div_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_m_untied, svfloat32_t, float, + z0 = svdiv_n_f32_m (p0, z1, d4), + z0 = svdiv_m (p0, z1, d4)) + +/* +** div_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_m_tied1, svfloat32_t, + z0 = svdiv_n_f32_m (p0, z0, 1), + z0 = svdiv_m (p0, z0, 1)) + +/* +** div_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_m_untied, svfloat32_t, + z0 = svdiv_n_f32_m (p0, z1, 1), + z0 = svdiv_m (p0, z1, 1)) + +/* +** div_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_z_tied1, svfloat32_t, + z0 = svdiv_f32_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_z_tied2, svfloat32_t, + z0 = svdiv_f32_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f32_z_untied, svfloat32_t, + z0 = svdiv_f32_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_z_tied1, svfloat32_t, float, + z0 = svdiv_n_f32_z (p0, z0, d4), + z0 = svdiv_z (p0, z0, d4)) + +/* +** div_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_z_untied, svfloat32_t, float, + z0 = svdiv_n_f32_z (p0, z1, d4), + z0 = svdiv_z (p0, z1, d4)) + +/* +** div_1_f32_z_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_z_tied1, svfloat32_t, + z0 = svdiv_n_f32_z (p0, z0, 1), + z0 = svdiv_z (p0, z0, 1)) + +/* +** div_1_f32_z_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_z_untied, svfloat32_t, + z0 = svdiv_n_f32_z (p0, z1, 1), + z0 = svdiv_z (p0, z1, 1)) + +/* +** div_0p5_f32_z: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0\.s, p0/z, z0\.s +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_0p5_f32_z, svfloat32_t, + z0 = svdiv_n_f32_z (p0, z0, 0.5), + z0 = svdiv_z (p0, z0, 0.5)) + +/* +** div_f32_x_tied1: +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_x_tied1, svfloat32_t, + z0 = svdiv_f32_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_f32_x_tied2: +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_f32_x_tied2, svfloat32_t, + z0 = svdiv_f32_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_f32_x_untied: +** ( +** movprfx z0, z1 +** fdiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f32_x_untied, svfloat32_t, + z0 = svdiv_f32_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_x_tied1, svfloat32_t, float, + z0 = svdiv_n_f32_x (p0, z0, d4), + z0 = svdiv_x (p0, z0, d4)) + +/* +** div_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (div_s4_f32_x_untied, svfloat32_t, float, + z0 = svdiv_n_f32_x (p0, z1, d4), + z0 = svdiv_x (p0, z1, d4)) + +/* +** div_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_x_tied1, svfloat32_t, + z0 = svdiv_n_f32_x (p0, z0, 1), + z0 = svdiv_x (p0, z0, 1)) + +/* +** div_1_f32_x_untied: +** fmov z0\.s, #1\.0(?:e\+0)? +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_1_f32_x_untied, svfloat32_t, + z0 = svdiv_n_f32_x (p0, z1, 1), + z0 = svdiv_x (p0, z1, 1)) + +/* +** ptrue_div_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f32_x_tied1, svfloat32_t, + z0 = svdiv_f32_x (svptrue_b32 (), z0, z1), + z0 = svdiv_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_div_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f32_x_tied2, svfloat32_t, + z0 = svdiv_f32_x (svptrue_b32 (), z1, z0), + z0 = svdiv_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_div_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f32_x_untied, svfloat32_t, + z0 = svdiv_f32_x (svptrue_b32 (), z1, z2), + z0 = svdiv_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_div_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f32_x_tied1, svfloat32_t, + z0 = svdiv_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svdiv_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_div_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f32_x_untied, svfloat32_t, + z0 = svdiv_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svdiv_x (svptrue_b32 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f64.c new file mode 100644 index 00000000000..56acbbe9550 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_f64.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_f64_m_tied1: +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_m_tied1, svfloat64_t, + z0 = svdiv_f64_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_f64_m_tied2, svfloat64_t, + z0 = svdiv_f64_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_f64_m_untied: +** movprfx z0, z1 +** fdiv z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_m_untied, svfloat64_t, + z0 = svdiv_f64_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_m_tied1, svfloat64_t, double, + z0 = svdiv_n_f64_m (p0, z0, d4), + z0 = svdiv_m (p0, z0, d4)) + +/* +** div_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_m_untied, svfloat64_t, double, + z0 = svdiv_n_f64_m (p0, z1, d4), + z0 = svdiv_m (p0, z1, d4)) + +/* +** div_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_m_tied1, svfloat64_t, + z0 = svdiv_n_f64_m (p0, z0, 1), + z0 = svdiv_m (p0, z0, 1)) + +/* +** div_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_m_untied, svfloat64_t, + z0 = svdiv_n_f64_m (p0, z1, 1), + z0 = svdiv_m (p0, z1, 1)) + +/* +** div_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_z_tied1, svfloat64_t, + z0 = svdiv_f64_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_z_tied2, svfloat64_t, + z0 = svdiv_f64_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f64_z_untied, svfloat64_t, + z0 = svdiv_f64_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_z_tied1, svfloat64_t, double, + z0 = svdiv_n_f64_z (p0, z0, d4), + z0 = svdiv_z (p0, z0, d4)) + +/* +** div_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_z_untied, svfloat64_t, double, + z0 = svdiv_n_f64_z (p0, z1, d4), + z0 = svdiv_z (p0, z1, d4)) + +/* +** div_1_f64_z_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_z_tied1, svfloat64_t, + z0 = svdiv_n_f64_z (p0, z0, 1), + z0 = svdiv_z (p0, z0, 1)) + +/* +** div_1_f64_z_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_z_untied, svfloat64_t, + z0 = svdiv_n_f64_z (p0, z1, 1), + z0 = svdiv_z (p0, z1, 1)) + +/* +** div_0p5_f64_z: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0\.d, p0/z, z0\.d +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_0p5_f64_z, svfloat64_t, + z0 = svdiv_n_f64_z (p0, z0, 0.5), + z0 = svdiv_z (p0, z0, 0.5)) + +/* +** div_f64_x_tied1: +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_x_tied1, svfloat64_t, + z0 = svdiv_f64_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_f64_x_tied2: +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_f64_x_tied2, svfloat64_t, + z0 = svdiv_f64_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_f64_x_untied: +** ( +** movprfx z0, z1 +** fdiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_f64_x_untied, svfloat64_t, + z0 = svdiv_f64_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_x_tied1, svfloat64_t, double, + z0 = svdiv_n_f64_x (p0, z0, d4), + z0 = svdiv_x (p0, z0, d4)) + +/* +** div_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (div_d4_f64_x_untied, svfloat64_t, double, + z0 = svdiv_n_f64_x (p0, z1, d4), + z0 = svdiv_x (p0, z1, d4)) + +/* +** div_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_x_tied1, svfloat64_t, + z0 = svdiv_n_f64_x (p0, z0, 1), + z0 = svdiv_x (p0, z0, 1)) + +/* +** div_1_f64_x_untied: +** fmov z0\.d, #1\.0(?:e\+0)? +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_1_f64_x_untied, svfloat64_t, + z0 = svdiv_n_f64_x (p0, z1, 1), + z0 = svdiv_x (p0, z1, 1)) + +/* +** ptrue_div_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f64_x_tied1, svfloat64_t, + z0 = svdiv_f64_x (svptrue_b64 (), z0, z1), + z0 = svdiv_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_div_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f64_x_tied2, svfloat64_t, + z0 = svdiv_f64_x (svptrue_b64 (), z1, z0), + z0 = svdiv_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_div_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_f64_x_untied, svfloat64_t, + z0 = svdiv_f64_x (svptrue_b64 (), z1, z2), + z0 = svdiv_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_div_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f64_x_tied1, svfloat64_t, + z0 = svdiv_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svdiv_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_div_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_div_1_f64_x_untied, svfloat64_t, + z0 = svdiv_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svdiv_x (svptrue_b64 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s32.c new file mode 100644 index 00000000000..8e70ae797a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_s32_m_tied1: +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_m_tied1, svint32_t, + z0 = svdiv_s32_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sdiv z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_m_tied2, svint32_t, + z0 = svdiv_s32_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_s32_m_untied: +** movprfx z0, z1 +** sdiv z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_m_untied, svint32_t, + z0 = svdiv_s32_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svdiv_n_s32_m (p0, z0, x0), + z0 = svdiv_m (p0, z0, x0)) + +/* +** div_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_m_untied, svint32_t, int32_t, + z0 = svdiv_n_s32_m (p0, z1, x0), + z0 = svdiv_m (p0, z1, x0)) + +/* +** div_2_s32_m_tied1: +** mov (z[0-9]+\.s), #2 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_m_tied1, svint32_t, + z0 = svdiv_n_s32_m (p0, z0, 2), + z0 = svdiv_m (p0, z0, 2)) + +/* +** div_2_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_m_untied, svint32_t, + z0 = svdiv_n_s32_m (p0, z1, 2), + z0 = svdiv_m (p0, z1, 2)) + +/* +** div_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_z_tied1, svint32_t, + z0 = svdiv_s32_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_z_tied2, svint32_t, + z0 = svdiv_s32_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_s32_z_untied, svint32_t, + z0 = svdiv_s32_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svdiv_n_s32_z (p0, z0, x0), + z0 = svdiv_z (p0, z0, x0)) + +/* +** div_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_z_untied, svint32_t, int32_t, + z0 = svdiv_n_s32_z (p0, z1, x0), + z0 = svdiv_z (p0, z1, x0)) + +/* +** div_2_s32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_z_tied1, svint32_t, + z0 = svdiv_n_s32_z (p0, z0, 2), + z0 = svdiv_z (p0, z0, 2)) + +/* +** div_2_s32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_z_untied, svint32_t, + z0 = svdiv_n_s32_z (p0, z1, 2), + z0 = svdiv_z (p0, z1, 2)) + +/* +** div_s32_x_tied1: +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_x_tied1, svint32_t, + z0 = svdiv_s32_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_s32_x_tied2: +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_s32_x_tied2, svint32_t, + z0 = svdiv_s32_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_s32_x_untied: +** ( +** movprfx z0, z1 +** sdiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_s32_x_untied, svint32_t, + z0 = svdiv_s32_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svdiv_n_s32_x (p0, z0, x0), + z0 = svdiv_x (p0, z0, x0)) + +/* +** div_w0_s32_x_untied: +** mov z0\.s, w0 +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (div_w0_s32_x_untied, svint32_t, int32_t, + z0 = svdiv_n_s32_x (p0, z1, x0), + z0 = svdiv_x (p0, z1, x0)) + +/* +** div_2_s32_x_tied1: +** mov (z[0-9]+\.s), #2 +** sdiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_x_tied1, svint32_t, + z0 = svdiv_n_s32_x (p0, z0, 2), + z0 = svdiv_x (p0, z0, 2)) + +/* +** div_2_s32_x_untied: +** mov z0\.s, #2 +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_2_s32_x_untied, svint32_t, + z0 = svdiv_n_s32_x (p0, z1, 2), + z0 = svdiv_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s64.c new file mode 100644 index 00000000000..439da1f571f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_s64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_s64_m_tied1: +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_m_tied1, svint64_t, + z0 = svdiv_s64_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_s64_m_tied2, svint64_t, + z0 = svdiv_s64_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_s64_m_untied: +** movprfx z0, z1 +** sdiv z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_m_untied, svint64_t, + z0 = svdiv_s64_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svdiv_n_s64_m (p0, z0, x0), + z0 = svdiv_m (p0, z0, x0)) + +/* +** div_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_m_untied, svint64_t, int64_t, + z0 = svdiv_n_s64_m (p0, z1, x0), + z0 = svdiv_m (p0, z1, x0)) + +/* +** div_2_s64_m_tied1: +** mov (z[0-9]+\.d), #2 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_m_tied1, svint64_t, + z0 = svdiv_n_s64_m (p0, z0, 2), + z0 = svdiv_m (p0, z0, 2)) + +/* +** div_2_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_m_untied, svint64_t, + z0 = svdiv_n_s64_m (p0, z1, 2), + z0 = svdiv_m (p0, z1, 2)) + +/* +** div_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_z_tied1, svint64_t, + z0 = svdiv_s64_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_z_tied2, svint64_t, + z0 = svdiv_s64_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_s64_z_untied, svint64_t, + z0 = svdiv_s64_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svdiv_n_s64_z (p0, z0, x0), + z0 = svdiv_z (p0, z0, x0)) + +/* +** div_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_z_untied, svint64_t, int64_t, + z0 = svdiv_n_s64_z (p0, z1, x0), + z0 = svdiv_z (p0, z1, x0)) + +/* +** div_2_s64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_z_tied1, svint64_t, + z0 = svdiv_n_s64_z (p0, z0, 2), + z0 = svdiv_z (p0, z0, 2)) + +/* +** div_2_s64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_z_untied, svint64_t, + z0 = svdiv_n_s64_z (p0, z1, 2), + z0 = svdiv_z (p0, z1, 2)) + +/* +** div_s64_x_tied1: +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_x_tied1, svint64_t, + z0 = svdiv_s64_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_s64_x_tied2: +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_s64_x_tied2, svint64_t, + z0 = svdiv_s64_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_s64_x_untied: +** ( +** movprfx z0, z1 +** sdiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_s64_x_untied, svint64_t, + z0 = svdiv_s64_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svdiv_n_s64_x (p0, z0, x0), + z0 = svdiv_x (p0, z0, x0)) + +/* +** div_x0_s64_x_untied: +** mov z0\.d, x0 +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (div_x0_s64_x_untied, svint64_t, int64_t, + z0 = svdiv_n_s64_x (p0, z1, x0), + z0 = svdiv_x (p0, z1, x0)) + +/* +** div_2_s64_x_tied1: +** mov (z[0-9]+\.d), #2 +** sdiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_x_tied1, svint64_t, + z0 = svdiv_n_s64_x (p0, z0, 2), + z0 = svdiv_x (p0, z0, 2)) + +/* +** div_2_s64_x_untied: +** mov z0\.d, #2 +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_2_s64_x_untied, svint64_t, + z0 = svdiv_n_s64_x (p0, z1, 2), + z0 = svdiv_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u32.c new file mode 100644 index 00000000000..8e8e464b777 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_u32_m_tied1: +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_m_tied1, svuint32_t, + z0 = svdiv_u32_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** udiv z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_m_tied2, svuint32_t, + z0 = svdiv_u32_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_u32_m_untied: +** movprfx z0, z1 +** udiv z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_m_untied, svuint32_t, + z0 = svdiv_u32_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svdiv_n_u32_m (p0, z0, x0), + z0 = svdiv_m (p0, z0, x0)) + +/* +** div_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svdiv_n_u32_m (p0, z1, x0), + z0 = svdiv_m (p0, z1, x0)) + +/* +** div_2_u32_m_tied1: +** mov (z[0-9]+\.s), #2 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_m_tied1, svuint32_t, + z0 = svdiv_n_u32_m (p0, z0, 2), + z0 = svdiv_m (p0, z0, 2)) + +/* +** div_2_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_m_untied, svuint32_t, + z0 = svdiv_n_u32_m (p0, z1, 2), + z0 = svdiv_m (p0, z1, 2)) + +/* +** div_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_z_tied1, svuint32_t, + z0 = svdiv_u32_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_z_tied2, svuint32_t, + z0 = svdiv_u32_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** udiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_u32_z_untied, svuint32_t, + z0 = svdiv_u32_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svdiv_n_u32_z (p0, z0, x0), + z0 = svdiv_z (p0, z0, x0)) + +/* +** div_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** udiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svdiv_n_u32_z (p0, z1, x0), + z0 = svdiv_z (p0, z1, x0)) + +/* +** div_2_u32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_z_tied1, svuint32_t, + z0 = svdiv_n_u32_z (p0, z0, 2), + z0 = svdiv_z (p0, z0, 2)) + +/* +** div_2_u32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** udiv z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_z_untied, svuint32_t, + z0 = svdiv_n_u32_z (p0, z1, 2), + z0 = svdiv_z (p0, z1, 2)) + +/* +** div_u32_x_tied1: +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_x_tied1, svuint32_t, + z0 = svdiv_u32_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_u32_x_tied2: +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_u32_x_tied2, svuint32_t, + z0 = svdiv_u32_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_u32_x_untied: +** ( +** movprfx z0, z1 +** udiv z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (div_u32_x_untied, svuint32_t, + z0 = svdiv_u32_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svdiv_n_u32_x (p0, z0, x0), + z0 = svdiv_x (p0, z0, x0)) + +/* +** div_w0_u32_x_untied: +** mov z0\.s, w0 +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (div_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svdiv_n_u32_x (p0, z1, x0), + z0 = svdiv_x (p0, z1, x0)) + +/* +** div_2_u32_x_tied1: +** mov (z[0-9]+\.s), #2 +** udiv z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_x_tied1, svuint32_t, + z0 = svdiv_n_u32_x (p0, z0, 2), + z0 = svdiv_x (p0, z0, 2)) + +/* +** div_2_u32_x_untied: +** mov z0\.s, #2 +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (div_2_u32_x_untied, svuint32_t, + z0 = svdiv_n_u32_x (p0, z1, 2), + z0 = svdiv_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u64.c new file mode 100644 index 00000000000..fc152e8e57b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/div_u64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** div_u64_m_tied1: +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_m_tied1, svuint64_t, + z0 = svdiv_u64_m (p0, z0, z1), + z0 = svdiv_m (p0, z0, z1)) + +/* +** div_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_u64_m_tied2, svuint64_t, + z0 = svdiv_u64_m (p0, z1, z0), + z0 = svdiv_m (p0, z1, z0)) + +/* +** div_u64_m_untied: +** movprfx z0, z1 +** udiv z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_m_untied, svuint64_t, + z0 = svdiv_u64_m (p0, z1, z2), + z0 = svdiv_m (p0, z1, z2)) + +/* +** div_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svdiv_n_u64_m (p0, z0, x0), + z0 = svdiv_m (p0, z0, x0)) + +/* +** div_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svdiv_n_u64_m (p0, z1, x0), + z0 = svdiv_m (p0, z1, x0)) + +/* +** div_2_u64_m_tied1: +** mov (z[0-9]+\.d), #2 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_m_tied1, svuint64_t, + z0 = svdiv_n_u64_m (p0, z0, 2), + z0 = svdiv_m (p0, z0, 2)) + +/* +** div_2_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_m_untied, svuint64_t, + z0 = svdiv_n_u64_m (p0, z1, 2), + z0 = svdiv_m (p0, z1, 2)) + +/* +** div_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_z_tied1, svuint64_t, + z0 = svdiv_u64_z (p0, z0, z1), + z0 = svdiv_z (p0, z0, z1)) + +/* +** div_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_z_tied2, svuint64_t, + z0 = svdiv_u64_z (p0, z1, z0), + z0 = svdiv_z (p0, z1, z0)) + +/* +** div_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** udiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_u64_z_untied, svuint64_t, + z0 = svdiv_u64_z (p0, z1, z2), + z0 = svdiv_z (p0, z1, z2)) + +/* +** div_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svdiv_n_u64_z (p0, z0, x0), + z0 = svdiv_z (p0, z0, x0)) + +/* +** div_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** udiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svdiv_n_u64_z (p0, z1, x0), + z0 = svdiv_z (p0, z1, x0)) + +/* +** div_2_u64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_z_tied1, svuint64_t, + z0 = svdiv_n_u64_z (p0, z0, 2), + z0 = svdiv_z (p0, z0, 2)) + +/* +** div_2_u64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** udiv z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_z_untied, svuint64_t, + z0 = svdiv_n_u64_z (p0, z1, 2), + z0 = svdiv_z (p0, z1, 2)) + +/* +** div_u64_x_tied1: +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_x_tied1, svuint64_t, + z0 = svdiv_u64_x (p0, z0, z1), + z0 = svdiv_x (p0, z0, z1)) + +/* +** div_u64_x_tied2: +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_u64_x_tied2, svuint64_t, + z0 = svdiv_u64_x (p0, z1, z0), + z0 = svdiv_x (p0, z1, z0)) + +/* +** div_u64_x_untied: +** ( +** movprfx z0, z1 +** udiv z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (div_u64_x_untied, svuint64_t, + z0 = svdiv_u64_x (p0, z1, z2), + z0 = svdiv_x (p0, z1, z2)) + +/* +** div_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svdiv_n_u64_x (p0, z0, x0), + z0 = svdiv_x (p0, z0, x0)) + +/* +** div_x0_u64_x_untied: +** mov z0\.d, x0 +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (div_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svdiv_n_u64_x (p0, z1, x0), + z0 = svdiv_x (p0, z1, x0)) + +/* +** div_2_u64_x_tied1: +** mov (z[0-9]+\.d), #2 +** udiv z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_x_tied1, svuint64_t, + z0 = svdiv_n_u64_x (p0, z0, 2), + z0 = svdiv_x (p0, z0, 2)) + +/* +** div_2_u64_x_untied: +** mov z0\.d, #2 +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (div_2_u64_x_untied, svuint64_t, + z0 = svdiv_n_u64_x (p0, z1, 2), + z0 = svdiv_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f16.c new file mode 100644 index 00000000000..03cc0343bd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f16.c @@ -0,0 +1,324 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_f16_m_tied1: +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_m_tied1, svfloat16_t, + z0 = svdivr_f16_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_m_tied2, svfloat16_t, + z0 = svdivr_f16_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_f16_m_untied: +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_m_untied, svfloat16_t, + z0 = svdivr_f16_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svdivr_n_f16_m (p0, z0, d4), + z0 = svdivr_m (p0, z0, d4)) + +/* +** divr_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svdivr_n_f16_m (p0, z1, d4), + z0 = svdivr_m (p0, z1, d4)) + +/* +** divr_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f16_m_tied1, svfloat16_t, + z0 = svdivr_n_f16_m (p0, z0, 1), + z0 = svdivr_m (p0, z0, 1)) + +/* +** divr_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f16_m_untied, svfloat16_t, + z0 = svdivr_n_f16_m (p0, z1, 1), + z0 = svdivr_m (p0, z1, 1)) + +/* +** divr_0p5_f16_m_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f16_m_tied1, svfloat16_t, + z0 = svdivr_n_f16_m (p0, z0, 0.5), + z0 = svdivr_m (p0, z0, 0.5)) + +/* +** divr_0p5_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f16_m_untied, svfloat16_t, + z0 = svdivr_n_f16_m (p0, z1, 0.5), + z0 = svdivr_m (p0, z1, 0.5)) + +/* +** divr_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_z_tied1, svfloat16_t, + z0 = svdivr_f16_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_z_tied2, svfloat16_t, + z0 = svdivr_f16_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdivr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f16_z_untied, svfloat16_t, + z0 = svdivr_f16_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svdivr_n_f16_z (p0, z0, d4), + z0 = svdivr_z (p0, z0, d4)) + +/* +** divr_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdivr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svdivr_n_f16_z (p0, z1, d4), + z0 = svdivr_z (p0, z1, d4)) + +/* +** divr_1_f16_z: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f16_z, svfloat16_t, + z0 = svdivr_n_f16_z (p0, z0, 1), + z0 = svdivr_z (p0, z0, 1)) + +/* +** divr_0p5_f16_z_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0\.h, p0/z, z0\.h +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f16_z_tied1, svfloat16_t, + z0 = svdivr_n_f16_z (p0, z0, 0.5), + z0 = svdivr_z (p0, z0, 0.5)) + +/* +** divr_0p5_f16_z_untied: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.h, p0/z, z1\.h +** fdivr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f16_z_untied, svfloat16_t, + z0 = svdivr_n_f16_z (p0, z1, 0.5), + z0 = svdivr_z (p0, z1, 0.5)) + +/* +** divr_f16_x_tied1: +** fdivr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_x_tied1, svfloat16_t, + z0 = svdivr_f16_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_f16_x_tied2: +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_f16_x_tied2, svfloat16_t, + z0 = svdivr_f16_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_f16_x_untied: +** ( +** movprfx z0, z1 +** fdivr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f16_x_untied, svfloat16_t, + z0 = svdivr_f16_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svdivr_n_f16_x (p0, z0, d4), + z0 = svdivr_x (p0, z0, d4)) + +/* +** divr_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (divr_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svdivr_n_f16_x (p0, z1, d4), + z0 = svdivr_x (p0, z1, d4)) + +/* +** divr_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fdivr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f16_x_tied1, svfloat16_t, + z0 = svdivr_n_f16_x (p0, z0, 1), + z0 = svdivr_x (p0, z0, 1)) + +/* +** divr_1_f16_x_untied: +** fmov z0\.h, #1\.0(?:e\+0)? +** fdiv z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (divr_1_f16_x_untied, svfloat16_t, + z0 = svdivr_n_f16_x (p0, z1, 1), + z0 = svdivr_x (p0, z1, 1)) + +/* +** ptrue_divr_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f16_x_tied1, svfloat16_t, + z0 = svdivr_f16_x (svptrue_b16 (), z0, z1), + z0 = svdivr_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_divr_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f16_x_tied2, svfloat16_t, + z0 = svdivr_f16_x (svptrue_b16 (), z1, z0), + z0 = svdivr_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_divr_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f16_x_untied, svfloat16_t, + z0 = svdivr_f16_x (svptrue_b16 (), z1, z2), + z0 = svdivr_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_divr_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f16_x_tied1, svfloat16_t, + z0 = svdivr_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svdivr_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_divr_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f16_x_untied, svfloat16_t, + z0 = svdivr_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svdivr_x (svptrue_b16 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f32.c new file mode 100644 index 00000000000..c2b65fc33fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f32.c @@ -0,0 +1,324 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_f32_m_tied1: +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_m_tied1, svfloat32_t, + z0 = svdivr_f32_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_m_tied2, svfloat32_t, + z0 = svdivr_f32_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_f32_m_untied: +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_m_untied, svfloat32_t, + z0 = svdivr_f32_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_m_tied1, svfloat32_t, float, + z0 = svdivr_n_f32_m (p0, z0, d4), + z0 = svdivr_m (p0, z0, d4)) + +/* +** divr_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_m_untied, svfloat32_t, float, + z0 = svdivr_n_f32_m (p0, z1, d4), + z0 = svdivr_m (p0, z1, d4)) + +/* +** divr_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f32_m_tied1, svfloat32_t, + z0 = svdivr_n_f32_m (p0, z0, 1), + z0 = svdivr_m (p0, z0, 1)) + +/* +** divr_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f32_m_untied, svfloat32_t, + z0 = svdivr_n_f32_m (p0, z1, 1), + z0 = svdivr_m (p0, z1, 1)) + +/* +** divr_0p5_f32_m_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f32_m_tied1, svfloat32_t, + z0 = svdivr_n_f32_m (p0, z0, 0.5), + z0 = svdivr_m (p0, z0, 0.5)) + +/* +** divr_0p5_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f32_m_untied, svfloat32_t, + z0 = svdivr_n_f32_m (p0, z1, 0.5), + z0 = svdivr_m (p0, z1, 0.5)) + +/* +** divr_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_z_tied1, svfloat32_t, + z0 = svdivr_f32_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_z_tied2, svfloat32_t, + z0 = svdivr_f32_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f32_z_untied, svfloat32_t, + z0 = svdivr_f32_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_z_tied1, svfloat32_t, float, + z0 = svdivr_n_f32_z (p0, z0, d4), + z0 = svdivr_z (p0, z0, d4)) + +/* +** divr_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_z_untied, svfloat32_t, float, + z0 = svdivr_n_f32_z (p0, z1, d4), + z0 = svdivr_z (p0, z1, d4)) + +/* +** divr_1_f32_z: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f32_z, svfloat32_t, + z0 = svdivr_n_f32_z (p0, z0, 1), + z0 = svdivr_z (p0, z0, 1)) + +/* +** divr_0p5_f32_z_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0\.s, p0/z, z0\.s +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f32_z_tied1, svfloat32_t, + z0 = svdivr_n_f32_z (p0, z0, 0.5), + z0 = svdivr_z (p0, z0, 0.5)) + +/* +** divr_0p5_f32_z_untied: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.s, p0/z, z1\.s +** fdivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f32_z_untied, svfloat32_t, + z0 = svdivr_n_f32_z (p0, z1, 0.5), + z0 = svdivr_z (p0, z1, 0.5)) + +/* +** divr_f32_x_tied1: +** fdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_x_tied1, svfloat32_t, + z0 = svdivr_f32_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_f32_x_tied2: +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_f32_x_tied2, svfloat32_t, + z0 = svdivr_f32_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_f32_x_untied: +** ( +** movprfx z0, z1 +** fdivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f32_x_untied, svfloat32_t, + z0 = svdivr_f32_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_x_tied1, svfloat32_t, float, + z0 = svdivr_n_f32_x (p0, z0, d4), + z0 = svdivr_x (p0, z0, d4)) + +/* +** divr_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (divr_s4_f32_x_untied, svfloat32_t, float, + z0 = svdivr_n_f32_x (p0, z1, d4), + z0 = svdivr_x (p0, z1, d4)) + +/* +** divr_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f32_x_tied1, svfloat32_t, + z0 = svdivr_n_f32_x (p0, z0, 1), + z0 = svdivr_x (p0, z0, 1)) + +/* +** divr_1_f32_x_untied: +** fmov z0\.s, #1\.0(?:e\+0)? +** fdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_1_f32_x_untied, svfloat32_t, + z0 = svdivr_n_f32_x (p0, z1, 1), + z0 = svdivr_x (p0, z1, 1)) + +/* +** ptrue_divr_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f32_x_tied1, svfloat32_t, + z0 = svdivr_f32_x (svptrue_b32 (), z0, z1), + z0 = svdivr_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_divr_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f32_x_tied2, svfloat32_t, + z0 = svdivr_f32_x (svptrue_b32 (), z1, z0), + z0 = svdivr_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_divr_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f32_x_untied, svfloat32_t, + z0 = svdivr_f32_x (svptrue_b32 (), z1, z2), + z0 = svdivr_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_divr_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f32_x_tied1, svfloat32_t, + z0 = svdivr_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svdivr_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_divr_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f32_x_untied, svfloat32_t, + z0 = svdivr_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svdivr_x (svptrue_b32 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f64.c new file mode 100644 index 00000000000..0a72a37b1d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_f64.c @@ -0,0 +1,324 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_f64_m_tied1: +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_m_tied1, svfloat64_t, + z0 = svdivr_f64_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_f64_m_tied2, svfloat64_t, + z0 = svdivr_f64_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_f64_m_untied: +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_m_untied, svfloat64_t, + z0 = svdivr_f64_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_m_tied1, svfloat64_t, double, + z0 = svdivr_n_f64_m (p0, z0, d4), + z0 = svdivr_m (p0, z0, d4)) + +/* +** divr_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_m_untied, svfloat64_t, double, + z0 = svdivr_n_f64_m (p0, z1, d4), + z0 = svdivr_m (p0, z1, d4)) + +/* +** divr_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f64_m_tied1, svfloat64_t, + z0 = svdivr_n_f64_m (p0, z0, 1), + z0 = svdivr_m (p0, z0, 1)) + +/* +** divr_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f64_m_untied, svfloat64_t, + z0 = svdivr_n_f64_m (p0, z1, 1), + z0 = svdivr_m (p0, z1, 1)) + +/* +** divr_0p5_f64_m_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f64_m_tied1, svfloat64_t, + z0 = svdivr_n_f64_m (p0, z0, 0.5), + z0 = svdivr_m (p0, z0, 0.5)) + +/* +** divr_0p5_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f64_m_untied, svfloat64_t, + z0 = svdivr_n_f64_m (p0, z1, 0.5), + z0 = svdivr_m (p0, z1, 0.5)) + +/* +** divr_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_z_tied1, svfloat64_t, + z0 = svdivr_f64_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_z_tied2, svfloat64_t, + z0 = svdivr_f64_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f64_z_untied, svfloat64_t, + z0 = svdivr_f64_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_z_tied1, svfloat64_t, double, + z0 = svdivr_n_f64_z (p0, z0, d4), + z0 = svdivr_z (p0, z0, d4)) + +/* +** divr_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_z_untied, svfloat64_t, double, + z0 = svdivr_n_f64_z (p0, z1, d4), + z0 = svdivr_z (p0, z1, d4)) + +/* +** divr_1_f64_z: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f64_z, svfloat64_t, + z0 = svdivr_n_f64_z (p0, z0, 1), + z0 = svdivr_z (p0, z0, 1)) + +/* +** divr_0p5_f64_z_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0\.d, p0/z, z0\.d +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f64_z_tied1, svfloat64_t, + z0 = svdivr_n_f64_z (p0, z0, 0.5), + z0 = svdivr_z (p0, z0, 0.5)) + +/* +** divr_0p5_f64_z_untied: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.d, p0/z, z1\.d +** fdivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_0p5_f64_z_untied, svfloat64_t, + z0 = svdivr_n_f64_z (p0, z1, 0.5), + z0 = svdivr_z (p0, z1, 0.5)) + +/* +** divr_f64_x_tied1: +** fdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_x_tied1, svfloat64_t, + z0 = svdivr_f64_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_f64_x_tied2: +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_f64_x_tied2, svfloat64_t, + z0 = svdivr_f64_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_f64_x_untied: +** ( +** movprfx z0, z1 +** fdivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_f64_x_untied, svfloat64_t, + z0 = svdivr_f64_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_x_tied1, svfloat64_t, double, + z0 = svdivr_n_f64_x (p0, z0, d4), + z0 = svdivr_x (p0, z0, d4)) + +/* +** divr_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (divr_d4_f64_x_untied, svfloat64_t, double, + z0 = svdivr_n_f64_x (p0, z1, d4), + z0 = svdivr_x (p0, z1, d4)) + +/* +** divr_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_1_f64_x_tied1, svfloat64_t, + z0 = svdivr_n_f64_x (p0, z0, 1), + z0 = svdivr_x (p0, z0, 1)) + +/* +** divr_1_f64_x_untied: +** fmov z0\.d, #1\.0(?:e\+0)? +** fdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_1_f64_x_untied, svfloat64_t, + z0 = svdivr_n_f64_x (p0, z1, 1), + z0 = svdivr_x (p0, z1, 1)) + +/* +** ptrue_divr_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f64_x_tied1, svfloat64_t, + z0 = svdivr_f64_x (svptrue_b64 (), z0, z1), + z0 = svdivr_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_divr_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f64_x_tied2, svfloat64_t, + z0 = svdivr_f64_x (svptrue_b64 (), z1, z0), + z0 = svdivr_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_divr_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_f64_x_untied, svfloat64_t, + z0 = svdivr_f64_x (svptrue_b64 (), z1, z2), + z0 = svdivr_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_divr_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f64_x_tied1, svfloat64_t, + z0 = svdivr_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svdivr_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_divr_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_divr_1_f64_x_untied, svfloat64_t, + z0 = svdivr_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svdivr_x (svptrue_b64 (), z1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s32.c new file mode 100644 index 00000000000..75a6c1d979d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s32.c @@ -0,0 +1,247 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_s32_m_tied1: +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_m_tied1, svint32_t, + z0 = svdivr_s32_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sdivr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_m_tied2, svint32_t, + z0 = svdivr_s32_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_s32_m_untied: +** movprfx z0, z1 +** sdivr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_m_untied, svint32_t, + z0 = svdivr_s32_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svdivr_n_s32_m (p0, z0, x0), + z0 = svdivr_m (p0, z0, x0)) + +/* +** divr_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_m_untied, svint32_t, int32_t, + z0 = svdivr_n_s32_m (p0, z1, x0), + z0 = svdivr_m (p0, z1, x0)) + +/* +** divr_2_s32_m_tied1: +** mov (z[0-9]+\.s), #2 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_m_tied1, svint32_t, + z0 = svdivr_n_s32_m (p0, z0, 2), + z0 = svdivr_m (p0, z0, 2)) + +/* +** divr_2_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_m_untied, svint32_t, + z0 = svdivr_n_s32_m (p0, z1, 2), + z0 = svdivr_m (p0, z1, 2)) + +/* +** divr_m1_s32_m: +** mov (z[0-9]+)\.b, #-1 +** sdivr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_m1_s32_m, svint32_t, + z0 = svdivr_n_s32_m (p0, z0, -1), + z0 = svdivr_m (p0, z0, -1)) + +/* +** divr_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_z_tied1, svint32_t, + z0 = svdivr_s32_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_z_tied2, svint32_t, + z0 = svdivr_s32_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_s32_z_untied, svint32_t, + z0 = svdivr_s32_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svdivr_n_s32_z (p0, z0, x0), + z0 = svdivr_z (p0, z0, x0)) + +/* +** divr_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_z_untied, svint32_t, int32_t, + z0 = svdivr_n_s32_z (p0, z1, x0), + z0 = svdivr_z (p0, z1, x0)) + +/* +** divr_2_s32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_z_tied1, svint32_t, + z0 = svdivr_n_s32_z (p0, z0, 2), + z0 = svdivr_z (p0, z0, 2)) + +/* +** divr_2_s32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sdivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_z_untied, svint32_t, + z0 = svdivr_n_s32_z (p0, z1, 2), + z0 = svdivr_z (p0, z1, 2)) + +/* +** divr_s32_x_tied1: +** sdivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_x_tied1, svint32_t, + z0 = svdivr_s32_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_s32_x_tied2: +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_s32_x_tied2, svint32_t, + z0 = svdivr_s32_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_s32_x_untied: +** ( +** movprfx z0, z1 +** sdivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_s32_x_untied, svint32_t, + z0 = svdivr_s32_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svdivr_n_s32_x (p0, z0, x0), + z0 = svdivr_x (p0, z0, x0)) + +/* +** divr_w0_s32_x_untied: +** mov z0\.s, w0 +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_s32_x_untied, svint32_t, int32_t, + z0 = svdivr_n_s32_x (p0, z1, x0), + z0 = svdivr_x (p0, z1, x0)) + +/* +** divr_2_s32_x_tied1: +** mov (z[0-9]+\.s), #2 +** sdivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_x_tied1, svint32_t, + z0 = svdivr_n_s32_x (p0, z0, 2), + z0 = svdivr_x (p0, z0, 2)) + +/* +** divr_2_s32_x_untied: +** mov z0\.s, #2 +** sdiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_2_s32_x_untied, svint32_t, + z0 = svdivr_n_s32_x (p0, z1, 2), + z0 = svdivr_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s64.c new file mode 100644 index 00000000000..8f4939a91fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_s64.c @@ -0,0 +1,247 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_s64_m_tied1: +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_m_tied1, svint64_t, + z0 = svdivr_s64_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_s64_m_tied2, svint64_t, + z0 = svdivr_s64_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_s64_m_untied: +** movprfx z0, z1 +** sdivr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_m_untied, svint64_t, + z0 = svdivr_s64_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svdivr_n_s64_m (p0, z0, x0), + z0 = svdivr_m (p0, z0, x0)) + +/* +** divr_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_m_untied, svint64_t, int64_t, + z0 = svdivr_n_s64_m (p0, z1, x0), + z0 = svdivr_m (p0, z1, x0)) + +/* +** divr_2_s64_m_tied1: +** mov (z[0-9]+\.d), #2 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_m_tied1, svint64_t, + z0 = svdivr_n_s64_m (p0, z0, 2), + z0 = svdivr_m (p0, z0, 2)) + +/* +** divr_2_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_m_untied, svint64_t, + z0 = svdivr_n_s64_m (p0, z1, 2), + z0 = svdivr_m (p0, z1, 2)) + +/* +** divr_m1_s64_m: +** mov (z[0-9]+)\.b, #-1 +** sdivr z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_m1_s64_m, svint64_t, + z0 = svdivr_n_s64_m (p0, z0, -1), + z0 = svdivr_m (p0, z0, -1)) + +/* +** divr_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_z_tied1, svint64_t, + z0 = svdivr_s64_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_z_tied2, svint64_t, + z0 = svdivr_s64_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_s64_z_untied, svint64_t, + z0 = svdivr_s64_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svdivr_n_s64_z (p0, z0, x0), + z0 = svdivr_z (p0, z0, x0)) + +/* +** divr_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_z_untied, svint64_t, int64_t, + z0 = svdivr_n_s64_z (p0, z1, x0), + z0 = svdivr_z (p0, z1, x0)) + +/* +** divr_2_s64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_z_tied1, svint64_t, + z0 = svdivr_n_s64_z (p0, z0, 2), + z0 = svdivr_z (p0, z0, 2)) + +/* +** divr_2_s64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sdivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_z_untied, svint64_t, + z0 = svdivr_n_s64_z (p0, z1, 2), + z0 = svdivr_z (p0, z1, 2)) + +/* +** divr_s64_x_tied1: +** sdivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_x_tied1, svint64_t, + z0 = svdivr_s64_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_s64_x_tied2: +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_s64_x_tied2, svint64_t, + z0 = svdivr_s64_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_s64_x_untied: +** ( +** movprfx z0, z1 +** sdivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_s64_x_untied, svint64_t, + z0 = svdivr_s64_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svdivr_n_s64_x (p0, z0, x0), + z0 = svdivr_x (p0, z0, x0)) + +/* +** divr_x0_s64_x_untied: +** mov z0\.d, x0 +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_s64_x_untied, svint64_t, int64_t, + z0 = svdivr_n_s64_x (p0, z1, x0), + z0 = svdivr_x (p0, z1, x0)) + +/* +** divr_2_s64_x_tied1: +** mov (z[0-9]+\.d), #2 +** sdivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_x_tied1, svint64_t, + z0 = svdivr_n_s64_x (p0, z0, 2), + z0 = svdivr_x (p0, z0, 2)) + +/* +** divr_2_s64_x_untied: +** mov z0\.d, #2 +** sdiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_2_s64_x_untied, svint64_t, + z0 = svdivr_n_s64_x (p0, z1, 2), + z0 = svdivr_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u32.c new file mode 100644 index 00000000000..84c243b44c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u32.c @@ -0,0 +1,247 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_u32_m_tied1: +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_m_tied1, svuint32_t, + z0 = svdivr_u32_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** udivr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_m_tied2, svuint32_t, + z0 = svdivr_u32_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_u32_m_untied: +** movprfx z0, z1 +** udivr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_m_untied, svuint32_t, + z0 = svdivr_u32_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svdivr_n_u32_m (p0, z0, x0), + z0 = svdivr_m (p0, z0, x0)) + +/* +** divr_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svdivr_n_u32_m (p0, z1, x0), + z0 = svdivr_m (p0, z1, x0)) + +/* +** divr_2_u32_m_tied1: +** mov (z[0-9]+\.s), #2 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_m_tied1, svuint32_t, + z0 = svdivr_n_u32_m (p0, z0, 2), + z0 = svdivr_m (p0, z0, 2)) + +/* +** divr_2_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_m_untied, svuint32_t, + z0 = svdivr_n_u32_m (p0, z1, 2), + z0 = svdivr_m (p0, z1, 2)) + +/* +** divr_m1_u32_m: +** mov (z[0-9]+)\.b, #-1 +** udivr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_m1_u32_m, svuint32_t, + z0 = svdivr_n_u32_m (p0, z0, -1), + z0 = svdivr_m (p0, z0, -1)) + +/* +** divr_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_z_tied1, svuint32_t, + z0 = svdivr_u32_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_z_tied2, svuint32_t, + z0 = svdivr_u32_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** udivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_u32_z_untied, svuint32_t, + z0 = svdivr_u32_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svdivr_n_u32_z (p0, z0, x0), + z0 = svdivr_z (p0, z0, x0)) + +/* +** divr_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** udivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svdivr_n_u32_z (p0, z1, x0), + z0 = svdivr_z (p0, z1, x0)) + +/* +** divr_2_u32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_z_tied1, svuint32_t, + z0 = svdivr_n_u32_z (p0, z0, 2), + z0 = svdivr_z (p0, z0, 2)) + +/* +** divr_2_u32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** udivr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_z_untied, svuint32_t, + z0 = svdivr_n_u32_z (p0, z1, 2), + z0 = svdivr_z (p0, z1, 2)) + +/* +** divr_u32_x_tied1: +** udivr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_x_tied1, svuint32_t, + z0 = svdivr_u32_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_u32_x_tied2: +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_u32_x_tied2, svuint32_t, + z0 = svdivr_u32_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_u32_x_untied: +** ( +** movprfx z0, z1 +** udivr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_u32_x_untied, svuint32_t, + z0 = svdivr_u32_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svdivr_n_u32_x (p0, z0, x0), + z0 = svdivr_x (p0, z0, x0)) + +/* +** divr_w0_u32_x_untied: +** mov z0\.s, w0 +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (divr_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svdivr_n_u32_x (p0, z1, x0), + z0 = svdivr_x (p0, z1, x0)) + +/* +** divr_2_u32_x_tied1: +** mov (z[0-9]+\.s), #2 +** udivr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_x_tied1, svuint32_t, + z0 = svdivr_n_u32_x (p0, z0, 2), + z0 = svdivr_x (p0, z0, 2)) + +/* +** divr_2_u32_x_untied: +** mov z0\.s, #2 +** udiv z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (divr_2_u32_x_untied, svuint32_t, + z0 = svdivr_n_u32_x (p0, z1, 2), + z0 = svdivr_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u64.c new file mode 100644 index 00000000000..03bb624726f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/divr_u64.c @@ -0,0 +1,247 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** divr_u64_m_tied1: +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_m_tied1, svuint64_t, + z0 = svdivr_u64_m (p0, z0, z1), + z0 = svdivr_m (p0, z0, z1)) + +/* +** divr_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_u64_m_tied2, svuint64_t, + z0 = svdivr_u64_m (p0, z1, z0), + z0 = svdivr_m (p0, z1, z0)) + +/* +** divr_u64_m_untied: +** movprfx z0, z1 +** udivr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_m_untied, svuint64_t, + z0 = svdivr_u64_m (p0, z1, z2), + z0 = svdivr_m (p0, z1, z2)) + +/* +** divr_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svdivr_n_u64_m (p0, z0, x0), + z0 = svdivr_m (p0, z0, x0)) + +/* +** divr_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svdivr_n_u64_m (p0, z1, x0), + z0 = svdivr_m (p0, z1, x0)) + +/* +** divr_2_u64_m_tied1: +** mov (z[0-9]+\.d), #2 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_m_tied1, svuint64_t, + z0 = svdivr_n_u64_m (p0, z0, 2), + z0 = svdivr_m (p0, z0, 2)) + +/* +** divr_2_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_m_untied, svuint64_t, + z0 = svdivr_n_u64_m (p0, z1, 2), + z0 = svdivr_m (p0, z1, 2)) + +/* +** divr_m1_u64_m: +** mov (z[0-9]+)\.b, #-1 +** udivr z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_m1_u64_m, svuint64_t, + z0 = svdivr_n_u64_m (p0, z0, -1), + z0 = svdivr_m (p0, z0, -1)) + +/* +** divr_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_z_tied1, svuint64_t, + z0 = svdivr_u64_z (p0, z0, z1), + z0 = svdivr_z (p0, z0, z1)) + +/* +** divr_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_z_tied2, svuint64_t, + z0 = svdivr_u64_z (p0, z1, z0), + z0 = svdivr_z (p0, z1, z0)) + +/* +** divr_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** udivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_u64_z_untied, svuint64_t, + z0 = svdivr_u64_z (p0, z1, z2), + z0 = svdivr_z (p0, z1, z2)) + +/* +** divr_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svdivr_n_u64_z (p0, z0, x0), + z0 = svdivr_z (p0, z0, x0)) + +/* +** divr_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** udivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svdivr_n_u64_z (p0, z1, x0), + z0 = svdivr_z (p0, z1, x0)) + +/* +** divr_2_u64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_z_tied1, svuint64_t, + z0 = svdivr_n_u64_z (p0, z0, 2), + z0 = svdivr_z (p0, z0, 2)) + +/* +** divr_2_u64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** udivr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_z_untied, svuint64_t, + z0 = svdivr_n_u64_z (p0, z1, 2), + z0 = svdivr_z (p0, z1, 2)) + +/* +** divr_u64_x_tied1: +** udivr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_x_tied1, svuint64_t, + z0 = svdivr_u64_x (p0, z0, z1), + z0 = svdivr_x (p0, z0, z1)) + +/* +** divr_u64_x_tied2: +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_u64_x_tied2, svuint64_t, + z0 = svdivr_u64_x (p0, z1, z0), + z0 = svdivr_x (p0, z1, z0)) + +/* +** divr_u64_x_untied: +** ( +** movprfx z0, z1 +** udivr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (divr_u64_x_untied, svuint64_t, + z0 = svdivr_u64_x (p0, z1, z2), + z0 = svdivr_x (p0, z1, z2)) + +/* +** divr_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svdivr_n_u64_x (p0, z0, x0), + z0 = svdivr_x (p0, z0, x0)) + +/* +** divr_x0_u64_x_untied: +** mov z0\.d, x0 +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (divr_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svdivr_n_u64_x (p0, z1, x0), + z0 = svdivr_x (p0, z1, x0)) + +/* +** divr_2_u64_x_tied1: +** mov (z[0-9]+\.d), #2 +** udivr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_x_tied1, svuint64_t, + z0 = svdivr_n_u64_x (p0, z0, 2), + z0 = svdivr_x (p0, z0, 2)) + +/* +** divr_2_u64_x_untied: +** mov z0\.d, #2 +** udiv z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (divr_2_u64_x_untied, svuint64_t, + z0 = svdivr_n_u64_x (p0, z1, 2), + z0 = svdivr_x (p0, z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s32.c new file mode 100644 index 00000000000..a4d713e295f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s32.c @@ -0,0 +1,93 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_lane_0_s32_tied1: +** sdot z0\.s, z4\.b, z5\.b\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_s32_tied1, svint32_t, svint8_t, + z0 = svdot_lane_s32 (z0, z4, z5, 0), + z0 = svdot_lane (z0, z4, z5, 0)) + +/* +** dot_lane_0_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.s, \1\.b, z1\.b\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_s32_tied2, svint32_t, svint8_t, + z0_res = svdot_lane_s32 (z4, z0, z1, 0), + z0_res = svdot_lane (z4, z0, z1, 0)) + +/* +** dot_lane_0_s32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.s, z1\.b, \1\.b\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_s32_tied3, svint32_t, svint8_t, + z0_res = svdot_lane_s32 (z4, z1, z0, 0), + z0_res = svdot_lane (z4, z1, z0, 0)) + +/* +** dot_lane_0_s32_untied: +** movprfx z0, z1 +** sdot z0\.s, z4\.b, z5\.b\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_s32_untied, svint32_t, svint8_t, + z0 = svdot_lane_s32 (z1, z4, z5, 0), + z0 = svdot_lane (z1, z4, z5, 0)) + +/* +** dot_lane_1_s32: +** sdot z0\.s, z4\.b, z5\.b\[1\] +** ret +*/ +TEST_DUAL_Z (dot_lane_1_s32, svint32_t, svint8_t, + z0 = svdot_lane_s32 (z0, z4, z5, 1), + z0 = svdot_lane (z0, z4, z5, 1)) + +/* +** dot_lane_2_s32: +** sdot z0\.s, z4\.b, z5\.b\[2\] +** ret +*/ +TEST_DUAL_Z (dot_lane_2_s32, svint32_t, svint8_t, + z0 = svdot_lane_s32 (z0, z4, z5, 2), + z0 = svdot_lane (z0, z4, z5, 2)) + +/* +** dot_lane_3_s32: +** sdot z0\.s, z4\.b, z5\.b\[3\] +** ret +*/ +TEST_DUAL_Z (dot_lane_3_s32, svint32_t, svint8_t, + z0 = svdot_lane_s32 (z0, z4, z5, 3), + z0 = svdot_lane (z0, z4, z5, 3)) + +/* +** dot_lane_z8_s32: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** sdot z0\.s, z1\.b, \1\.b\[1\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z8_s32, svint32_t, svint8_t, z8, + z0 = svdot_lane_s32 (z0, z1, z8, 1), + z0 = svdot_lane (z0, z1, z8, 1)) + +/* +** dot_lane_z16_s32: +** mov (z[0-7])\.d, z16\.d +** sdot z0\.s, z1\.b, \1\.b\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z16_s32, svint32_t, svint8_t, z16, + z0 = svdot_lane_s32 (z0, z1, z16, 1), + z0 = svdot_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s64.c new file mode 100644 index 00000000000..daee74091ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_s64.c @@ -0,0 +1,74 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_lane_0_s64_tied1: +** sdot z0\.d, z4\.h, z5\.h\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_s64_tied1, svint64_t, svint16_t, + z0 = svdot_lane_s64 (z0, z4, z5, 0), + z0 = svdot_lane (z0, z4, z5, 0)) + +/* +** dot_lane_0_s64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.d, \1\.h, z1\.h\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_s64_tied2, svint64_t, svint16_t, + z0_res = svdot_lane_s64 (z4, z0, z1, 0), + z0_res = svdot_lane (z4, z0, z1, 0)) + +/* +** dot_lane_0_s64_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.d, z1\.h, \1\.h\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_s64_tied3, svint64_t, svint16_t, + z0_res = svdot_lane_s64 (z4, z1, z0, 0), + z0_res = svdot_lane (z4, z1, z0, 0)) + +/* +** dot_lane_0_s64_untied: +** movprfx z0, z1 +** sdot z0\.d, z4\.h, z5\.h\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_s64_untied, svint64_t, svint16_t, + z0 = svdot_lane_s64 (z1, z4, z5, 0), + z0 = svdot_lane (z1, z4, z5, 0)) + +/* +** dot_lane_1_s64: +** sdot z0\.d, z4\.h, z5\.h\[1\] +** ret +*/ +TEST_DUAL_Z (dot_lane_1_s64, svint64_t, svint16_t, + z0 = svdot_lane_s64 (z0, z4, z5, 1), + z0 = svdot_lane (z0, z4, z5, 1)) + +/* +** dot_lane_z15_s64: +** str d15, \[sp, -16\]! +** sdot z0\.d, z1\.h, z15\.h\[1\] +** ldr d15, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z15_s64, svint64_t, svint16_t, z15, + z0 = svdot_lane_s64 (z0, z1, z15, 1), + z0 = svdot_lane (z0, z1, z15, 1)) + +/* +** dot_lane_z16_s64: +** mov (z[0-9]|z1[0-5])\.d, z16\.d +** sdot z0\.d, z1\.h, \1\.h\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z16_s64, svint64_t, svint16_t, z16, + z0 = svdot_lane_s64 (z0, z1, z16, 1), + z0 = svdot_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u32.c new file mode 100644 index 00000000000..6d69df76d6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u32.c @@ -0,0 +1,93 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_lane_0_u32_tied1: +** udot z0\.s, z4\.b, z5\.b\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_u32_tied1, svuint32_t, svuint8_t, + z0 = svdot_lane_u32 (z0, z4, z5, 0), + z0 = svdot_lane (z0, z4, z5, 0)) + +/* +** dot_lane_0_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.s, \1\.b, z1\.b\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_u32_tied2, svuint32_t, svuint8_t, + z0_res = svdot_lane_u32 (z4, z0, z1, 0), + z0_res = svdot_lane (z4, z0, z1, 0)) + +/* +** dot_lane_0_u32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.s, z1\.b, \1\.b\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_u32_tied3, svuint32_t, svuint8_t, + z0_res = svdot_lane_u32 (z4, z1, z0, 0), + z0_res = svdot_lane (z4, z1, z0, 0)) + +/* +** dot_lane_0_u32_untied: +** movprfx z0, z1 +** udot z0\.s, z4\.b, z5\.b\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_u32_untied, svuint32_t, svuint8_t, + z0 = svdot_lane_u32 (z1, z4, z5, 0), + z0 = svdot_lane (z1, z4, z5, 0)) + +/* +** dot_lane_1_u32: +** udot z0\.s, z4\.b, z5\.b\[1\] +** ret +*/ +TEST_DUAL_Z (dot_lane_1_u32, svuint32_t, svuint8_t, + z0 = svdot_lane_u32 (z0, z4, z5, 1), + z0 = svdot_lane (z0, z4, z5, 1)) + +/* +** dot_lane_2_u32: +** udot z0\.s, z4\.b, z5\.b\[2\] +** ret +*/ +TEST_DUAL_Z (dot_lane_2_u32, svuint32_t, svuint8_t, + z0 = svdot_lane_u32 (z0, z4, z5, 2), + z0 = svdot_lane (z0, z4, z5, 2)) + +/* +** dot_lane_3_u32: +** udot z0\.s, z4\.b, z5\.b\[3\] +** ret +*/ +TEST_DUAL_Z (dot_lane_3_u32, svuint32_t, svuint8_t, + z0 = svdot_lane_u32 (z0, z4, z5, 3), + z0 = svdot_lane (z0, z4, z5, 3)) + +/* +** dot_lane_z8_u32: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** udot z0\.s, z1\.b, \1\.b\[1\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z8_u32, svuint32_t, svuint8_t, z8, + z0 = svdot_lane_u32 (z0, z1, z8, 1), + z0 = svdot_lane (z0, z1, z8, 1)) + +/* +** dot_lane_z16_u32: +** mov (z[0-7])\.d, z16\.d +** udot z0\.s, z1\.b, \1\.b\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z16_u32, svuint32_t, svuint8_t, z16, + z0 = svdot_lane_u32 (z0, z1, z16, 1), + z0 = svdot_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u64.c new file mode 100644 index 00000000000..242e21c783a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_lane_u64.c @@ -0,0 +1,74 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_lane_0_u64_tied1: +** udot z0\.d, z4\.h, z5\.h\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_u64_tied1, svuint64_t, svuint16_t, + z0 = svdot_lane_u64 (z0, z4, z5, 0), + z0 = svdot_lane (z0, z4, z5, 0)) + +/* +** dot_lane_0_u64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.d, \1\.h, z1\.h\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_u64_tied2, svuint64_t, svuint16_t, + z0_res = svdot_lane_u64 (z4, z0, z1, 0), + z0_res = svdot_lane (z4, z0, z1, 0)) + +/* +** dot_lane_0_u64_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.d, z1\.h, \1\.h\[0\] +** ret +*/ +TEST_DUAL_Z_REV (dot_lane_0_u64_tied3, svuint64_t, svuint16_t, + z0_res = svdot_lane_u64 (z4, z1, z0, 0), + z0_res = svdot_lane (z4, z1, z0, 0)) + +/* +** dot_lane_0_u64_untied: +** movprfx z0, z1 +** udot z0\.d, z4\.h, z5\.h\[0\] +** ret +*/ +TEST_DUAL_Z (dot_lane_0_u64_untied, svuint64_t, svuint16_t, + z0 = svdot_lane_u64 (z1, z4, z5, 0), + z0 = svdot_lane (z1, z4, z5, 0)) + +/* +** dot_lane_1_u64: +** udot z0\.d, z4\.h, z5\.h\[1\] +** ret +*/ +TEST_DUAL_Z (dot_lane_1_u64, svuint64_t, svuint16_t, + z0 = svdot_lane_u64 (z0, z4, z5, 1), + z0 = svdot_lane (z0, z4, z5, 1)) + +/* +** dot_lane_z15_u64: +** str d15, \[sp, -16\]! +** udot z0\.d, z1\.h, z15\.h\[1\] +** ldr d15, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z15_u64, svuint64_t, svuint16_t, z15, + z0 = svdot_lane_u64 (z0, z1, z15, 1), + z0 = svdot_lane (z0, z1, z15, 1)) + +/* +** dot_lane_z16_u64: +** mov (z[0-9]|z1[0-5])\.d, z16\.d +** udot z0\.d, z1\.h, \1\.h\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (dot_lane_z16_u64, svuint64_t, svuint16_t, z16, + z0 = svdot_lane_u64 (z0, z1, z16, 1), + z0 = svdot_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c new file mode 100644 index 00000000000..605bd1b30f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_s32_tied1: +** sdot z0\.s, z4\.b, z5\.b +** ret +*/ +TEST_DUAL_Z (dot_s32_tied1, svint32_t, svint8_t, + z0 = svdot_s32 (z0, z4, z5), + z0 = svdot (z0, z4, z5)) + +/* +** dot_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.s, \1\.b, z1\.b +** ret +*/ +TEST_DUAL_Z_REV (dot_s32_tied2, svint32_t, svint8_t, + z0_res = svdot_s32 (z4, z0, z1), + z0_res = svdot (z4, z0, z1)) + +/* +** dot_s32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.s, z1\.b, \1\.b +** ret +*/ +TEST_DUAL_Z_REV (dot_s32_tied3, svint32_t, svint8_t, + z0_res = svdot_s32 (z4, z1, z0), + z0_res = svdot (z4, z1, z0)) + +/* +** dot_s32_untied: +** movprfx z0, z1 +** sdot z0\.s, z4\.b, z5\.b +** ret +*/ +TEST_DUAL_Z (dot_s32_untied, svint32_t, svint8_t, + z0 = svdot_s32 (z1, z4, z5), + z0 = svdot (z1, z4, z5)) + +/* +** dot_w0_s32_tied1: +** mov (z[0-9]+\.b), w0 +** sdot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_s32_tied1, svint32_t, svint8_t, int8_t, + z0 = svdot_n_s32 (z0, z4, x0), + z0 = svdot (z0, z4, x0)) + +/* +** dot_w0_s32_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** sdot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_s32_untied, svint32_t, svint8_t, int8_t, + z0 = svdot_n_s32 (z1, z4, x0), + z0 = svdot (z1, z4, x0)) + +/* +** dot_9_s32_tied1: +** mov (z[0-9]+\.b), #9 +** sdot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_s32_tied1, svint32_t, svint8_t, + z0 = svdot_n_s32 (z0, z4, 9), + z0 = svdot (z0, z4, 9)) + +/* +** dot_9_s32_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #9 +** movprfx z0, z1 +** sdot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_s32_untied, svint32_t, svint8_t, + z0 = svdot_n_s32 (z1, z4, 9), + z0 = svdot (z1, z4, 9)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c new file mode 100644 index 00000000000..b6574740b7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_s64_tied1: +** sdot z0\.d, z4\.h, z5\.h +** ret +*/ +TEST_DUAL_Z (dot_s64_tied1, svint64_t, svint16_t, + z0 = svdot_s64 (z0, z4, z5), + z0 = svdot (z0, z4, z5)) + +/* +** dot_s64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.d, \1\.h, z1\.h +** ret +*/ +TEST_DUAL_Z_REV (dot_s64_tied2, svint64_t, svint16_t, + z0_res = svdot_s64 (z4, z0, z1), + z0_res = svdot (z4, z0, z1)) + +/* +** dot_s64_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** sdot z0\.d, z1\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (dot_s64_tied3, svint64_t, svint16_t, + z0_res = svdot_s64 (z4, z1, z0), + z0_res = svdot (z4, z1, z0)) + +/* +** dot_s64_untied: +** movprfx z0, z1 +** sdot z0\.d, z4\.h, z5\.h +** ret +*/ +TEST_DUAL_Z (dot_s64_untied, svint64_t, svint16_t, + z0 = svdot_s64 (z1, z4, z5), + z0 = svdot (z1, z4, z5)) + +/* +** dot_w0_s64_tied1: +** mov (z[0-9]+\.h), w0 +** sdot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_s64_tied1, svint64_t, svint16_t, int16_t, + z0 = svdot_n_s64 (z0, z4, x0), + z0 = svdot (z0, z4, x0)) + +/* +** dot_w0_s64_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** sdot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_s64_untied, svint64_t, svint16_t, int16_t, + z0 = svdot_n_s64 (z1, z4, x0), + z0 = svdot (z1, z4, x0)) + +/* +** dot_9_s64_tied1: +** mov (z[0-9]+\.h), #9 +** sdot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_s64_tied1, svint64_t, svint16_t, + z0 = svdot_n_s64 (z0, z4, 9), + z0 = svdot (z0, z4, 9)) + +/* +** dot_9_s64_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #9 +** movprfx z0, z1 +** sdot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_s64_untied, svint64_t, svint16_t, + z0 = svdot_n_s64 (z1, z4, 9), + z0 = svdot (z1, z4, 9)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c new file mode 100644 index 00000000000..541e71cc212 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_u32_tied1: +** udot z0\.s, z4\.b, z5\.b +** ret +*/ +TEST_DUAL_Z (dot_u32_tied1, svuint32_t, svuint8_t, + z0 = svdot_u32 (z0, z4, z5), + z0 = svdot (z0, z4, z5)) + +/* +** dot_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.s, \1\.b, z1\.b +** ret +*/ +TEST_DUAL_Z_REV (dot_u32_tied2, svuint32_t, svuint8_t, + z0_res = svdot_u32 (z4, z0, z1), + z0_res = svdot (z4, z0, z1)) + +/* +** dot_u32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.s, z1\.b, \1\.b +** ret +*/ +TEST_DUAL_Z_REV (dot_u32_tied3, svuint32_t, svuint8_t, + z0_res = svdot_u32 (z4, z1, z0), + z0_res = svdot (z4, z1, z0)) + +/* +** dot_u32_untied: +** movprfx z0, z1 +** udot z0\.s, z4\.b, z5\.b +** ret +*/ +TEST_DUAL_Z (dot_u32_untied, svuint32_t, svuint8_t, + z0 = svdot_u32 (z1, z4, z5), + z0 = svdot (z1, z4, z5)) + +/* +** dot_w0_u32_tied1: +** mov (z[0-9]+\.b), w0 +** udot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_u32_tied1, svuint32_t, svuint8_t, uint8_t, + z0 = svdot_n_u32 (z0, z4, x0), + z0 = svdot (z0, z4, x0)) + +/* +** dot_w0_u32_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** udot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_u32_untied, svuint32_t, svuint8_t, uint8_t, + z0 = svdot_n_u32 (z1, z4, x0), + z0 = svdot (z1, z4, x0)) + +/* +** dot_9_u32_tied1: +** mov (z[0-9]+\.b), #9 +** udot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_u32_tied1, svuint32_t, svuint8_t, + z0 = svdot_n_u32 (z0, z4, 9), + z0 = svdot (z0, z4, 9)) + +/* +** dot_9_u32_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #9 +** movprfx z0, z1 +** udot z0\.s, z4\.b, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_u32_untied, svuint32_t, svuint8_t, + z0 = svdot_n_u32 (z1, z4, 9), + z0 = svdot (z1, z4, 9)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c new file mode 100644 index 00000000000..cc0e853737d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dot_u64_tied1: +** udot z0\.d, z4\.h, z5\.h +** ret +*/ +TEST_DUAL_Z (dot_u64_tied1, svuint64_t, svuint16_t, + z0 = svdot_u64 (z0, z4, z5), + z0 = svdot (z0, z4, z5)) + +/* +** dot_u64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.d, \1\.h, z1\.h +** ret +*/ +TEST_DUAL_Z_REV (dot_u64_tied2, svuint64_t, svuint16_t, + z0_res = svdot_u64 (z4, z0, z1), + z0_res = svdot (z4, z0, z1)) + +/* +** dot_u64_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** udot z0\.d, z1\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (dot_u64_tied3, svuint64_t, svuint16_t, + z0_res = svdot_u64 (z4, z1, z0), + z0_res = svdot (z4, z1, z0)) + +/* +** dot_u64_untied: +** movprfx z0, z1 +** udot z0\.d, z4\.h, z5\.h +** ret +*/ +TEST_DUAL_Z (dot_u64_untied, svuint64_t, svuint16_t, + z0 = svdot_u64 (z1, z4, z5), + z0 = svdot (z1, z4, z5)) + +/* +** dot_w0_u64_tied1: +** mov (z[0-9]+\.h), w0 +** udot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_u64_tied1, svuint64_t, svuint16_t, uint16_t, + z0 = svdot_n_u64 (z0, z4, x0), + z0 = svdot (z0, z4, x0)) + +/* +** dot_w0_u64_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** udot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_ZX (dot_w0_u64_untied, svuint64_t, svuint16_t, uint16_t, + z0 = svdot_n_u64 (z1, z4, x0), + z0 = svdot (z1, z4, x0)) + +/* +** dot_9_u64_tied1: +** mov (z[0-9]+\.h), #9 +** udot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_u64_tied1, svuint64_t, svuint16_t, + z0 = svdot_n_u64 (z0, z4, 9), + z0 = svdot (z0, z4, 9)) + +/* +** dot_9_u64_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #9 +** movprfx z0, z1 +** udot z0\.d, z4\.h, \1 +** ret +*/ +TEST_DUAL_Z (dot_9_u64_untied, svuint64_t, svuint16_t, + z0 = svdot_n_u64 (z1, z4, 9), + z0 = svdot (z1, z4, 9)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b16.c new file mode 100644 index 00000000000..785832ab39e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b16.c @@ -0,0 +1,32 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include +#include "test_sve_acle.h" + +/* +** dup_false_b16: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dup_false_b16, + p0 = svdup_n_b16 (false), + p0 = svdup_b16 (false)) + +/* +** dup_true_b16: +** ptrue p0\.h, all +** ret +*/ +TEST_UNIFORM_P (dup_true_b16, + p0 = svdup_n_b16 (true), + p0 = svdup_b16 (true)) + +/* +** dup_w0_b16: +** lsl (x[0-9]+), x0, 63 +** whilelo p0\.h, xzr, \1 +** ret +*/ +TEST_UNIFORM_PS (dup_w0_b16, + p0 = svdup_n_b16 (x0), + p0 = svdup_b16 (x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b32.c new file mode 100644 index 00000000000..6e9d91eaf25 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b32.c @@ -0,0 +1,32 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include +#include "test_sve_acle.h" + +/* +** dup_false_b32: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dup_false_b32, + p0 = svdup_n_b32 (false), + p0 = svdup_b32 (false)) + +/* +** dup_true_b32: +** ptrue p0\.s, all +** ret +*/ +TEST_UNIFORM_P (dup_true_b32, + p0 = svdup_n_b32 (true), + p0 = svdup_b32 (true)) + +/* +** dup_w0_b32: +** lsl (x[0-9]+), x0, 63 +** whilelo p0\.s, xzr, \1 +** ret +*/ +TEST_UNIFORM_PS (dup_w0_b32, + p0 = svdup_n_b32 (x0), + p0 = svdup_b32 (x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b64.c new file mode 100644 index 00000000000..ed69896c471 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b64.c @@ -0,0 +1,32 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include +#include "test_sve_acle.h" + +/* +** dup_false_b64: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dup_false_b64, + p0 = svdup_n_b64 (false), + p0 = svdup_b64 (false)) + +/* +** dup_true_b64: +** ptrue p0\.d, all +** ret +*/ +TEST_UNIFORM_P (dup_true_b64, + p0 = svdup_n_b64 (true), + p0 = svdup_b64 (true)) + +/* +** dup_w0_b64: +** lsl (x[0-9]+), x0, 63 +** whilelo p0\.d, xzr, \1 +** ret +*/ +TEST_UNIFORM_PS (dup_w0_b64, + p0 = svdup_n_b64 (x0), + p0 = svdup_b64 (x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b8.c new file mode 100644 index 00000000000..a99ab552a03 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_b8.c @@ -0,0 +1,32 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include +#include "test_sve_acle.h" + +/* +** dup_false_b8: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dup_false_b8, + p0 = svdup_n_b8 (false), + p0 = svdup_b8 (false)) + +/* +** dup_true_b8: +** ptrue p0\.b, all +** ret +*/ +TEST_UNIFORM_P (dup_true_b8, + p0 = svdup_n_b8 (true), + p0 = svdup_b8 (true)) + +/* +** dup_w0_b8: +** lsl (x[0-9]+), x0, 63 +** whilelo p0\.b, xzr, \1 +** ret +*/ +TEST_UNIFORM_PS (dup_w0_b8, + p0 = svdup_n_b8 (x0), + p0 = svdup_b8 (x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c new file mode 100644 index 00000000000..2d48b9a3dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f16.c @@ -0,0 +1,215 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_f16: +** fmov z0\.h, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f16, svfloat16_t, + z0 = svdup_n_f16 (1), + z0 = svdup_f16 (1)) + +/* +** dup_0_f16: +** mov z0\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f16, svfloat16_t, + z0 = svdup_n_f16 (0), + z0 = svdup_f16 (0)) + +/* +** dup_8_f16: +** fmov z0\.h, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f16, svfloat16_t, + z0 = svdup_n_f16 (8), + z0 = svdup_f16 (8)) + +/* +** dup_512_f16: +** mov z0\.h, #24576 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f16, svfloat16_t, + z0 = svdup_n_f16 (512), + z0 = svdup_f16 (512)) + +/* +** dup_513_f16: +** mov (w[0-7]+), 24578 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_513_f16, svfloat16_t, + z0 = svdup_n_f16 (513), + z0 = svdup_f16 (513)) + +/* +** dup_h4_f16: +** mov z0\.h, h4 +** ret +*/ +TEST_UNIFORM_ZD (dup_h4_f16, svfloat16_t, __fp16, + z0 = svdup_n_f16 (d4), + z0 = svdup_f16 (d4)) + +/* +** dup_1_f16_m: +** mov z0\.h, p0/m, #15360 +** ret +*/ +TEST_UNIFORM_Z (dup_1_f16_m, svfloat16_t, + z0 = svdup_n_f16_m (z0, p0, 1), + z0 = svdup_f16_m (z0, p0, 1)) + +/* +** dup_0_f16_m: +** mov z0\.h, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f16_m, svfloat16_t, + z0 = svdup_n_f16_m (z0, p0, 0), + z0 = svdup_f16_m (z0, p0, 0)) + +/* +** dup_8_f16_m: +** mov z0\.h, p0/m, #18432 +** ret +*/ +TEST_UNIFORM_Z (dup_8_f16_m, svfloat16_t, + z0 = svdup_n_f16_m (z0, p0, 8), + z0 = svdup_f16_m (z0, p0, 8)) + +/* +** dup_512_f16_m: +** mov z0\.h, p0/m, #24576 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f16_m, svfloat16_t, + z0 = svdup_n_f16_m (z0, p0, 512), + z0 = svdup_f16_m (z0, p0, 512)) + + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f16_m, svfloat16_t, + z0 = svdup_n_f16_m (z0, p0, 513), + z0 = svdup_f16_m (z0, p0, 513)) + +/* +** dup_h4_f16_m: +** movprfx z0, z1 +** mov z0\.h, p0/m, h4 +** ret +*/ +TEST_UNIFORM_ZD (dup_h4_f16_m, svfloat16_t, __fp16, + z0 = svdup_n_f16_m (z1, p0, d4), + z0 = svdup_f16_m (z1, p0, d4)) + +/* +** dup_1_f16_z: +** mov z0\.h, p0/z, #15360 +** ret +*/ +TEST_UNIFORM_Z (dup_1_f16_z, svfloat16_t, + z0 = svdup_n_f16_z (p0, 1), + z0 = svdup_f16_z (p0, 1)) + +/* +** dup_0_f16_z: +** mov z0\.h, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f16_z, svfloat16_t, + z0 = svdup_n_f16_z (p0, 0), + z0 = svdup_f16_z (p0, 0)) + +/* +** dup_8_f16_z: +** mov z0\.h, p0/z, #18432 +** ret +*/ +TEST_UNIFORM_Z (dup_8_f16_z, svfloat16_t, + z0 = svdup_n_f16_z (p0, 8), + z0 = svdup_f16_z (p0, 8)) + +/* +** dup_512_f16_z: +** mov z0\.h, p0/z, #24576 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f16_z, svfloat16_t, + z0 = svdup_n_f16_z (p0, 512), + z0 = svdup_f16_z (p0, 512)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f16_z, svfloat16_t, + z0 = svdup_n_f16_z (p0, 513), + z0 = svdup_f16_z (p0, 513)) +/* +** dup_h4_f16_z: +** movprfx z0\.h, p0/z, z0\.h +** mov z0\.h, p0/m, h4 +** ret +*/ +TEST_UNIFORM_ZD (dup_h4_f16_z, svfloat16_t, __fp16, + z0 = svdup_n_f16_z (p0, d4), + z0 = svdup_f16_z (p0, d4)) + +/* +** dup_1_f16_x: +** fmov z0\.h, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f16_x, svfloat16_t, + z0 = svdup_n_f16_x (p0, 1), + z0 = svdup_f16_x (p0, 1)) + +/* +** dup_0_f16_x: +** mov z0\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f16_x, svfloat16_t, + z0 = svdup_n_f16_x (p0, 0), + z0 = svdup_f16_x (p0, 0)) + +/* +** dup_8_f16_x: +** fmov z0\.h, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f16_x, svfloat16_t, + z0 = svdup_n_f16_x (p0, 8), + z0 = svdup_f16_x (p0, 8)) + +/* +** dup_512_f16_x: +** mov z0\.h, #24576 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f16_x, svfloat16_t, + z0 = svdup_n_f16_x (p0, 512), + z0 = svdup_f16_x (p0, 512)) + +/* +** dup_513_f16_x: +** mov (w[0-7]+), 24578 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_513_f16_x, svfloat16_t, + z0 = svdup_n_f16_x (p0, 513), + z0 = svdup_f16_x (p0, 513)) + +/* +** dup_h4_f16_x: +** mov z0\.h, h4 +** ret +*/ +TEST_UNIFORM_ZD (dup_h4_f16_x, svfloat16_t, __fp16, + z0 = svdup_n_f16_x (p0, d4), + z0 = svdup_f16_x (p0, d4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c new file mode 100644 index 00000000000..f997b7a7dc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f32.c @@ -0,0 +1,212 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_f32: +** fmov z0\.s, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f32, svfloat32_t, + z0 = svdup_n_f32 (1), + z0 = svdup_f32 (1)) + +/* +** dup_0_f32: +** mov z0\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f32, svfloat32_t, + z0 = svdup_n_f32 (0), + z0 = svdup_f32 (0)) + +/* +** dup_8_f32: +** fmov z0\.s, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f32, svfloat32_t, + z0 = svdup_n_f32 (8), + z0 = svdup_f32 (8)) + +/* +** dup_512_f32: +** movi v([0-9]+).4s, 0x44, lsl 24 +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_512_f32, svfloat32_t, + z0 = svdup_n_f32 (512), + z0 = svdup_f32 (512)) + +/* +** dup_513_f32: +** ... +** ld1rw z0\.s, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dup_513_f32, svfloat32_t, + z0 = svdup_n_f32 (513), + z0 = svdup_f32 (513)) + +/* +** dup_s4_f32: +** mov z0\.s, s4 +** ret +*/ +TEST_UNIFORM_ZD (dup_s4_f32, svfloat32_t, float, + z0 = svdup_n_f32 (d4), + z0 = svdup_f32 (d4)) + +/* +** dup_1_f32_m: +** fmov z0\.s, p0/m, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f32_m, svfloat32_t, + z0 = svdup_n_f32_m (z0, p0, 1), + z0 = svdup_f32_m (z0, p0, 1)) + +/* +** dup_0_f32_m: +** mov z0\.s, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f32_m, svfloat32_t, + z0 = svdup_n_f32_m (z0, p0, 0), + z0 = svdup_f32_m (z0, p0, 0)) + +/* +** dup_8_f32_m: +** fmov z0\.s, p0/m, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f32_m, svfloat32_t, + z0 = svdup_n_f32_m (z0, p0, 8), + z0 = svdup_f32_m (z0, p0, 8)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_512_f32_m, svfloat32_t, + z0 = svdup_n_f32_m (z0, p0, 512), + z0 = svdup_f32_m (z0, p0, 512)) + + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f32_m, svfloat32_t, + z0 = svdup_n_f32_m (z0, p0, 513), + z0 = svdup_f32_m (z0, p0, 513)) + +/* +** dup_s4_f32_m: +** movprfx z0, z1 +** mov z0\.s, p0/m, s4 +** ret +*/ +TEST_UNIFORM_ZD (dup_s4_f32_m, svfloat32_t, float, + z0 = svdup_n_f32_m (z1, p0, d4), + z0 = svdup_f32_m (z1, p0, d4)) + +/* +** dup_1_f32_z: +** movprfx z0\.s, p0/z, z0\.s +** fmov z0\.s, p0/m, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f32_z, svfloat32_t, + z0 = svdup_n_f32_z (p0, 1), + z0 = svdup_f32_z (p0, 1)) + +/* +** dup_0_f32_z: +** mov z0\.s, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f32_z, svfloat32_t, + z0 = svdup_n_f32_z (p0, 0), + z0 = svdup_f32_z (p0, 0)) + +/* +** dup_8_f32_z: +** movprfx z0\.s, p0/z, z0\.s +** fmov z0\.s, p0/m, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f32_z, svfloat32_t, + z0 = svdup_n_f32_z (p0, 8), + z0 = svdup_f32_z (p0, 8)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_512_f32_z, svfloat32_t, + z0 = svdup_n_f32_z (p0, 512), + z0 = svdup_f32_z (p0, 512)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f32_z, svfloat32_t, + z0 = svdup_n_f32_z (p0, 513), + z0 = svdup_f32_z (p0, 513)) + +/* +** dup_s4_f32_z: +** movprfx z0\.s, p0/z, z0\.s +** mov z0\.s, p0/m, s4 +** ret +*/ +TEST_UNIFORM_ZD (dup_s4_f32_z, svfloat32_t, float, + z0 = svdup_n_f32_z (p0, d4), + z0 = svdup_f32_z (p0, d4)) + +/* +** dup_1_f32_x: +** fmov z0\.s, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f32_x, svfloat32_t, + z0 = svdup_n_f32_x (p0, 1), + z0 = svdup_f32_x (p0, 1)) + +/* +** dup_0_f32_x: +** mov z0\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f32_x, svfloat32_t, + z0 = svdup_n_f32_x (p0, 0), + z0 = svdup_f32_x (p0, 0)) + +/* +** dup_8_f32_x: +** fmov z0\.s, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f32_x, svfloat32_t, + z0 = svdup_n_f32_x (p0, 8), + z0 = svdup_f32_x (p0, 8)) + +/* +** dup_512_f32_x: +** movi v([0-9]+).4s, 0x44, lsl 24 +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_512_f32_x, svfloat32_t, + z0 = svdup_n_f32_x (p0, 512), + z0 = svdup_f32_x (p0, 512)) + +/* +** dup_513_f32_x: +** ... +** ld1rw z0\.s, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dup_513_f32_x, svfloat32_t, + z0 = svdup_n_f32_x (p0, 513), + z0 = svdup_f32_x (p0, 513)) + +/* +** dup_s4_f32_x: +** mov z0\.s, s4 +** ret +*/ +TEST_UNIFORM_ZD (dup_s4_f32_x, svfloat32_t, float, + z0 = svdup_n_f32_x (p0, d4), + z0 = svdup_f32_x (p0, d4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c new file mode 100644 index 00000000000..e177d91086d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_f64.c @@ -0,0 +1,212 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_f64: +** fmov z0\.d, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f64, svfloat64_t, + z0 = svdup_n_f64 (1), + z0 = svdup_f64 (1)) + +/* +** dup_0_f64: +** mov z0\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f64, svfloat64_t, + z0 = svdup_n_f64 (0), + z0 = svdup_f64 (0)) + +/* +** dup_8_f64: +** fmov z0\.d, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f64, svfloat64_t, + z0 = svdup_n_f64 (8), + z0 = svdup_f64 (8)) + +/* +** dup_512_f64: +** mov (x[0-9]+), 4647714815446351872 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f64, svfloat64_t, + z0 = svdup_n_f64 (512), + z0 = svdup_f64 (512)) + +/* +** dup_513_f64: +** ... +** ld1rd z0\.d, p[0-7]/z, \[x[0-9+]\] +** ret +*/ +TEST_UNIFORM_Z (dup_513_f64, svfloat64_t, + z0 = svdup_n_f64 (513), + z0 = svdup_f64 (513)) + +/* +** dup_d4_f64: +** mov z0\.d, d4 +** ret +*/ +TEST_UNIFORM_ZD (dup_d4_f64, svfloat64_t, double, + z0 = svdup_n_f64 (d4), + z0 = svdup_f64 (d4)) + +/* +** dup_1_f64_m: +** fmov z0\.d, p0/m, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f64_m, svfloat64_t, + z0 = svdup_n_f64_m (z0, p0, 1), + z0 = svdup_f64_m (z0, p0, 1)) + +/* +** dup_0_f64_m: +** mov z0\.d, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f64_m, svfloat64_t, + z0 = svdup_n_f64_m (z0, p0, 0), + z0 = svdup_f64_m (z0, p0, 0)) + +/* +** dup_8_f64_m: +** fmov z0\.d, p0/m, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f64_m, svfloat64_t, + z0 = svdup_n_f64_m (z0, p0, 8), + z0 = svdup_f64_m (z0, p0, 8)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_512_f64_m, svfloat64_t, + z0 = svdup_n_f64_m (z0, p0, 512), + z0 = svdup_f64_m (z0, p0, 512)) + + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f64_m, svfloat64_t, + z0 = svdup_n_f64_m (z0, p0, 513), + z0 = svdup_f64_m (z0, p0, 513)) + +/* +** dup_d4_f64_m: +** movprfx z0, z1 +** mov z0\.d, p0/m, d4 +** ret +*/ +TEST_UNIFORM_ZD (dup_d4_f64_m, svfloat64_t, double, + z0 = svdup_n_f64_m (z1, p0, d4), + z0 = svdup_f64_m (z1, p0, d4)) + +/* +** dup_1_f64_z: +** movprfx z0\.d, p0/z, z0\.d +** fmov z0\.d, p0/m, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f64_z, svfloat64_t, + z0 = svdup_n_f64_z (p0, 1), + z0 = svdup_f64_z (p0, 1)) + +/* +** dup_0_f64_z: +** mov z0\.d, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f64_z, svfloat64_t, + z0 = svdup_n_f64_z (p0, 0), + z0 = svdup_f64_z (p0, 0)) + +/* +** dup_8_f64_z: +** movprfx z0\.d, p0/z, z0\.d +** fmov z0\.d, p0/m, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f64_z, svfloat64_t, + z0 = svdup_n_f64_z (p0, 8), + z0 = svdup_f64_z (p0, 8)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_512_f64_z, svfloat64_t, + z0 = svdup_n_f64_z (p0, 512), + z0 = svdup_f64_z (p0, 512)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_513_f64_z, svfloat64_t, + z0 = svdup_n_f64_z (p0, 513), + z0 = svdup_f64_z (p0, 513)) + +/* +** dup_d4_f64_z: +** movprfx z0\.d, p0/z, z0\.d +** mov z0\.d, p0/m, d4 +** ret +*/ +TEST_UNIFORM_ZD (dup_d4_f64_z, svfloat64_t, double, + z0 = svdup_n_f64_z (p0, d4), + z0 = svdup_f64_z (p0, d4)) + +/* +** dup_1_f64_x: +** fmov z0\.d, #1\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_1_f64_x, svfloat64_t, + z0 = svdup_n_f64_x (p0, 1), + z0 = svdup_f64_x (p0, 1)) + +/* +** dup_0_f64_x: +** mov z0\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_f64_x, svfloat64_t, + z0 = svdup_n_f64_x (p0, 0), + z0 = svdup_f64_x (p0, 0)) + +/* +** dup_8_f64_x: +** fmov z0\.d, #8\.0(?:e\+0)? +** ret +*/ +TEST_UNIFORM_Z (dup_8_f64_x, svfloat64_t, + z0 = svdup_n_f64_x (p0, 8), + z0 = svdup_f64_x (p0, 8)) + +/* +** dup_512_f64_x: +** mov (x[0-9]+), 4647714815446351872 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_512_f64_x, svfloat64_t, + z0 = svdup_n_f64_x (p0, 512), + z0 = svdup_f64_x (p0, 512)) + +/* +** dup_513_f64_x: +** ... +** ld1rd z0\.d, p[0-7]/z, \[x[0-9+]\] +** ret +*/ +TEST_UNIFORM_Z (dup_513_f64_x, svfloat64_t, + z0 = svdup_n_f64_x (p0, 513), + z0 = svdup_f64_x (p0, 513)) + +/* +** dup_d4_f64_x: +** mov z0\.d, d4 +** ret +*/ +TEST_UNIFORM_ZD (dup_d4_f64_x, svfloat64_t, double, + z0 = svdup_n_f64_x (p0, d4), + z0 = svdup_f64_x (p0, d4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f16.c new file mode 100644 index 00000000000..142afbb2452 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f16.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_f16_tied1: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_f16_tied1, svfloat16_t, uint16_t, + z0 = svdup_lane_f16 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_f16_untied: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_f16_untied, svfloat16_t, uint16_t, + z0 = svdup_lane_f16 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_f16_tied1: +** dup z0\.h, z0\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f16_tied1, svfloat16_t, + z0 = svdup_lane_f16 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_f16_untied: +** dup z0\.h, z1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f16_untied, svfloat16_t, + z0 = svdup_lane_f16 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_15_f16: +** dup z0\.h, z0\.h\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_f16: +** dup z0\.h, z0\.h\[16\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_f16: +** dup z0\.h, z0\.h\[31\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_f16: +** mov (z[0-9]+\.h), #32 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_f16: +** mov (z[0-9]+\.h), #63 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_f16: +** mov (z[0-9]+\.h), #64 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_f16: +** mov (z[0-9]+\.h), #255 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_f16, svfloat16_t, + z0 = svdup_lane_f16 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f32.c new file mode 100644 index 00000000000..b32068a37d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f32.c @@ -0,0 +1,110 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_f32_tied1: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_f32_tied1, svfloat32_t, uint32_t, + z0 = svdup_lane_f32 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_f32_untied: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_f32_untied, svfloat32_t, uint32_t, + z0 = svdup_lane_f32 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_f32_tied1: +** dup z0\.s, z0\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f32_tied1, svfloat32_t, + z0 = svdup_lane_f32 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_f32_untied: +** dup z0\.s, z1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f32_untied, svfloat32_t, + z0 = svdup_lane_f32 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_15_f32: +** dup z0\.s, z0\.s\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_f32: +** mov (z[0-9]+\.s), #16 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_f32: +** mov (z[0-9]+\.s), #31 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_f32: +** mov (z[0-9]+\.s), #32 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_f32: +** mov (z[0-9]+\.s), #63 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_f32: +** mov (z[0-9]+\.s), #64 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_f32: +** mov (z[0-9]+\.s), #255 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_f32, svfloat32_t, + z0 = svdup_lane_f32 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f64.c new file mode 100644 index 00000000000..64af50d0c09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_f64.c @@ -0,0 +1,111 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_x0_f64_tied1: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_f64_tied1, svfloat64_t, uint64_t, + z0 = svdup_lane_f64 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_x0_f64_untied: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_f64_untied, svfloat64_t, uint64_t, + z0 = svdup_lane_f64 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_f64_tied1: +** dup z0\.d, z0\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f64_tied1, svfloat64_t, + z0 = svdup_lane_f64 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_f64_untied: +** dup z0\.d, z1\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_f64_untied, svfloat64_t, + z0 = svdup_lane_f64 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_15_f64: +** mov (z[0-9]+\.d), #15 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_f64: +** mov (z[0-9]+\.d), #16 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_f64: +** mov (z[0-9]+\.d), #31 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_f64: +** mov (z[0-9]+\.d), #32 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_f64: +** mov (z[0-9]+\.d), #63 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_f64: +** mov (z[0-9]+\.d), #64 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_f64: +** mov (z[0-9]+\.d), #255 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_f64, svfloat64_t, + z0 = svdup_lane_f64 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s16.c new file mode 100644 index 00000000000..3b6f20696fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s16.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_s16_tied1: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s16_tied1, svint16_t, uint16_t, + z0 = svdup_lane_s16 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_s16_untied: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s16_untied, svint16_t, uint16_t, + z0 = svdup_lane_s16 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_s16_tied1: +** dup z0\.h, z0\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s16_tied1, svint16_t, + z0 = svdup_lane_s16 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_s16_untied: +** dup z0\.h, z1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s16_untied, svint16_t, + z0 = svdup_lane_s16 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_s16: +** dup z0\.h, z0\.h\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_s16: +** dup z0\.h, z0\.h\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_s16: +** dup z0\.h, z0\.h\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_s16: +** dup z0\.h, z0\.h\[16\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_s16: +** dup z0\.h, z0\.h\[31\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_s16: +** mov (z[0-9]+\.h), #32 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_s16: +** mov (z[0-9]+\.h), #63 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_s16: +** mov (z[0-9]+\.h), #64 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_s16: +** mov (z[0-9]+\.h), #255 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_s16, svint16_t, + z0 = svdup_lane_s16 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s32.c new file mode 100644 index 00000000000..bf597fdf66c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s32.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_s32_tied1: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s32_tied1, svint32_t, uint32_t, + z0 = svdup_lane_s32 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_s32_untied: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s32_untied, svint32_t, uint32_t, + z0 = svdup_lane_s32 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_s32_tied1: +** dup z0\.s, z0\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s32_tied1, svint32_t, + z0 = svdup_lane_s32 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_s32_untied: +** dup z0\.s, z1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s32_untied, svint32_t, + z0 = svdup_lane_s32 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_s32: +** dup z0\.s, z0\.s\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_s32: +** dup z0\.s, z0\.s\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_s32: +** dup z0\.s, z0\.s\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_s32: +** mov (z[0-9]+\.s), #16 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_s32: +** mov (z[0-9]+\.s), #31 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_s32: +** mov (z[0-9]+\.s), #32 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_s32: +** mov (z[0-9]+\.s), #63 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_s32: +** mov (z[0-9]+\.s), #64 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_s32: +** mov (z[0-9]+\.s), #255 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_s32, svint32_t, + z0 = svdup_lane_s32 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s64.c new file mode 100644 index 00000000000..f2f3a1770cd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s64.c @@ -0,0 +1,130 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_x0_s64_tied1: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_s64_tied1, svint64_t, uint64_t, + z0 = svdup_lane_s64 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_x0_s64_untied: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_s64_untied, svint64_t, uint64_t, + z0 = svdup_lane_s64 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_s64_tied1: +** dup z0\.d, z0\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s64_tied1, svint64_t, + z0 = svdup_lane_s64 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_s64_untied: +** dup z0\.d, z1\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s64_untied, svint64_t, + z0 = svdup_lane_s64 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_s64: +** dup z0\.d, z0\.d\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_s64: +** mov (z[0-9]+\.d), #8 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_s64: +** mov (z[0-9]+\.d), #15 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_s64: +** mov (z[0-9]+\.d), #16 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_s64: +** mov (z[0-9]+\.d), #31 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_s64: +** mov (z[0-9]+\.d), #32 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_s64: +** mov (z[0-9]+\.d), #63 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_s64: +** mov (z[0-9]+\.d), #64 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_s64: +** mov (z[0-9]+\.d), #255 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_s64, svint64_t, + z0 = svdup_lane_s64 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s8.c new file mode 100644 index 00000000000..f5a07e9f337 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_s8.c @@ -0,0 +1,124 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_s8_tied1: +** mov (z[0-9]+\.b), w0 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s8_tied1, svint8_t, uint8_t, + z0 = svdup_lane_s8 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_s8_untied: +** mov (z[0-9]+\.b), w0 +** tbl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_s8_untied, svint8_t, uint8_t, + z0 = svdup_lane_s8 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_s8_tied1: +** dup z0\.b, z0\.b\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s8_tied1, svint8_t, + z0 = svdup_lane_s8 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_s8_untied: +** dup z0\.b, z1\.b\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_s8_untied, svint8_t, + z0 = svdup_lane_s8 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_s8: +** dup z0\.b, z0\.b\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_s8: +** dup z0\.b, z0\.b\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_s8: +** dup z0\.b, z0\.b\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_s8: +** dup z0\.b, z0\.b\[16\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_s8: +** dup z0\.b, z0\.b\[31\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_s8: +** dup z0\.b, z0\.b\[32\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_s8: +** dup z0\.b, z0\.b\[63\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_s8: +** mov (z[0-9]+\.b), #64 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_s8: +** mov (z[0-9]+\.b), #-1 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_s8, svint8_t, + z0 = svdup_lane_s8 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u16.c new file mode 100644 index 00000000000..e5135caa545 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u16.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svdup_lane_u16 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** tbl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u16_untied, svuint16_t, uint16_t, + z0 = svdup_lane_u16 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_u16_tied1: +** dup z0\.h, z0\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u16_tied1, svuint16_t, + z0 = svdup_lane_u16 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_u16_untied: +** dup z0\.h, z1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u16_untied, svuint16_t, + z0 = svdup_lane_u16 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_u16: +** dup z0\.h, z0\.h\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_u16: +** dup z0\.h, z0\.h\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_u16: +** dup z0\.h, z0\.h\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_u16: +** dup z0\.h, z0\.h\[16\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_u16: +** dup z0\.h, z0\.h\[31\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_u16: +** mov (z[0-9]+\.h), #32 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_u16: +** mov (z[0-9]+\.h), #63 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_u16: +** mov (z[0-9]+\.h), #64 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_u16: +** mov (z[0-9]+\.h), #255 +** tbl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_u16, svuint16_t, + z0 = svdup_lane_u16 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u32.c new file mode 100644 index 00000000000..7e972aca70a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u32.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svdup_lane_u32 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** tbl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u32_untied, svuint32_t, uint32_t, + z0 = svdup_lane_u32 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_u32_tied1: +** dup z0\.s, z0\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u32_tied1, svuint32_t, + z0 = svdup_lane_u32 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_u32_untied: +** dup z0\.s, z1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u32_untied, svuint32_t, + z0 = svdup_lane_u32 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_u32: +** dup z0\.s, z0\.s\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_u32: +** dup z0\.s, z0\.s\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_u32: +** dup z0\.s, z0\.s\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_u32: +** mov (z[0-9]+\.s), #16 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_u32: +** mov (z[0-9]+\.s), #31 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_u32: +** mov (z[0-9]+\.s), #32 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_u32: +** mov (z[0-9]+\.s), #63 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_u32: +** mov (z[0-9]+\.s), #64 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_u32: +** mov (z[0-9]+\.s), #255 +** tbl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_u32, svuint32_t, + z0 = svdup_lane_u32 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u64.c new file mode 100644 index 00000000000..5097b7e9673 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u64.c @@ -0,0 +1,130 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svdup_lane_u64 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** tbl z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_x0_u64_untied, svuint64_t, uint64_t, + z0 = svdup_lane_u64 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_u64_tied1: +** dup z0\.d, z0\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u64_tied1, svuint64_t, + z0 = svdup_lane_u64 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_u64_untied: +** dup z0\.d, z1\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u64_untied, svuint64_t, + z0 = svdup_lane_u64 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_u64: +** dup z0\.d, z0\.d\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_u64: +** mov (z[0-9]+\.d), #8 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_u64: +** mov (z[0-9]+\.d), #15 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_u64: +** mov (z[0-9]+\.d), #16 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_u64: +** mov (z[0-9]+\.d), #31 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_u64: +** mov (z[0-9]+\.d), #32 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_u64: +** mov (z[0-9]+\.d), #63 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_u64: +** mov (z[0-9]+\.d), #64 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_u64: +** mov (z[0-9]+\.d), #255 +** tbl z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_u64, svuint64_t, + z0 = svdup_lane_u64 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u8.c new file mode 100644 index 00000000000..25fdf0acb4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_lane_u8.c @@ -0,0 +1,124 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_lane_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svdup_lane_u8 (z0, x0), + z0 = svdup_lane (z0, x0)) + +/* +** dup_lane_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** tbl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (dup_lane_w0_u8_untied, svuint8_t, uint8_t, + z0 = svdup_lane_u8 (z1, x0), + z0 = svdup_lane (z1, x0)) + +/* +** dup_lane_0_u8_tied1: +** dup z0\.b, z0\.b\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u8_tied1, svuint8_t, + z0 = svdup_lane_u8 (z0, 0), + z0 = svdup_lane (z0, 0)) + +/* +** dup_lane_0_u8_untied: +** dup z0\.b, z1\.b\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_0_u8_untied, svuint8_t, + z0 = svdup_lane_u8 (z1, 0), + z0 = svdup_lane (z1, 0)) + +/* +** dup_lane_7_u8: +** dup z0\.b, z0\.b\[7\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_7_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 7), + z0 = svdup_lane (z0, 7)) + +/* +** dup_lane_8_u8: +** dup z0\.b, z0\.b\[8\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_8_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 8), + z0 = svdup_lane (z0, 8)) + +/* +** dup_lane_15_u8: +** dup z0\.b, z0\.b\[15\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_15_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 15), + z0 = svdup_lane (z0, 15)) + +/* +** dup_lane_16_u8: +** dup z0\.b, z0\.b\[16\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_16_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 16), + z0 = svdup_lane (z0, 16)) + +/* +** dup_lane_31_u8: +** dup z0\.b, z0\.b\[31\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_31_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 31), + z0 = svdup_lane (z0, 31)) + +/* +** dup_lane_32_u8: +** dup z0\.b, z0\.b\[32\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_32_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 32), + z0 = svdup_lane (z0, 32)) + +/* +** dup_lane_63_u8: +** dup z0\.b, z0\.b\[63\] +** ret +*/ +TEST_UNIFORM_Z (dup_lane_63_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 63), + z0 = svdup_lane (z0, 63)) + +/* +** dup_lane_64_u8: +** mov (z[0-9]+\.b), #64 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_64_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 64), + z0 = svdup_lane (z0, 64)) + +/* +** dup_lane_255_u8: +** mov (z[0-9]+\.b), #-1 +** tbl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_lane_255_u8, svuint8_t, + z0 = svdup_lane_u8 (z0, 255), + z0 = svdup_lane (z0, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c new file mode 100644 index 00000000000..876f36db7f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s16.c @@ -0,0 +1,1193 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_s16: +** mov z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s16, svint16_t, + z0 = svdup_n_s16 (1), + z0 = svdup_s16 (1)) + +/* +** dup_127_s16: +** mov z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s16, svint16_t, + z0 = svdup_n_s16 (127), + z0 = svdup_s16 (127)) + +/* +** dup_128_s16: +** mov z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s16, svint16_t, + z0 = svdup_n_s16 (128), + z0 = svdup_s16 (128)) + +/* +** dup_129_s16: +** movi v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_s16, svint16_t, + z0 = svdup_n_s16 (129), + z0 = svdup_s16 (129)) + +/* +** dup_253_s16: +** movi v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_s16, svint16_t, + z0 = svdup_n_s16 (253), + z0 = svdup_s16 (253)) + +/* +** dup_254_s16: +** mov z0\.h, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s16, svint16_t, + z0 = svdup_n_s16 (254), + z0 = svdup_s16 (254)) + +/* +** dup_255_s16: +** mov z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s16, svint16_t, + z0 = svdup_n_s16 (255), + z0 = svdup_s16 (255)) + +/* +** dup_256_s16: +** mov z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s16, svint16_t, + z0 = svdup_n_s16 (256), + z0 = svdup_s16 (256)) + +/* +** dup_257_s16: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s16, svint16_t, + z0 = svdup_n_s16 (257), + z0 = svdup_s16 (257)) + +/* +** dup_512_s16: +** mov z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s16, svint16_t, + z0 = svdup_n_s16 (512), + z0 = svdup_s16 (512)) + +/* +** dup_7f00_s16: +** mov z0\.h, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s16, svint16_t, + z0 = svdup_n_s16 (0x7f00), + z0 = svdup_s16 (0x7f00)) + +/* +** dup_7f01_s16: +** mov (w[0-9]+), 32513 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s16, svint16_t, + z0 = svdup_n_s16 (0x7f01), + z0 = svdup_s16 (0x7f01)) + +/* +** dup_7ffd_s16: +** mov (w[0-9]+), 32765 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s16, svint16_t, + z0 = svdup_n_s16 (0x7ffd), + z0 = svdup_s16 (0x7ffd)) + +/* +** dup_7ffe_s16: +** mov z0\.h, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s16, svint16_t, + z0 = svdup_n_s16 (0x7ffe), + z0 = svdup_s16 (0x7ffe)) + +/* +** dup_7fff_s16: +** mov z0\.h, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s16, svint16_t, + z0 = svdup_n_s16 (0x7fff), + z0 = svdup_s16 (0x7fff)) + +/* +** dup_m1_s16: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s16, svint16_t, + z0 = svdup_n_s16 (-1), + z0 = svdup_s16 (-1)) + +/* +** dup_m128_s16: +** mov z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s16, svint16_t, + z0 = svdup_n_s16 (-128), + z0 = svdup_s16 (-128)) + +/* +** dup_m129_s16: +** mov z0\.h, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s16, svint16_t, + z0 = svdup_n_s16 (-129), + z0 = svdup_s16 (-129)) + +/* +** dup_m130_s16: +** mvni v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s16, svint16_t, + z0 = svdup_n_s16 (-130), + z0 = svdup_s16 (-130)) + +/* +** dup_m254_s16: +** mvni v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s16, svint16_t, + z0 = svdup_n_s16 (-254), + z0 = svdup_s16 (-254)) + +/* +** dup_m255_s16: +** mov z0\.h, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s16, svint16_t, + z0 = svdup_n_s16 (-255), + z0 = svdup_s16 (-255)) + +/* +** dup_m256_s16: +** mov z0\.h, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s16, svint16_t, + z0 = svdup_n_s16 (-256), + z0 = svdup_s16 (-256)) + +/* +** dup_m257_s16: +** mov z0\.h, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s16, svint16_t, + z0 = svdup_n_s16 (-257), + z0 = svdup_s16 (-257)) + +/* +** dup_m258_s16: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s16, svint16_t, + z0 = svdup_n_s16 (-258), + z0 = svdup_s16 (-258)) + +/* +** dup_m259_s16: +** mov (w[0-9]+), -259 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s16, svint16_t, + z0 = svdup_n_s16 (-259), + z0 = svdup_s16 (-259)) + +/* +** dup_m512_s16: +** mov z0\.h, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s16, svint16_t, + z0 = svdup_n_s16 (-512), + z0 = svdup_s16 (-512)) + +/* +** dup_m7f00_s16: +** mov z0\.h, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s16, svint16_t, + z0 = svdup_n_s16 (-0x7f00), + z0 = svdup_s16 (-0x7f00)) + +/* +** dup_m7f01_s16: +** mov z0\.h, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s16, svint16_t, + z0 = svdup_n_s16 (-0x7f01), + z0 = svdup_s16 (-0x7f01)) + +/* +** dup_m7f02_s16: +** mov (w[0-9]+), -32514 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s16, svint16_t, + z0 = svdup_n_s16 (-0x7f02), + z0 = svdup_s16 (-0x7f02)) + +/* +** dup_m7ffe_s16: +** mov (w[0-9]+), -32766 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s16, svint16_t, + z0 = svdup_n_s16 (-0x7ffe), + z0 = svdup_s16 (-0x7ffe)) + +/* +** dup_m7fff_s16: +** mov z0\.h, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s16, svint16_t, + z0 = svdup_n_s16 (-0x7fff), + z0 = svdup_s16 (-0x7fff)) + +/* +** dup_m8000_s16: +** mov z0\.h, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s16, svint16_t, + z0 = svdup_n_s16 (-0x8000), + z0 = svdup_s16 (-0x8000)) + +/* +** dup_w0_s16: +** mov z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s16, svint16_t, int16_t, + z0 = svdup_n_s16 (x0), + z0 = svdup_s16 (x0)) + +/* +** dup_1_s16_m: +** mov z0\.h, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 1), + z0 = svdup_s16_m (z0, p0, 1)) + +/* +** dup_127_s16_m: +** mov z0\.h, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 127), + z0 = svdup_s16_m (z0, p0, 127)) + +/* +** dup_128_s16_m: +** mov (z[0-9]+\.h), #128 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_128_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 128), + z0 = svdup_s16_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 129), + z0 = svdup_s16_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 253), + z0 = svdup_s16_m (z0, p0, 253)) + +/* +** dup_254_s16_m: +** mov (z[0-9]+\.h), #254 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_254_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 254), + z0 = svdup_s16_m (z0, p0, 254)) + +/* +** dup_255_s16_m: +** mov (z[0-9]+\.h), #255 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_255_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 255), + z0 = svdup_s16_m (z0, p0, 255)) + +/* +** dup_256_s16_m: +** mov z0\.h, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 256), + z0 = svdup_s16_m (z0, p0, 256)) + +/* +** dup_257_s16_m: +** mov (z[0-9]+)\.b, #1 +** sel z0\.h, p0, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_257_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 257), + z0 = svdup_s16_m (z0, p0, 257)) + +/* +** dup_512_s16_m: +** mov z0\.h, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 512), + z0 = svdup_s16_m (z0, p0, 512)) + +/* +** dup_7f00_s16_m: +** mov z0\.h, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0x7f00), + z0 = svdup_s16_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0x7f01), + z0 = svdup_s16_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0x7ffd), + z0 = svdup_s16_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_s16_m: +** mov (z[0-9]+\.h), #32766 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0x7ffe), + z0 = svdup_s16_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_s16_m: +** mov (z[0-9]+\.h), #32767 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0x7fff), + z0 = svdup_s16_m (z0, p0, 0x7fff)) + +/* +** dup_m1_s16_m: +** mov z0\.h, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -1), + z0 = svdup_s16_m (z0, p0, -1)) + +/* +** dup_m128_s16_m: +** mov z0\.h, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -128), + z0 = svdup_s16_m (z0, p0, -128)) + +/* +** dup_m129_s16_m: +** mov (z[0-9]+\.h), #-129 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -129), + z0 = svdup_s16_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -130), + z0 = svdup_s16_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -254), + z0 = svdup_s16_m (z0, p0, -254)) + +/* +** dup_m255_s16_m: +** mov (z[0-9]+\.h), #-255 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -255), + z0 = svdup_s16_m (z0, p0, -255)) + +/* +** dup_m256_s16_m: +** mov z0\.h, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -256), + z0 = svdup_s16_m (z0, p0, -256)) + +/* +** dup_m257_s16_m: +** mov (z[0-9]+\.h), #-257 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -257), + z0 = svdup_s16_m (z0, p0, -257)) + +/* +** dup_m258_s16_m: +** mov (z[0-9]+)\.b, #-2 +** sel z0\.h, p0, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -258), + z0 = svdup_s16_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -259), + z0 = svdup_s16_m (z0, p0, -259)) + +/* +** dup_m512_s16_m: +** mov z0\.h, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -512), + z0 = svdup_s16_m (z0, p0, -512)) + +/* +** dup_m7f00_s16_m: +** mov z0\.h, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x7f00), + z0 = svdup_s16_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_s16_m: +** mov (z[0-9]+\.h), #-32513 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x7f01), + z0 = svdup_s16_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x7f02), + z0 = svdup_s16_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x7ffe), + z0 = svdup_s16_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_s16_m: +** mov (z[0-9]+\.h), #-32767 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x7fff), + z0 = svdup_s16_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_s16_m: +** mov z0\.h, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, -0x8000), + z0 = svdup_s16_m (z0, p0, -0x8000)) + +/* +** dup_0_s16_m: +** mov z0\.h, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s16_m, svint16_t, + z0 = svdup_n_s16_m (z0, p0, 0), + z0 = svdup_s16_m (z0, p0, 0)) + +/* +** dup_w0_s16_m: +** movprfx z0, z1 +** mov z0\.h, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s16_m, svint16_t, int16_t, + z0 = svdup_n_s16_m (z1, p0, x0), + z0 = svdup_s16_m (z1, p0, x0)) + +/* +** dup_1_s16_z: +** mov z0\.h, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 1), + z0 = svdup_s16_z (p0, 1)) + +/* +** dup_127_s16_z: +** mov z0\.h, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 127), + z0 = svdup_s16_z (p0, 127)) + +/* +** dup_128_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #128 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_128_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 128), + z0 = svdup_s16_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 129), + z0 = svdup_s16_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 253), + z0 = svdup_s16_z (p0, 253)) + +/* +** dup_254_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #254 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_254_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 254), + z0 = svdup_s16_z (p0, 254)) + +/* +** dup_255_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #255 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_255_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 255), + z0 = svdup_s16_z (p0, 255)) + +/* +** dup_256_s16_z: +** mov z0\.h, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 256), + z0 = svdup_s16_z (p0, 256)) + +/* +** dup_257_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+)\.b, #1 +** sel z0\.h, p0, \2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_257_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 257), + z0 = svdup_s16_z (p0, 257)) + +/* +** dup_512_s16_z: +** mov z0\.h, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 512), + z0 = svdup_s16_z (p0, 512)) + +/* +** dup_7f00_s16_z: +** mov z0\.h, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0x7f00), + z0 = svdup_s16_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0x7f01), + z0 = svdup_s16_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0x7ffd), + z0 = svdup_s16_z (p0, 0x7ffd)) + +/* +** dup_7ffe_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #32766 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0x7ffe), + z0 = svdup_s16_z (p0, 0x7ffe)) + +/* +** dup_7fff_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #32767 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0x7fff), + z0 = svdup_s16_z (p0, 0x7fff)) + +/* +** dup_m1_s16_z: +** mov z0\.h, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -1), + z0 = svdup_s16_z (p0, -1)) + +/* +** dup_m128_s16_z: +** mov z0\.h, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -128), + z0 = svdup_s16_z (p0, -128)) + +/* +** dup_m129_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-129 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -129), + z0 = svdup_s16_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -130), + z0 = svdup_s16_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -254), + z0 = svdup_s16_z (p0, -254)) + +/* +** dup_m255_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-255 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -255), + z0 = svdup_s16_z (p0, -255)) + +/* +** dup_m256_s16_z: +** mov z0\.h, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -256), + z0 = svdup_s16_z (p0, -256)) + +/* +** dup_m257_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-257 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -257), + z0 = svdup_s16_z (p0, -257)) + +/* +** dup_m258_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+)\.b, #-2 +** sel z0\.h, p0, \2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -258), + z0 = svdup_s16_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -259), + z0 = svdup_s16_z (p0, -259)) + +/* +** dup_m512_s16_z: +** mov z0\.h, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -512), + z0 = svdup_s16_z (p0, -512)) + +/* +** dup_m7f00_s16_z: +** mov z0\.h, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x7f00), + z0 = svdup_s16_z (p0, -0x7f00)) + +/* +** dup_m7f01_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-32513 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x7f01), + z0 = svdup_s16_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x7f02), + z0 = svdup_s16_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x7ffe), + z0 = svdup_s16_z (p0, -0x7ffe)) + +/* +** dup_m7fff_s16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-32767 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x7fff), + z0 = svdup_s16_z (p0, -0x7fff)) + +/* +** dup_m8000_s16_z: +** mov z0\.h, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, -0x8000), + z0 = svdup_s16_z (p0, -0x8000)) + +/* +** dup_0_s16_z: +** mov z0\.h, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s16_z, svint16_t, + z0 = svdup_n_s16_z (p0, 0), + z0 = svdup_s16_z (p0, 0)) + +/* +** dup_w0_s16_z: +** movprfx z0\.h, p0/z, z0\.h +** mov z0\.h, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s16_z, svint16_t, int16_t, + z0 = svdup_n_s16_z (p0, x0), + z0 = svdup_s16_z (p0, x0)) + +/* +** dup_1_s16_x: +** mov z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 1), + z0 = svdup_s16_x (p0, 1)) + +/* +** dup_127_s16_x: +** mov z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 127), + z0 = svdup_s16_x (p0, 127)) + +/* +** dup_128_s16_x: +** mov z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 128), + z0 = svdup_s16_x (p0, 128)) + +/* +** dup_129_s16_x: +** movi v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 129), + z0 = svdup_s16_x (p0, 129)) + +/* +** dup_253_s16_x: +** movi v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 253), + z0 = svdup_s16_x (p0, 253)) + +/* +** dup_254_s16_x: +** mov z0\.h, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 254), + z0 = svdup_s16_x (p0, 254)) + +/* +** dup_255_s16_x: +** mov z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 255), + z0 = svdup_s16_x (p0, 255)) + +/* +** dup_256_s16_x: +** mov z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 256), + z0 = svdup_s16_x (p0, 256)) + +/* +** dup_257_s16_x: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 257), + z0 = svdup_s16_x (p0, 257)) + +/* +** dup_512_s16_x: +** mov z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 512), + z0 = svdup_s16_x (p0, 512)) + +/* +** dup_7f00_s16_x: +** mov z0\.h, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 0x7f00), + z0 = svdup_s16_x (p0, 0x7f00)) + +/* +** dup_7f01_s16_x: +** mov (w[0-9]+), 32513 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 0x7f01), + z0 = svdup_s16_x (p0, 0x7f01)) + +/* +** dup_7ffd_s16_x: +** mov (w[0-9]+), 32765 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 0x7ffd), + z0 = svdup_s16_x (p0, 0x7ffd)) + +/* +** dup_7ffe_s16_x: +** mov z0\.h, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 0x7ffe), + z0 = svdup_s16_x (p0, 0x7ffe)) + +/* +** dup_7fff_s16_x: +** mov z0\.h, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, 0x7fff), + z0 = svdup_s16_x (p0, 0x7fff)) + +/* +** dup_m1_s16_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -1), + z0 = svdup_s16_x (p0, -1)) + +/* +** dup_m128_s16_x: +** mov z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -128), + z0 = svdup_s16_x (p0, -128)) + +/* +** dup_m129_s16_x: +** mov z0\.h, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -129), + z0 = svdup_s16_x (p0, -129)) + +/* +** dup_m130_s16_x: +** mvni v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -130), + z0 = svdup_s16_x (p0, -130)) + +/* +** dup_m254_s16_x: +** mvni v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -254), + z0 = svdup_s16_x (p0, -254)) + +/* +** dup_m255_s16_x: +** mov z0\.h, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -255), + z0 = svdup_s16_x (p0, -255)) + +/* +** dup_m256_s16_x: +** mov z0\.h, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -256), + z0 = svdup_s16_x (p0, -256)) + +/* +** dup_m257_s16_x: +** mov z0\.h, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -257), + z0 = svdup_s16_x (p0, -257)) + +/* +** dup_m258_s16_x: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -258), + z0 = svdup_s16_x (p0, -258)) + +/* +** dup_m259_s16_x: +** mov (w[0-9]+), -259 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -259), + z0 = svdup_s16_x (p0, -259)) + +/* +** dup_m512_s16_x: +** mov z0\.h, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -512), + z0 = svdup_s16_x (p0, -512)) + +/* +** dup_m7f00_s16_x: +** mov z0\.h, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x7f00), + z0 = svdup_s16_x (p0, -0x7f00)) + +/* +** dup_m7f01_s16_x: +** mov z0\.h, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x7f01), + z0 = svdup_s16_x (p0, -0x7f01)) + +/* +** dup_m7f02_s16_x: +** mov (w[0-9]+), -32514 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x7f02), + z0 = svdup_s16_x (p0, -0x7f02)) + +/* +** dup_m7ffe_s16_x: +** mov (w[0-9]+), -32766 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x7ffe), + z0 = svdup_s16_x (p0, -0x7ffe)) + +/* +** dup_m7fff_s16_x: +** mov z0\.h, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x7fff), + z0 = svdup_s16_x (p0, -0x7fff)) + +/* +** dup_m8000_s16_x: +** mov z0\.h, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s16_x, svint16_t, + z0 = svdup_n_s16_x (p0, -0x8000), + z0 = svdup_s16_x (p0, -0x8000)) + +/* +** dup_w0_s16_x: +** mov z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s16_x, svint16_t, int16_t, + z0 = svdup_n_s16_x (p0, x0), + z0 = svdup_s16_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c new file mode 100644 index 00000000000..0b396dbeb50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s32.c @@ -0,0 +1,1175 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_s32: +** mov z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s32, svint32_t, + z0 = svdup_n_s32 (1), + z0 = svdup_s32 (1)) + +/* +** dup_127_s32: +** mov z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s32, svint32_t, + z0 = svdup_n_s32 (127), + z0 = svdup_s32 (127)) + +/* +** dup_128_s32: +** mov z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s32, svint32_t, + z0 = svdup_n_s32 (128), + z0 = svdup_s32 (128)) + +/* +** dup_129_s32: +** movi v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_s32, svint32_t, + z0 = svdup_n_s32 (129), + z0 = svdup_s32 (129)) + +/* +** dup_253_s32: +** movi v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_s32, svint32_t, + z0 = svdup_n_s32 (253), + z0 = svdup_s32 (253)) + +/* +** dup_254_s32: +** mov z0\.s, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s32, svint32_t, + z0 = svdup_n_s32 (254), + z0 = svdup_s32 (254)) + +/* +** dup_255_s32: +** mov z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s32, svint32_t, + z0 = svdup_n_s32 (255), + z0 = svdup_s32 (255)) + +/* +** dup_256_s32: +** mov z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s32, svint32_t, + z0 = svdup_n_s32 (256), + z0 = svdup_s32 (256)) + +/* +** dup_257_s32: +** mov (w[0-9]+), 257 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s32, svint32_t, + z0 = svdup_n_s32 (257), + z0 = svdup_s32 (257)) + +/* +** dup_512_s32: +** mov z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s32, svint32_t, + z0 = svdup_n_s32 (512), + z0 = svdup_s32 (512)) + +/* +** dup_7f00_s32: +** mov z0\.s, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s32, svint32_t, + z0 = svdup_n_s32 (0x7f00), + z0 = svdup_s32 (0x7f00)) + +/* +** dup_7f01_s32: +** mov (w[0-9]+), 32513 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s32, svint32_t, + z0 = svdup_n_s32 (0x7f01), + z0 = svdup_s32 (0x7f01)) + +/* +** dup_7ffd_s32: +** mov (w[0-9]+), 32765 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s32, svint32_t, + z0 = svdup_n_s32 (0x7ffd), + z0 = svdup_s32 (0x7ffd)) + +/* +** dup_7ffe_s32: +** mov z0\.s, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s32, svint32_t, + z0 = svdup_n_s32 (0x7ffe), + z0 = svdup_s32 (0x7ffe)) + +/* +** dup_7fff_s32: +** mov z0\.s, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s32, svint32_t, + z0 = svdup_n_s32 (0x7fff), + z0 = svdup_s32 (0x7fff)) + +/* +** dup_m1_s32: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s32, svint32_t, + z0 = svdup_n_s32 (-1), + z0 = svdup_s32 (-1)) + +/* +** dup_m128_s32: +** mov z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s32, svint32_t, + z0 = svdup_n_s32 (-128), + z0 = svdup_s32 (-128)) + +/* +** dup_m129_s32: +** mov z0\.s, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s32, svint32_t, + z0 = svdup_n_s32 (-129), + z0 = svdup_s32 (-129)) + +/* +** dup_m130_s32: +** mvni v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s32, svint32_t, + z0 = svdup_n_s32 (-130), + z0 = svdup_s32 (-130)) + +/* +** dup_m254_s32: +** mvni v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s32, svint32_t, + z0 = svdup_n_s32 (-254), + z0 = svdup_s32 (-254)) + +/* +** dup_m255_s32: +** mov z0\.s, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s32, svint32_t, + z0 = svdup_n_s32 (-255), + z0 = svdup_s32 (-255)) + +/* +** dup_m256_s32: +** mov z0\.s, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s32, svint32_t, + z0 = svdup_n_s32 (-256), + z0 = svdup_s32 (-256)) + +/* +** dup_m257_s32: +** mov z0\.s, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s32, svint32_t, + z0 = svdup_n_s32 (-257), + z0 = svdup_s32 (-257)) + +/* +** dup_m258_s32: +** mov (w[0-9]+), -258 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s32, svint32_t, + z0 = svdup_n_s32 (-258), + z0 = svdup_s32 (-258)) + +/* +** dup_m259_s32: +** mov (w[0-9]+), -259 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s32, svint32_t, + z0 = svdup_n_s32 (-259), + z0 = svdup_s32 (-259)) + +/* +** dup_m512_s32: +** mov z0\.s, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s32, svint32_t, + z0 = svdup_n_s32 (-512), + z0 = svdup_s32 (-512)) + +/* +** dup_m7f00_s32: +** mov z0\.s, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s32, svint32_t, + z0 = svdup_n_s32 (-0x7f00), + z0 = svdup_s32 (-0x7f00)) + +/* +** dup_m7f01_s32: +** mov z0\.s, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s32, svint32_t, + z0 = svdup_n_s32 (-0x7f01), + z0 = svdup_s32 (-0x7f01)) + +/* +** dup_m7f02_s32: +** mov (w[0-9]+), -32514 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s32, svint32_t, + z0 = svdup_n_s32 (-0x7f02), + z0 = svdup_s32 (-0x7f02)) + +/* +** dup_m7ffe_s32: +** mov (w[0-9]+), -32766 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s32, svint32_t, + z0 = svdup_n_s32 (-0x7ffe), + z0 = svdup_s32 (-0x7ffe)) + +/* +** dup_m7fff_s32: +** mov z0\.s, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s32, svint32_t, + z0 = svdup_n_s32 (-0x7fff), + z0 = svdup_s32 (-0x7fff)) + +/* +** dup_m8000_s32: +** mov z0\.s, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s32, svint32_t, + z0 = svdup_n_s32 (-0x8000), + z0 = svdup_s32 (-0x8000)) + +/* +** dup_w0_s32: +** mov z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s32, svint32_t, int32_t, + z0 = svdup_n_s32 (x0), + z0 = svdup_s32 (x0)) + +/* +** dup_1_s32_m: +** mov z0\.s, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 1), + z0 = svdup_s32_m (z0, p0, 1)) + +/* +** dup_127_s32_m: +** mov z0\.s, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 127), + z0 = svdup_s32_m (z0, p0, 127)) + +/* +** dup_128_s32_m: +** mov (z[0-9]+\.s), #128 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_128_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 128), + z0 = svdup_s32_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 129), + z0 = svdup_s32_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 253), + z0 = svdup_s32_m (z0, p0, 253)) + +/* +** dup_254_s32_m: +** mov (z[0-9]+\.s), #254 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_254_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 254), + z0 = svdup_s32_m (z0, p0, 254)) + +/* +** dup_255_s32_m: +** mov (z[0-9]+\.s), #255 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_255_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 255), + z0 = svdup_s32_m (z0, p0, 255)) + +/* +** dup_256_s32_m: +** mov z0\.s, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 256), + z0 = svdup_s32_m (z0, p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 257), + z0 = svdup_s32_m (z0, p0, 257)) + +/* +** dup_512_s32_m: +** mov z0\.s, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 512), + z0 = svdup_s32_m (z0, p0, 512)) + +/* +** dup_7f00_s32_m: +** mov z0\.s, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0x7f00), + z0 = svdup_s32_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0x7f01), + z0 = svdup_s32_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0x7ffd), + z0 = svdup_s32_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_s32_m: +** mov (z[0-9]+\.s), #32766 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0x7ffe), + z0 = svdup_s32_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_s32_m: +** mov (z[0-9]+\.s), #32767 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0x7fff), + z0 = svdup_s32_m (z0, p0, 0x7fff)) + +/* +** dup_m1_s32_m: +** mov z0\.s, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -1), + z0 = svdup_s32_m (z0, p0, -1)) + +/* +** dup_m128_s32_m: +** mov z0\.s, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -128), + z0 = svdup_s32_m (z0, p0, -128)) + +/* +** dup_m129_s32_m: +** mov (z[0-9]+\.s), #-129 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -129), + z0 = svdup_s32_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -130), + z0 = svdup_s32_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -254), + z0 = svdup_s32_m (z0, p0, -254)) + +/* +** dup_m255_s32_m: +** mov (z[0-9]+\.s), #-255 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -255), + z0 = svdup_s32_m (z0, p0, -255)) + +/* +** dup_m256_s32_m: +** mov z0\.s, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -256), + z0 = svdup_s32_m (z0, p0, -256)) + +/* +** dup_m257_s32_m: +** mov (z[0-9]+\.s), #-257 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -257), + z0 = svdup_s32_m (z0, p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -258), + z0 = svdup_s32_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -259), + z0 = svdup_s32_m (z0, p0, -259)) + +/* +** dup_m512_s32_m: +** mov z0\.s, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -512), + z0 = svdup_s32_m (z0, p0, -512)) + +/* +** dup_m7f00_s32_m: +** mov z0\.s, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x7f00), + z0 = svdup_s32_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_s32_m: +** mov (z[0-9]+\.s), #-32513 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x7f01), + z0 = svdup_s32_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x7f02), + z0 = svdup_s32_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x7ffe), + z0 = svdup_s32_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_s32_m: +** mov (z[0-9]+\.s), #-32767 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x7fff), + z0 = svdup_s32_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_s32_m: +** mov z0\.s, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, -0x8000), + z0 = svdup_s32_m (z0, p0, -0x8000)) + +/* +** dup_0_s32_m: +** mov z0\.s, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s32_m, svint32_t, + z0 = svdup_n_s32_m (z0, p0, 0), + z0 = svdup_s32_m (z0, p0, 0)) + +/* +** dup_w0_s32_m: +** movprfx z0, z1 +** mov z0\.s, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s32_m, svint32_t, int32_t, + z0 = svdup_n_s32_m (z1, p0, x0), + z0 = svdup_s32_m (z1, p0, x0)) + +/* +** dup_1_s32_z: +** mov z0\.s, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 1), + z0 = svdup_s32_z (p0, 1)) + +/* +** dup_127_s32_z: +** mov z0\.s, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 127), + z0 = svdup_s32_z (p0, 127)) + +/* +** dup_128_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #128 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_128_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 128), + z0 = svdup_s32_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 129), + z0 = svdup_s32_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 253), + z0 = svdup_s32_z (p0, 253)) + +/* +** dup_254_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #254 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_254_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 254), + z0 = svdup_s32_z (p0, 254)) + +/* +** dup_255_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #255 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_255_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 255), + z0 = svdup_s32_z (p0, 255)) + +/* +** dup_256_s32_z: +** mov z0\.s, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 256), + z0 = svdup_s32_z (p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 257), + z0 = svdup_s32_z (p0, 257)) + +/* +** dup_512_s32_z: +** mov z0\.s, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 512), + z0 = svdup_s32_z (p0, 512)) + +/* +** dup_7f00_s32_z: +** mov z0\.s, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0x7f00), + z0 = svdup_s32_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0x7f01), + z0 = svdup_s32_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0x7ffd), + z0 = svdup_s32_z (p0, 0x7ffd)) + +/* +** dup_7ffe_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #32766 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0x7ffe), + z0 = svdup_s32_z (p0, 0x7ffe)) + +/* +** dup_7fff_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #32767 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0x7fff), + z0 = svdup_s32_z (p0, 0x7fff)) + +/* +** dup_m1_s32_z: +** mov z0\.s, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -1), + z0 = svdup_s32_z (p0, -1)) + +/* +** dup_m128_s32_z: +** mov z0\.s, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -128), + z0 = svdup_s32_z (p0, -128)) + +/* +** dup_m129_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-129 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -129), + z0 = svdup_s32_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -130), + z0 = svdup_s32_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -254), + z0 = svdup_s32_z (p0, -254)) + +/* +** dup_m255_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-255 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -255), + z0 = svdup_s32_z (p0, -255)) + +/* +** dup_m256_s32_z: +** mov z0\.s, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -256), + z0 = svdup_s32_z (p0, -256)) + +/* +** dup_m257_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-257 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -257), + z0 = svdup_s32_z (p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -258), + z0 = svdup_s32_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -259), + z0 = svdup_s32_z (p0, -259)) + +/* +** dup_m512_s32_z: +** mov z0\.s, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -512), + z0 = svdup_s32_z (p0, -512)) + +/* +** dup_m7f00_s32_z: +** mov z0\.s, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x7f00), + z0 = svdup_s32_z (p0, -0x7f00)) + +/* +** dup_m7f01_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-32513 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x7f01), + z0 = svdup_s32_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x7f02), + z0 = svdup_s32_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x7ffe), + z0 = svdup_s32_z (p0, -0x7ffe)) + +/* +** dup_m7fff_s32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-32767 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x7fff), + z0 = svdup_s32_z (p0, -0x7fff)) + +/* +** dup_m8000_s32_z: +** mov z0\.s, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, -0x8000), + z0 = svdup_s32_z (p0, -0x8000)) + +/* +** dup_0_s32_z: +** mov z0\.s, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s32_z, svint32_t, + z0 = svdup_n_s32_z (p0, 0), + z0 = svdup_s32_z (p0, 0)) + +/* +** dup_w0_s32_z: +** movprfx z0\.s, p0/z, z0\.s +** mov z0\.s, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s32_z, svint32_t, int32_t, + z0 = svdup_n_s32_z (p0, x0), + z0 = svdup_s32_z (p0, x0)) + +/* +** dup_1_s32_x: +** mov z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 1), + z0 = svdup_s32_x (p0, 1)) + +/* +** dup_127_s32_x: +** mov z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 127), + z0 = svdup_s32_x (p0, 127)) + +/* +** dup_128_s32_x: +** mov z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 128), + z0 = svdup_s32_x (p0, 128)) + +/* +** dup_129_s32_x: +** movi v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 129), + z0 = svdup_s32_x (p0, 129)) + +/* +** dup_253_s32_x: +** movi v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 253), + z0 = svdup_s32_x (p0, 253)) + +/* +** dup_254_s32_x: +** mov z0\.s, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 254), + z0 = svdup_s32_x (p0, 254)) + +/* +** dup_255_s32_x: +** mov z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 255), + z0 = svdup_s32_x (p0, 255)) + +/* +** dup_256_s32_x: +** mov z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 256), + z0 = svdup_s32_x (p0, 256)) + +/* +** dup_257_s32_x: +** mov (w[0-9]+), 257 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 257), + z0 = svdup_s32_x (p0, 257)) + +/* +** dup_512_s32_x: +** mov z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 512), + z0 = svdup_s32_x (p0, 512)) + +/* +** dup_7f00_s32_x: +** mov z0\.s, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 0x7f00), + z0 = svdup_s32_x (p0, 0x7f00)) + +/* +** dup_7f01_s32_x: +** mov (w[0-9]+), 32513 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 0x7f01), + z0 = svdup_s32_x (p0, 0x7f01)) + +/* +** dup_7ffd_s32_x: +** mov (w[0-9]+), 32765 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 0x7ffd), + z0 = svdup_s32_x (p0, 0x7ffd)) + +/* +** dup_7ffe_s32_x: +** mov z0\.s, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 0x7ffe), + z0 = svdup_s32_x (p0, 0x7ffe)) + +/* +** dup_7fff_s32_x: +** mov z0\.s, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, 0x7fff), + z0 = svdup_s32_x (p0, 0x7fff)) + +/* +** dup_m1_s32_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -1), + z0 = svdup_s32_x (p0, -1)) + +/* +** dup_m128_s32_x: +** mov z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -128), + z0 = svdup_s32_x (p0, -128)) + +/* +** dup_m129_s32_x: +** mov z0\.s, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -129), + z0 = svdup_s32_x (p0, -129)) + +/* +** dup_m130_s32_x: +** mvni v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -130), + z0 = svdup_s32_x (p0, -130)) + +/* +** dup_m254_s32_x: +** mvni v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -254), + z0 = svdup_s32_x (p0, -254)) + +/* +** dup_m255_s32_x: +** mov z0\.s, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -255), + z0 = svdup_s32_x (p0, -255)) + +/* +** dup_m256_s32_x: +** mov z0\.s, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -256), + z0 = svdup_s32_x (p0, -256)) + +/* +** dup_m257_s32_x: +** mov z0\.s, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -257), + z0 = svdup_s32_x (p0, -257)) + +/* +** dup_m258_s32_x: +** mov (w[0-9]+), -258 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -258), + z0 = svdup_s32_x (p0, -258)) + +/* +** dup_m259_s32_x: +** mov (w[0-9]+), -259 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -259), + z0 = svdup_s32_x (p0, -259)) + +/* +** dup_m512_s32_x: +** mov z0\.s, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -512), + z0 = svdup_s32_x (p0, -512)) + +/* +** dup_m7f00_s32_x: +** mov z0\.s, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x7f00), + z0 = svdup_s32_x (p0, -0x7f00)) + +/* +** dup_m7f01_s32_x: +** mov z0\.s, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x7f01), + z0 = svdup_s32_x (p0, -0x7f01)) + +/* +** dup_m7f02_s32_x: +** mov (w[0-9]+), -32514 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x7f02), + z0 = svdup_s32_x (p0, -0x7f02)) + +/* +** dup_m7ffe_s32_x: +** mov (w[0-9]+), -32766 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x7ffe), + z0 = svdup_s32_x (p0, -0x7ffe)) + +/* +** dup_m7fff_s32_x: +** mov z0\.s, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x7fff), + z0 = svdup_s32_x (p0, -0x7fff)) + +/* +** dup_m8000_s32_x: +** mov z0\.s, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s32_x, svint32_t, + z0 = svdup_n_s32_x (p0, -0x8000), + z0 = svdup_s32_x (p0, -0x8000)) + +/* +** dup_w0_s32_x: +** mov z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s32_x, svint32_t, int32_t, + z0 = svdup_n_s32_x (p0, x0), + z0 = svdup_s32_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c new file mode 100644 index 00000000000..6259b7fb55d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s64.c @@ -0,0 +1,1175 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_s64: +** mov z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s64, svint64_t, + z0 = svdup_n_s64 (1), + z0 = svdup_s64 (1)) + +/* +** dup_127_s64: +** mov z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s64, svint64_t, + z0 = svdup_n_s64 (127), + z0 = svdup_s64 (127)) + +/* +** dup_128_s64: +** mov z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s64, svint64_t, + z0 = svdup_n_s64 (128), + z0 = svdup_s64 (128)) + +/* +** dup_129_s64: +** mov (x[0-9]+), 129 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s64, svint64_t, + z0 = svdup_n_s64 (129), + z0 = svdup_s64 (129)) + +/* +** dup_253_s64: +** mov (x[0-9]+), 253 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s64, svint64_t, + z0 = svdup_n_s64 (253), + z0 = svdup_s64 (253)) + +/* +** dup_254_s64: +** mov z0\.d, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s64, svint64_t, + z0 = svdup_n_s64 (254), + z0 = svdup_s64 (254)) + +/* +** dup_255_s64: +** mov z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s64, svint64_t, + z0 = svdup_n_s64 (255), + z0 = svdup_s64 (255)) + +/* +** dup_256_s64: +** mov z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s64, svint64_t, + z0 = svdup_n_s64 (256), + z0 = svdup_s64 (256)) + +/* +** dup_257_s64: +** mov (x[0-9]+), 257 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s64, svint64_t, + z0 = svdup_n_s64 (257), + z0 = svdup_s64 (257)) + +/* +** dup_512_s64: +** mov z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s64, svint64_t, + z0 = svdup_n_s64 (512), + z0 = svdup_s64 (512)) + +/* +** dup_7f00_s64: +** mov z0\.d, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s64, svint64_t, + z0 = svdup_n_s64 (0x7f00), + z0 = svdup_s64 (0x7f00)) + +/* +** dup_7f01_s64: +** mov (x[0-9]+), 32513 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s64, svint64_t, + z0 = svdup_n_s64 (0x7f01), + z0 = svdup_s64 (0x7f01)) + +/* +** dup_7ffd_s64: +** mov (x[0-9]+), 32765 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s64, svint64_t, + z0 = svdup_n_s64 (0x7ffd), + z0 = svdup_s64 (0x7ffd)) + +/* +** dup_7ffe_s64: +** mov z0\.d, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s64, svint64_t, + z0 = svdup_n_s64 (0x7ffe), + z0 = svdup_s64 (0x7ffe)) + +/* +** dup_7fff_s64: +** mov z0\.d, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s64, svint64_t, + z0 = svdup_n_s64 (0x7fff), + z0 = svdup_s64 (0x7fff)) + +/* +** dup_m1_s64: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s64, svint64_t, + z0 = svdup_n_s64 (-1), + z0 = svdup_s64 (-1)) + +/* +** dup_m128_s64: +** mov z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s64, svint64_t, + z0 = svdup_n_s64 (-128), + z0 = svdup_s64 (-128)) + +/* +** dup_m129_s64: +** mov z0\.d, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s64, svint64_t, + z0 = svdup_n_s64 (-129), + z0 = svdup_s64 (-129)) + +/* +** dup_m130_s64: +** mov (x[0-9]+), -130 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s64, svint64_t, + z0 = svdup_n_s64 (-130), + z0 = svdup_s64 (-130)) + +/* +** dup_m254_s64: +** mov (x[0-9]+), -254 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s64, svint64_t, + z0 = svdup_n_s64 (-254), + z0 = svdup_s64 (-254)) + +/* +** dup_m255_s64: +** mov z0\.d, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s64, svint64_t, + z0 = svdup_n_s64 (-255), + z0 = svdup_s64 (-255)) + +/* +** dup_m256_s64: +** mov z0\.d, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s64, svint64_t, + z0 = svdup_n_s64 (-256), + z0 = svdup_s64 (-256)) + +/* +** dup_m257_s64: +** mov z0\.d, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s64, svint64_t, + z0 = svdup_n_s64 (-257), + z0 = svdup_s64 (-257)) + +/* +** dup_m258_s64: +** mov (x[0-9]+), -258 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s64, svint64_t, + z0 = svdup_n_s64 (-258), + z0 = svdup_s64 (-258)) + +/* +** dup_m259_s64: +** mov (x[0-9]+), -259 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s64, svint64_t, + z0 = svdup_n_s64 (-259), + z0 = svdup_s64 (-259)) + +/* +** dup_m512_s64: +** mov z0\.d, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s64, svint64_t, + z0 = svdup_n_s64 (-512), + z0 = svdup_s64 (-512)) + +/* +** dup_m7f00_s64: +** mov z0\.d, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s64, svint64_t, + z0 = svdup_n_s64 (-0x7f00), + z0 = svdup_s64 (-0x7f00)) + +/* +** dup_m7f01_s64: +** mov z0\.d, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s64, svint64_t, + z0 = svdup_n_s64 (-0x7f01), + z0 = svdup_s64 (-0x7f01)) + +/* +** dup_m7f02_s64: +** mov (x[0-9]+), -32514 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s64, svint64_t, + z0 = svdup_n_s64 (-0x7f02), + z0 = svdup_s64 (-0x7f02)) + +/* +** dup_m7ffe_s64: +** mov (x[0-9]+), -32766 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s64, svint64_t, + z0 = svdup_n_s64 (-0x7ffe), + z0 = svdup_s64 (-0x7ffe)) + +/* +** dup_m7fff_s64: +** mov z0\.d, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s64, svint64_t, + z0 = svdup_n_s64 (-0x7fff), + z0 = svdup_s64 (-0x7fff)) + +/* +** dup_m8000_s64: +** mov z0\.d, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s64, svint64_t, + z0 = svdup_n_s64 (-0x8000), + z0 = svdup_s64 (-0x8000)) + +/* +** dup_x0_s64: +** mov z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_s64, svint64_t, int64_t, + z0 = svdup_n_s64 (x0), + z0 = svdup_s64 (x0)) + +/* +** dup_1_s64_m: +** mov z0\.d, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 1), + z0 = svdup_s64_m (z0, p0, 1)) + +/* +** dup_127_s64_m: +** mov z0\.d, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 127), + z0 = svdup_s64_m (z0, p0, 127)) + +/* +** dup_128_s64_m: +** mov (z[0-9]+\.d), #128 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_128_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 128), + z0 = svdup_s64_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 129), + z0 = svdup_s64_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 253), + z0 = svdup_s64_m (z0, p0, 253)) + +/* +** dup_254_s64_m: +** mov (z[0-9]+\.d), #254 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_254_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 254), + z0 = svdup_s64_m (z0, p0, 254)) + +/* +** dup_255_s64_m: +** mov (z[0-9]+\.d), #255 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_255_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 255), + z0 = svdup_s64_m (z0, p0, 255)) + +/* +** dup_256_s64_m: +** mov z0\.d, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 256), + z0 = svdup_s64_m (z0, p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 257), + z0 = svdup_s64_m (z0, p0, 257)) + +/* +** dup_512_s64_m: +** mov z0\.d, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 512), + z0 = svdup_s64_m (z0, p0, 512)) + +/* +** dup_7f00_s64_m: +** mov z0\.d, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0x7f00), + z0 = svdup_s64_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0x7f01), + z0 = svdup_s64_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0x7ffd), + z0 = svdup_s64_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_s64_m: +** mov (z[0-9]+\.d), #32766 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0x7ffe), + z0 = svdup_s64_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_s64_m: +** mov (z[0-9]+\.d), #32767 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0x7fff), + z0 = svdup_s64_m (z0, p0, 0x7fff)) + +/* +** dup_m1_s64_m: +** mov z0\.d, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -1), + z0 = svdup_s64_m (z0, p0, -1)) + +/* +** dup_m128_s64_m: +** mov z0\.d, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -128), + z0 = svdup_s64_m (z0, p0, -128)) + +/* +** dup_m129_s64_m: +** mov (z[0-9]+\.d), #-129 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -129), + z0 = svdup_s64_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -130), + z0 = svdup_s64_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -254), + z0 = svdup_s64_m (z0, p0, -254)) + +/* +** dup_m255_s64_m: +** mov (z[0-9]+\.d), #-255 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -255), + z0 = svdup_s64_m (z0, p0, -255)) + +/* +** dup_m256_s64_m: +** mov z0\.d, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -256), + z0 = svdup_s64_m (z0, p0, -256)) + +/* +** dup_m257_s64_m: +** mov (z[0-9]+\.d), #-257 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -257), + z0 = svdup_s64_m (z0, p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -258), + z0 = svdup_s64_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -259), + z0 = svdup_s64_m (z0, p0, -259)) + +/* +** dup_m512_s64_m: +** mov z0\.d, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -512), + z0 = svdup_s64_m (z0, p0, -512)) + +/* +** dup_m7f00_s64_m: +** mov z0\.d, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x7f00), + z0 = svdup_s64_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_s64_m: +** mov (z[0-9]+\.d), #-32513 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x7f01), + z0 = svdup_s64_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x7f02), + z0 = svdup_s64_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x7ffe), + z0 = svdup_s64_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_s64_m: +** mov (z[0-9]+\.d), #-32767 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x7fff), + z0 = svdup_s64_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_s64_m: +** mov z0\.d, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, -0x8000), + z0 = svdup_s64_m (z0, p0, -0x8000)) + +/* +** dup_0_s64_m: +** mov z0\.d, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s64_m, svint64_t, + z0 = svdup_n_s64_m (z0, p0, 0), + z0 = svdup_s64_m (z0, p0, 0)) + +/* +** dup_x0_s64_m: +** movprfx z0, z1 +** mov z0\.d, p0/m, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_s64_m, svint64_t, int64_t, + z0 = svdup_n_s64_m (z1, p0, x0), + z0 = svdup_s64_m (z1, p0, x0)) + +/* +** dup_1_s64_z: +** mov z0\.d, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 1), + z0 = svdup_s64_z (p0, 1)) + +/* +** dup_127_s64_z: +** mov z0\.d, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 127), + z0 = svdup_s64_z (p0, 127)) + +/* +** dup_128_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #128 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_128_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 128), + z0 = svdup_s64_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 129), + z0 = svdup_s64_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 253), + z0 = svdup_s64_z (p0, 253)) + +/* +** dup_254_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #254 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_254_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 254), + z0 = svdup_s64_z (p0, 254)) + +/* +** dup_255_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #255 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_255_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 255), + z0 = svdup_s64_z (p0, 255)) + +/* +** dup_256_s64_z: +** mov z0\.d, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 256), + z0 = svdup_s64_z (p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 257), + z0 = svdup_s64_z (p0, 257)) + +/* +** dup_512_s64_z: +** mov z0\.d, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 512), + z0 = svdup_s64_z (p0, 512)) + +/* +** dup_7f00_s64_z: +** mov z0\.d, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0x7f00), + z0 = svdup_s64_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0x7f01), + z0 = svdup_s64_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0x7ffd), + z0 = svdup_s64_z (p0, 0x7ffd)) + +/* +** dup_7ffe_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #32766 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0x7ffe), + z0 = svdup_s64_z (p0, 0x7ffe)) + +/* +** dup_7fff_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #32767 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0x7fff), + z0 = svdup_s64_z (p0, 0x7fff)) + +/* +** dup_m1_s64_z: +** mov z0\.d, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -1), + z0 = svdup_s64_z (p0, -1)) + +/* +** dup_m128_s64_z: +** mov z0\.d, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -128), + z0 = svdup_s64_z (p0, -128)) + +/* +** dup_m129_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-129 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -129), + z0 = svdup_s64_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -130), + z0 = svdup_s64_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -254), + z0 = svdup_s64_z (p0, -254)) + +/* +** dup_m255_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-255 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -255), + z0 = svdup_s64_z (p0, -255)) + +/* +** dup_m256_s64_z: +** mov z0\.d, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -256), + z0 = svdup_s64_z (p0, -256)) + +/* +** dup_m257_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-257 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -257), + z0 = svdup_s64_z (p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -258), + z0 = svdup_s64_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -259), + z0 = svdup_s64_z (p0, -259)) + +/* +** dup_m512_s64_z: +** mov z0\.d, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -512), + z0 = svdup_s64_z (p0, -512)) + +/* +** dup_m7f00_s64_z: +** mov z0\.d, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x7f00), + z0 = svdup_s64_z (p0, -0x7f00)) + +/* +** dup_m7f01_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-32513 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x7f01), + z0 = svdup_s64_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x7f02), + z0 = svdup_s64_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x7ffe), + z0 = svdup_s64_z (p0, -0x7ffe)) + +/* +** dup_m7fff_s64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-32767 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x7fff), + z0 = svdup_s64_z (p0, -0x7fff)) + +/* +** dup_m8000_s64_z: +** mov z0\.d, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, -0x8000), + z0 = svdup_s64_z (p0, -0x8000)) + +/* +** dup_0_s64_z: +** mov z0\.d, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s64_z, svint64_t, + z0 = svdup_n_s64_z (p0, 0), + z0 = svdup_s64_z (p0, 0)) + +/* +** dup_x0_s64_z: +** movprfx z0\.d, p0/z, z0\.d +** mov z0\.d, p0/m, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_s64_z, svint64_t, int64_t, + z0 = svdup_n_s64_z (p0, x0), + z0 = svdup_s64_z (p0, x0)) + +/* +** dup_1_s64_x: +** mov z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 1), + z0 = svdup_s64_x (p0, 1)) + +/* +** dup_127_s64_x: +** mov z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 127), + z0 = svdup_s64_x (p0, 127)) + +/* +** dup_128_s64_x: +** mov z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 128), + z0 = svdup_s64_x (p0, 128)) + +/* +** dup_129_s64_x: +** mov (x[0-9]+), 129 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 129), + z0 = svdup_s64_x (p0, 129)) + +/* +** dup_253_s64_x: +** mov (x[0-9]+), 253 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 253), + z0 = svdup_s64_x (p0, 253)) + +/* +** dup_254_s64_x: +** mov z0\.d, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 254), + z0 = svdup_s64_x (p0, 254)) + +/* +** dup_255_s64_x: +** mov z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 255), + z0 = svdup_s64_x (p0, 255)) + +/* +** dup_256_s64_x: +** mov z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 256), + z0 = svdup_s64_x (p0, 256)) + +/* +** dup_257_s64_x: +** mov (x[0-9]+), 257 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 257), + z0 = svdup_s64_x (p0, 257)) + +/* +** dup_512_s64_x: +** mov z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 512), + z0 = svdup_s64_x (p0, 512)) + +/* +** dup_7f00_s64_x: +** mov z0\.d, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 0x7f00), + z0 = svdup_s64_x (p0, 0x7f00)) + +/* +** dup_7f01_s64_x: +** mov (x[0-9]+), 32513 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 0x7f01), + z0 = svdup_s64_x (p0, 0x7f01)) + +/* +** dup_7ffd_s64_x: +** mov (x[0-9]+), 32765 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 0x7ffd), + z0 = svdup_s64_x (p0, 0x7ffd)) + +/* +** dup_7ffe_s64_x: +** mov z0\.d, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 0x7ffe), + z0 = svdup_s64_x (p0, 0x7ffe)) + +/* +** dup_7fff_s64_x: +** mov z0\.d, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, 0x7fff), + z0 = svdup_s64_x (p0, 0x7fff)) + +/* +** dup_m1_s64_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -1), + z0 = svdup_s64_x (p0, -1)) + +/* +** dup_m128_s64_x: +** mov z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -128), + z0 = svdup_s64_x (p0, -128)) + +/* +** dup_m129_s64_x: +** mov z0\.d, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -129), + z0 = svdup_s64_x (p0, -129)) + +/* +** dup_m130_s64_x: +** mov (x[0-9]+), -130 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m130_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -130), + z0 = svdup_s64_x (p0, -130)) + +/* +** dup_m254_s64_x: +** mov (x[0-9]+), -254 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m254_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -254), + z0 = svdup_s64_x (p0, -254)) + +/* +** dup_m255_s64_x: +** mov z0\.d, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -255), + z0 = svdup_s64_x (p0, -255)) + +/* +** dup_m256_s64_x: +** mov z0\.d, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -256), + z0 = svdup_s64_x (p0, -256)) + +/* +** dup_m257_s64_x: +** mov z0\.d, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -257), + z0 = svdup_s64_x (p0, -257)) + +/* +** dup_m258_s64_x: +** mov (x[0-9]+), -258 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -258), + z0 = svdup_s64_x (p0, -258)) + +/* +** dup_m259_s64_x: +** mov (x[0-9]+), -259 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -259), + z0 = svdup_s64_x (p0, -259)) + +/* +** dup_m512_s64_x: +** mov z0\.d, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -512), + z0 = svdup_s64_x (p0, -512)) + +/* +** dup_m7f00_s64_x: +** mov z0\.d, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x7f00), + z0 = svdup_s64_x (p0, -0x7f00)) + +/* +** dup_m7f01_s64_x: +** mov z0\.d, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x7f01), + z0 = svdup_s64_x (p0, -0x7f01)) + +/* +** dup_m7f02_s64_x: +** mov (x[0-9]+), -32514 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x7f02), + z0 = svdup_s64_x (p0, -0x7f02)) + +/* +** dup_m7ffe_s64_x: +** mov (x[0-9]+), -32766 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x7ffe), + z0 = svdup_s64_x (p0, -0x7ffe)) + +/* +** dup_m7fff_s64_x: +** mov z0\.d, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x7fff), + z0 = svdup_s64_x (p0, -0x7fff)) + +/* +** dup_m8000_s64_x: +** mov z0\.d, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_s64_x, svint64_t, + z0 = svdup_n_s64_x (p0, -0x8000), + z0 = svdup_s64_x (p0, -0x8000)) + +/* +** dup_x0_s64_x: +** mov z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_s64_x, svint64_t, int64_t, + z0 = svdup_n_s64_x (p0, x0), + z0 = svdup_s64_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c new file mode 100644 index 00000000000..96fc5fa6494 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_s8.c @@ -0,0 +1,383 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_s8: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s8, svint8_t, + z0 = svdup_n_s8 (1), + z0 = svdup_s8 (1)) + +/* +** dup_127_s8: +** mov z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s8, svint8_t, + z0 = svdup_n_s8 (127), + z0 = svdup_s8 (127)) + +/* +** dup_128_s8: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s8, svint8_t, + z0 = svdup_n_s8 (128), + z0 = svdup_s8 (128)) + +/* +** dup_129_s8: +** mov z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s8, svint8_t, + z0 = svdup_n_s8 (129), + z0 = svdup_s8 (129)) + +/* +** dup_253_s8: +** mov z0\.b, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s8, svint8_t, + z0 = svdup_n_s8 (253), + z0 = svdup_s8 (253)) + +/* +** dup_254_s8: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s8, svint8_t, + z0 = svdup_n_s8 (254), + z0 = svdup_s8 (254)) + +/* +** dup_255_s8: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s8, svint8_t, + z0 = svdup_n_s8 (255), + z0 = svdup_s8 (255)) + +/* +** dup_m1_s8: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s8, svint8_t, + z0 = svdup_n_s8 (-1), + z0 = svdup_s8 (-1)) + +/* +** dup_m128_s8: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s8, svint8_t, + z0 = svdup_n_s8 (-128), + z0 = svdup_s8 (-128)) + +/* +** dup_w0_s8: +** mov z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s8, svint8_t, int8_t, + z0 = svdup_n_s8 (x0), + z0 = svdup_s8 (x0)) + +/* +** dup_1_s8_m: +** mov z0\.b, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 1), + z0 = svdup_s8_m (z0, p0, 1)) + +/* +** dup_127_s8_m: +** mov z0\.b, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 127), + z0 = svdup_s8_m (z0, p0, 127)) + +/* +** dup_128_s8_m: +** mov z0\.b, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 128), + z0 = svdup_s8_m (z0, p0, 128)) + +/* +** dup_129_s8_m: +** mov z0\.b, p0/m, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 129), + z0 = svdup_s8_m (z0, p0, 129)) + +/* +** dup_253_s8_m: +** mov z0\.b, p0/m, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 253), + z0 = svdup_s8_m (z0, p0, 253)) + +/* +** dup_254_s8_m: +** mov z0\.b, p0/m, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 254), + z0 = svdup_s8_m (z0, p0, 254)) + +/* +** dup_255_s8_m: +** mov z0\.b, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 255), + z0 = svdup_s8_m (z0, p0, 255)) + +/* +** dup_m1_s8_m: +** mov z0\.b, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, -1), + z0 = svdup_s8_m (z0, p0, -1)) + +/* +** dup_m128_s8_m: +** mov z0\.b, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, -128), + z0 = svdup_s8_m (z0, p0, -128)) + +/* +** dup_0_s8_m: +** mov z0\.b, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s8_m, svint8_t, + z0 = svdup_n_s8_m (z0, p0, 0), + z0 = svdup_s8_m (z0, p0, 0)) + +/* +** dup_w0_s8_m: +** movprfx z0, z1 +** mov z0\.b, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s8_m, svint8_t, int8_t, + z0 = svdup_n_s8_m (z1, p0, x0), + z0 = svdup_s8_m (z1, p0, x0)) + +/* +** dup_1_s8_z: +** mov z0\.b, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 1), + z0 = svdup_s8_z (p0, 1)) + +/* +** dup_127_s8_z: +** mov z0\.b, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 127), + z0 = svdup_s8_z (p0, 127)) + +/* +** dup_128_s8_z: +** mov z0\.b, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 128), + z0 = svdup_s8_z (p0, 128)) + +/* +** dup_129_s8_z: +** mov z0\.b, p0/z, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 129), + z0 = svdup_s8_z (p0, 129)) + +/* +** dup_253_s8_z: +** mov z0\.b, p0/z, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 253), + z0 = svdup_s8_z (p0, 253)) + +/* +** dup_254_s8_z: +** mov z0\.b, p0/z, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 254), + z0 = svdup_s8_z (p0, 254)) + +/* +** dup_255_s8_z: +** mov z0\.b, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 255), + z0 = svdup_s8_z (p0, 255)) + +/* +** dup_m1_s8_z: +** mov z0\.b, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, -1), + z0 = svdup_s8_z (p0, -1)) + +/* +** dup_m128_s8_z: +** mov z0\.b, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, -128), + z0 = svdup_s8_z (p0, -128)) + +/* +** dup_0_s8_z: +** mov z0\.b, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_s8_z, svint8_t, + z0 = svdup_n_s8_z (p0, 0), + z0 = svdup_s8_z (p0, 0)) + +/* +** dup_w0_s8_z: +** movprfx z0\.b, p0/z, z0\.b +** mov z0\.b, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s8_z, svint8_t, int8_t, + z0 = svdup_n_s8_z (p0, x0), + z0 = svdup_s8_z (p0, x0)) + +/* +** dup_1_s8_x: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 1), + z0 = svdup_s8_x (p0, 1)) + +/* +** dup_127_s8_x: +** mov z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 127), + z0 = svdup_s8_x (p0, 127)) + +/* +** dup_128_s8_x: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 128), + z0 = svdup_s8_x (p0, 128)) + +/* +** dup_129_s8_x: +** mov z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 129), + z0 = svdup_s8_x (p0, 129)) + +/* +** dup_253_s8_x: +** mov z0\.b, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 253), + z0 = svdup_s8_x (p0, 253)) + +/* +** dup_254_s8_x: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 254), + z0 = svdup_s8_x (p0, 254)) + +/* +** dup_255_s8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, 255), + z0 = svdup_s8_x (p0, 255)) + +/* +** dup_m1_s8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, -1), + z0 = svdup_s8_x (p0, -1)) + +/* +** dup_m128_s8_x: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_s8_x, svint8_t, + z0 = svdup_n_s8_x (p0, -128), + z0 = svdup_s8_x (p0, -128)) + +/* +** dup_w0_s8_x: +** mov z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_s8_x, svint8_t, int8_t, + z0 = svdup_n_s8_x (p0, x0), + z0 = svdup_s8_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c new file mode 100644 index 00000000000..263eafef0cd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u16.c @@ -0,0 +1,1193 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_u16: +** mov z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u16, svuint16_t, + z0 = svdup_n_u16 (1), + z0 = svdup_u16 (1)) + +/* +** dup_127_u16: +** mov z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u16, svuint16_t, + z0 = svdup_n_u16 (127), + z0 = svdup_u16 (127)) + +/* +** dup_128_u16: +** mov z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u16, svuint16_t, + z0 = svdup_n_u16 (128), + z0 = svdup_u16 (128)) + +/* +** dup_129_u16: +** movi v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_u16, svuint16_t, + z0 = svdup_n_u16 (129), + z0 = svdup_u16 (129)) + +/* +** dup_253_u16: +** movi v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_u16, svuint16_t, + z0 = svdup_n_u16 (253), + z0 = svdup_u16 (253)) + +/* +** dup_254_u16: +** mov z0\.h, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u16, svuint16_t, + z0 = svdup_n_u16 (254), + z0 = svdup_u16 (254)) + +/* +** dup_255_u16: +** mov z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u16, svuint16_t, + z0 = svdup_n_u16 (255), + z0 = svdup_u16 (255)) + +/* +** dup_256_u16: +** mov z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u16, svuint16_t, + z0 = svdup_n_u16 (256), + z0 = svdup_u16 (256)) + +/* +** dup_257_u16: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u16, svuint16_t, + z0 = svdup_n_u16 (257), + z0 = svdup_u16 (257)) + +/* +** dup_512_u16: +** mov z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u16, svuint16_t, + z0 = svdup_n_u16 (512), + z0 = svdup_u16 (512)) + +/* +** dup_7f00_u16: +** mov z0\.h, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u16, svuint16_t, + z0 = svdup_n_u16 (0x7f00), + z0 = svdup_u16 (0x7f00)) + +/* +** dup_7f01_u16: +** mov (w[0-9]+), 32513 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u16, svuint16_t, + z0 = svdup_n_u16 (0x7f01), + z0 = svdup_u16 (0x7f01)) + +/* +** dup_7ffd_u16: +** mov (w[0-9]+), 32765 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u16, svuint16_t, + z0 = svdup_n_u16 (0x7ffd), + z0 = svdup_u16 (0x7ffd)) + +/* +** dup_7ffe_u16: +** mov z0\.h, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u16, svuint16_t, + z0 = svdup_n_u16 (0x7ffe), + z0 = svdup_u16 (0x7ffe)) + +/* +** dup_7fff_u16: +** mov z0\.h, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u16, svuint16_t, + z0 = svdup_n_u16 (0x7fff), + z0 = svdup_u16 (0x7fff)) + +/* +** dup_m1_u16: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u16, svuint16_t, + z0 = svdup_n_u16 (-1), + z0 = svdup_u16 (-1)) + +/* +** dup_m128_u16: +** mov z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u16, svuint16_t, + z0 = svdup_n_u16 (-128), + z0 = svdup_u16 (-128)) + +/* +** dup_m129_u16: +** mov z0\.h, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u16, svuint16_t, + z0 = svdup_n_u16 (-129), + z0 = svdup_u16 (-129)) + +/* +** dup_m130_u16: +** mvni v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u16, svuint16_t, + z0 = svdup_n_u16 (-130), + z0 = svdup_u16 (-130)) + +/* +** dup_m254_u16: +** mvni v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u16, svuint16_t, + z0 = svdup_n_u16 (-254), + z0 = svdup_u16 (-254)) + +/* +** dup_m255_u16: +** mov z0\.h, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u16, svuint16_t, + z0 = svdup_n_u16 (-255), + z0 = svdup_u16 (-255)) + +/* +** dup_m256_u16: +** mov z0\.h, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u16, svuint16_t, + z0 = svdup_n_u16 (-256), + z0 = svdup_u16 (-256)) + +/* +** dup_m257_u16: +** mov z0\.h, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u16, svuint16_t, + z0 = svdup_n_u16 (-257), + z0 = svdup_u16 (-257)) + +/* +** dup_m258_u16: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u16, svuint16_t, + z0 = svdup_n_u16 (-258), + z0 = svdup_u16 (-258)) + +/* +** dup_m259_u16: +** mov (w[0-9]+), -259 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u16, svuint16_t, + z0 = svdup_n_u16 (-259), + z0 = svdup_u16 (-259)) + +/* +** dup_m512_u16: +** mov z0\.h, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u16, svuint16_t, + z0 = svdup_n_u16 (-512), + z0 = svdup_u16 (-512)) + +/* +** dup_m7f00_u16: +** mov z0\.h, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u16, svuint16_t, + z0 = svdup_n_u16 (-0x7f00), + z0 = svdup_u16 (-0x7f00)) + +/* +** dup_m7f01_u16: +** mov z0\.h, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u16, svuint16_t, + z0 = svdup_n_u16 (-0x7f01), + z0 = svdup_u16 (-0x7f01)) + +/* +** dup_m7f02_u16: +** mov (w[0-9]+), -32514 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u16, svuint16_t, + z0 = svdup_n_u16 (-0x7f02), + z0 = svdup_u16 (-0x7f02)) + +/* +** dup_m7ffe_u16: +** mov (w[0-9]+), -32766 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u16, svuint16_t, + z0 = svdup_n_u16 (-0x7ffe), + z0 = svdup_u16 (-0x7ffe)) + +/* +** dup_m7fff_u16: +** mov z0\.h, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u16, svuint16_t, + z0 = svdup_n_u16 (-0x7fff), + z0 = svdup_u16 (-0x7fff)) + +/* +** dup_m8000_u16: +** mov z0\.h, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u16, svuint16_t, + z0 = svdup_n_u16 (-0x8000), + z0 = svdup_u16 (-0x8000)) + +/* +** dup_w0_u16: +** mov z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u16, svuint16_t, uint16_t, + z0 = svdup_n_u16 (x0), + z0 = svdup_u16 (x0)) + +/* +** dup_1_u16_m: +** mov z0\.h, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 1), + z0 = svdup_u16_m (z0, p0, 1)) + +/* +** dup_127_u16_m: +** mov z0\.h, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 127), + z0 = svdup_u16_m (z0, p0, 127)) + +/* +** dup_128_u16_m: +** mov (z[0-9]+\.h), #128 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_128_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 128), + z0 = svdup_u16_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 129), + z0 = svdup_u16_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 253), + z0 = svdup_u16_m (z0, p0, 253)) + +/* +** dup_254_u16_m: +** mov (z[0-9]+\.h), #254 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_254_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 254), + z0 = svdup_u16_m (z0, p0, 254)) + +/* +** dup_255_u16_m: +** mov (z[0-9]+\.h), #255 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_255_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 255), + z0 = svdup_u16_m (z0, p0, 255)) + +/* +** dup_256_u16_m: +** mov z0\.h, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 256), + z0 = svdup_u16_m (z0, p0, 256)) + +/* +** dup_257_u16_m: +** mov (z[0-9]+)\.b, #1 +** sel z0\.h, p0, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_257_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 257), + z0 = svdup_u16_m (z0, p0, 257)) + +/* +** dup_512_u16_m: +** mov z0\.h, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 512), + z0 = svdup_u16_m (z0, p0, 512)) + +/* +** dup_7f00_u16_m: +** mov z0\.h, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0x7f00), + z0 = svdup_u16_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0x7f01), + z0 = svdup_u16_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0x7ffd), + z0 = svdup_u16_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_u16_m: +** mov (z[0-9]+\.h), #32766 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0x7ffe), + z0 = svdup_u16_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_u16_m: +** mov (z[0-9]+\.h), #32767 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0x7fff), + z0 = svdup_u16_m (z0, p0, 0x7fff)) + +/* +** dup_m1_u16_m: +** mov z0\.h, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -1), + z0 = svdup_u16_m (z0, p0, -1)) + +/* +** dup_m128_u16_m: +** mov z0\.h, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -128), + z0 = svdup_u16_m (z0, p0, -128)) + +/* +** dup_m129_u16_m: +** mov (z[0-9]+\.h), #-129 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -129), + z0 = svdup_u16_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -130), + z0 = svdup_u16_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -254), + z0 = svdup_u16_m (z0, p0, -254)) + +/* +** dup_m255_u16_m: +** mov (z[0-9]+\.h), #-255 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -255), + z0 = svdup_u16_m (z0, p0, -255)) + +/* +** dup_m256_u16_m: +** mov z0\.h, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -256), + z0 = svdup_u16_m (z0, p0, -256)) + +/* +** dup_m257_u16_m: +** mov (z[0-9]+\.h), #-257 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -257), + z0 = svdup_u16_m (z0, p0, -257)) + +/* +** dup_m258_u16_m: +** mov (z[0-9]+)\.b, #-2 +** sel z0\.h, p0, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -258), + z0 = svdup_u16_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -259), + z0 = svdup_u16_m (z0, p0, -259)) + +/* +** dup_m512_u16_m: +** mov z0\.h, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -512), + z0 = svdup_u16_m (z0, p0, -512)) + +/* +** dup_m7f00_u16_m: +** mov z0\.h, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x7f00), + z0 = svdup_u16_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_u16_m: +** mov (z[0-9]+\.h), #-32513 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x7f01), + z0 = svdup_u16_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x7f02), + z0 = svdup_u16_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x7ffe), + z0 = svdup_u16_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_u16_m: +** mov (z[0-9]+\.h), #-32767 +** sel z0\.h, p0, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x7fff), + z0 = svdup_u16_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_u16_m: +** mov z0\.h, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, -0x8000), + z0 = svdup_u16_m (z0, p0, -0x8000)) + +/* +** dup_0_u16_m: +** mov z0\.h, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u16_m, svuint16_t, + z0 = svdup_n_u16_m (z0, p0, 0), + z0 = svdup_u16_m (z0, p0, 0)) + +/* +** dup_w0_u16_m: +** movprfx z0, z1 +** mov z0\.h, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u16_m, svuint16_t, uint16_t, + z0 = svdup_n_u16_m (z1, p0, x0), + z0 = svdup_u16_m (z1, p0, x0)) + +/* +** dup_1_u16_z: +** mov z0\.h, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 1), + z0 = svdup_u16_z (p0, 1)) + +/* +** dup_127_u16_z: +** mov z0\.h, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 127), + z0 = svdup_u16_z (p0, 127)) + +/* +** dup_128_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #128 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_128_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 128), + z0 = svdup_u16_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 129), + z0 = svdup_u16_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 253), + z0 = svdup_u16_z (p0, 253)) + +/* +** dup_254_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #254 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_254_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 254), + z0 = svdup_u16_z (p0, 254)) + +/* +** dup_255_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #255 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_255_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 255), + z0 = svdup_u16_z (p0, 255)) + +/* +** dup_256_u16_z: +** mov z0\.h, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 256), + z0 = svdup_u16_z (p0, 256)) + +/* +** dup_257_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+)\.b, #1 +** sel z0\.h, p0, \2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_257_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 257), + z0 = svdup_u16_z (p0, 257)) + +/* +** dup_512_u16_z: +** mov z0\.h, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 512), + z0 = svdup_u16_z (p0, 512)) + +/* +** dup_7f00_u16_z: +** mov z0\.h, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0x7f00), + z0 = svdup_u16_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0x7f01), + z0 = svdup_u16_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0x7ffd), + z0 = svdup_u16_z (p0, 0x7ffd)) + +/* +** dup_7ffe_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #32766 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0x7ffe), + z0 = svdup_u16_z (p0, 0x7ffe)) + +/* +** dup_7fff_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #32767 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0x7fff), + z0 = svdup_u16_z (p0, 0x7fff)) + +/* +** dup_m1_u16_z: +** mov z0\.h, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -1), + z0 = svdup_u16_z (p0, -1)) + +/* +** dup_m128_u16_z: +** mov z0\.h, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -128), + z0 = svdup_u16_z (p0, -128)) + +/* +** dup_m129_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-129 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -129), + z0 = svdup_u16_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -130), + z0 = svdup_u16_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -254), + z0 = svdup_u16_z (p0, -254)) + +/* +** dup_m255_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-255 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -255), + z0 = svdup_u16_z (p0, -255)) + +/* +** dup_m256_u16_z: +** mov z0\.h, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -256), + z0 = svdup_u16_z (p0, -256)) + +/* +** dup_m257_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-257 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -257), + z0 = svdup_u16_z (p0, -257)) + +/* +** dup_m258_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+)\.b, #-2 +** sel z0\.h, p0, \2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -258), + z0 = svdup_u16_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -259), + z0 = svdup_u16_z (p0, -259)) + +/* +** dup_m512_u16_z: +** mov z0\.h, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -512), + z0 = svdup_u16_z (p0, -512)) + +/* +** dup_m7f00_u16_z: +** mov z0\.h, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x7f00), + z0 = svdup_u16_z (p0, -0x7f00)) + +/* +** dup_m7f01_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-32513 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x7f01), + z0 = svdup_u16_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x7f02), + z0 = svdup_u16_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x7ffe), + z0 = svdup_u16_z (p0, -0x7ffe)) + +/* +** dup_m7fff_u16_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.h), #-32767 +** sel z0\.h, p0, \2, \1\.h +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x7fff), + z0 = svdup_u16_z (p0, -0x7fff)) + +/* +** dup_m8000_u16_z: +** mov z0\.h, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, -0x8000), + z0 = svdup_u16_z (p0, -0x8000)) + +/* +** dup_0_u16_z: +** mov z0\.h, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u16_z, svuint16_t, + z0 = svdup_n_u16_z (p0, 0), + z0 = svdup_u16_z (p0, 0)) + +/* +** dup_w0_u16_z: +** movprfx z0\.h, p0/z, z0\.h +** mov z0\.h, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u16_z, svuint16_t, uint16_t, + z0 = svdup_n_u16_z (p0, x0), + z0 = svdup_u16_z (p0, x0)) + +/* +** dup_1_u16_x: +** mov z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 1), + z0 = svdup_u16_x (p0, 1)) + +/* +** dup_127_u16_x: +** mov z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 127), + z0 = svdup_u16_x (p0, 127)) + +/* +** dup_128_u16_x: +** mov z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 128), + z0 = svdup_u16_x (p0, 128)) + +/* +** dup_129_u16_x: +** movi v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 129), + z0 = svdup_u16_x (p0, 129)) + +/* +** dup_253_u16_x: +** movi v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 253), + z0 = svdup_u16_x (p0, 253)) + +/* +** dup_254_u16_x: +** mov z0\.h, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 254), + z0 = svdup_u16_x (p0, 254)) + +/* +** dup_255_u16_x: +** mov z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 255), + z0 = svdup_u16_x (p0, 255)) + +/* +** dup_256_u16_x: +** mov z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 256), + z0 = svdup_u16_x (p0, 256)) + +/* +** dup_257_u16_x: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 257), + z0 = svdup_u16_x (p0, 257)) + +/* +** dup_512_u16_x: +** mov z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 512), + z0 = svdup_u16_x (p0, 512)) + +/* +** dup_7f00_u16_x: +** mov z0\.h, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 0x7f00), + z0 = svdup_u16_x (p0, 0x7f00)) + +/* +** dup_7f01_u16_x: +** mov (w[0-9]+), 32513 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 0x7f01), + z0 = svdup_u16_x (p0, 0x7f01)) + +/* +** dup_7ffd_u16_x: +** mov (w[0-9]+), 32765 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 0x7ffd), + z0 = svdup_u16_x (p0, 0x7ffd)) + +/* +** dup_7ffe_u16_x: +** mov z0\.h, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 0x7ffe), + z0 = svdup_u16_x (p0, 0x7ffe)) + +/* +** dup_7fff_u16_x: +** mov z0\.h, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, 0x7fff), + z0 = svdup_u16_x (p0, 0x7fff)) + +/* +** dup_m1_u16_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -1), + z0 = svdup_u16_x (p0, -1)) + +/* +** dup_m128_u16_x: +** mov z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -128), + z0 = svdup_u16_x (p0, -128)) + +/* +** dup_m129_u16_x: +** mov z0\.h, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -129), + z0 = svdup_u16_x (p0, -129)) + +/* +** dup_m130_u16_x: +** mvni v([0-9]+)\.8h, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -130), + z0 = svdup_u16_x (p0, -130)) + +/* +** dup_m254_u16_x: +** mvni v([0-9]+)\.8h, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -254), + z0 = svdup_u16_x (p0, -254)) + +/* +** dup_m255_u16_x: +** mov z0\.h, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -255), + z0 = svdup_u16_x (p0, -255)) + +/* +** dup_m256_u16_x: +** mov z0\.h, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -256), + z0 = svdup_u16_x (p0, -256)) + +/* +** dup_m257_u16_x: +** mov z0\.h, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -257), + z0 = svdup_u16_x (p0, -257)) + +/* +** dup_m258_u16_x: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -258), + z0 = svdup_u16_x (p0, -258)) + +/* +** dup_m259_u16_x: +** mov (w[0-9]+), -259 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -259), + z0 = svdup_u16_x (p0, -259)) + +/* +** dup_m512_u16_x: +** mov z0\.h, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -512), + z0 = svdup_u16_x (p0, -512)) + +/* +** dup_m7f00_u16_x: +** mov z0\.h, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x7f00), + z0 = svdup_u16_x (p0, -0x7f00)) + +/* +** dup_m7f01_u16_x: +** mov z0\.h, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x7f01), + z0 = svdup_u16_x (p0, -0x7f01)) + +/* +** dup_m7f02_u16_x: +** mov (w[0-9]+), -32514 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x7f02), + z0 = svdup_u16_x (p0, -0x7f02)) + +/* +** dup_m7ffe_u16_x: +** mov (w[0-9]+), -32766 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x7ffe), + z0 = svdup_u16_x (p0, -0x7ffe)) + +/* +** dup_m7fff_u16_x: +** mov z0\.h, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x7fff), + z0 = svdup_u16_x (p0, -0x7fff)) + +/* +** dup_m8000_u16_x: +** mov z0\.h, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u16_x, svuint16_t, + z0 = svdup_n_u16_x (p0, -0x8000), + z0 = svdup_u16_x (p0, -0x8000)) + +/* +** dup_w0_u16_x: +** mov z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u16_x, svuint16_t, uint16_t, + z0 = svdup_n_u16_x (p0, x0), + z0 = svdup_u16_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c new file mode 100644 index 00000000000..667feea6453 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u32.c @@ -0,0 +1,1175 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_u32: +** mov z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u32, svuint32_t, + z0 = svdup_n_u32 (1), + z0 = svdup_u32 (1)) + +/* +** dup_127_u32: +** mov z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u32, svuint32_t, + z0 = svdup_n_u32 (127), + z0 = svdup_u32 (127)) + +/* +** dup_128_u32: +** mov z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u32, svuint32_t, + z0 = svdup_n_u32 (128), + z0 = svdup_u32 (128)) + +/* +** dup_129_u32: +** movi v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_u32, svuint32_t, + z0 = svdup_n_u32 (129), + z0 = svdup_u32 (129)) + +/* +** dup_253_u32: +** movi v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_u32, svuint32_t, + z0 = svdup_n_u32 (253), + z0 = svdup_u32 (253)) + +/* +** dup_254_u32: +** mov z0\.s, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u32, svuint32_t, + z0 = svdup_n_u32 (254), + z0 = svdup_u32 (254)) + +/* +** dup_255_u32: +** mov z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u32, svuint32_t, + z0 = svdup_n_u32 (255), + z0 = svdup_u32 (255)) + +/* +** dup_256_u32: +** mov z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u32, svuint32_t, + z0 = svdup_n_u32 (256), + z0 = svdup_u32 (256)) + +/* +** dup_257_u32: +** mov (w[0-9]+), 257 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u32, svuint32_t, + z0 = svdup_n_u32 (257), + z0 = svdup_u32 (257)) + +/* +** dup_512_u32: +** mov z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u32, svuint32_t, + z0 = svdup_n_u32 (512), + z0 = svdup_u32 (512)) + +/* +** dup_7f00_u32: +** mov z0\.s, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u32, svuint32_t, + z0 = svdup_n_u32 (0x7f00), + z0 = svdup_u32 (0x7f00)) + +/* +** dup_7f01_u32: +** mov (w[0-9]+), 32513 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u32, svuint32_t, + z0 = svdup_n_u32 (0x7f01), + z0 = svdup_u32 (0x7f01)) + +/* +** dup_7ffd_u32: +** mov (w[0-9]+), 32765 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u32, svuint32_t, + z0 = svdup_n_u32 (0x7ffd), + z0 = svdup_u32 (0x7ffd)) + +/* +** dup_7ffe_u32: +** mov z0\.s, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u32, svuint32_t, + z0 = svdup_n_u32 (0x7ffe), + z0 = svdup_u32 (0x7ffe)) + +/* +** dup_7fff_u32: +** mov z0\.s, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u32, svuint32_t, + z0 = svdup_n_u32 (0x7fff), + z0 = svdup_u32 (0x7fff)) + +/* +** dup_m1_u32: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u32, svuint32_t, + z0 = svdup_n_u32 (-1), + z0 = svdup_u32 (-1)) + +/* +** dup_m128_u32: +** mov z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u32, svuint32_t, + z0 = svdup_n_u32 (-128), + z0 = svdup_u32 (-128)) + +/* +** dup_m129_u32: +** mov z0\.s, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u32, svuint32_t, + z0 = svdup_n_u32 (-129), + z0 = svdup_u32 (-129)) + +/* +** dup_m130_u32: +** mvni v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u32, svuint32_t, + z0 = svdup_n_u32 (-130), + z0 = svdup_u32 (-130)) + +/* +** dup_m254_u32: +** mvni v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u32, svuint32_t, + z0 = svdup_n_u32 (-254), + z0 = svdup_u32 (-254)) + +/* +** dup_m255_u32: +** mov z0\.s, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u32, svuint32_t, + z0 = svdup_n_u32 (-255), + z0 = svdup_u32 (-255)) + +/* +** dup_m256_u32: +** mov z0\.s, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u32, svuint32_t, + z0 = svdup_n_u32 (-256), + z0 = svdup_u32 (-256)) + +/* +** dup_m257_u32: +** mov z0\.s, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u32, svuint32_t, + z0 = svdup_n_u32 (-257), + z0 = svdup_u32 (-257)) + +/* +** dup_m258_u32: +** mov (w[0-9]+), -258 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u32, svuint32_t, + z0 = svdup_n_u32 (-258), + z0 = svdup_u32 (-258)) + +/* +** dup_m259_u32: +** mov (w[0-9]+), -259 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u32, svuint32_t, + z0 = svdup_n_u32 (-259), + z0 = svdup_u32 (-259)) + +/* +** dup_m512_u32: +** mov z0\.s, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u32, svuint32_t, + z0 = svdup_n_u32 (-512), + z0 = svdup_u32 (-512)) + +/* +** dup_m7f00_u32: +** mov z0\.s, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u32, svuint32_t, + z0 = svdup_n_u32 (-0x7f00), + z0 = svdup_u32 (-0x7f00)) + +/* +** dup_m7f01_u32: +** mov z0\.s, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u32, svuint32_t, + z0 = svdup_n_u32 (-0x7f01), + z0 = svdup_u32 (-0x7f01)) + +/* +** dup_m7f02_u32: +** mov (w[0-9]+), -32514 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u32, svuint32_t, + z0 = svdup_n_u32 (-0x7f02), + z0 = svdup_u32 (-0x7f02)) + +/* +** dup_m7ffe_u32: +** mov (w[0-9]+), -32766 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u32, svuint32_t, + z0 = svdup_n_u32 (-0x7ffe), + z0 = svdup_u32 (-0x7ffe)) + +/* +** dup_m7fff_u32: +** mov z0\.s, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u32, svuint32_t, + z0 = svdup_n_u32 (-0x7fff), + z0 = svdup_u32 (-0x7fff)) + +/* +** dup_m8000_u32: +** mov z0\.s, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u32, svuint32_t, + z0 = svdup_n_u32 (-0x8000), + z0 = svdup_u32 (-0x8000)) + +/* +** dup_w0_u32: +** mov z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u32, svuint32_t, uint32_t, + z0 = svdup_n_u32 (x0), + z0 = svdup_u32 (x0)) + +/* +** dup_1_u32_m: +** mov z0\.s, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 1), + z0 = svdup_u32_m (z0, p0, 1)) + +/* +** dup_127_u32_m: +** mov z0\.s, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 127), + z0 = svdup_u32_m (z0, p0, 127)) + +/* +** dup_128_u32_m: +** mov (z[0-9]+\.s), #128 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_128_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 128), + z0 = svdup_u32_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 129), + z0 = svdup_u32_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 253), + z0 = svdup_u32_m (z0, p0, 253)) + +/* +** dup_254_u32_m: +** mov (z[0-9]+\.s), #254 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_254_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 254), + z0 = svdup_u32_m (z0, p0, 254)) + +/* +** dup_255_u32_m: +** mov (z[0-9]+\.s), #255 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_255_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 255), + z0 = svdup_u32_m (z0, p0, 255)) + +/* +** dup_256_u32_m: +** mov z0\.s, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 256), + z0 = svdup_u32_m (z0, p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 257), + z0 = svdup_u32_m (z0, p0, 257)) + +/* +** dup_512_u32_m: +** mov z0\.s, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 512), + z0 = svdup_u32_m (z0, p0, 512)) + +/* +** dup_7f00_u32_m: +** mov z0\.s, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0x7f00), + z0 = svdup_u32_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0x7f01), + z0 = svdup_u32_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0x7ffd), + z0 = svdup_u32_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_u32_m: +** mov (z[0-9]+\.s), #32766 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0x7ffe), + z0 = svdup_u32_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_u32_m: +** mov (z[0-9]+\.s), #32767 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0x7fff), + z0 = svdup_u32_m (z0, p0, 0x7fff)) + +/* +** dup_m1_u32_m: +** mov z0\.s, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -1), + z0 = svdup_u32_m (z0, p0, -1)) + +/* +** dup_m128_u32_m: +** mov z0\.s, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -128), + z0 = svdup_u32_m (z0, p0, -128)) + +/* +** dup_m129_u32_m: +** mov (z[0-9]+\.s), #-129 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -129), + z0 = svdup_u32_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -130), + z0 = svdup_u32_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -254), + z0 = svdup_u32_m (z0, p0, -254)) + +/* +** dup_m255_u32_m: +** mov (z[0-9]+\.s), #-255 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -255), + z0 = svdup_u32_m (z0, p0, -255)) + +/* +** dup_m256_u32_m: +** mov z0\.s, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -256), + z0 = svdup_u32_m (z0, p0, -256)) + +/* +** dup_m257_u32_m: +** mov (z[0-9]+\.s), #-257 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -257), + z0 = svdup_u32_m (z0, p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -258), + z0 = svdup_u32_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -259), + z0 = svdup_u32_m (z0, p0, -259)) + +/* +** dup_m512_u32_m: +** mov z0\.s, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -512), + z0 = svdup_u32_m (z0, p0, -512)) + +/* +** dup_m7f00_u32_m: +** mov z0\.s, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x7f00), + z0 = svdup_u32_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_u32_m: +** mov (z[0-9]+\.s), #-32513 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x7f01), + z0 = svdup_u32_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x7f02), + z0 = svdup_u32_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x7ffe), + z0 = svdup_u32_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_u32_m: +** mov (z[0-9]+\.s), #-32767 +** sel z0\.s, p0, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x7fff), + z0 = svdup_u32_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_u32_m: +** mov z0\.s, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, -0x8000), + z0 = svdup_u32_m (z0, p0, -0x8000)) + +/* +** dup_0_u32_m: +** mov z0\.s, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u32_m, svuint32_t, + z0 = svdup_n_u32_m (z0, p0, 0), + z0 = svdup_u32_m (z0, p0, 0)) + +/* +** dup_w0_u32_m: +** movprfx z0, z1 +** mov z0\.s, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u32_m, svuint32_t, uint32_t, + z0 = svdup_n_u32_m (z1, p0, x0), + z0 = svdup_u32_m (z1, p0, x0)) + +/* +** dup_1_u32_z: +** mov z0\.s, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 1), + z0 = svdup_u32_z (p0, 1)) + +/* +** dup_127_u32_z: +** mov z0\.s, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 127), + z0 = svdup_u32_z (p0, 127)) + +/* +** dup_128_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #128 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_128_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 128), + z0 = svdup_u32_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 129), + z0 = svdup_u32_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 253), + z0 = svdup_u32_z (p0, 253)) + +/* +** dup_254_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #254 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_254_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 254), + z0 = svdup_u32_z (p0, 254)) + +/* +** dup_255_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #255 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_255_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 255), + z0 = svdup_u32_z (p0, 255)) + +/* +** dup_256_u32_z: +** mov z0\.s, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 256), + z0 = svdup_u32_z (p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 257), + z0 = svdup_u32_z (p0, 257)) + +/* +** dup_512_u32_z: +** mov z0\.s, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 512), + z0 = svdup_u32_z (p0, 512)) + +/* +** dup_7f00_u32_z: +** mov z0\.s, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0x7f00), + z0 = svdup_u32_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0x7f01), + z0 = svdup_u32_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0x7ffd), + z0 = svdup_u32_z (p0, 0x7ffd)) + +/* +** dup_7ffe_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #32766 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0x7ffe), + z0 = svdup_u32_z (p0, 0x7ffe)) + +/* +** dup_7fff_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #32767 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0x7fff), + z0 = svdup_u32_z (p0, 0x7fff)) + +/* +** dup_m1_u32_z: +** mov z0\.s, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -1), + z0 = svdup_u32_z (p0, -1)) + +/* +** dup_m128_u32_z: +** mov z0\.s, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -128), + z0 = svdup_u32_z (p0, -128)) + +/* +** dup_m129_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-129 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -129), + z0 = svdup_u32_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -130), + z0 = svdup_u32_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -254), + z0 = svdup_u32_z (p0, -254)) + +/* +** dup_m255_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-255 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -255), + z0 = svdup_u32_z (p0, -255)) + +/* +** dup_m256_u32_z: +** mov z0\.s, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -256), + z0 = svdup_u32_z (p0, -256)) + +/* +** dup_m257_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-257 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -257), + z0 = svdup_u32_z (p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -258), + z0 = svdup_u32_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -259), + z0 = svdup_u32_z (p0, -259)) + +/* +** dup_m512_u32_z: +** mov z0\.s, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -512), + z0 = svdup_u32_z (p0, -512)) + +/* +** dup_m7f00_u32_z: +** mov z0\.s, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x7f00), + z0 = svdup_u32_z (p0, -0x7f00)) + +/* +** dup_m7f01_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-32513 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x7f01), + z0 = svdup_u32_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x7f02), + z0 = svdup_u32_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x7ffe), + z0 = svdup_u32_z (p0, -0x7ffe)) + +/* +** dup_m7fff_u32_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.s), #-32767 +** sel z0\.s, p0, \2, \1\.s +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x7fff), + z0 = svdup_u32_z (p0, -0x7fff)) + +/* +** dup_m8000_u32_z: +** mov z0\.s, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, -0x8000), + z0 = svdup_u32_z (p0, -0x8000)) + +/* +** dup_0_u32_z: +** mov z0\.s, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u32_z, svuint32_t, + z0 = svdup_n_u32_z (p0, 0), + z0 = svdup_u32_z (p0, 0)) + +/* +** dup_w0_u32_z: +** movprfx z0\.s, p0/z, z0\.s +** mov z0\.s, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u32_z, svuint32_t, uint32_t, + z0 = svdup_n_u32_z (p0, x0), + z0 = svdup_u32_z (p0, x0)) + +/* +** dup_1_u32_x: +** mov z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 1), + z0 = svdup_u32_x (p0, 1)) + +/* +** dup_127_u32_x: +** mov z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 127), + z0 = svdup_u32_x (p0, 127)) + +/* +** dup_128_u32_x: +** mov z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 128), + z0 = svdup_u32_x (p0, 128)) + +/* +** dup_129_u32_x: +** movi v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_129_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 129), + z0 = svdup_u32_x (p0, 129)) + +/* +** dup_253_u32_x: +** movi v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_253_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 253), + z0 = svdup_u32_x (p0, 253)) + +/* +** dup_254_u32_x: +** mov z0\.s, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 254), + z0 = svdup_u32_x (p0, 254)) + +/* +** dup_255_u32_x: +** mov z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 255), + z0 = svdup_u32_x (p0, 255)) + +/* +** dup_256_u32_x: +** mov z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 256), + z0 = svdup_u32_x (p0, 256)) + +/* +** dup_257_u32_x: +** mov (w[0-9]+), 257 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 257), + z0 = svdup_u32_x (p0, 257)) + +/* +** dup_512_u32_x: +** mov z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 512), + z0 = svdup_u32_x (p0, 512)) + +/* +** dup_7f00_u32_x: +** mov z0\.s, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 0x7f00), + z0 = svdup_u32_x (p0, 0x7f00)) + +/* +** dup_7f01_u32_x: +** mov (w[0-9]+), 32513 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 0x7f01), + z0 = svdup_u32_x (p0, 0x7f01)) + +/* +** dup_7ffd_u32_x: +** mov (w[0-9]+), 32765 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 0x7ffd), + z0 = svdup_u32_x (p0, 0x7ffd)) + +/* +** dup_7ffe_u32_x: +** mov z0\.s, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 0x7ffe), + z0 = svdup_u32_x (p0, 0x7ffe)) + +/* +** dup_7fff_u32_x: +** mov z0\.s, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, 0x7fff), + z0 = svdup_u32_x (p0, 0x7fff)) + +/* +** dup_m1_u32_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -1), + z0 = svdup_u32_x (p0, -1)) + +/* +** dup_m128_u32_x: +** mov z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -128), + z0 = svdup_u32_x (p0, -128)) + +/* +** dup_m129_u32_x: +** mov z0\.s, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -129), + z0 = svdup_u32_x (p0, -129)) + +/* +** dup_m130_u32_x: +** mvni v([0-9]+)\.4s, 0x81 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -130), + z0 = svdup_u32_x (p0, -130)) + +/* +** dup_m254_u32_x: +** mvni v([0-9]+)\.4s, 0xfd +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -254), + z0 = svdup_u32_x (p0, -254)) + +/* +** dup_m255_u32_x: +** mov z0\.s, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -255), + z0 = svdup_u32_x (p0, -255)) + +/* +** dup_m256_u32_x: +** mov z0\.s, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -256), + z0 = svdup_u32_x (p0, -256)) + +/* +** dup_m257_u32_x: +** mov z0\.s, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -257), + z0 = svdup_u32_x (p0, -257)) + +/* +** dup_m258_u32_x: +** mov (w[0-9]+), -258 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -258), + z0 = svdup_u32_x (p0, -258)) + +/* +** dup_m259_u32_x: +** mov (w[0-9]+), -259 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -259), + z0 = svdup_u32_x (p0, -259)) + +/* +** dup_m512_u32_x: +** mov z0\.s, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -512), + z0 = svdup_u32_x (p0, -512)) + +/* +** dup_m7f00_u32_x: +** mov z0\.s, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x7f00), + z0 = svdup_u32_x (p0, -0x7f00)) + +/* +** dup_m7f01_u32_x: +** mov z0\.s, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x7f01), + z0 = svdup_u32_x (p0, -0x7f01)) + +/* +** dup_m7f02_u32_x: +** mov (w[0-9]+), -32514 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x7f02), + z0 = svdup_u32_x (p0, -0x7f02)) + +/* +** dup_m7ffe_u32_x: +** mov (w[0-9]+), -32766 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x7ffe), + z0 = svdup_u32_x (p0, -0x7ffe)) + +/* +** dup_m7fff_u32_x: +** mov z0\.s, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x7fff), + z0 = svdup_u32_x (p0, -0x7fff)) + +/* +** dup_m8000_u32_x: +** mov z0\.s, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u32_x, svuint32_t, + z0 = svdup_n_u32_x (p0, -0x8000), + z0 = svdup_u32_x (p0, -0x8000)) + +/* +** dup_w0_u32_x: +** mov z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u32_x, svuint32_t, uint32_t, + z0 = svdup_n_u32_x (p0, x0), + z0 = svdup_u32_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c new file mode 100644 index 00000000000..a7cca7af021 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u64.c @@ -0,0 +1,1175 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_u64: +** mov z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u64, svuint64_t, + z0 = svdup_n_u64 (1), + z0 = svdup_u64 (1)) + +/* +** dup_127_u64: +** mov z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u64, svuint64_t, + z0 = svdup_n_u64 (127), + z0 = svdup_u64 (127)) + +/* +** dup_128_u64: +** mov z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u64, svuint64_t, + z0 = svdup_n_u64 (128), + z0 = svdup_u64 (128)) + +/* +** dup_129_u64: +** mov (x[0-9]+), 129 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u64, svuint64_t, + z0 = svdup_n_u64 (129), + z0 = svdup_u64 (129)) + +/* +** dup_253_u64: +** mov (x[0-9]+), 253 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u64, svuint64_t, + z0 = svdup_n_u64 (253), + z0 = svdup_u64 (253)) + +/* +** dup_254_u64: +** mov z0\.d, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u64, svuint64_t, + z0 = svdup_n_u64 (254), + z0 = svdup_u64 (254)) + +/* +** dup_255_u64: +** mov z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u64, svuint64_t, + z0 = svdup_n_u64 (255), + z0 = svdup_u64 (255)) + +/* +** dup_256_u64: +** mov z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u64, svuint64_t, + z0 = svdup_n_u64 (256), + z0 = svdup_u64 (256)) + +/* +** dup_257_u64: +** mov (x[0-9]+), 257 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u64, svuint64_t, + z0 = svdup_n_u64 (257), + z0 = svdup_u64 (257)) + +/* +** dup_512_u64: +** mov z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u64, svuint64_t, + z0 = svdup_n_u64 (512), + z0 = svdup_u64 (512)) + +/* +** dup_7f00_u64: +** mov z0\.d, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u64, svuint64_t, + z0 = svdup_n_u64 (0x7f00), + z0 = svdup_u64 (0x7f00)) + +/* +** dup_7f01_u64: +** mov (x[0-9]+), 32513 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u64, svuint64_t, + z0 = svdup_n_u64 (0x7f01), + z0 = svdup_u64 (0x7f01)) + +/* +** dup_7ffd_u64: +** mov (x[0-9]+), 32765 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u64, svuint64_t, + z0 = svdup_n_u64 (0x7ffd), + z0 = svdup_u64 (0x7ffd)) + +/* +** dup_7ffe_u64: +** mov z0\.d, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u64, svuint64_t, + z0 = svdup_n_u64 (0x7ffe), + z0 = svdup_u64 (0x7ffe)) + +/* +** dup_7fff_u64: +** mov z0\.d, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u64, svuint64_t, + z0 = svdup_n_u64 (0x7fff), + z0 = svdup_u64 (0x7fff)) + +/* +** dup_m1_u64: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u64, svuint64_t, + z0 = svdup_n_u64 (-1), + z0 = svdup_u64 (-1)) + +/* +** dup_m128_u64: +** mov z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u64, svuint64_t, + z0 = svdup_n_u64 (-128), + z0 = svdup_u64 (-128)) + +/* +** dup_m129_u64: +** mov z0\.d, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u64, svuint64_t, + z0 = svdup_n_u64 (-129), + z0 = svdup_u64 (-129)) + +/* +** dup_m130_u64: +** mov (x[0-9]+), -130 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u64, svuint64_t, + z0 = svdup_n_u64 (-130), + z0 = svdup_u64 (-130)) + +/* +** dup_m254_u64: +** mov (x[0-9]+), -254 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u64, svuint64_t, + z0 = svdup_n_u64 (-254), + z0 = svdup_u64 (-254)) + +/* +** dup_m255_u64: +** mov z0\.d, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u64, svuint64_t, + z0 = svdup_n_u64 (-255), + z0 = svdup_u64 (-255)) + +/* +** dup_m256_u64: +** mov z0\.d, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u64, svuint64_t, + z0 = svdup_n_u64 (-256), + z0 = svdup_u64 (-256)) + +/* +** dup_m257_u64: +** mov z0\.d, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u64, svuint64_t, + z0 = svdup_n_u64 (-257), + z0 = svdup_u64 (-257)) + +/* +** dup_m258_u64: +** mov (x[0-9]+), -258 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u64, svuint64_t, + z0 = svdup_n_u64 (-258), + z0 = svdup_u64 (-258)) + +/* +** dup_m259_u64: +** mov (x[0-9]+), -259 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u64, svuint64_t, + z0 = svdup_n_u64 (-259), + z0 = svdup_u64 (-259)) + +/* +** dup_m512_u64: +** mov z0\.d, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u64, svuint64_t, + z0 = svdup_n_u64 (-512), + z0 = svdup_u64 (-512)) + +/* +** dup_m7f00_u64: +** mov z0\.d, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u64, svuint64_t, + z0 = svdup_n_u64 (-0x7f00), + z0 = svdup_u64 (-0x7f00)) + +/* +** dup_m7f01_u64: +** mov z0\.d, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u64, svuint64_t, + z0 = svdup_n_u64 (-0x7f01), + z0 = svdup_u64 (-0x7f01)) + +/* +** dup_m7f02_u64: +** mov (x[0-9]+), -32514 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u64, svuint64_t, + z0 = svdup_n_u64 (-0x7f02), + z0 = svdup_u64 (-0x7f02)) + +/* +** dup_m7ffe_u64: +** mov (x[0-9]+), -32766 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u64, svuint64_t, + z0 = svdup_n_u64 (-0x7ffe), + z0 = svdup_u64 (-0x7ffe)) + +/* +** dup_m7fff_u64: +** mov z0\.d, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u64, svuint64_t, + z0 = svdup_n_u64 (-0x7fff), + z0 = svdup_u64 (-0x7fff)) + +/* +** dup_m8000_u64: +** mov z0\.d, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u64, svuint64_t, + z0 = svdup_n_u64 (-0x8000), + z0 = svdup_u64 (-0x8000)) + +/* +** dup_x0_u64: +** mov z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_u64, svuint64_t, uint64_t, + z0 = svdup_n_u64 (x0), + z0 = svdup_u64 (x0)) + +/* +** dup_1_u64_m: +** mov z0\.d, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 1), + z0 = svdup_u64_m (z0, p0, 1)) + +/* +** dup_127_u64_m: +** mov z0\.d, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 127), + z0 = svdup_u64_m (z0, p0, 127)) + +/* +** dup_128_u64_m: +** mov (z[0-9]+\.d), #128 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_128_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 128), + z0 = svdup_u64_m (z0, p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 129), + z0 = svdup_u64_m (z0, p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 253), + z0 = svdup_u64_m (z0, p0, 253)) + +/* +** dup_254_u64_m: +** mov (z[0-9]+\.d), #254 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_254_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 254), + z0 = svdup_u64_m (z0, p0, 254)) + +/* +** dup_255_u64_m: +** mov (z[0-9]+\.d), #255 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_255_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 255), + z0 = svdup_u64_m (z0, p0, 255)) + +/* +** dup_256_u64_m: +** mov z0\.d, p0/m, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 256), + z0 = svdup_u64_m (z0, p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 257), + z0 = svdup_u64_m (z0, p0, 257)) + +/* +** dup_512_u64_m: +** mov z0\.d, p0/m, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 512), + z0 = svdup_u64_m (z0, p0, 512)) + +/* +** dup_7f00_u64_m: +** mov z0\.d, p0/m, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0x7f00), + z0 = svdup_u64_m (z0, p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0x7f01), + z0 = svdup_u64_m (z0, p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0x7ffd), + z0 = svdup_u64_m (z0, p0, 0x7ffd)) + +/* +** dup_7ffe_u64_m: +** mov (z[0-9]+\.d), #32766 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0x7ffe), + z0 = svdup_u64_m (z0, p0, 0x7ffe)) + +/* +** dup_7fff_u64_m: +** mov (z[0-9]+\.d), #32767 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0x7fff), + z0 = svdup_u64_m (z0, p0, 0x7fff)) + +/* +** dup_m1_u64_m: +** mov z0\.d, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -1), + z0 = svdup_u64_m (z0, p0, -1)) + +/* +** dup_m128_u64_m: +** mov z0\.d, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -128), + z0 = svdup_u64_m (z0, p0, -128)) + +/* +** dup_m129_u64_m: +** mov (z[0-9]+\.d), #-129 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -129), + z0 = svdup_u64_m (z0, p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -130), + z0 = svdup_u64_m (z0, p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -254), + z0 = svdup_u64_m (z0, p0, -254)) + +/* +** dup_m255_u64_m: +** mov (z[0-9]+\.d), #-255 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -255), + z0 = svdup_u64_m (z0, p0, -255)) + +/* +** dup_m256_u64_m: +** mov z0\.d, p0/m, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -256), + z0 = svdup_u64_m (z0, p0, -256)) + +/* +** dup_m257_u64_m: +** mov (z[0-9]+\.d), #-257 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -257), + z0 = svdup_u64_m (z0, p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -258), + z0 = svdup_u64_m (z0, p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -259), + z0 = svdup_u64_m (z0, p0, -259)) + +/* +** dup_m512_u64_m: +** mov z0\.d, p0/m, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -512), + z0 = svdup_u64_m (z0, p0, -512)) + +/* +** dup_m7f00_u64_m: +** mov z0\.d, p0/m, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x7f00), + z0 = svdup_u64_m (z0, p0, -0x7f00)) + +/* +** dup_m7f01_u64_m: +** mov (z[0-9]+\.d), #-32513 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x7f01), + z0 = svdup_u64_m (z0, p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x7f02), + z0 = svdup_u64_m (z0, p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x7ffe), + z0 = svdup_u64_m (z0, p0, -0x7ffe)) + +/* +** dup_m7fff_u64_m: +** mov (z[0-9]+\.d), #-32767 +** sel z0\.d, p0, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x7fff), + z0 = svdup_u64_m (z0, p0, -0x7fff)) + +/* +** dup_m8000_u64_m: +** mov z0\.d, p0/m, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, -0x8000), + z0 = svdup_u64_m (z0, p0, -0x8000)) + +/* +** dup_0_u64_m: +** mov z0\.d, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u64_m, svuint64_t, + z0 = svdup_n_u64_m (z0, p0, 0), + z0 = svdup_u64_m (z0, p0, 0)) + +/* +** dup_x0_u64_m: +** movprfx z0, z1 +** mov z0\.d, p0/m, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_u64_m, svuint64_t, uint64_t, + z0 = svdup_n_u64_m (z1, p0, x0), + z0 = svdup_u64_m (z1, p0, x0)) + +/* +** dup_1_u64_z: +** mov z0\.d, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 1), + z0 = svdup_u64_z (p0, 1)) + +/* +** dup_127_u64_z: +** mov z0\.d, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 127), + z0 = svdup_u64_z (p0, 127)) + +/* +** dup_128_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #128 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_128_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 128), + z0 = svdup_u64_z (p0, 128)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_129_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 129), + z0 = svdup_u64_z (p0, 129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_253_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 253), + z0 = svdup_u64_z (p0, 253)) + +/* +** dup_254_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #254 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_254_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 254), + z0 = svdup_u64_z (p0, 254)) + +/* +** dup_255_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #255 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_255_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 255), + z0 = svdup_u64_z (p0, 255)) + +/* +** dup_256_u64_z: +** mov z0\.d, p0/z, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 256), + z0 = svdup_u64_z (p0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_257_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 257), + z0 = svdup_u64_z (p0, 257)) + +/* +** dup_512_u64_z: +** mov z0\.d, p0/z, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 512), + z0 = svdup_u64_z (p0, 512)) + +/* +** dup_7f00_u64_z: +** mov z0\.d, p0/z, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0x7f00), + z0 = svdup_u64_z (p0, 0x7f00)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7f01_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0x7f01), + z0 = svdup_u64_z (p0, 0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_7ffd_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0x7ffd), + z0 = svdup_u64_z (p0, 0x7ffd)) + +/* +** dup_7ffe_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #32766 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0x7ffe), + z0 = svdup_u64_z (p0, 0x7ffe)) + +/* +** dup_7fff_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #32767 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0x7fff), + z0 = svdup_u64_z (p0, 0x7fff)) + +/* +** dup_m1_u64_z: +** mov z0\.d, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -1), + z0 = svdup_u64_z (p0, -1)) + +/* +** dup_m128_u64_z: +** mov z0\.d, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -128), + z0 = svdup_u64_z (p0, -128)) + +/* +** dup_m129_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-129 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -129), + z0 = svdup_u64_z (p0, -129)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m130_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -130), + z0 = svdup_u64_z (p0, -130)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m254_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -254), + z0 = svdup_u64_z (p0, -254)) + +/* +** dup_m255_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-255 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -255), + z0 = svdup_u64_z (p0, -255)) + +/* +** dup_m256_u64_z: +** mov z0\.d, p0/z, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -256), + z0 = svdup_u64_z (p0, -256)) + +/* +** dup_m257_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-257 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -257), + z0 = svdup_u64_z (p0, -257)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m258_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -258), + z0 = svdup_u64_z (p0, -258)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m259_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -259), + z0 = svdup_u64_z (p0, -259)) + +/* +** dup_m512_u64_z: +** mov z0\.d, p0/z, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -512), + z0 = svdup_u64_z (p0, -512)) + +/* +** dup_m7f00_u64_z: +** mov z0\.d, p0/z, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x7f00), + z0 = svdup_u64_z (p0, -0x7f00)) + +/* +** dup_m7f01_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-32513 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x7f01), + z0 = svdup_u64_z (p0, -0x7f01)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7f02_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x7f02), + z0 = svdup_u64_z (p0, -0x7f02)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (dup_m7ffe_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x7ffe), + z0 = svdup_u64_z (p0, -0x7ffe)) + +/* +** dup_m7fff_u64_z: +** mov (z[0-9]+)\.b, #0 +** mov (z[0-9]+\.d), #-32767 +** sel z0\.d, p0, \2, \1\.d +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x7fff), + z0 = svdup_u64_z (p0, -0x7fff)) + +/* +** dup_m8000_u64_z: +** mov z0\.d, p0/z, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, -0x8000), + z0 = svdup_u64_z (p0, -0x8000)) + +/* +** dup_0_u64_z: +** mov z0\.d, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u64_z, svuint64_t, + z0 = svdup_n_u64_z (p0, 0), + z0 = svdup_u64_z (p0, 0)) + +/* +** dup_x0_u64_z: +** movprfx z0\.d, p0/z, z0\.d +** mov z0\.d, p0/m, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_u64_z, svuint64_t, uint64_t, + z0 = svdup_n_u64_z (p0, x0), + z0 = svdup_u64_z (p0, x0)) + +/* +** dup_1_u64_x: +** mov z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 1), + z0 = svdup_u64_x (p0, 1)) + +/* +** dup_127_u64_x: +** mov z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 127), + z0 = svdup_u64_x (p0, 127)) + +/* +** dup_128_u64_x: +** mov z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 128), + z0 = svdup_u64_x (p0, 128)) + +/* +** dup_129_u64_x: +** mov (x[0-9]+), 129 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 129), + z0 = svdup_u64_x (p0, 129)) + +/* +** dup_253_u64_x: +** mov (x[0-9]+), 253 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 253), + z0 = svdup_u64_x (p0, 253)) + +/* +** dup_254_u64_x: +** mov z0\.d, #254 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 254), + z0 = svdup_u64_x (p0, 254)) + +/* +** dup_255_u64_x: +** mov z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 255), + z0 = svdup_u64_x (p0, 255)) + +/* +** dup_256_u64_x: +** mov z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (dup_256_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 256), + z0 = svdup_u64_x (p0, 256)) + +/* +** dup_257_u64_x: +** mov (x[0-9]+), 257 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_257_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 257), + z0 = svdup_u64_x (p0, 257)) + +/* +** dup_512_u64_x: +** mov z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (dup_512_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 512), + z0 = svdup_u64_x (p0, 512)) + +/* +** dup_7f00_u64_x: +** mov z0\.d, #32512 +** ret +*/ +TEST_UNIFORM_Z (dup_7f00_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 0x7f00), + z0 = svdup_u64_x (p0, 0x7f00)) + +/* +** dup_7f01_u64_x: +** mov (x[0-9]+), 32513 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7f01_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 0x7f01), + z0 = svdup_u64_x (p0, 0x7f01)) + +/* +** dup_7ffd_u64_x: +** mov (x[0-9]+), 32765 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffd_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 0x7ffd), + z0 = svdup_u64_x (p0, 0x7ffd)) + +/* +** dup_7ffe_u64_x: +** mov z0\.d, #32766 +** ret +*/ +TEST_UNIFORM_Z (dup_7ffe_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 0x7ffe), + z0 = svdup_u64_x (p0, 0x7ffe)) + +/* +** dup_7fff_u64_x: +** mov z0\.d, #32767 +** ret +*/ +TEST_UNIFORM_Z (dup_7fff_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, 0x7fff), + z0 = svdup_u64_x (p0, 0x7fff)) + +/* +** dup_m1_u64_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -1), + z0 = svdup_u64_x (p0, -1)) + +/* +** dup_m128_u64_x: +** mov z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -128), + z0 = svdup_u64_x (p0, -128)) + +/* +** dup_m129_u64_x: +** mov z0\.d, #-129 +** ret +*/ +TEST_UNIFORM_Z (dup_m129_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -129), + z0 = svdup_u64_x (p0, -129)) + +/* +** dup_m130_u64_x: +** mov (x[0-9]+), -130 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m130_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -130), + z0 = svdup_u64_x (p0, -130)) + +/* +** dup_m254_u64_x: +** mov (x[0-9]+), -254 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m254_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -254), + z0 = svdup_u64_x (p0, -254)) + +/* +** dup_m255_u64_x: +** mov z0\.d, #-255 +** ret +*/ +TEST_UNIFORM_Z (dup_m255_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -255), + z0 = svdup_u64_x (p0, -255)) + +/* +** dup_m256_u64_x: +** mov z0\.d, #-256 +** ret +*/ +TEST_UNIFORM_Z (dup_m256_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -256), + z0 = svdup_u64_x (p0, -256)) + +/* +** dup_m257_u64_x: +** mov z0\.d, #-257 +** ret +*/ +TEST_UNIFORM_Z (dup_m257_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -257), + z0 = svdup_u64_x (p0, -257)) + +/* +** dup_m258_u64_x: +** mov (x[0-9]+), -258 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m258_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -258), + z0 = svdup_u64_x (p0, -258)) + +/* +** dup_m259_u64_x: +** mov (x[0-9]+), -259 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m259_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -259), + z0 = svdup_u64_x (p0, -259)) + +/* +** dup_m512_u64_x: +** mov z0\.d, #-512 +** ret +*/ +TEST_UNIFORM_Z (dup_m512_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -512), + z0 = svdup_u64_x (p0, -512)) + +/* +** dup_m7f00_u64_x: +** mov z0\.d, #-32512 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f00_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x7f00), + z0 = svdup_u64_x (p0, -0x7f00)) + +/* +** dup_m7f01_u64_x: +** mov z0\.d, #-32513 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f01_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x7f01), + z0 = svdup_u64_x (p0, -0x7f01)) + +/* +** dup_m7f02_u64_x: +** mov (x[0-9]+), -32514 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7f02_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x7f02), + z0 = svdup_u64_x (p0, -0x7f02)) + +/* +** dup_m7ffe_u64_x: +** mov (x[0-9]+), -32766 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dup_m7ffe_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x7ffe), + z0 = svdup_u64_x (p0, -0x7ffe)) + +/* +** dup_m7fff_u64_x: +** mov z0\.d, #-32767 +** ret +*/ +TEST_UNIFORM_Z (dup_m7fff_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x7fff), + z0 = svdup_u64_x (p0, -0x7fff)) + +/* +** dup_m8000_u64_x: +** mov z0\.d, #-32768 +** ret +*/ +TEST_UNIFORM_Z (dup_m8000_u64_x, svuint64_t, + z0 = svdup_n_u64_x (p0, -0x8000), + z0 = svdup_u64_x (p0, -0x8000)) + +/* +** dup_x0_u64_x: +** mov z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (dup_x0_u64_x, svuint64_t, uint64_t, + z0 = svdup_n_u64_x (p0, x0), + z0 = svdup_u64_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c new file mode 100644 index 00000000000..d27f4bba9e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dup_u8.c @@ -0,0 +1,383 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dup_1_u8: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u8, svuint8_t, + z0 = svdup_n_u8 (1), + z0 = svdup_u8 (1)) + +/* +** dup_127_u8: +** mov z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u8, svuint8_t, + z0 = svdup_n_u8 (127), + z0 = svdup_u8 (127)) + +/* +** dup_128_u8: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u8, svuint8_t, + z0 = svdup_n_u8 (128), + z0 = svdup_u8 (128)) + +/* +** dup_129_u8: +** mov z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u8, svuint8_t, + z0 = svdup_n_u8 (129), + z0 = svdup_u8 (129)) + +/* +** dup_253_u8: +** mov z0\.b, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u8, svuint8_t, + z0 = svdup_n_u8 (253), + z0 = svdup_u8 (253)) + +/* +** dup_254_u8: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u8, svuint8_t, + z0 = svdup_n_u8 (254), + z0 = svdup_u8 (254)) + +/* +** dup_255_u8: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u8, svuint8_t, + z0 = svdup_n_u8 (255), + z0 = svdup_u8 (255)) + +/* +** dup_m1_u8: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u8, svuint8_t, + z0 = svdup_n_u8 (-1), + z0 = svdup_u8 (-1)) + +/* +** dup_m128_u8: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u8, svuint8_t, + z0 = svdup_n_u8 (-128), + z0 = svdup_u8 (-128)) + +/* +** dup_w0_u8: +** mov z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u8, svuint8_t, uint8_t, + z0 = svdup_n_u8 (x0), + z0 = svdup_u8 (x0)) + +/* +** dup_1_u8_m: +** mov z0\.b, p0/m, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 1), + z0 = svdup_u8_m (z0, p0, 1)) + +/* +** dup_127_u8_m: +** mov z0\.b, p0/m, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 127), + z0 = svdup_u8_m (z0, p0, 127)) + +/* +** dup_128_u8_m: +** mov z0\.b, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 128), + z0 = svdup_u8_m (z0, p0, 128)) + +/* +** dup_129_u8_m: +** mov z0\.b, p0/m, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 129), + z0 = svdup_u8_m (z0, p0, 129)) + +/* +** dup_253_u8_m: +** mov z0\.b, p0/m, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 253), + z0 = svdup_u8_m (z0, p0, 253)) + +/* +** dup_254_u8_m: +** mov z0\.b, p0/m, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 254), + z0 = svdup_u8_m (z0, p0, 254)) + +/* +** dup_255_u8_m: +** mov z0\.b, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 255), + z0 = svdup_u8_m (z0, p0, 255)) + +/* +** dup_m1_u8_m: +** mov z0\.b, p0/m, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, -1), + z0 = svdup_u8_m (z0, p0, -1)) + +/* +** dup_m128_u8_m: +** mov z0\.b, p0/m, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, -128), + z0 = svdup_u8_m (z0, p0, -128)) + +/* +** dup_0_u8_m: +** mov z0\.b, p0/m, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u8_m, svuint8_t, + z0 = svdup_n_u8_m (z0, p0, 0), + z0 = svdup_u8_m (z0, p0, 0)) + +/* +** dup_w0_u8_m: +** movprfx z0, z1 +** mov z0\.b, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u8_m, svuint8_t, uint8_t, + z0 = svdup_n_u8_m (z1, p0, x0), + z0 = svdup_u8_m (z1, p0, x0)) + +/* +** dup_1_u8_z: +** mov z0\.b, p0/z, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 1), + z0 = svdup_u8_z (p0, 1)) + +/* +** dup_127_u8_z: +** mov z0\.b, p0/z, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 127), + z0 = svdup_u8_z (p0, 127)) + +/* +** dup_128_u8_z: +** mov z0\.b, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 128), + z0 = svdup_u8_z (p0, 128)) + +/* +** dup_129_u8_z: +** mov z0\.b, p0/z, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 129), + z0 = svdup_u8_z (p0, 129)) + +/* +** dup_253_u8_z: +** mov z0\.b, p0/z, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 253), + z0 = svdup_u8_z (p0, 253)) + +/* +** dup_254_u8_z: +** mov z0\.b, p0/z, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 254), + z0 = svdup_u8_z (p0, 254)) + +/* +** dup_255_u8_z: +** mov z0\.b, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 255), + z0 = svdup_u8_z (p0, 255)) + +/* +** dup_m1_u8_z: +** mov z0\.b, p0/z, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, -1), + z0 = svdup_u8_z (p0, -1)) + +/* +** dup_m128_u8_z: +** mov z0\.b, p0/z, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, -128), + z0 = svdup_u8_z (p0, -128)) + +/* +** dup_0_u8_z: +** mov z0\.b, p0/z, #0 +** ret +*/ +TEST_UNIFORM_Z (dup_0_u8_z, svuint8_t, + z0 = svdup_n_u8_z (p0, 0), + z0 = svdup_u8_z (p0, 0)) + +/* +** dup_w0_u8_z: +** movprfx z0\.b, p0/z, z0\.b +** mov z0\.b, p0/m, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u8_z, svuint8_t, uint8_t, + z0 = svdup_n_u8_z (p0, x0), + z0 = svdup_u8_z (p0, x0)) + +/* +** dup_1_u8_x: +** mov z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (dup_1_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 1), + z0 = svdup_u8_x (p0, 1)) + +/* +** dup_127_u8_x: +** mov z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (dup_127_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 127), + z0 = svdup_u8_x (p0, 127)) + +/* +** dup_128_u8_x: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_128_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 128), + z0 = svdup_u8_x (p0, 128)) + +/* +** dup_129_u8_x: +** mov z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (dup_129_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 129), + z0 = svdup_u8_x (p0, 129)) + +/* +** dup_253_u8_x: +** mov z0\.b, #-3 +** ret +*/ +TEST_UNIFORM_Z (dup_253_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 253), + z0 = svdup_u8_x (p0, 253)) + +/* +** dup_254_u8_x: +** mov z0\.b, #-2 +** ret +*/ +TEST_UNIFORM_Z (dup_254_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 254), + z0 = svdup_u8_x (p0, 254)) + +/* +** dup_255_u8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_255_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, 255), + z0 = svdup_u8_x (p0, 255)) + +/* +** dup_m1_u8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (dup_m1_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, -1), + z0 = svdup_u8_x (p0, -1)) + +/* +** dup_m128_u8_x: +** mov z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (dup_m128_u8_x, svuint8_t, + z0 = svdup_n_u8_x (p0, -128), + z0 = svdup_u8_x (p0, -128)) + +/* +** dup_w0_u8_x: +** mov z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (dup_w0_u8_x, svuint8_t, uint8_t, + z0 = svdup_n_u8_x (p0, x0), + z0 = svdup_u8_x (p0, x0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c new file mode 100644 index 00000000000..ecbacd7e98b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b16.c @@ -0,0 +1,276 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_00_b16: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dupq_00_b16, + p0 = svdupq_n_b16 (0, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b16 (0, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_11_b16: +** ptrue p0\.d, all +** ret +*/ +TEST_UNIFORM_P (dupq_11_b16, + p0 = svdupq_n_b16 (1, 0, 0, 0, 1, 0, 0, 0), + p0 = svdupq_b16 (1, 0, 0, 0, 1, 0, 0, 0)) + +/* +** dupq_22_b16: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.h, \1\.h, \2\.h +** | +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.h, \4\.h, \3\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_22_b16, + p0 = svdupq_n_b16 (0, 1, 0, 0, 0, 1, 0, 0), + p0 = svdupq_b16 (0, 1, 0, 0, 0, 1, 0, 0)) + +/* +** dupq_33_b16: +** ptrue (p[0-7])\.d, all +** trn1 p0\.h, \1\.h, \1\.h +** ret +*/ +TEST_UNIFORM_P (dupq_33_b16, + p0 = svdupq_n_b16 (1, 1, 0, 0, 1, 1, 0, 0), + p0 = svdupq_b16 (1, 1, 0, 0, 1, 1, 0, 0)) + +/* +** dupq_44_b16: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.s, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.d, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_44_b16, + p0 = svdupq_n_b16 (0, 0, 1, 0, 0, 0, 1, 0), + p0 = svdupq_b16 (0, 0, 1, 0, 0, 0, 1, 0)) + +/* +** dupq_55_b16: +** ptrue p0\.s, all +** ret +*/ +TEST_UNIFORM_P (dupq_55_b16, + p0 = svdupq_n_b16 (1, 0, 1, 0, 1, 0, 1, 0), + p0 = svdupq_b16 (1, 0, 1, 0, 1, 0, 1, 0)) + +/* +** dupq_66_b16: +** ... +** cmpne p0\.b, p[0-7]/z, z[0-9]+\.b, #0 +** ret +*/ +TEST_UNIFORM_P (dupq_66_b16, + p0 = svdupq_n_b16 (0, 1, 1, 0, 0, 1, 1, 0), + p0 = svdupq_b16 (0, 1, 1, 0, 0, 1, 1, 0)) + +/* +** dupq_77_b16: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.[hs], all +** trn1 p0\.h, \2\.h, \1\.h +** | +** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-7])\.s, all +** trn1 p0\.h, \3\.h, \4\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_77_b16, + p0 = svdupq_n_b16 (1, 1, 1, 0, 1, 1, 1, 0), + p0 = svdupq_b16 (1, 1, 1, 0, 1, 1, 1, 0)) + +/* +** dupq_88_b16: +** ( +** mov (z[0-9]+)\.d, #71776119061217280 +** ptrue (p[0-7])\.b, all +** cmpne p0\.b, \2/z, \1\.b, #0 +** | +** ptrue (p[0-7])\.b, all +** mov (z[0-9]+)\.d, #71776119061217280 +** cmpne p0\.b, \3/z, \4\.b, #0 +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_88_b16, + p0 = svdupq_n_b16 (0, 0, 0, 1, 0, 0, 0, 1), + p0 = svdupq_b16 (0, 0, 0, 1, 0, 0, 0, 1)) + +/* +** dupq_99_b16: +** ... +** cmpne p0\.b, p[0-7]/z, z[0-9]+\.b, #0 +** ret +*/ +TEST_UNIFORM_P (dupq_99_b16, + p0 = svdupq_n_b16 (1, 0, 0, 1, 1, 0, 0, 1), + p0 = svdupq_b16 (1, 0, 0, 1, 1, 0, 0, 1)) + +/* +** dupq_aa_b16: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.h, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.s, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_aa_b16, + p0 = svdupq_n_b16 (0, 1, 0, 1, 0, 1, 0, 1), + p0 = svdupq_b16 (0, 1, 0, 1, 0, 1, 0, 1)) + +/* +** dupq_bb_b16: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.[hs], all +** trn1 p0\.h, \1\.h, \2\.h +** | +** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-7])\.d, all +** trn1 p0\.h, \4\.h, \3\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_bb_b16, + p0 = svdupq_n_b16 (1, 1, 0, 1, 1, 1, 0, 1), + p0 = svdupq_b16 (1, 1, 0, 1, 1, 1, 0, 1)) + +/* +** dupq_cc_b16: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.h, all +** trn1 p0\.s, \1\.s, \2\.s +** | +** ptrue (p[0-7])\.h, all +** pfalse (p[0-7])\.b +** trn1 p0\.s, \4\.s, \3\.s +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_cc_b16, + p0 = svdupq_n_b16 (0, 0, 1, 1, 0, 0, 1, 1), + p0 = svdupq_b16 (0, 0, 1, 1, 0, 0, 1, 1)) + +/* +** dupq_dd_b16: +** ( +** ptrue (p[0-7])\.[sd], all +** ptrue (p[0-7])\.h, all +** trn1 p0\.s, \1\.s, \2\.s +** | +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.[sd], all +** trn1 p0\.s, \4\.s, \3\.s +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_dd_b16, + p0 = svdupq_n_b16 (1, 0, 1, 1, 1, 0, 1, 1), + p0 = svdupq_b16 (1, 0, 1, 1, 1, 0, 1, 1)) + +/* +** dupq_ee_b16: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.h, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.d, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_ee_b16, + p0 = svdupq_n_b16 (0, 1, 1, 1, 0, 1, 1, 1), + p0 = svdupq_b16 (0, 1, 1, 1, 0, 1, 1, 1)) + +/* +** dupq_ff_b16: +** ptrue p0\.h, all +** ret +*/ +TEST_UNIFORM_P (dupq_ff_b16, + p0 = svdupq_n_b16 (1, 1, 1, 1, 1, 1, 1, 1), + p0 = svdupq_b16 (1, 1, 1, 1, 1, 1, 1, 1)) + +/* +** dupq_01_b16: +** ( +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \1\.d, \2\.d +** | +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_01_b16, + p0 = svdupq_n_b16 (1, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b16 (1, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_03_b16: +** ... +** cmpne p0\.b, p[0-7]/z, z[0-9]+\.b, #0 +** ret +*/ +TEST_UNIFORM_P (dupq_03_b16, + p0 = svdupq_n_b16 (1, 1, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b16 (1, 1, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_0f_b16: +** ( +** ptrue (p[0-7])\.h, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \1\.d, \2\.d +** | +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.h, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_0f_b16, + p0 = svdupq_n_b16 (1, 1, 1, 1, 0, 0, 0, 0), + p0 = svdupq_b16 (1, 1, 1, 1, 0, 0, 0, 0)) + +/* +** dupq_3f_b16: +** ... +** cmpne p0\.b, p[0-7]/z, z[0-9]+\.b, #0 +** ret +*/ +TEST_UNIFORM_P (dupq_3f_b16, + p0 = svdupq_n_b16 (1, 1, 1, 1, 1, 1, 0, 0), + p0 = svdupq_b16 (1, 1, 1, 1, 1, 1, 0, 0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c new file mode 100644 index 00000000000..39719a76d3c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b32.c @@ -0,0 +1,132 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_0_b32: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dupq_0_b32, + p0 = svdupq_n_b32 (0, 0, 0, 0), + p0 = svdupq_b32 (0, 0, 0, 0)) + +/* +** dupq_1_b32: +** ( +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \1\.d, \2\.d +** | +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_1_b32, + p0 = svdupq_n_b32 (1, 0, 0, 0), + p0 = svdupq_b32 (1, 0, 0, 0)) + +/* +** dupq_3_b32: +** ( +** ptrue (p[0-7])\.s, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \1\.d, \2\.d +** | +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.s, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_3_b32, + p0 = svdupq_n_b32 (1, 1, 0, 0), + p0 = svdupq_b32 (1, 1, 0, 0)) + +/* +** dupq_4_b32: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \1\.d, \2\.d +** | +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_4_b32, + p0 = svdupq_n_b32 (0, 0, 1, 0), + p0 = svdupq_b32 (0, 0, 1, 0)) + +/* +** dupq_5_b32: +** ptrue p0\.d, all +** ret +*/ +TEST_UNIFORM_P (dupq_5_b32, + p0 = svdupq_n_b32 (1, 0, 1, 0), + p0 = svdupq_b32 (1, 0, 1, 0)) + +/* +** dupq_7_b32: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \1\.d, \2\.d +** | +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.s, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_7_b32, + p0 = svdupq_n_b32 (1, 1, 1, 0), + p0 = svdupq_b32 (1, 1, 1, 0)) + +/* +** dupq_a_b32: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.s, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.d, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_a_b32, + p0 = svdupq_n_b32 (0, 1, 0, 1), + p0 = svdupq_b32 (0, 1, 0, 1)) + +/* +** dupq_e_b32: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.s, all +** trn1 p0\.d, \1\.d, \2\.d +** | +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_e_b32, + p0 = svdupq_n_b32 (1, 0, 1, 1), + p0 = svdupq_b32 (1, 0, 1, 1)) + +/* +** dupq_f_b32: +** ptrue p0\.s, all +** ret +*/ +TEST_UNIFORM_P (dupq_f_b32, + p0 = svdupq_n_b32 (1, 1, 1, 1), + p0 = svdupq_b32 (1, 1, 1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c new file mode 100644 index 00000000000..820ace43189 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b64.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_0_b64: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dupq_0_b64, + p0 = svdupq_n_b64 (0, 0), + p0 = svdupq_b64 (0, 0)) + +/* +** dupq_1_b64: +** ( +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \1\.d, \2\.d +** | +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_1_b64, + p0 = svdupq_n_b64 (1, 0), + p0 = svdupq_b64 (1, 0)) + +/* +** dupq_2_b64: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \1\.d, \2\.d +** | +** ptrue (p[0-7])\.d, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \4\.d, \3\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_2_b64, + p0 = svdupq_n_b64 (0, 1), + p0 = svdupq_b64 (0, 1)) + +/* +** dupq_3_b64: +** ptrue p0\.d, all +** ret +*/ +TEST_UNIFORM_P (dupq_3_b64, + p0 = svdupq_n_b64 (1, 1), + p0 = svdupq_b64 (1, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c new file mode 100644 index 00000000000..4762f950bad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_b8.c @@ -0,0 +1,413 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_0000_b8: +** pfalse p0\.b +** ret +*/ +TEST_UNIFORM_P (dupq_0000_b8, + p0 = svdupq_n_b8 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_1111_b8: +** ptrue p0\.s, all +** ret +*/ +TEST_UNIFORM_P (dupq_1111_b8, + p0 = svdupq_n_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 1, 0, 0, 0, 1, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 1, 0, 0, 0, 1, 0, 0, 0)) + +/* +** dupq_2222_b8: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.s, all +** trn1 p0\.b, \1\.b, \2\.b +** | +** ptrue (p[0-7])\.s, all +** pfalse (p[0-7])\.b +** trn1 p0\.b, \4\.b, \3\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_2222_b8, + p0 = svdupq_n_b8 (0, 1, 0, 0, 0, 1, 0, 0, + 0, 1, 0, 0, 0, 1, 0, 0), + p0 = svdupq_b8 (0, 1, 0, 0, 0, 1, 0, 0, + 0, 1, 0, 0, 0, 1, 0, 0)) + +/* +** dupq_3333_b8: +** ptrue (p[0-7])\.s, all +** trn1 p0\.b, \1\.b, \1\.b +** ret +*/ +TEST_UNIFORM_P (dupq_3333_b8, + p0 = svdupq_n_b8 (1, 1, 0, 0, 1, 1, 0, 0, + 1, 1, 0, 0, 1, 1, 0, 0), + p0 = svdupq_b8 (1, 1, 0, 0, 1, 1, 0, 0, + 1, 1, 0, 0, 1, 1, 0, 0)) + +/* +** dupq_4444_b8: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.h, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.s, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_4444_b8, + p0 = svdupq_n_b8 (0, 0, 1, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 1, 0), + p0 = svdupq_b8 (0, 0, 1, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 1, 0)) + +/* +** dupq_5555_b8: +** ptrue p0\.h, all +** ret +*/ +TEST_UNIFORM_P (dupq_5555_b8, + p0 = svdupq_n_b8 (1, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 1, 0, 1, 0, 1, 0), + p0 = svdupq_b8 (1, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 1, 0, 1, 0, 1, 0)) + +/* +** dupq_6666_b8: +** ( +** mov (z[0-9]+)\.s, #16776960 +** ptrue (p[0-7])\.b, all +** cmpne p0\.b, \2/z, \1\.b, #0 +** | +** ptrue (p[0-7])\.b, all +** mov (z[0-9]+)\.s, #16776960 +** cmpne p0\.b, \3/z, \4\.b, #0 +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_6666_b8, + p0 = svdupq_n_b8 (0, 1, 1, 0, 0, 1, 1, 0, + 0, 1, 1, 0, 0, 1, 1, 0), + p0 = svdupq_b8 (0, 1, 1, 0, 0, 1, 1, 0, + 0, 1, 1, 0, 0, 1, 1, 0)) + +/* +** dupq_7777_b8: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.[bh], all +** trn1 p0\.b, \2\.b, \1\.b +** | +** ptrue (p[0-7])\.[bh], all +** ptrue (p[0-7])\.s, all +** trn1 p0\.b, \3\.b, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_7777_b8, + p0 = svdupq_n_b8 (1, 1, 1, 0, 1, 1, 1, 0, + 1, 1, 1, 0, 1, 1, 1, 0), + p0 = svdupq_b8 (1, 1, 1, 0, 1, 1, 1, 0, + 1, 1, 1, 0, 1, 1, 1, 0)) + +/* +** dupq_8888_b8: +** ( +** mov (z[0-9]+)\.s, #-16777216 +** ptrue (p[0-7])\.b, all +** cmpne p0\.b, \2/z, \1\.b, #0 +** | +** ptrue (p[0-7])\.b, all +** mov (z[0-9]+)\.s, #-16777216 +** cmpne p0\.b, \3/z, \4\.b, #0 +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_8888_b8, + p0 = svdupq_n_b8 (0, 0, 0, 1, 0, 0, 0, 1, + 0, 0, 0, 1, 0, 0, 0, 1), + p0 = svdupq_b8 (0, 0, 0, 1, 0, 0, 0, 1, + 0, 0, 0, 1, 0, 0, 0, 1)) + +/* +** dupq_9999_b8: +** ( +** mov (z[0-9]+)\.s, #-16776961 +** ptrue (p[0-7])\.b, all +** cmpne p0\.b, \2/z, \1\.b, #0 +** | +** ptrue (p[0-7])\.b, all +** mov (z[0-9]+)\.s, #-16776961 +** cmpne p0\.b, \3/z, \4\.b, #0 +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_9999_b8, + p0 = svdupq_n_b8 (1, 0, 0, 1, 1, 0, 0, 1, + 1, 0, 0, 1, 1, 0, 0, 1), + p0 = svdupq_b8 (1, 0, 0, 1, 1, 0, 0, 1, + 1, 0, 0, 1, 1, 0, 0, 1)) + +/* +** dupq_aaaa_b8: +** ( +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.b, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.b, all +** ptrue (p[0-7])\.h, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_aaaa_b8, + p0 = svdupq_n_b8 (0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1), + p0 = svdupq_b8 (0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1)) + +/* +** dupq_bbbb_b8: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.[bh], all +** trn1 p0\.b, \1\.b, \2\.b +** | +** ptrue (p[0-7])\.[bh], all +** ptrue (p[0-7])\.s, all +** trn1 p0\.b, \4\.b, \3\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_bbbb_b8, + p0 = svdupq_n_b8 (1, 1, 0, 1, 1, 1, 0, 1, + 1, 1, 0, 1, 1, 1, 0, 1), + p0 = svdupq_b8 (1, 1, 0, 1, 1, 1, 0, 1, + 1, 1, 0, 1, 1, 1, 0, 1)) + +/* +** dupq_cccc_b8: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.b, all +** trn1 p0\.h, \1\.h, \2\.h +** | +** ptrue (p[0-7])\.b, all +** pfalse (p[0-7])\.b +** trn1 p0\.h, \4\.h, \3\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_cccc_b8, + p0 = svdupq_n_b8 (0, 0, 1, 1, 0, 0, 1, 1, + 0, 0, 1, 1, 0, 0, 1, 1), + p0 = svdupq_b8 (0, 0, 1, 1, 0, 0, 1, 1, + 0, 0, 1, 1, 0, 0, 1, 1)) + +/* +** dupq_dddd_b8: +** ( +** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-7])\.b, all +** trn1 p0\.h, \1\.h, \2\.h +** | +** ptrue (p[0-7])\.b, all +** ptrue (p[0-7])\.[hs], all +** trn1 p0\.h, \4\.h, \3\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_dddd_b8, + p0 = svdupq_n_b8 (1, 0, 1, 1, 1, 0, 1, 1, + 1, 0, 1, 1, 1, 0, 1, 1), + p0 = svdupq_b8 (1, 0, 1, 1, 1, 0, 1, 1, + 1, 0, 1, 1, 1, 0, 1, 1)) + +/* +** dupq_eeee_b8: +** ( +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.b, all +** not p0\.b, \2/z, \1\.b +** | +** ptrue (p[0-7])\.b, all +** ptrue (p[0-7])\.s, all +** not p0\.b, \3/z, \4\.b +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_eeee_b8, + p0 = svdupq_n_b8 (0, 1, 1, 1, 0, 1, 1, 1, + 0, 1, 1, 1, 0, 1, 1, 1), + p0 = svdupq_b8 (0, 1, 1, 1, 0, 1, 1, 1, + 0, 1, 1, 1, 0, 1, 1, 1)) + +/* +** dupq_ffff_b8: +** ptrue p0\.b, all +** ret +*/ +TEST_UNIFORM_P (dupq_ffff_b8, + p0 = svdupq_n_b8 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + p0 = svdupq_b8 (1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1)) + +/* +** dupq_5f5f_b8: +** ( +** ptrue (p[0-7])\.h, all +** ptrue (p[0-7])\.b, all +** trn1 p0\.s, \2\.s, \1\.s +** | +** ptrue (p[0-7])\.b, all +** ptrue (p[0-7])\.h, all +** trn1 p0\.s, \3\.s, \4\.s +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_5f5f_b8, + p0 = svdupq_n_b8 (1, 1, 1, 1, 1, 0, 1, 0, + 1, 1, 1, 1, 1, 0, 1, 0), + p0 = svdupq_b8 (1, 1, 1, 1, 1, 0, 1, 0, + 1, 1, 1, 1, 1, 0, 1, 0)) + +/* +** dupq_1f1f_b8: +** ( +** ptrue (p[0-7])\.[sd], all +** ptrue (p[0-7])\.b, all +** trn1 p0\.s, \2\.s, \1\.s +** | +** ptrue (p[0-7])\.b, all +** ptrue (p[0-7])\.[sd], all +** trn1 p0\.s, \3\.s, \4\.s +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_1f1f_b8, + p0 = svdupq_n_b8 (1, 1, 1, 1, 1, 0, 0, 0, + 1, 1, 1, 1, 1, 0, 0, 0), + p0 = svdupq_b8 (1, 1, 1, 1, 1, 0, 0, 0, + 1, 1, 1, 1, 1, 0, 0, 0)) + +/* +** dupq_1515_b8: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.[hs], all +** trn1 p0\.h, \2\.h, \1\.h +** | +** ptrue (p[0-7])\.[hs], all +** ptrue (p[0-7])\.d, all +** trn1 p0\.h, \3\.h, \4\.h +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_1515_b8, + p0 = svdupq_n_b8 (1, 0, 1, 0, 1, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 1, 0, 1, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 0)) + +/* +** dupq_0505_b8: +** ptrue (p[0-7])\.d, all +** trn1 p0\.h, \1\.h, \1\.h +** ret +*/ +TEST_UNIFORM_P (dupq_0505_b8, + p0 = svdupq_n_b8 (1, 0, 1, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 1, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0, 0, 0)) + +/* +** dupq_00ff_b8: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.b, all +** trn1 p0\.d, \2\.d, \1\.d +** | +** ptrue (p[0-7])\.b, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \3\.d, \4\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_00ff_b8, + p0 = svdupq_n_b8 (1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_0055_b8: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.h, all +** trn1 p0\.d, \2\.d, \1\.d +** | +** ptrue (p[0-7])\.h, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \3\.d, \4\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_0055_b8, + p0 = svdupq_n_b8 (1, 0, 1, 0, 1, 0, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 1, 0, 1, 0, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_0011_b8: +** ( +** pfalse (p[0-7])\.b +** ptrue (p[0-7])\.s, all +** trn1 p0\.d, \2\.d, \1\.d +** | +** ptrue (p[0-7])\.s, all +** pfalse (p[0-7])\.b +** trn1 p0\.d, \3\.d, \4\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_0011_b8, + p0 = svdupq_n_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0)) + +/* +** dupq_0111_b8: +** ( +** ptrue (p[0-7])\.d, all +** ptrue (p[0-7])\.s, all +** trn1 p0\.d, \2\.d, \1\.d +** | +** ptrue (p[0-7])\.s, all +** ptrue (p[0-7])\.d, all +** trn1 p0\.d, \3\.d, \4\.d +** ) +** ret +*/ +TEST_UNIFORM_P (dupq_0111_b8, + p0 = svdupq_n_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0), + p0 = svdupq_b8 (1, 0, 0, 0, 1, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f16.c new file mode 100644 index 00000000000..91de8344c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f16.c @@ -0,0 +1,53 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_1c_f16: +** mov z0\.s, #15360 +** ret +*/ +TEST_UNIFORM_Z (dupq_1c_f16, svfloat16_t, + z0 = svdupq_n_f16 (1.0, 0, 1.0, 0, 1.0, 0, 1.0, 0), + z0 = svdupq_f16 (1.0, 0, 1.0, 0, 1.0, 0, 1.0, 0)); + +/* +** dupq_5ic_f16: +** movi v([0-9]+)\.4s, 0x45, lsl 24 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_5ic_f16, svfloat16_t, + z0 = svdupq_n_f16 (0, 5.0, 0, 5.0, 0, 5.0, 0, 5.0), + z0 = svdupq_f16 (0, 5.0, 0, 5.0, 0, 5.0, 0, 5.0)); + + +/* +** dupq_m1c_f16: +** movi v([0-9]+)\.4s, 0xbc, lsl 8 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_m1c_f16, svfloat16_t, + z0 = svdupq_n_f16 (-1.0, 0, -1.0, 0, -1.0, 0, -1.0, 0), + z0 = svdupq_f16 (-1.0, 0, -1.0, 0, -1.0, 0, -1.0, 0)); + +/* +** dupq_40p5c_f16: +** mov (w[0-9]+), 20752 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_40p5c_f16, svfloat16_t, + z0 = svdupq_n_f16 (40.5, 0, 40.5, 0, 40.5, 0, 40.5, 0), + z0 = svdupq_f16 (40.5, 0, 40.5, 0, 40.5, 0, 40.5, 0)); + +/* +** dupq_pool_f16: +** ... +** ld1rqh z0\.h, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_f16, svfloat16_t, + z0 = svdupq_n_f16 (4.75, 1.0, 9, 77, 5.25, 22, 19, 50), + z0 = svdupq_f16 (4.75, 1.0, 9, 77, 5.25, 22, 19, 50)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f32.c new file mode 100644 index 00000000000..4f9c04f1a6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f32.c @@ -0,0 +1,53 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_1c_f32: +** mov z0\.d, #1065353216 +** ret +*/ +TEST_UNIFORM_Z (dupq_1c_f32, svfloat32_t, + z0 = svdupq_n_f32 (1.0, 0, 1.0, 0), + z0 = svdupq_f32 (1.0, 0, 1.0, 0)); + +/* +** dupq_5ic_f32: +** mov (x[0-9]+), 4656722014701092864 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_5ic_f32, svfloat32_t, + z0 = svdupq_n_f32 (0, 5.0, 0, 5.0), + z0 = svdupq_f32 (0, 5.0, 0, 5.0)); + + +/* +** dupq_m1c_f32: +** mov (x[0-9]+), 3212836864 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_m1c_f32, svfloat32_t, + z0 = svdupq_n_f32 (-1.0, 0, -1.0, 0), + z0 = svdupq_f32 (-1.0, 0, -1.0, 0)); + +/* +** dupq_40p5c_f32: +** mov (x[0-9]+), 1109524480 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_40p5c_f32, svfloat32_t, + z0 = svdupq_n_f32 (40.5, 0, 40.5, 0), + z0 = svdupq_f32 (40.5, 0, 40.5, 0)); + +/* +** dupq_pool_f32: +** ... +** ld1rqw z0\.s, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_f32, svfloat32_t, + z0 = svdupq_n_f32 (4.5, 10.1, 7.3, 11.8), + z0 = svdupq_f32 (4.5, 10.1, 7.3, 11.8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f64.c new file mode 100644 index 00000000000..27d14480ef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_f64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_pool_f64: +** ... +** ld1rqd z0\.d, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_f64, svfloat64_t, + z0 = svdupq_n_f64 (4.5, 10.1), + z0 = svdupq_f64 (4.5, 10.1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f16.c new file mode 100644 index 00000000000..6fa97ca3a1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f16.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_f16_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f16_tied, svfloat16_t, + z0 = svdupq_lane_f16 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_f16_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f16_untied, svfloat16_t, + z0 = svdupq_lane_f16 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_f16: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_f16, svfloat16_t, + z0 = svdupq_lane_f16 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_f16: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_f16, svfloat16_t, + z0 = svdupq_lane_f16 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_f16: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_f16, svfloat16_t, + z0 = svdupq_lane_f16 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f32.c new file mode 100644 index 00000000000..69ce5452e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f32.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_f32_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f32_tied, svfloat32_t, + z0 = svdupq_lane_f32 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_f32_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f32_untied, svfloat32_t, + z0 = svdupq_lane_f32 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_f32: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_f32, svfloat32_t, + z0 = svdupq_lane_f32 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_f32: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_f32, svfloat32_t, + z0 = svdupq_lane_f32 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_f32: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_f32, svfloat32_t, + z0 = svdupq_lane_f32 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f64.c new file mode 100644 index 00000000000..51a8d9f2dee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_f64.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_f64_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f64_tied, svfloat64_t, + z0 = svdupq_lane_f64 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_f64_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_f64_untied, svfloat64_t, + z0 = svdupq_lane_f64 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_f64: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_f64, svfloat64_t, + z0 = svdupq_lane_f64 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_f64: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_f64, svfloat64_t, + z0 = svdupq_lane_f64 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_f64: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_f64, svfloat64_t, + z0 = svdupq_lane_f64 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s16.c new file mode 100644 index 00000000000..08a0510be02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s16.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_s16_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s16_tied, svint16_t, + z0 = svdupq_lane_s16 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_s16_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s16_untied, svint16_t, + z0 = svdupq_lane_s16 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_s16: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_s16, svint16_t, + z0 = svdupq_lane_s16 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_s16: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_s16, svint16_t, + z0 = svdupq_lane_s16 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_s16: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_s16, svint16_t, + z0 = svdupq_lane_s16 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s32.c new file mode 100644 index 00000000000..e9a9c9a603b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s32.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_s32_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s32_tied, svint32_t, + z0 = svdupq_lane_s32 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_s32_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s32_untied, svint32_t, + z0 = svdupq_lane_s32 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_s32: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_s32, svint32_t, + z0 = svdupq_lane_s32 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_s32: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_s32, svint32_t, + z0 = svdupq_lane_s32 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_s32: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_s32, svint32_t, + z0 = svdupq_lane_s32 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s64.c new file mode 100644 index 00000000000..2c634214925 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s64.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_s64_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s64_tied, svint64_t, + z0 = svdupq_lane_s64 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_s64_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s64_untied, svint64_t, + z0 = svdupq_lane_s64 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_s64: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_s64, svint64_t, + z0 = svdupq_lane_s64 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_s64: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_s64, svint64_t, + z0 = svdupq_lane_s64 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_s64: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_s64, svint64_t, + z0 = svdupq_lane_s64 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s8.c new file mode 100644 index 00000000000..2c2e6ee721d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_s8.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_s8_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s8_tied, svint8_t, + z0 = svdupq_lane_s8 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_s8_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_s8_untied, svint8_t, + z0 = svdupq_lane_s8 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_s8: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_s8, svint8_t, + z0 = svdupq_lane_s8 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_s8: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_s8, svint8_t, + z0 = svdupq_lane_s8 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_s8: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_s8, svint8_t, + z0 = svdupq_lane_s8 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u16.c new file mode 100644 index 00000000000..e5fba592f47 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u16.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_u16_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u16_tied, svuint16_t, + z0 = svdupq_lane_u16 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_u16_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u16_untied, svuint16_t, + z0 = svdupq_lane_u16 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_u16: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_u16, svuint16_t, + z0 = svdupq_lane_u16 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_u16: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_u16, svuint16_t, + z0 = svdupq_lane_u16 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_u16: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_u16, svuint16_t, + z0 = svdupq_lane_u16 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u32.c new file mode 100644 index 00000000000..fb3346e457b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u32.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_u32_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u32_tied, svuint32_t, + z0 = svdupq_lane_u32 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_u32_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u32_untied, svuint32_t, + z0 = svdupq_lane_u32 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_u32: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_u32, svuint32_t, + z0 = svdupq_lane_u32 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_u32: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_u32, svuint32_t, + z0 = svdupq_lane_u32 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_u32: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_u32, svuint32_t, + z0 = svdupq_lane_u32 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u64.c new file mode 100644 index 00000000000..22f1d5d55d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u64.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_u64_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u64_tied, svuint64_t, + z0 = svdupq_lane_u64 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_u64_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u64_untied, svuint64_t, + z0 = svdupq_lane_u64 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_u64: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_u64, svuint64_t, + z0 = svdupq_lane_u64 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_u64: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_u64, svuint64_t, + z0 = svdupq_lane_u64 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_u64: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_u64, svuint64_t, + z0 = svdupq_lane_u64 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u8.c new file mode 100644 index 00000000000..ba16f836a88 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_lane_u8.c @@ -0,0 +1,48 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_lane_0_u8_tied: +** dup z0\.q, z0\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u8_tied, svuint8_t, + z0 = svdupq_lane_u8 (z0, 0), + z0 = svdupq_lane (z0, 0)) + +/* +** dupq_lane_0_u8_untied: +** dup z0\.q, z1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_0_u8_untied, svuint8_t, + z0 = svdupq_lane_u8 (z1, 0), + z0 = svdupq_lane (z1, 0)) + +/* +** dupq_lane_1_u8: +** dup z0\.q, z0\.q\[1\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_1_u8, svuint8_t, + z0 = svdupq_lane_u8 (z0, 1), + z0 = svdupq_lane (z0, 1)) + +/* +** dupq_lane_2_u8: +** dup z0\.q, z0\.q\[2\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_2_u8, svuint8_t, + z0 = svdupq_lane_u8 (z0, 2), + z0 = svdupq_lane (z0, 2)) + +/* +** dupq_lane_3_u8: +** dup z0\.q, z0\.q\[3\] +** ret +*/ +TEST_UNIFORM_Z (dupq_lane_3_u8, svuint8_t, + z0 = svdupq_lane_u8 (z0, 3), + z0 = svdupq_lane (z0, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s16.c new file mode 100644 index 00000000000..5a9a53b2ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s16.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_25600s_s16: +** mov z0\.s, #25600 +** ret +*/ +TEST_UNIFORM_Z (dupq_25600s_s16, svint16_t, + z0 = svdupq_n_s16 (25600, 0, 25600, 0, 25600, 0, 25600, 0), + z0 = svdupq_s16 (25600, 0, 25600, 0, 25600, 0, 25600, 0)) + +/* +** dupq_7ff00s_s16: +** mov z0\.s, #524032 +** ret +*/ +TEST_UNIFORM_Z (dupq_7ff00s_s16, svint16_t, + z0 = svdupq_n_s16 (0xff00, 7, 0xff00, 7, 0xff00, 7, 0xff00, 7), + z0 = svdupq_s16 (0xff00, 7, 0xff00, 7, 0xff00, 7, 0xff00, 7)) + +/* +** dupq_65536d_s16: +** mov z0\.d, #65536 +** ret +*/ +TEST_UNIFORM_Z (dupq_65536d_s16, svint16_t, + z0 = svdupq_n_s16 (0, 1, 0, 0, 0, 1, 0, 0), + z0 = svdupq_s16 (0, 1, 0, 0, 0, 1, 0, 0)) + +/* +** dupq_m2d_s16: +** mov z0\.d, #-2 +** ret +*/ +TEST_UNIFORM_Z (dupq_m2d_s16, svint16_t, + z0 = svdupq_n_s16 (-2, -1, -1, -1, -2, -1, -1, -1), + z0 = svdupq_s16 (-2, -1, -1, -1, -2, -1, -1, -1)) + +/* +** dupq_4ddb_s16: +** movi v([0-9]+)\.2d, 0xff0000ffff00ff +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_4ddb_s16, svint16_t, + z0 = svdupq_n_s16 (0xff, -1, 0, 0xff, 0xff, -1, 0, 0xff), + z0 = svdupq_s16 (0xff, -1, 0, 0xff, 0xff, -1, 0, 0xff)) + + +/* +** dupq_a093s_s16: +** mov (w[0-9]+), 41107 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_a093s_s16, svint16_t, + z0 = svdupq_n_s16 (0xa093, 0, 0xa093, 0, 0xa093, 0, 0xa093, 0), + z0 = svdupq_s16 (0xa093, 0, 0xa093, 0, 0xa093, 0, 0xa093, 0)); + +/* +** dupq_pool_s16: +** ... +** ld1rqh z0\.h, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_s16, svint16_t, + z0 = svdupq_n_s16 (4, 10, 9, 77, 52, 22, 19, 50), + z0 = svdupq_s16 (4, 10, 9, 77, 52, 22, 19, 50)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s32.c new file mode 100644 index 00000000000..13b24c0db9f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s32.c @@ -0,0 +1,61 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_12800d_s32: +** mov z0\.d, #12800 +** ret +*/ +TEST_UNIFORM_Z (dupq_12800d_s32, svint32_t, + z0 = svdupq_n_s32 (12800, 0, 12800, 0), + z0 = svdupq_s32 (12800, 0, 12800, 0)) + +/* +** dupq_fffffffed_s32: +** mov z0\.d, #4294967294 +** ret +*/ +TEST_UNIFORM_Z (dupq_fffffffed_s32, svint32_t, + z0 = svdupq_n_s32 (-2, 0, -2, 0), + z0 = svdupq_s32 (-2, 0, -2, 0)) + +/* +** dupq_ff00ffffff00d_s32: +** movi v([0-9]+)\.2d, 0xff00ffffff00 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_ff00ffffff00d_s32, svint32_t, + z0 = svdupq_n_s32 (-256, 0xff00, -256, 0xff00), + z0 = svdupq_s32 (-256, 0xff00, -256, 0xff00)) + +/* +** dupq_fedcd_s32: +** mov (x[0-9]+), 65244 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_fedcd_s32, svint32_t, + z0 = svdupq_n_s32 (0xfedc, 0, 0xfedc, 0), + z0 = svdupq_s32 (0xfedc, 0, 0xfedc, 0)) + +/* +** dupq_1357ud_s32: +** mov (x[0-9]+), 21264383082496 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_1357ud_s32, svint32_t, + z0 = svdupq_n_s32 (0, 0x1357, 0, 0x1357), + z0 = svdupq_s32 (0, 0x1357, 0, 0x1357)) + +/* +** dupq_pool_s32: +** ... +** ld1rqw z0\.s, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_s32, svint32_t, + z0 = svdupq_n_s32 (4, 10, 9, 77), + z0 = svdupq_s32 (4, 10, 9, 77)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s64.c new file mode 100644 index 00000000000..d2689fa5cdf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_pool_s64: +** ... +** ld1rqd z0\.d, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_s64, svint64_t, + z0 = svdupq_n_s64 (4, 10), + z0 = svdupq_s64 (4, 10)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s8.c new file mode 100644 index 00000000000..30b36c1620e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_s8.c @@ -0,0 +1,99 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_54h_s8: +** mov z0\.h, #54 +** ret +*/ +TEST_UNIFORM_Z (dupq_54h_s8, svint8_t, + z0 = svdupq_n_s8 (54, 0, 54, 0, 54, 0, 54, 0, + 54, 0, 54, 0, 54, 0, 54, 0), + z0 = svdupq_s8 (54, 0, 54, 0, 54, 0, 54, 0, + 54, 0, 54, 0, 54, 0, 54, 0)) + +/* +** dupq_2560h_s8: +** mov z0\.h, #2560 +** ret +*/ +TEST_UNIFORM_Z (dupq_2560h_s8, svint8_t, + z0 = svdupq_n_s8 (0, 10, 0, 10, 0, 10, 0, 10, + 0, 10, 0, 10, 0, 10, 0, 10), + z0 = svdupq_s8 (0, 10, 0, 10, 0, 10, 0, 10, + 0, 10, 0, 10, 0, 10, 0, 10)) + +/* +** dupq_5120s_s8: +** mov z0\.s, #5120 +** ret +*/ +TEST_UNIFORM_Z (dupq_5120s_s8, svint8_t, + z0 = svdupq_n_s8 (0, 20, 0, 0, 0, 20, 0, 0, + 0, 20, 0, 0, 0, 20, 0, 0), + z0 = svdupq_s8 (0, 20, 0, 0, 0, 20, 0, 0, + 0, 20, 0, 0, 0, 20, 0, 0)) + +/* +** dupq_1ff00s_s8: +** mov z0\.s, #130816 +** ret +*/ +TEST_UNIFORM_Z (dupq_1ff00s_s8, svint8_t, + z0 = svdupq_n_s8 (0, -1, 1, 0, 0, -1, 1, 0, + 0, -1, 1, 0, 0, -1, 1, 0), + z0 = svdupq_s8 (0, -1, 1, 0, 0, -1, 1, 0, + 0, -1, 1, 0, 0, -1, 1, 0)) + +/* +** dupq_96db_s8: +** movi v([0-9]+)\.2d, 0xff0000ff00ffff00 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_96db_s8, svint8_t, + z0 = svdupq_n_s8 (0, -1, -1, 0, -1, 0, 0, -1, + 0, -1, -1, 0, -1, 0, 0, -1), + z0 = svdupq_s8 (0, -1, -1, 0, -1, 0, 0, -1, + 0, -1, -1, 0, -1, 0, 0, -1)) + +/* +** dupq_7755h_s8: +** mov (w[0-9]+), 21879 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_7755h_s8, svint8_t, + z0 = svdupq_n_s8 (0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55), + z0 = svdupq_s8 (0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55)) + +/* +** dupq_729a0000s_s8: +** mov (w[0-9]+), 1922695168 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_729a0000s_s8, svint8_t, + z0 = svdupq_n_s8 (0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72, + 0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72), + z0 = svdupq_s8 (0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72, + 0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72)) + +/* +** dupq_pool_s8: +** ... +** ld1rqb z0\.b, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_s8, svint8_t, + z0 = svdupq_n_s8 (4, 10, 9, 77, 52, 22, 19, 50, + -1, 32, 44, 17, 23, 99, 53, 39), + z0 = svdupq_s8 (4, 10, 9, 77, 52, 22, 19, 50, + -1, 32, 44, 17, 23, 99, 53, 39)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u16.c new file mode 100644 index 00000000000..6ca13222d5f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u16.c @@ -0,0 +1,70 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_25600s_u16: +** mov z0\.s, #25600 +** ret +*/ +TEST_UNIFORM_Z (dupq_25600s_u16, svuint16_t, + z0 = svdupq_n_u16 (25600, 0, 25600, 0, 25600, 0, 25600, 0), + z0 = svdupq_u16 (25600, 0, 25600, 0, 25600, 0, 25600, 0)) + +/* +** dupq_7ff00s_u16: +** mov z0\.s, #524032 +** ret +*/ +TEST_UNIFORM_Z (dupq_7ff00s_u16, svuint16_t, + z0 = svdupq_n_u16 (0xff00, 7, 0xff00, 7, 0xff00, 7, 0xff00, 7), + z0 = svdupq_u16 (0xff00, 7, 0xff00, 7, 0xff00, 7, 0xff00, 7)) + +/* +** dupq_65536d_u16: +** mov z0\.d, #65536 +** ret +*/ +TEST_UNIFORM_Z (dupq_65536d_u16, svuint16_t, + z0 = svdupq_n_u16 (0, 1, 0, 0, 0, 1, 0, 0), + z0 = svdupq_u16 (0, 1, 0, 0, 0, 1, 0, 0)) + +/* +** dupq_m2d_u16: +** mov z0\.d, #-2 +** ret +*/ +TEST_UNIFORM_Z (dupq_m2d_u16, svuint16_t, + z0 = svdupq_n_u16 (-2, -1, -1, -1, -2, -1, -1, -1), + z0 = svdupq_u16 (-2, -1, -1, -1, -2, -1, -1, -1)) + +/* +** dupq_4ddb_u16: +** movi v([0-9]+)\.2d, 0xff0000ffff00ff +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_4ddb_u16, svuint16_t, + z0 = svdupq_n_u16 (0xff, -1, 0, 0xff, 0xff, -1, 0, 0xff), + z0 = svdupq_u16 (0xff, -1, 0, 0xff, 0xff, -1, 0, 0xff)) + + +/* +** dupq_a093s_u16: +** mov (w[0-9]+), 41107 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_a093s_u16, svuint16_t, + z0 = svdupq_n_u16 (0xa093, 0, 0xa093, 0, 0xa093, 0, 0xa093, 0), + z0 = svdupq_u16 (0xa093, 0, 0xa093, 0, 0xa093, 0, 0xa093, 0)); + +/* +** dupq_pool_u16: +** ... +** ld1rqh z0\.h, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_u16, svuint16_t, + z0 = svdupq_n_u16 (4, 10, 9, 77, 52, 22, 19, 50), + z0 = svdupq_u16 (4, 10, 9, 77, 52, 22, 19, 50)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u32.c new file mode 100644 index 00000000000..3669bf8a123 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u32.c @@ -0,0 +1,61 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_12800d_u32: +** mov z0\.d, #12800 +** ret +*/ +TEST_UNIFORM_Z (dupq_12800d_u32, svuint32_t, + z0 = svdupq_n_u32 (12800, 0, 12800, 0), + z0 = svdupq_u32 (12800, 0, 12800, 0)) + +/* +** dupq_fffffffed_u32: +** mov z0\.d, #4294967294 +** ret +*/ +TEST_UNIFORM_Z (dupq_fffffffed_u32, svuint32_t, + z0 = svdupq_n_u32 (-2, 0, -2, 0), + z0 = svdupq_u32 (-2, 0, -2, 0)) + +/* +** dupq_ff00ffffff00d_u32: +** movi v([0-9]+)\.2d, 0xff00ffffff00 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_ff00ffffff00d_u32, svuint32_t, + z0 = svdupq_n_u32 (-256, 0xff00, -256, 0xff00), + z0 = svdupq_u32 (-256, 0xff00, -256, 0xff00)) + +/* +** dupq_fedcd_u32: +** mov (x[0-9]+), 65244 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_fedcd_u32, svuint32_t, + z0 = svdupq_n_u32 (0xfedc, 0, 0xfedc, 0), + z0 = svdupq_u32 (0xfedc, 0, 0xfedc, 0)) + +/* +** dupq_1357ud_u32: +** mov (x[0-9]+), 21264383082496 +** mov z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_1357ud_u32, svuint32_t, + z0 = svdupq_n_u32 (0, 0x1357, 0, 0x1357), + z0 = svdupq_u32 (0, 0x1357, 0, 0x1357)) + +/* +** dupq_pool_u32: +** ... +** ld1rqw z0\.s, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_u32, svuint32_t, + z0 = svdupq_n_u32 (4, 10, 9, 77), + z0 = svdupq_u32 (4, 10, 9, 77)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u64.c new file mode 100644 index 00000000000..cb655a15aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_pool_u64: +** ... +** ld1rqd z0\.d, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_u64, svuint64_t, + z0 = svdupq_n_u64 (4, 10), + z0 = svdupq_u64 (4, 10)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u8.c new file mode 100644 index 00000000000..8b40c2b41f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dupq_u8.c @@ -0,0 +1,99 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** dupq_54h_u8: +** mov z0\.h, #54 +** ret +*/ +TEST_UNIFORM_Z (dupq_54h_u8, svuint8_t, + z0 = svdupq_n_u8 (54, 0, 54, 0, 54, 0, 54, 0, + 54, 0, 54, 0, 54, 0, 54, 0), + z0 = svdupq_u8 (54, 0, 54, 0, 54, 0, 54, 0, + 54, 0, 54, 0, 54, 0, 54, 0)) + +/* +** dupq_2560h_u8: +** mov z0\.h, #2560 +** ret +*/ +TEST_UNIFORM_Z (dupq_2560h_u8, svuint8_t, + z0 = svdupq_n_u8 (0, 10, 0, 10, 0, 10, 0, 10, + 0, 10, 0, 10, 0, 10, 0, 10), + z0 = svdupq_u8 (0, 10, 0, 10, 0, 10, 0, 10, + 0, 10, 0, 10, 0, 10, 0, 10)) + +/* +** dupq_5120s_u8: +** mov z0\.s, #5120 +** ret +*/ +TEST_UNIFORM_Z (dupq_5120s_u8, svuint8_t, + z0 = svdupq_n_u8 (0, 20, 0, 0, 0, 20, 0, 0, + 0, 20, 0, 0, 0, 20, 0, 0), + z0 = svdupq_u8 (0, 20, 0, 0, 0, 20, 0, 0, + 0, 20, 0, 0, 0, 20, 0, 0)) + +/* +** dupq_1ff00s_u8: +** mov z0\.s, #130816 +** ret +*/ +TEST_UNIFORM_Z (dupq_1ff00s_u8, svuint8_t, + z0 = svdupq_n_u8 (0, -1, 1, 0, 0, -1, 1, 0, + 0, -1, 1, 0, 0, -1, 1, 0), + z0 = svdupq_u8 (0, -1, 1, 0, 0, -1, 1, 0, + 0, -1, 1, 0, 0, -1, 1, 0)) + +/* +** dupq_96db_u8: +** movi v([0-9]+)\.2d, 0xff0000ff00ffff00 +** dup z0\.q, z\1\.q\[0\] +** ret +*/ +TEST_UNIFORM_Z (dupq_96db_u8, svuint8_t, + z0 = svdupq_n_u8 (0, -1, -1, 0, -1, 0, 0, -1, + 0, -1, -1, 0, -1, 0, 0, -1), + z0 = svdupq_u8 (0, -1, -1, 0, -1, 0, 0, -1, + 0, -1, -1, 0, -1, 0, 0, -1)) + +/* +** dupq_7755h_u8: +** mov (w[0-9]+), 21879 +** mov z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_7755h_u8, svuint8_t, + z0 = svdupq_n_u8 (0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55), + z0 = svdupq_u8 (0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55, + 0x77, 0x55, 0x77, 0x55)) + +/* +** dupq_729a0000s_u8: +** mov (w[0-9]+), 1922695168 +** mov z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (dupq_729a0000s_u8, svuint8_t, + z0 = svdupq_n_u8 (0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72, + 0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72), + z0 = svdupq_u8 (0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72, + 0, 0, 0x9a, 0x72, 0, 0, 0x9a, 0x72)) + +/* +** dupq_pool_u8: +** ... +** ld1rqb z0\.b, p[0-7]/z, \[x[0-9]+\] +** ret +*/ +TEST_UNIFORM_Z (dupq_pool_u8, svuint8_t, + z0 = svdupq_n_u8 (4, 10, 9, 77, 52, 22, 19, 50, + -1, 32, 44, 17, 23, 99, 53, 39), + z0 = svdupq_u8 (4, 10, 9, 77, 52, 22, 19, 50, + -1, 32, 44, 17, 23, 99, 53, 39)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_b.c new file mode 100644 index 00000000000..961ae84c007 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_b_z_tied1: +** eor p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (eor_b_z_tied1, + p0 = sveor_b_z (p3, p0, p1), + p0 = sveor_z (p3, p0, p1)) + +/* +** eor_b_z_tied2: +** eor p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (eor_b_z_tied2, + p0 = sveor_b_z (p3, p1, p0), + p0 = sveor_z (p3, p1, p0)) + +/* +** eor_b_z_untied: +** eor p0\.b, p3/z, (p1\.b, p2\.b|p2\.b, p1\.b) +** ret +*/ +TEST_UNIFORM_P (eor_b_z_untied, + p0 = sveor_b_z (p3, p1, p2), + p0 = sveor_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c new file mode 100644 index 00000000000..7cf73609a1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c @@ -0,0 +1,376 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_s16_m_tied1: +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_s16_m_tied1, svint16_t, + z0 = sveor_s16_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_s16_m_tied2, svint16_t, + z0 = sveor_s16_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_s16_m_untied: +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (eor_s16_m_untied, svint16_t, + z0 = sveor_s16_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_m_tied1, svint16_t, int16_t, + z0 = sveor_n_s16_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_m_untied, svint16_t, int16_t, + z0 = sveor_n_s16_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_m_tied1, svint16_t, + z0 = sveor_n_s16_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_m_untied, svint16_t, + z0 = sveor_n_s16_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_s16_m: +** mov (z[0-9]+\.h), #-2 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_s16_m, svint16_t, + z0 = sveor_n_s16_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_s16_z_tied1, svint16_t, + z0 = sveor_s16_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_s16_z_tied2, svint16_t, + z0 = sveor_s16_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_s16_z_untied, svint16_t, + z0 = sveor_s16_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_z_tied1, svint16_t, int16_t, + z0 = sveor_n_s16_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_z_untied, svint16_t, int16_t, + z0 = sveor_n_s16_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_z_tied1, svint16_t, + z0 = sveor_n_s16_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_z_untied, svint16_t, + z0 = sveor_n_s16_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_s16_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s16_x_tied1, svint16_t, + z0 = sveor_s16_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_s16_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s16_x_tied2, svint16_t, + z0 = sveor_s16_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_s16_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s16_x_untied, svint16_t, + z0 = sveor_s16_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_s16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_x_tied1, svint16_t, int16_t, + z0 = sveor_n_s16_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_s16_x_untied: +** mov (z[0-9]+)\.h, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s16_x_untied, svint16_t, int16_t, + z0 = sveor_n_s16_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_s16_x_tied1: +** eor z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_x_tied1, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_s16_x_untied: +** movprfx z0, z1 +** eor z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s16_x_untied, svint16_t, + z0 = sveor_n_s16_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_s16_x: +** eor z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_s16_x: +** eor z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_s16_x: +** eor z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_s16_x: +** eor z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* +** eor_257_s16_x: +** eor z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (eor_257_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_s16_x: +** eor z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_s16_x: +** eor z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_s16_x: +** eor z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_s16_x: +** eor z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_s16_x: +** eor z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_s16_x: +** eor z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_s16_x: +** eor z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_s16_x: +** eor z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_s16_x: +** eor z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_s16_x: +** mov (z[0-9]+)\.h, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_s16_x, svint16_t, + z0 = sveor_n_s16_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s32.c new file mode 100644 index 00000000000..d5aecb20133 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s32.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_s32_m_tied1: +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_s32_m_tied1, svint32_t, + z0 = sveor_s32_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_s32_m_tied2, svint32_t, + z0 = sveor_s32_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_s32_m_untied: +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (eor_s32_m_untied, svint32_t, + z0 = sveor_s32_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_m_tied1, svint32_t, int32_t, + z0 = sveor_n_s32_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_m_untied, svint32_t, int32_t, + z0 = sveor_n_s32_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_m_tied1, svint32_t, + z0 = sveor_n_s32_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_m_untied, svint32_t, + z0 = sveor_n_s32_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_s32_m: +** mov (z[0-9]+\.s), #-2 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_s32_m, svint32_t, + z0 = sveor_n_s32_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_s32_z_tied1, svint32_t, + z0 = sveor_s32_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_s32_z_tied2, svint32_t, + z0 = sveor_s32_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_s32_z_untied, svint32_t, + z0 = sveor_s32_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_z_tied1, svint32_t, int32_t, + z0 = sveor_n_s32_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_z_untied, svint32_t, int32_t, + z0 = sveor_n_s32_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_z_tied1, svint32_t, + z0 = sveor_n_s32_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_z_untied, svint32_t, + z0 = sveor_n_s32_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_s32_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s32_x_tied1, svint32_t, + z0 = sveor_s32_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_s32_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s32_x_tied2, svint32_t, + z0 = sveor_s32_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_s32_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s32_x_untied, svint32_t, + z0 = sveor_s32_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_s32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_x_tied1, svint32_t, int32_t, + z0 = sveor_n_s32_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_s32_x_untied: +** mov (z[0-9]+)\.s, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s32_x_untied, svint32_t, int32_t, + z0 = sveor_n_s32_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_s32_x_tied1: +** eor z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_x_tied1, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_s32_x_untied: +** movprfx z0, z1 +** eor z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s32_x_untied, svint32_t, + z0 = sveor_n_s32_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_s32_x: +** eor z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_s32_x: +** eor z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_s32_x: +** eor z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_s32_x: +** eor z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (eor_257_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_s32_x: +** eor z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_s32_x: +** eor z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_s32_x: +** eor z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_s32_x: +** eor z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_s32_x: +** eor z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_s32_x: +** eor z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_s32_x: +** eor z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_s32_x: +** eor z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_s32_x: +** eor z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_s32_x: +** mov (z[0-9]+)\.s, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_s32_x, svint32_t, + z0 = sveor_n_s32_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s64.c new file mode 100644 index 00000000000..157128974bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s64.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_s64_m_tied1: +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_s64_m_tied1, svint64_t, + z0 = sveor_s64_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_s64_m_tied2, svint64_t, + z0 = sveor_s64_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_s64_m_untied: +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (eor_s64_m_untied, svint64_t, + z0 = sveor_s64_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_m_tied1, svint64_t, int64_t, + z0 = sveor_n_s64_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_m_untied, svint64_t, int64_t, + z0 = sveor_n_s64_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_m_tied1, svint64_t, + z0 = sveor_n_s64_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_m_untied, svint64_t, + z0 = sveor_n_s64_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_s64_m: +** mov (z[0-9]+\.d), #-2 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_s64_m, svint64_t, + z0 = sveor_n_s64_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_s64_z_tied1, svint64_t, + z0 = sveor_s64_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_s64_z_tied2, svint64_t, + z0 = sveor_s64_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_s64_z_untied, svint64_t, + z0 = sveor_s64_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_z_tied1, svint64_t, int64_t, + z0 = sveor_n_s64_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_z_untied, svint64_t, int64_t, + z0 = sveor_n_s64_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_z_tied1, svint64_t, + z0 = sveor_n_s64_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_z_untied, svint64_t, + z0 = sveor_n_s64_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_s64_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s64_x_tied1, svint64_t, + z0 = sveor_s64_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_s64_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s64_x_tied2, svint64_t, + z0 = sveor_s64_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_s64_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s64_x_untied, svint64_t, + z0 = sveor_s64_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_x_tied1, svint64_t, int64_t, + z0 = sveor_n_s64_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_s64_x_untied, svint64_t, int64_t, + z0 = sveor_n_s64_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_s64_x_tied1: +** eor z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_x_tied1, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_s64_x_untied: +** movprfx z0, z1 +** eor z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s64_x_untied, svint64_t, + z0 = sveor_n_s64_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_s64_x: +** eor z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_s64_x: +** eor z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_s64_x: +** eor z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_s64_x: +** eor z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (eor_257_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_s64_x: +** eor z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_s64_x: +** eor z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_s64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_s64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_s64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_s64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_s64_x: +** eor z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_s64_x: +** eor z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_s64_x: +** eor z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_s64_x: +** mov (z[0-9]+\.d), #5 +** eor z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_s64_x, svint64_t, + z0 = sveor_n_s64_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c new file mode 100644 index 00000000000..083ac2dde06 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c @@ -0,0 +1,296 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_s8_m_tied1: +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_s8_m_tied1, svint8_t, + z0 = sveor_s8_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_s8_m_tied2, svint8_t, + z0 = sveor_s8_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_s8_m_untied: +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (eor_s8_m_untied, svint8_t, + z0 = sveor_s8_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_m_tied1, svint8_t, int8_t, + z0 = sveor_n_s8_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_m_untied, svint8_t, int8_t, + z0 = sveor_n_s8_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_m_tied1, svint8_t, + z0 = sveor_n_s8_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_m_untied, svint8_t, + z0 = sveor_n_s8_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_s8_m: +** mov (z[0-9]+\.b), #-2 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_s8_m, svint8_t, + z0 = sveor_n_s8_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_s8_z_tied1, svint8_t, + z0 = sveor_s8_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_s8_z_tied2, svint8_t, + z0 = sveor_s8_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_s8_z_untied, svint8_t, + z0 = sveor_s8_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_z_tied1, svint8_t, int8_t, + z0 = sveor_n_s8_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_z_untied, svint8_t, int8_t, + z0 = sveor_n_s8_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_z_tied1, svint8_t, + z0 = sveor_n_s8_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_z_untied, svint8_t, + z0 = sveor_n_s8_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_s8_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s8_x_tied1, svint8_t, + z0 = sveor_s8_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_s8_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s8_x_tied2, svint8_t, + z0 = sveor_s8_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_s8_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_s8_x_untied, svint8_t, + z0 = sveor_s8_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_s8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_x_tied1, svint8_t, int8_t, + z0 = sveor_n_s8_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_s8_x_untied: +** mov (z[0-9]+)\.b, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_s8_x_untied, svint8_t, int8_t, + z0 = sveor_n_s8_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_s8_x_tied1: +** eor z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_x_tied1, svint8_t, + z0 = sveor_n_s8_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_s8_x_untied: +** movprfx z0, z1 +** eor z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_s8_x_untied, svint8_t, + z0 = sveor_n_s8_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_s8_x: +** eor z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_s8_x: +** eor z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_s8_x: +** mov (z[0-9]+)\.b, #-1 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_255_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_m127_s8_x: +** eor z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_s8_x: +** eor z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_5_s8_x: +** mov (z[0-9]+)\.b, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_s8_x, svint8_t, + z0 = sveor_n_s8_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c new file mode 100644 index 00000000000..40b43a5f89b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c @@ -0,0 +1,376 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_u16_m_tied1: +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_u16_m_tied1, svuint16_t, + z0 = sveor_u16_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_u16_m_tied2, svuint16_t, + z0 = sveor_u16_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_u16_m_untied: +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (eor_u16_m_untied, svuint16_t, + z0 = sveor_u16_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = sveor_n_u16_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = sveor_n_u16_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_m_tied1, svuint16_t, + z0 = sveor_n_u16_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_m_untied, svuint16_t, + z0 = sveor_n_u16_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_u16_m: +** mov (z[0-9]+\.h), #-2 +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_u16_m, svuint16_t, + z0 = sveor_n_u16_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_u16_z_tied1, svuint16_t, + z0 = sveor_u16_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (eor_u16_z_tied2, svuint16_t, + z0 = sveor_u16_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_u16_z_untied, svuint16_t, + z0 = sveor_u16_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = sveor_n_u16_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = sveor_n_u16_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** eor z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_z_tied1, svuint16_t, + z0 = sveor_n_u16_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** eor z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** eor z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_z_untied, svuint16_t, + z0 = sveor_n_u16_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_u16_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u16_x_tied1, svuint16_t, + z0 = sveor_u16_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_u16_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u16_x_tied2, svuint16_t, + z0 = sveor_u16_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_u16_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u16_x_untied, svuint16_t, + z0 = sveor_u16_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_u16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = sveor_n_u16_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_u16_x_untied: +** mov (z[0-9]+)\.h, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = sveor_n_u16_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_u16_x_tied1: +** eor z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_x_tied1, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_u16_x_untied: +** movprfx z0, z1 +** eor z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u16_x_untied, svuint16_t, + z0 = sveor_n_u16_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_u16_x: +** eor z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_u16_x: +** eor z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_u16_x: +** eor z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_u16_x: +** eor z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* +** eor_257_u16_x: +** eor z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (eor_257_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_u16_x: +** eor z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_u16_x: +** eor z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_u16_x: +** eor z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_u16_x: +** eor z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_u16_x: +** eor z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_u16_x: +** eor z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_u16_x: +** eor z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_u16_x: +** eor z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_u16_x: +** eor z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_u16_x: +** mov (z[0-9]+)\.h, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_u16_x, svuint16_t, + z0 = sveor_n_u16_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u32.c new file mode 100644 index 00000000000..8e46d08cacc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u32.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_u32_m_tied1: +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_u32_m_tied1, svuint32_t, + z0 = sveor_u32_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_u32_m_tied2, svuint32_t, + z0 = sveor_u32_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_u32_m_untied: +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (eor_u32_m_untied, svuint32_t, + z0 = sveor_u32_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = sveor_n_u32_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = sveor_n_u32_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_m_tied1, svuint32_t, + z0 = sveor_n_u32_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_m_untied, svuint32_t, + z0 = sveor_n_u32_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_u32_m: +** mov (z[0-9]+\.s), #-2 +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_u32_m, svuint32_t, + z0 = sveor_n_u32_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_u32_z_tied1, svuint32_t, + z0 = sveor_u32_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (eor_u32_z_tied2, svuint32_t, + z0 = sveor_u32_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_u32_z_untied, svuint32_t, + z0 = sveor_u32_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = sveor_n_u32_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = sveor_n_u32_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** eor z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_z_tied1, svuint32_t, + z0 = sveor_n_u32_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** eor z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** eor z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_z_untied, svuint32_t, + z0 = sveor_n_u32_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_u32_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u32_x_tied1, svuint32_t, + z0 = sveor_u32_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_u32_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u32_x_tied2, svuint32_t, + z0 = sveor_u32_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_u32_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u32_x_untied, svuint32_t, + z0 = sveor_u32_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_u32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = sveor_n_u32_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_u32_x_untied: +** mov (z[0-9]+)\.s, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = sveor_n_u32_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_u32_x_tied1: +** eor z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_x_tied1, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_u32_x_untied: +** movprfx z0, z1 +** eor z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u32_x_untied, svuint32_t, + z0 = sveor_n_u32_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_u32_x: +** eor z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_u32_x: +** eor z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_u32_x: +** eor z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_u32_x: +** eor z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (eor_257_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_u32_x: +** eor z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_u32_x: +** eor z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_u32_x: +** eor z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_u32_x: +** eor z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_u32_x: +** eor z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_u32_x: +** eor z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_u32_x: +** eor z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_u32_x: +** eor z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_u32_x: +** eor z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_u32_x: +** mov (z[0-9]+)\.s, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_u32_x, svuint32_t, + z0 = sveor_n_u32_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u64.c new file mode 100644 index 00000000000..a82398f919a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u64.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_u64_m_tied1: +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_u64_m_tied1, svuint64_t, + z0 = sveor_u64_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_u64_m_tied2, svuint64_t, + z0 = sveor_u64_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_u64_m_untied: +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (eor_u64_m_untied, svuint64_t, + z0 = sveor_u64_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = sveor_n_u64_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = sveor_n_u64_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_m_tied1, svuint64_t, + z0 = sveor_n_u64_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_m_untied, svuint64_t, + z0 = sveor_n_u64_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_u64_m: +** mov (z[0-9]+\.d), #-2 +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_u64_m, svuint64_t, + z0 = sveor_n_u64_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_u64_z_tied1, svuint64_t, + z0 = sveor_u64_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (eor_u64_z_tied2, svuint64_t, + z0 = sveor_u64_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_u64_z_untied, svuint64_t, + z0 = sveor_u64_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = sveor_n_u64_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = sveor_n_u64_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** eor z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_z_tied1, svuint64_t, + z0 = sveor_n_u64_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** eor z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** eor z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_z_untied, svuint64_t, + z0 = sveor_n_u64_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_u64_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u64_x_tied1, svuint64_t, + z0 = sveor_u64_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_u64_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u64_x_tied2, svuint64_t, + z0 = sveor_u64_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_u64_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u64_x_untied, svuint64_t, + z0 = sveor_u64_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = sveor_n_u64_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** eor z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = sveor_n_u64_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_u64_x_tied1: +** eor z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_x_tied1, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_u64_x_untied: +** movprfx z0, z1 +** eor z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u64_x_untied, svuint64_t, + z0 = sveor_n_u64_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_u64_x: +** eor z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_u64_x: +** eor z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_u64_x: +** eor z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (eor_255_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_256_u64_x: +** eor z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (eor_256_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 256), + z0 = sveor_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (eor_257_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 257), + z0 = sveor_x (p0, z0, 257)) + +/* +** eor_512_u64_x: +** eor z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (eor_512_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 512), + z0 = sveor_x (p0, z0, 512)) + +/* +** eor_65280_u64_x: +** eor z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (eor_65280_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 0xff00), + z0 = sveor_x (p0, z0, 0xff00)) + +/* +** eor_m127_u64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_u64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_m255_u64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (eor_m255_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -255), + z0 = sveor_x (p0, z0, -255)) + +/* +** eor_m256_u64_x: +** eor z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (eor_m256_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -256), + z0 = sveor_x (p0, z0, -256)) + +/* +** eor_m257_u64_x: +** eor z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (eor_m257_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -257), + z0 = sveor_x (p0, z0, -257)) + +/* +** eor_m512_u64_x: +** eor z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (eor_m512_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -512), + z0 = sveor_x (p0, z0, -512)) + +/* +** eor_m32768_u64_x: +** eor z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (eor_m32768_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, -0x8000), + z0 = sveor_x (p0, z0, -0x8000)) + +/* +** eor_5_u64_x: +** mov (z[0-9]+\.d), #5 +** eor z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_u64_x, svuint64_t, + z0 = sveor_n_u64_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c new file mode 100644 index 00000000000..006637699e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c @@ -0,0 +1,296 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eor_u8_m_tied1: +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_u8_m_tied1, svuint8_t, + z0 = sveor_u8_m (p0, z0, z1), + z0 = sveor_m (p0, z0, z1)) + +/* +** eor_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_u8_m_tied2, svuint8_t, + z0 = sveor_u8_m (p0, z1, z0), + z0 = sveor_m (p0, z1, z0)) + +/* +** eor_u8_m_untied: +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (eor_u8_m_untied, svuint8_t, + z0 = sveor_u8_m (p0, z1, z2), + z0 = sveor_m (p0, z1, z2)) + +/* +** eor_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = sveor_n_u8_m (p0, z0, x0), + z0 = sveor_m (p0, z0, x0)) + +/* +** eor_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = sveor_n_u8_m (p0, z1, x0), + z0 = sveor_m (p0, z1, x0)) + +/* +** eor_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_m_tied1, svuint8_t, + z0 = sveor_n_u8_m (p0, z0, 1), + z0 = sveor_m (p0, z0, 1)) + +/* +** eor_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_m_untied, svuint8_t, + z0 = sveor_n_u8_m (p0, z1, 1), + z0 = sveor_m (p0, z1, 1)) + +/* +** eor_m2_u8_m: +** mov (z[0-9]+\.b), #-2 +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_m2_u8_m, svuint8_t, + z0 = sveor_n_u8_m (p0, z0, -2), + z0 = sveor_m (p0, z0, -2)) + +/* +** eor_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_u8_z_tied1, svuint8_t, + z0 = sveor_u8_z (p0, z0, z1), + z0 = sveor_z (p0, z0, z1)) + +/* +** eor_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (eor_u8_z_tied2, svuint8_t, + z0 = sveor_u8_z (p0, z1, z0), + z0 = sveor_z (p0, z1, z0)) + +/* +** eor_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_u8_z_untied, svuint8_t, + z0 = sveor_u8_z (p0, z1, z2), + z0 = sveor_z (p0, z1, z2)) + +/* +** eor_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = sveor_n_u8_z (p0, z0, x0), + z0 = sveor_z (p0, z0, x0)) + +/* +** eor_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = sveor_n_u8_z (p0, z1, x0), + z0 = sveor_z (p0, z1, x0)) + +/* +** eor_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** eor z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_z_tied1, svuint8_t, + z0 = sveor_n_u8_z (p0, z0, 1), + z0 = sveor_z (p0, z0, 1)) + +/* +** eor_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** eor z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** eor z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_z_untied, svuint8_t, + z0 = sveor_n_u8_z (p0, z1, 1), + z0 = sveor_z (p0, z1, 1)) + +/* +** eor_u8_x_tied1: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u8_x_tied1, svuint8_t, + z0 = sveor_u8_x (p0, z0, z1), + z0 = sveor_x (p0, z0, z1)) + +/* +** eor_u8_x_tied2: +** eor z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u8_x_tied2, svuint8_t, + z0 = sveor_u8_x (p0, z1, z0), + z0 = sveor_x (p0, z1, z0)) + +/* +** eor_u8_x_untied: +** eor z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_u8_x_untied, svuint8_t, + z0 = sveor_u8_x (p0, z1, z2), + z0 = sveor_x (p0, z1, z2)) + +/* +** eor_w0_u8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = sveor_n_u8_x (p0, z0, x0), + z0 = sveor_x (p0, z0, x0)) + +/* +** eor_w0_u8_x_untied: +** mov (z[0-9]+)\.b, w0 +** eor z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (eor_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = sveor_n_u8_x (p0, z1, x0), + z0 = sveor_x (p0, z1, x0)) + +/* +** eor_1_u8_x_tied1: +** eor z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_x_tied1, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, 1), + z0 = sveor_x (p0, z0, 1)) + +/* +** eor_1_u8_x_untied: +** movprfx z0, z1 +** eor z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (eor_1_u8_x_untied, svuint8_t, + z0 = sveor_n_u8_x (p0, z1, 1), + z0 = sveor_x (p0, z1, 1)) + +/* +** eor_127_u8_x: +** eor z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (eor_127_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, 127), + z0 = sveor_x (p0, z0, 127)) + +/* +** eor_128_u8_x: +** eor z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_128_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, 128), + z0 = sveor_x (p0, z0, 128)) + +/* +** eor_255_u8_x: +** mov (z[0-9]+)\.b, #-1 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_255_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, 255), + z0 = sveor_x (p0, z0, 255)) + +/* +** eor_m127_u8_x: +** eor z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (eor_m127_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, -127), + z0 = sveor_x (p0, z0, -127)) + +/* +** eor_m128_u8_x: +** eor z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (eor_m128_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, -128), + z0 = sveor_x (p0, z0, -128)) + +/* +** eor_5_u8_x: +** mov (z[0-9]+)\.b, #5 +** eor z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (eor_5_u8_x, svuint8_t, + z0 = sveor_n_u8_x (p0, z0, 5), + z0 = sveor_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s16.c new file mode 100644 index 00000000000..0675d7ed9d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_s16: +** eorv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (eorv_x0_s16, int16_t, svint16_t, + x0 = sveorv_s16 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s32.c new file mode 100644 index 00000000000..9c0c1089f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_s32: +** eorv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (eorv_x0_s32, int32_t, svint32_t, + x0 = sveorv_s32 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s64.c new file mode 100644 index 00000000000..7a474556c17 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_s64: +** eorv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (eorv_x0_s64, int64_t, svint64_t, + x0 = sveorv_s64 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s8.c new file mode 100644 index 00000000000..43f056d3a1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_s8: +** eorv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (eorv_x0_s8, int8_t, svint8_t, + x0 = sveorv_s8 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u16.c new file mode 100644 index 00000000000..5f7836db4d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_u16: +** eorv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (eorv_x0_u16, uint16_t, svuint16_t, + x0 = sveorv_u16 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u32.c new file mode 100644 index 00000000000..f112a0dc2a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_u32: +** eorv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (eorv_x0_u32, uint32_t, svuint32_t, + x0 = sveorv_u32 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u64.c new file mode 100644 index 00000000000..5f8b8f86b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_u64: +** eorv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (eorv_x0_u64, uint64_t, svuint64_t, + x0 = sveorv_u64 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u8.c new file mode 100644 index 00000000000..eed4d49150d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eorv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** eorv_x0_u8: +** eorv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (eorv_x0_u8, uint8_t, svuint8_t, + x0 = sveorv_u8 (p0, z0), + x0 = sveorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f16.c new file mode 100644 index 00000000000..5a5411e46cb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** expa_f16_tied1: +** fexpa z0\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (expa_f16_tied1, svfloat16_t, svuint16_t, + z0_res = svexpa_f16 (z0), + z0_res = svexpa (z0)) + +/* +** expa_f16_untied: +** fexpa z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (expa_f16_untied, svfloat16_t, svuint16_t, + z0 = svexpa_f16 (z4), + z0 = svexpa (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f32.c new file mode 100644 index 00000000000..4ded1c5756e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** expa_f32_tied1: +** fexpa z0\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (expa_f32_tied1, svfloat32_t, svuint32_t, + z0_res = svexpa_f32 (z0), + z0_res = svexpa (z0)) + +/* +** expa_f32_untied: +** fexpa z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (expa_f32_untied, svfloat32_t, svuint32_t, + z0 = svexpa_f32 (z4), + z0 = svexpa (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f64.c new file mode 100644 index 00000000000..c31f9ccb5b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/expa_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** expa_f64_tied1: +** fexpa z0\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (expa_f64_tied1, svfloat64_t, svuint64_t, + z0_res = svexpa_f64 (z0), + z0_res = svexpa (z0)) + +/* +** expa_f64_untied: +** fexpa z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (expa_f64_untied, svfloat64_t, svuint64_t, + z0 = svexpa_f64 (z4), + z0 = svexpa (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f16.c new file mode 100644 index 00000000000..d8edccb9fa1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f16.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_f16_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f16_tied1, svfloat16_t, + z0 = svext_f16 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f16_tied2, svfloat16_t, + z0 = svext_f16 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_f16_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f16_untied, svfloat16_t, + z0 = svext_f16 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_f16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (ext_1_f16, svfloat16_t, + z0 = svext_f16 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_f16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_2_f16, svfloat16_t, + z0 = svext_f16 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_f16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #6 +** ret +*/ +TEST_UNIFORM_Z (ext_3_f16, svfloat16_t, + z0 = svext_f16 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_127_f16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #254 +** ret +*/ +TEST_UNIFORM_Z (ext_127_f16, svfloat16_t, + z0 = svext_f16 (z1, z2, 127), + z0 = svext (z1, z2, 127)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f32.c new file mode 100644 index 00000000000..c00ea06fb82 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f32.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_f32_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f32_tied1, svfloat32_t, + z0 = svext_f32 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f32_tied2, svfloat32_t, + z0 = svext_f32 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_f32_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f32_untied, svfloat32_t, + z0 = svext_f32 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_f32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_1_f32, svfloat32_t, + z0 = svext_f32 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_f32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_2_f32, svfloat32_t, + z0 = svext_f32 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_f32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #12 +** ret +*/ +TEST_UNIFORM_Z (ext_3_f32, svfloat32_t, + z0 = svext_f32 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_63_f32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #252 +** ret +*/ +TEST_UNIFORM_Z (ext_63_f32, svfloat32_t, + z0 = svext_f32 (z1, z2, 63), + z0 = svext (z1, z2, 63)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f64.c new file mode 100644 index 00000000000..af72870ca21 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_f64.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_f64_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f64_tied1, svfloat64_t, + z0 = svext_f64 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_f64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f64_tied2, svfloat64_t, + z0 = svext_f64 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_f64_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_f64_untied, svfloat64_t, + z0 = svext_f64 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_f64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_1_f64, svfloat64_t, + z0 = svext_f64 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_f64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #16 +** ret +*/ +TEST_UNIFORM_Z (ext_2_f64, svfloat64_t, + z0 = svext_f64 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_f64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #24 +** ret +*/ +TEST_UNIFORM_Z (ext_3_f64, svfloat64_t, + z0 = svext_f64 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_31_f64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #248 +** ret +*/ +TEST_UNIFORM_Z (ext_31_f64, svfloat64_t, + z0 = svext_f64 (z1, z2, 31), + z0 = svext (z1, z2, 31)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s16.c new file mode 100644 index 00000000000..a7c4484ac24 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s16.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_s16_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s16_tied1, svint16_t, + z0 = svext_s16 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_s16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s16_tied2, svint16_t, + z0 = svext_s16 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_s16_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s16_untied, svint16_t, + z0 = svext_s16 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_s16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (ext_1_s16, svint16_t, + z0 = svext_s16 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_s16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_2_s16, svint16_t, + z0 = svext_s16 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_s16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #6 +** ret +*/ +TEST_UNIFORM_Z (ext_3_s16, svint16_t, + z0 = svext_s16 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_127_s16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #254 +** ret +*/ +TEST_UNIFORM_Z (ext_127_s16, svint16_t, + z0 = svext_s16 (z1, z2, 127), + z0 = svext (z1, z2, 127)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s32.c new file mode 100644 index 00000000000..68242a9ec55 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s32.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_s32_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s32_tied1, svint32_t, + z0 = svext_s32 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s32_tied2, svint32_t, + z0 = svext_s32 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_s32_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s32_untied, svint32_t, + z0 = svext_s32 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_s32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_1_s32, svint32_t, + z0 = svext_s32 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_s32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_2_s32, svint32_t, + z0 = svext_s32 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_s32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #12 +** ret +*/ +TEST_UNIFORM_Z (ext_3_s32, svint32_t, + z0 = svext_s32 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_63_s32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #252 +** ret +*/ +TEST_UNIFORM_Z (ext_63_s32, svint32_t, + z0 = svext_s32 (z1, z2, 63), + z0 = svext (z1, z2, 63)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s64.c new file mode 100644 index 00000000000..8bdbd0561fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s64.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_s64_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s64_tied1, svint64_t, + z0 = svext_s64 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_s64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s64_tied2, svint64_t, + z0 = svext_s64 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_s64_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s64_untied, svint64_t, + z0 = svext_s64 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_s64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_1_s64, svint64_t, + z0 = svext_s64 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_s64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #16 +** ret +*/ +TEST_UNIFORM_Z (ext_2_s64, svint64_t, + z0 = svext_s64 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_s64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #24 +** ret +*/ +TEST_UNIFORM_Z (ext_3_s64, svint64_t, + z0 = svext_s64 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_31_s64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #248 +** ret +*/ +TEST_UNIFORM_Z (ext_31_s64, svint64_t, + z0 = svext_s64 (z1, z2, 31), + z0 = svext (z1, z2, 31)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s8.c new file mode 100644 index 00000000000..52490f00e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_s8.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_s8_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s8_tied1, svint8_t, + z0 = svext_s8 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_s8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s8_tied2, svint8_t, + z0 = svext_s8 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_s8_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_s8_untied, svint8_t, + z0 = svext_s8 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_s8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (ext_1_s8, svint8_t, + z0 = svext_s8 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_s8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (ext_2_s8, svint8_t, + z0 = svext_s8 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_s8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #3 +** ret +*/ +TEST_UNIFORM_Z (ext_3_s8, svint8_t, + z0 = svext_s8 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_255_s8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (ext_255_s8, svint8_t, + z0 = svext_s8 (z1, z2, 255), + z0 = svext (z1, z2, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u16.c new file mode 100644 index 00000000000..dc7574ffa2c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u16.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_u16_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u16_tied1, svuint16_t, + z0 = svext_u16 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_u16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u16_tied2, svuint16_t, + z0 = svext_u16 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_u16_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u16_untied, svuint16_t, + z0 = svext_u16 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_u16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (ext_1_u16, svuint16_t, + z0 = svext_u16 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_u16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_2_u16, svuint16_t, + z0 = svext_u16 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_u16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #6 +** ret +*/ +TEST_UNIFORM_Z (ext_3_u16, svuint16_t, + z0 = svext_u16 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_127_u16: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #254 +** ret +*/ +TEST_UNIFORM_Z (ext_127_u16, svuint16_t, + z0 = svext_u16 (z1, z2, 127), + z0 = svext (z1, z2, 127)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u32.c new file mode 100644 index 00000000000..0d417fc43b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u32.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_u32_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u32_tied1, svuint32_t, + z0 = svext_u32 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u32_tied2, svuint32_t, + z0 = svext_u32 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_u32_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u32_untied, svuint32_t, + z0 = svext_u32 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_u32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #4 +** ret +*/ +TEST_UNIFORM_Z (ext_1_u32, svuint32_t, + z0 = svext_u32 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_u32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_2_u32, svuint32_t, + z0 = svext_u32 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_u32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #12 +** ret +*/ +TEST_UNIFORM_Z (ext_3_u32, svuint32_t, + z0 = svext_u32 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_63_u32: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #252 +** ret +*/ +TEST_UNIFORM_Z (ext_63_u32, svuint32_t, + z0 = svext_u32 (z1, z2, 63), + z0 = svext (z1, z2, 63)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u64.c new file mode 100644 index 00000000000..ed81f811e5b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u64.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_u64_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u64_tied1, svuint64_t, + z0 = svext_u64 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_u64_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u64_tied2, svuint64_t, + z0 = svext_u64 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_u64_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u64_untied, svuint64_t, + z0 = svext_u64 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_u64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (ext_1_u64, svuint64_t, + z0 = svext_u64 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_u64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #16 +** ret +*/ +TEST_UNIFORM_Z (ext_2_u64, svuint64_t, + z0 = svext_u64 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_u64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #24 +** ret +*/ +TEST_UNIFORM_Z (ext_3_u64, svuint64_t, + z0 = svext_u64 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_31_u64: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #248 +** ret +*/ +TEST_UNIFORM_Z (ext_31_u64, svuint64_t, + z0 = svext_u64 (z1, z2, 31), + z0 = svext (z1, z2, 31)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u8.c new file mode 100644 index 00000000000..6c061406b48 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ext_u8.c @@ -0,0 +1,73 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ext_0_u8_tied1: +** ext z0\.b, z0\.b, z1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u8_tied1, svuint8_t, + z0 = svext_u8 (z0, z1, 0), + z0 = svext (z0, z1, 0)) + +/* +** ext_0_u8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ext z0\.b, z0\.b, \1\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u8_tied2, svuint8_t, + z0 = svext_u8 (z1, z0, 0), + z0 = svext (z1, z0, 0)) + +/* +** ext_0_u8_untied: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #0 +** ret +*/ +TEST_UNIFORM_Z (ext_0_u8_untied, svuint8_t, + z0 = svext_u8 (z1, z2, 0), + z0 = svext (z1, z2, 0)) + +/* +** ext_1_u8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (ext_1_u8, svuint8_t, + z0 = svext_u8 (z1, z2, 1), + z0 = svext (z1, z2, 1)) + +/* +** ext_2_u8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (ext_2_u8, svuint8_t, + z0 = svext_u8 (z1, z2, 2), + z0 = svext (z1, z2, 2)) + +/* +** ext_3_u8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #3 +** ret +*/ +TEST_UNIFORM_Z (ext_3_u8, svuint8_t, + z0 = svext_u8 (z1, z2, 3), + z0 = svext (z1, z2, 3)) + +/* +** ext_255_u8: +** movprfx z0, z1 +** ext z0\.b, z0\.b, z2\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (ext_255_u8, svuint8_t, + z0 = svext_u8 (z1, z2, 255), + z0 = svext (z1, z2, 255)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c new file mode 100644 index 00000000000..32e836f013b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_s16_m_tied12: +** sxtb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_m_tied12, svint16_t, + z0 = svextb_s16_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_s16_m_tied1: +** sxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_m_tied1, svint16_t, + z0 = svextb_s16_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sxtb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_m_tied2, svint16_t, + z0 = svextb_s16_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_s16_m_untied: +** movprfx z0, z2 +** sxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_m_untied, svint16_t, + z0 = svextb_s16_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** sxtb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_z_tied1, svint16_t, + z0 = svextb_s16_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** sxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_z_untied, svint16_t, + z0 = svextb_s16_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_s16_x_tied1: +** sxtb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_x_tied1, svint16_t, + z0 = svextb_s16_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_s16_x_untied: +** sxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_s16_x_untied, svint16_t, + z0 = svextb_s16_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c new file mode 100644 index 00000000000..e2f13f41cf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_s32_m_tied12: +** sxtb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_m_tied12, svint32_t, + z0 = svextb_s32_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_s32_m_tied1: +** sxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_m_tied1, svint32_t, + z0 = svextb_s32_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sxtb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_m_tied2, svint32_t, + z0 = svextb_s32_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_s32_m_untied: +** movprfx z0, z2 +** sxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_m_untied, svint32_t, + z0 = svextb_s32_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** sxtb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_z_tied1, svint32_t, + z0 = svextb_s32_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** sxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_z_untied, svint32_t, + z0 = svextb_s32_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_s32_x_tied1: +** sxtb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_x_tied1, svint32_t, + z0 = svextb_s32_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_s32_x_untied: +** sxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_s32_x_untied, svint32_t, + z0 = svextb_s32_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c new file mode 100644 index 00000000000..83363efdb7f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_s64_m_tied12: +** sxtb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_m_tied12, svint64_t, + z0 = svextb_s64_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_s64_m_tied1: +** sxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_m_tied1, svint64_t, + z0 = svextb_s64_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sxtb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extb_s64_m_tied2, svint64_t, + z0 = svextb_s64_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_s64_m_untied: +** movprfx z0, z2 +** sxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_m_untied, svint64_t, + z0 = svextb_s64_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** sxtb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extb_s64_z_tied1, svint64_t, + z0 = svextb_s64_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** sxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_z_untied, svint64_t, + z0 = svextb_s64_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_s64_x_tied1: +** sxtb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_x_tied1, svint64_t, + z0 = svextb_s64_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_s64_x_untied: +** sxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_s64_x_untied, svint64_t, + z0 = svextb_s64_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u16.c new file mode 100644 index 00000000000..d806edfaad0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u16.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_u16_m_tied12: +** uxtb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_m_tied12, svuint16_t, + z0 = svextb_u16_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_u16_m_tied1: +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_m_tied1, svuint16_t, + z0 = svextb_u16_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uxtb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_m_tied2, svuint16_t, + z0 = svextb_u16_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_u16_m_untied: +** movprfx z0, z2 +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_m_untied, svuint16_t, + z0 = svextb_u16_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** uxtb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_z_tied1, svuint16_t, + z0 = svextb_u16_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** uxtb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (extb_u16_z_untied, svuint16_t, + z0 = svextb_u16_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_u16_x_tied1: +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u16_x_tied1, svuint16_t, + z0 = svextb_u16_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_u16_x_untied: +** movprfx z0, z1 +** and z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u16_x_untied, svuint16_t, + z0 = svextb_u16_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u32.c new file mode 100644 index 00000000000..274656dbdc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u32.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_u32_m_tied12: +** uxtb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_m_tied12, svuint32_t, + z0 = svextb_u32_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_u32_m_tied1: +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_m_tied1, svuint32_t, + z0 = svextb_u32_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uxtb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_m_tied2, svuint32_t, + z0 = svextb_u32_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_u32_m_untied: +** movprfx z0, z2 +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_m_untied, svuint32_t, + z0 = svextb_u32_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxtb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_z_tied1, svuint32_t, + z0 = svextb_u32_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxtb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (extb_u32_z_untied, svuint32_t, + z0 = svextb_u32_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_u32_x_tied1: +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u32_x_tied1, svuint32_t, + z0 = svextb_u32_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_u32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u32_x_untied, svuint32_t, + z0 = svextb_u32_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u64.c new file mode 100644 index 00000000000..de24cc6054f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_u64.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extb_u64_m_tied12: +** uxtb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extb_u64_m_tied12, svuint64_t, + z0 = svextb_u64_m (z0, p0, z0), + z0 = svextb_m (z0, p0, z0)) + +/* +** extb_u64_m_tied1: +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_u64_m_tied1, svuint64_t, + z0 = svextb_u64_m (z0, p0, z1), + z0 = svextb_m (z0, p0, z1)) + +/* +** extb_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** uxtb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extb_u64_m_tied2, svuint64_t, + z0 = svextb_u64_m (z1, p0, z0), + z0 = svextb_m (z1, p0, z0)) + +/* +** extb_u64_m_untied: +** movprfx z0, z2 +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_u64_m_untied, svuint64_t, + z0 = svextb_u64_m (z2, p0, z1), + z0 = svextb_m (z2, p0, z1)) + +/* +** extb_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extb_u64_z_tied1, svuint64_t, + z0 = svextb_u64_z (p0, z0), + z0 = svextb_z (p0, z0)) + +/* +** extb_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extb_u64_z_untied, svuint64_t, + z0 = svextb_u64_z (p0, z1), + z0 = svextb_z (p0, z1)) + +/* +** extb_u64_x_tied1: +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u64_x_tied1, svuint64_t, + z0 = svextb_u64_x (p0, z0), + z0 = svextb_x (p0, z0)) + +/* +** extb_u64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (extb_u64_x_untied, svuint64_t, + z0 = svextb_u64_x (p0, z1), + z0 = svextb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c new file mode 100644 index 00000000000..3bb0bf31f20 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** exth_s32_m_tied12: +** sxth z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_m_tied12, svint32_t, + z0 = svexth_s32_m (z0, p0, z0), + z0 = svexth_m (z0, p0, z0)) + +/* +** exth_s32_m_tied1: +** sxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_m_tied1, svint32_t, + z0 = svexth_s32_m (z0, p0, z1), + z0 = svexth_m (z0, p0, z1)) + +/* +** exth_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sxth z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_m_tied2, svint32_t, + z0 = svexth_s32_m (z1, p0, z0), + z0 = svexth_m (z1, p0, z0)) + +/* +** exth_s32_m_untied: +** movprfx z0, z2 +** sxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_m_untied, svint32_t, + z0 = svexth_s32_m (z2, p0, z1), + z0 = svexth_m (z2, p0, z1)) + +/* +** exth_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** sxth z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_z_tied1, svint32_t, + z0 = svexth_s32_z (p0, z0), + z0 = svexth_z (p0, z0)) + +/* +** exth_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** sxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_z_untied, svint32_t, + z0 = svexth_s32_z (p0, z1), + z0 = svexth_z (p0, z1)) + +/* +** exth_s32_x_tied1: +** sxth z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_x_tied1, svint32_t, + z0 = svexth_s32_x (p0, z0), + z0 = svexth_x (p0, z0)) + +/* +** exth_s32_x_untied: +** sxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_s32_x_untied, svint32_t, + z0 = svexth_s32_x (p0, z1), + z0 = svexth_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c new file mode 100644 index 00000000000..0718b67ad14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** exth_s64_m_tied12: +** sxth z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_m_tied12, svint64_t, + z0 = svexth_s64_m (z0, p0, z0), + z0 = svexth_m (z0, p0, z0)) + +/* +** exth_s64_m_tied1: +** sxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_m_tied1, svint64_t, + z0 = svexth_s64_m (z0, p0, z1), + z0 = svexth_m (z0, p0, z1)) + +/* +** exth_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sxth z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (exth_s64_m_tied2, svint64_t, + z0 = svexth_s64_m (z1, p0, z0), + z0 = svexth_m (z1, p0, z0)) + +/* +** exth_s64_m_untied: +** movprfx z0, z2 +** sxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_m_untied, svint64_t, + z0 = svexth_s64_m (z2, p0, z1), + z0 = svexth_m (z2, p0, z1)) + +/* +** exth_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** sxth z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (exth_s64_z_tied1, svint64_t, + z0 = svexth_s64_z (p0, z0), + z0 = svexth_z (p0, z0)) + +/* +** exth_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** sxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_z_untied, svint64_t, + z0 = svexth_s64_z (p0, z1), + z0 = svexth_z (p0, z1)) + +/* +** exth_s64_x_tied1: +** sxth z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_x_tied1, svint64_t, + z0 = svexth_s64_x (p0, z0), + z0 = svexth_x (p0, z0)) + +/* +** exth_s64_x_untied: +** sxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_s64_x_untied, svint64_t, + z0 = svexth_s64_x (p0, z1), + z0 = svexth_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u32.c new file mode 100644 index 00000000000..1ba7fc8c312 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u32.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** exth_u32_m_tied12: +** uxth z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_m_tied12, svuint32_t, + z0 = svexth_u32_m (z0, p0, z0), + z0 = svexth_m (z0, p0, z0)) + +/* +** exth_u32_m_tied1: +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_m_tied1, svuint32_t, + z0 = svexth_u32_m (z0, p0, z1), + z0 = svexth_m (z0, p0, z1)) + +/* +** exth_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** uxth z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_m_tied2, svuint32_t, + z0 = svexth_u32_m (z1, p0, z0), + z0 = svexth_m (z1, p0, z0)) + +/* +** exth_u32_m_untied: +** movprfx z0, z2 +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_m_untied, svuint32_t, + z0 = svexth_u32_m (z2, p0, z1), + z0 = svexth_m (z2, p0, z1)) + +/* +** exth_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** uxth z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_z_tied1, svuint32_t, + z0 = svexth_u32_z (p0, z0), + z0 = svexth_z (p0, z0)) + +/* +** exth_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** uxth z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (exth_u32_z_untied, svuint32_t, + z0 = svexth_u32_z (p0, z1), + z0 = svexth_z (p0, z1)) + +/* +** exth_u32_x_tied1: +** and z0\.s, z0\.s, #0xffff +** ret +*/ +TEST_UNIFORM_Z (exth_u32_x_tied1, svuint32_t, + z0 = svexth_u32_x (p0, z0), + z0 = svexth_x (p0, z0)) + +/* +** exth_u32_x_untied: +** movprfx z0, z1 +** and z0\.s, z0\.s, #0xffff +** ret +*/ +TEST_UNIFORM_Z (exth_u32_x_untied, svuint32_t, + z0 = svexth_u32_x (p0, z1), + z0 = svexth_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u64.c new file mode 100644 index 00000000000..1555cf0b749 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_u64.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** exth_u64_m_tied12: +** uxth z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (exth_u64_m_tied12, svuint64_t, + z0 = svexth_u64_m (z0, p0, z0), + z0 = svexth_m (z0, p0, z0)) + +/* +** exth_u64_m_tied1: +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_u64_m_tied1, svuint64_t, + z0 = svexth_u64_m (z0, p0, z1), + z0 = svexth_m (z0, p0, z1)) + +/* +** exth_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** uxth z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (exth_u64_m_tied2, svuint64_t, + z0 = svexth_u64_m (z1, p0, z0), + z0 = svexth_m (z1, p0, z0)) + +/* +** exth_u64_m_untied: +** movprfx z0, z2 +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_u64_m_untied, svuint64_t, + z0 = svexth_u64_m (z2, p0, z1), + z0 = svexth_m (z2, p0, z1)) + +/* +** exth_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxth z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (exth_u64_z_tied1, svuint64_t, + z0 = svexth_u64_z (p0, z0), + z0 = svexth_z (p0, z0)) + +/* +** exth_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxth z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (exth_u64_z_untied, svuint64_t, + z0 = svexth_u64_z (p0, z1), + z0 = svexth_z (p0, z1)) + +/* +** exth_u64_x_tied1: +** and z0\.d, z0\.d, #0xffff +** ret +*/ +TEST_UNIFORM_Z (exth_u64_x_tied1, svuint64_t, + z0 = svexth_u64_x (p0, z0), + z0 = svexth_x (p0, z0)) + +/* +** exth_u64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0xffff +** ret +*/ +TEST_UNIFORM_Z (exth_u64_x_untied, svuint64_t, + z0 = svexth_u64_x (p0, z1), + z0 = svexth_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c new file mode 100644 index 00000000000..a6edadfa75c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extw_s64_m_tied12: +** sxtw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_m_tied12, svint64_t, + z0 = svextw_s64_m (z0, p0, z0), + z0 = svextw_m (z0, p0, z0)) + +/* +** extw_s64_m_tied1: +** sxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_m_tied1, svint64_t, + z0 = svextw_s64_m (z0, p0, z1), + z0 = svextw_m (z0, p0, z1)) + +/* +** extw_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sxtw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extw_s64_m_tied2, svint64_t, + z0 = svextw_s64_m (z1, p0, z0), + z0 = svextw_m (z1, p0, z0)) + +/* +** extw_s64_m_untied: +** movprfx z0, z2 +** sxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_m_untied, svint64_t, + z0 = svextw_s64_m (z2, p0, z1), + z0 = svextw_m (z2, p0, z1)) + +/* +** extw_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** sxtw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extw_s64_z_tied1, svint64_t, + z0 = svextw_s64_z (p0, z0), + z0 = svextw_z (p0, z0)) + +/* +** extw_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** sxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_z_untied, svint64_t, + z0 = svextw_s64_z (p0, z1), + z0 = svextw_z (p0, z1)) + +/* +** extw_s64_x_tied1: +** sxtw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_x_tied1, svint64_t, + z0 = svextw_s64_x (p0, z0), + z0 = svextw_x (p0, z0)) + +/* +** extw_s64_x_untied: +** sxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_s64_x_untied, svint64_t, + z0 = svextw_s64_x (p0, z1), + z0 = svextw_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_u64.c new file mode 100644 index 00000000000..880a287f309 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_u64.c @@ -0,0 +1,82 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** extw_u64_m_tied12: +** uxtw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (extw_u64_m_tied12, svuint64_t, + z0 = svextw_u64_m (z0, p0, z0), + z0 = svextw_m (z0, p0, z0)) + +/* +** extw_u64_m_tied1: +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_u64_m_tied1, svuint64_t, + z0 = svextw_u64_m (z0, p0, z1), + z0 = svextw_m (z0, p0, z1)) + +/* +** extw_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** uxtw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extw_u64_m_tied2, svuint64_t, + z0 = svextw_u64_m (z1, p0, z0), + z0 = svextw_m (z1, p0, z0)) + +/* +** extw_u64_m_untied: +** movprfx z0, z2 +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_u64_m_untied, svuint64_t, + z0 = svextw_u64_m (z2, p0, z1), + z0 = svextw_m (z2, p0, z1)) + +/* +** extw_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** uxtw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (extw_u64_z_tied1, svuint64_t, + z0 = svextw_u64_z (p0, z0), + z0 = svextw_z (p0, z0)) + +/* +** extw_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** uxtw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (extw_u64_z_untied, svuint64_t, + z0 = svextw_u64_z (p0, z1), + z0 = svextw_z (p0, z1)) + +/* +** extw_u64_x_tied1: +** and z0\.d, z0\.d, #0xffffffff +** ret +*/ +TEST_UNIFORM_Z (extw_u64_x_tied1, svuint64_t, + z0 = svextw_u64_x (p0, z0), + z0 = svextw_x (p0, z0)) + +/* +** extw_u64_x_untied: +** movprfx z0, z1 +** and z0\.d, z0\.d, #0xffffffff +** ret +*/ +TEST_UNIFORM_Z (extw_u64_x_untied, svuint64_t, + z0 = svextw_u64_x (p0, z1), + z0 = svextw_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f16.c new file mode 100644 index 00000000000..9b6379e0b21 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f16.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_f16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_f16_z0_0, svfloat16x2_t, svfloat16_t, + z0 = svget2_f16 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_f16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_f16_z0_1, svfloat16x2_t, svfloat16_t, + z0 = svget2_f16 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_f16_z4_0: +** ret +*/ +TEST_GET (get2_f16_z4_0, svfloat16x2_t, svfloat16_t, + z4_res = svget2_f16 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_f16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_f16_z4_1, svfloat16x2_t, svfloat16_t, + z4_res = svget2_f16 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_f16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_f16_z5_0, svfloat16x2_t, svfloat16_t, + z5_res = svget2_f16 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_f16_z5_1: +** ret +*/ +TEST_GET (get2_f16_z5_1, svfloat16x2_t, svfloat16_t, + z5_res = svget2_f16 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f32.c new file mode 100644 index 00000000000..76080dc6673 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f32.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_f32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_f32_z0_0, svfloat32x2_t, svfloat32_t, + z0 = svget2_f32 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_f32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_f32_z0_1, svfloat32x2_t, svfloat32_t, + z0 = svget2_f32 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_f32_z4_0: +** ret +*/ +TEST_GET (get2_f32_z4_0, svfloat32x2_t, svfloat32_t, + z4_res = svget2_f32 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_f32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_f32_z4_1, svfloat32x2_t, svfloat32_t, + z4_res = svget2_f32 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_f32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_f32_z5_0, svfloat32x2_t, svfloat32_t, + z5_res = svget2_f32 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_f32_z5_1: +** ret +*/ +TEST_GET (get2_f32_z5_1, svfloat32x2_t, svfloat32_t, + z5_res = svget2_f32 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f64.c new file mode 100644 index 00000000000..cabe6e7decb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_f64.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_f64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_f64_z0_0, svfloat64x2_t, svfloat64_t, + z0 = svget2_f64 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_f64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_f64_z0_1, svfloat64x2_t, svfloat64_t, + z0 = svget2_f64 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_f64_z4_0: +** ret +*/ +TEST_GET (get2_f64_z4_0, svfloat64x2_t, svfloat64_t, + z4_res = svget2_f64 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_f64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_f64_z4_1, svfloat64x2_t, svfloat64_t, + z4_res = svget2_f64 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_f64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_f64_z5_0, svfloat64x2_t, svfloat64_t, + z5_res = svget2_f64 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_f64_z5_1: +** ret +*/ +TEST_GET (get2_f64_z5_1, svfloat64x2_t, svfloat64_t, + z5_res = svget2_f64 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s16.c new file mode 100644 index 00000000000..387e6daad0a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s16.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_s16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_s16_z0_0, svint16x2_t, svint16_t, + z0 = svget2_s16 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_s16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_s16_z0_1, svint16x2_t, svint16_t, + z0 = svget2_s16 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_s16_z4_0: +** ret +*/ +TEST_GET (get2_s16_z4_0, svint16x2_t, svint16_t, + z4_res = svget2_s16 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_s16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_s16_z4_1, svint16x2_t, svint16_t, + z4_res = svget2_s16 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_s16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_s16_z5_0, svint16x2_t, svint16_t, + z5_res = svget2_s16 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_s16_z5_1: +** ret +*/ +TEST_GET (get2_s16_z5_1, svint16x2_t, svint16_t, + z5_res = svget2_s16 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s32.c new file mode 100644 index 00000000000..5c47286e084 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s32.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_s32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_s32_z0_0, svint32x2_t, svint32_t, + z0 = svget2_s32 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_s32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_s32_z0_1, svint32x2_t, svint32_t, + z0 = svget2_s32 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_s32_z4_0: +** ret +*/ +TEST_GET (get2_s32_z4_0, svint32x2_t, svint32_t, + z4_res = svget2_s32 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_s32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_s32_z4_1, svint32x2_t, svint32_t, + z4_res = svget2_s32 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_s32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_s32_z5_0, svint32x2_t, svint32_t, + z5_res = svget2_s32 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_s32_z5_1: +** ret +*/ +TEST_GET (get2_s32_z5_1, svint32x2_t, svint32_t, + z5_res = svget2_s32 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s64.c new file mode 100644 index 00000000000..18f930d4c80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s64.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_s64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_s64_z0_0, svint64x2_t, svint64_t, + z0 = svget2_s64 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_s64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_s64_z0_1, svint64x2_t, svint64_t, + z0 = svget2_s64 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_s64_z4_0: +** ret +*/ +TEST_GET (get2_s64_z4_0, svint64x2_t, svint64_t, + z4_res = svget2_s64 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_s64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_s64_z4_1, svint64x2_t, svint64_t, + z4_res = svget2_s64 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_s64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_s64_z5_0, svint64x2_t, svint64_t, + z5_res = svget2_s64 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_s64_z5_1: +** ret +*/ +TEST_GET (get2_s64_z5_1, svint64x2_t, svint64_t, + z5_res = svget2_s64 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s8.c new file mode 100644 index 00000000000..27e2cfafb41 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_s8.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_s8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_s8_z0_0, svint8x2_t, svint8_t, + z0 = svget2_s8 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_s8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_s8_z0_1, svint8x2_t, svint8_t, + z0 = svget2_s8 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_s8_z4_0: +** ret +*/ +TEST_GET (get2_s8_z4_0, svint8x2_t, svint8_t, + z4_res = svget2_s8 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_s8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_s8_z4_1, svint8x2_t, svint8_t, + z4_res = svget2_s8 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_s8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_s8_z5_0, svint8x2_t, svint8_t, + z5_res = svget2_s8 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_s8_z5_1: +** ret +*/ +TEST_GET (get2_s8_z5_1, svint8x2_t, svint8_t, + z5_res = svget2_s8 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u16.c new file mode 100644 index 00000000000..1804900cc7c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u16.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_u16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_u16_z0_0, svuint16x2_t, svuint16_t, + z0 = svget2_u16 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_u16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_u16_z0_1, svuint16x2_t, svuint16_t, + z0 = svget2_u16 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_u16_z4_0: +** ret +*/ +TEST_GET (get2_u16_z4_0, svuint16x2_t, svuint16_t, + z4_res = svget2_u16 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_u16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_u16_z4_1, svuint16x2_t, svuint16_t, + z4_res = svget2_u16 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_u16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_u16_z5_0, svuint16x2_t, svuint16_t, + z5_res = svget2_u16 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_u16_z5_1: +** ret +*/ +TEST_GET (get2_u16_z5_1, svuint16x2_t, svuint16_t, + z5_res = svget2_u16 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u32.c new file mode 100644 index 00000000000..5c14de6aa87 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u32.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_u32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_u32_z0_0, svuint32x2_t, svuint32_t, + z0 = svget2_u32 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_u32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_u32_z0_1, svuint32x2_t, svuint32_t, + z0 = svget2_u32 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_u32_z4_0: +** ret +*/ +TEST_GET (get2_u32_z4_0, svuint32x2_t, svuint32_t, + z4_res = svget2_u32 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_u32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_u32_z4_1, svuint32x2_t, svuint32_t, + z4_res = svget2_u32 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_u32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_u32_z5_0, svuint32x2_t, svuint32_t, + z5_res = svget2_u32 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_u32_z5_1: +** ret +*/ +TEST_GET (get2_u32_z5_1, svuint32x2_t, svuint32_t, + z5_res = svget2_u32 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u64.c new file mode 100644 index 00000000000..fd389a01e5a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u64.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_u64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_u64_z0_0, svuint64x2_t, svuint64_t, + z0 = svget2_u64 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_u64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_u64_z0_1, svuint64x2_t, svuint64_t, + z0 = svget2_u64 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_u64_z4_0: +** ret +*/ +TEST_GET (get2_u64_z4_0, svuint64x2_t, svuint64_t, + z4_res = svget2_u64 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_u64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_u64_z4_1, svuint64x2_t, svuint64_t, + z4_res = svget2_u64 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_u64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_u64_z5_0, svuint64x2_t, svuint64_t, + z5_res = svget2_u64 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_u64_z5_1: +** ret +*/ +TEST_GET (get2_u64_z5_1, svuint64x2_t, svuint64_t, + z5_res = svget2_u64 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u8.c new file mode 100644 index 00000000000..42ffb03447c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get2_u8.c @@ -0,0 +1,55 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get2_u8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get2_u8_z0_0, svuint8x2_t, svuint8_t, + z0 = svget2_u8 (z4, 0), + z0 = svget2 (z4, 0)) + +/* +** get2_u8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get2_u8_z0_1, svuint8x2_t, svuint8_t, + z0 = svget2_u8 (z4, 1), + z0 = svget2 (z4, 1)) + +/* +** get2_u8_z4_0: +** ret +*/ +TEST_GET (get2_u8_z4_0, svuint8x2_t, svuint8_t, + z4_res = svget2_u8 (z4, 0), + z4_res = svget2 (z4, 0)) + +/* +** get2_u8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get2_u8_z4_1, svuint8x2_t, svuint8_t, + z4_res = svget2_u8 (z4, 1), + z4_res = svget2 (z4, 1)) + +/* +** get2_u8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get2_u8_z5_0, svuint8x2_t, svuint8_t, + z5_res = svget2_u8 (z4, 0), + z5_res = svget2 (z4, 0)) + +/* +** get2_u8_z5_1: +** ret +*/ +TEST_GET (get2_u8_z5_1, svuint8x2_t, svuint8_t, + z5_res = svget2_u8 (z4, 1), + z5_res = svget2 (z4, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f16.c new file mode 100644 index 00000000000..8bea03bc517 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f16.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_f16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_f16_z0_0, svfloat16x3_t, svfloat16_t, + z0 = svget3_f16 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_f16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_f16_z0_1, svfloat16x3_t, svfloat16_t, + z0 = svget3_f16 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_f16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_f16_z0_2, svfloat16x3_t, svfloat16_t, + z0 = svget3_f16 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_f16_z4_0: +** ret +*/ +TEST_GET (get3_f16_z4_0, svfloat16x3_t, svfloat16_t, + z4_res = svget3_f16 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_f16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_f16_z4_1, svfloat16x3_t, svfloat16_t, + z4_res = svget3_f16 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_f16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_f16_z4_2, svfloat16x3_t, svfloat16_t, + z4_res = svget3_f16 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_f16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_f16_z5_0, svfloat16x3_t, svfloat16_t, + z5_res = svget3_f16 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_f16_z5_1: +** ret +*/ +TEST_GET (get3_f16_z5_1, svfloat16x3_t, svfloat16_t, + z5_res = svget3_f16 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_f16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_f16_z5_2, svfloat16x3_t, svfloat16_t, + z5_res = svget3_f16 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_f16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_f16_z6_0, svfloat16x3_t, svfloat16_t, + z6_res = svget3_f16 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_f16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_f16_z6_1, svfloat16x3_t, svfloat16_t, + z6_res = svget3_f16 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_f16_z6_2: +** ret +*/ +TEST_GET (get3_f16_z6_2, svfloat16x3_t, svfloat16_t, + z6_res = svget3_f16 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f32.c new file mode 100644 index 00000000000..24667958402 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f32.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_f32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_f32_z0_0, svfloat32x3_t, svfloat32_t, + z0 = svget3_f32 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_f32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_f32_z0_1, svfloat32x3_t, svfloat32_t, + z0 = svget3_f32 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_f32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_f32_z0_2, svfloat32x3_t, svfloat32_t, + z0 = svget3_f32 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_f32_z4_0: +** ret +*/ +TEST_GET (get3_f32_z4_0, svfloat32x3_t, svfloat32_t, + z4_res = svget3_f32 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_f32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_f32_z4_1, svfloat32x3_t, svfloat32_t, + z4_res = svget3_f32 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_f32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_f32_z4_2, svfloat32x3_t, svfloat32_t, + z4_res = svget3_f32 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_f32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_f32_z5_0, svfloat32x3_t, svfloat32_t, + z5_res = svget3_f32 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_f32_z5_1: +** ret +*/ +TEST_GET (get3_f32_z5_1, svfloat32x3_t, svfloat32_t, + z5_res = svget3_f32 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_f32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_f32_z5_2, svfloat32x3_t, svfloat32_t, + z5_res = svget3_f32 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_f32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_f32_z6_0, svfloat32x3_t, svfloat32_t, + z6_res = svget3_f32 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_f32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_f32_z6_1, svfloat32x3_t, svfloat32_t, + z6_res = svget3_f32 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_f32_z6_2: +** ret +*/ +TEST_GET (get3_f32_z6_2, svfloat32x3_t, svfloat32_t, + z6_res = svget3_f32 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f64.c new file mode 100644 index 00000000000..e44eb15fd6b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_f64.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_f64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_f64_z0_0, svfloat64x3_t, svfloat64_t, + z0 = svget3_f64 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_f64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_f64_z0_1, svfloat64x3_t, svfloat64_t, + z0 = svget3_f64 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_f64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_f64_z0_2, svfloat64x3_t, svfloat64_t, + z0 = svget3_f64 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_f64_z4_0: +** ret +*/ +TEST_GET (get3_f64_z4_0, svfloat64x3_t, svfloat64_t, + z4_res = svget3_f64 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_f64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_f64_z4_1, svfloat64x3_t, svfloat64_t, + z4_res = svget3_f64 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_f64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_f64_z4_2, svfloat64x3_t, svfloat64_t, + z4_res = svget3_f64 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_f64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_f64_z5_0, svfloat64x3_t, svfloat64_t, + z5_res = svget3_f64 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_f64_z5_1: +** ret +*/ +TEST_GET (get3_f64_z5_1, svfloat64x3_t, svfloat64_t, + z5_res = svget3_f64 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_f64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_f64_z5_2, svfloat64x3_t, svfloat64_t, + z5_res = svget3_f64 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_f64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_f64_z6_0, svfloat64x3_t, svfloat64_t, + z6_res = svget3_f64 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_f64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_f64_z6_1, svfloat64x3_t, svfloat64_t, + z6_res = svget3_f64 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_f64_z6_2: +** ret +*/ +TEST_GET (get3_f64_z6_2, svfloat64x3_t, svfloat64_t, + z6_res = svget3_f64 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s16.c new file mode 100644 index 00000000000..88f7e4986df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s16.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_s16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_s16_z0_0, svint16x3_t, svint16_t, + z0 = svget3_s16 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_s16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_s16_z0_1, svint16x3_t, svint16_t, + z0 = svget3_s16 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_s16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_s16_z0_2, svint16x3_t, svint16_t, + z0 = svget3_s16 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_s16_z4_0: +** ret +*/ +TEST_GET (get3_s16_z4_0, svint16x3_t, svint16_t, + z4_res = svget3_s16 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_s16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_s16_z4_1, svint16x3_t, svint16_t, + z4_res = svget3_s16 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_s16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_s16_z4_2, svint16x3_t, svint16_t, + z4_res = svget3_s16 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_s16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_s16_z5_0, svint16x3_t, svint16_t, + z5_res = svget3_s16 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_s16_z5_1: +** ret +*/ +TEST_GET (get3_s16_z5_1, svint16x3_t, svint16_t, + z5_res = svget3_s16 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_s16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_s16_z5_2, svint16x3_t, svint16_t, + z5_res = svget3_s16 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_s16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_s16_z6_0, svint16x3_t, svint16_t, + z6_res = svget3_s16 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_s16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_s16_z6_1, svint16x3_t, svint16_t, + z6_res = svget3_s16 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_s16_z6_2: +** ret +*/ +TEST_GET (get3_s16_z6_2, svint16x3_t, svint16_t, + z6_res = svget3_s16 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s32.c new file mode 100644 index 00000000000..f0f7785c852 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s32.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_s32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_s32_z0_0, svint32x3_t, svint32_t, + z0 = svget3_s32 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_s32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_s32_z0_1, svint32x3_t, svint32_t, + z0 = svget3_s32 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_s32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_s32_z0_2, svint32x3_t, svint32_t, + z0 = svget3_s32 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_s32_z4_0: +** ret +*/ +TEST_GET (get3_s32_z4_0, svint32x3_t, svint32_t, + z4_res = svget3_s32 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_s32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_s32_z4_1, svint32x3_t, svint32_t, + z4_res = svget3_s32 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_s32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_s32_z4_2, svint32x3_t, svint32_t, + z4_res = svget3_s32 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_s32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_s32_z5_0, svint32x3_t, svint32_t, + z5_res = svget3_s32 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_s32_z5_1: +** ret +*/ +TEST_GET (get3_s32_z5_1, svint32x3_t, svint32_t, + z5_res = svget3_s32 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_s32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_s32_z5_2, svint32x3_t, svint32_t, + z5_res = svget3_s32 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_s32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_s32_z6_0, svint32x3_t, svint32_t, + z6_res = svget3_s32 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_s32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_s32_z6_1, svint32x3_t, svint32_t, + z6_res = svget3_s32 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_s32_z6_2: +** ret +*/ +TEST_GET (get3_s32_z6_2, svint32x3_t, svint32_t, + z6_res = svget3_s32 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s64.c new file mode 100644 index 00000000000..92500bfdfc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s64.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_s64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_s64_z0_0, svint64x3_t, svint64_t, + z0 = svget3_s64 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_s64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_s64_z0_1, svint64x3_t, svint64_t, + z0 = svget3_s64 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_s64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_s64_z0_2, svint64x3_t, svint64_t, + z0 = svget3_s64 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_s64_z4_0: +** ret +*/ +TEST_GET (get3_s64_z4_0, svint64x3_t, svint64_t, + z4_res = svget3_s64 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_s64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_s64_z4_1, svint64x3_t, svint64_t, + z4_res = svget3_s64 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_s64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_s64_z4_2, svint64x3_t, svint64_t, + z4_res = svget3_s64 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_s64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_s64_z5_0, svint64x3_t, svint64_t, + z5_res = svget3_s64 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_s64_z5_1: +** ret +*/ +TEST_GET (get3_s64_z5_1, svint64x3_t, svint64_t, + z5_res = svget3_s64 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_s64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_s64_z5_2, svint64x3_t, svint64_t, + z5_res = svget3_s64 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_s64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_s64_z6_0, svint64x3_t, svint64_t, + z6_res = svget3_s64 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_s64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_s64_z6_1, svint64x3_t, svint64_t, + z6_res = svget3_s64 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_s64_z6_2: +** ret +*/ +TEST_GET (get3_s64_z6_2, svint64x3_t, svint64_t, + z6_res = svget3_s64 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s8.c new file mode 100644 index 00000000000..edf225ba52d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_s8.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_s8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_s8_z0_0, svint8x3_t, svint8_t, + z0 = svget3_s8 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_s8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_s8_z0_1, svint8x3_t, svint8_t, + z0 = svget3_s8 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_s8_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_s8_z0_2, svint8x3_t, svint8_t, + z0 = svget3_s8 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_s8_z4_0: +** ret +*/ +TEST_GET (get3_s8_z4_0, svint8x3_t, svint8_t, + z4_res = svget3_s8 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_s8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_s8_z4_1, svint8x3_t, svint8_t, + z4_res = svget3_s8 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_s8_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_s8_z4_2, svint8x3_t, svint8_t, + z4_res = svget3_s8 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_s8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_s8_z5_0, svint8x3_t, svint8_t, + z5_res = svget3_s8 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_s8_z5_1: +** ret +*/ +TEST_GET (get3_s8_z5_1, svint8x3_t, svint8_t, + z5_res = svget3_s8 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_s8_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_s8_z5_2, svint8x3_t, svint8_t, + z5_res = svget3_s8 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_s8_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_s8_z6_0, svint8x3_t, svint8_t, + z6_res = svget3_s8 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_s8_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_s8_z6_1, svint8x3_t, svint8_t, + z6_res = svget3_s8 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_s8_z6_2: +** ret +*/ +TEST_GET (get3_s8_z6_2, svint8x3_t, svint8_t, + z6_res = svget3_s8 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u16.c new file mode 100644 index 00000000000..1fa7c63c0a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u16.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_u16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_u16_z0_0, svuint16x3_t, svuint16_t, + z0 = svget3_u16 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_u16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_u16_z0_1, svuint16x3_t, svuint16_t, + z0 = svget3_u16 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_u16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_u16_z0_2, svuint16x3_t, svuint16_t, + z0 = svget3_u16 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_u16_z4_0: +** ret +*/ +TEST_GET (get3_u16_z4_0, svuint16x3_t, svuint16_t, + z4_res = svget3_u16 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_u16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_u16_z4_1, svuint16x3_t, svuint16_t, + z4_res = svget3_u16 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_u16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_u16_z4_2, svuint16x3_t, svuint16_t, + z4_res = svget3_u16 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_u16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_u16_z5_0, svuint16x3_t, svuint16_t, + z5_res = svget3_u16 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_u16_z5_1: +** ret +*/ +TEST_GET (get3_u16_z5_1, svuint16x3_t, svuint16_t, + z5_res = svget3_u16 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_u16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_u16_z5_2, svuint16x3_t, svuint16_t, + z5_res = svget3_u16 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_u16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_u16_z6_0, svuint16x3_t, svuint16_t, + z6_res = svget3_u16 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_u16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_u16_z6_1, svuint16x3_t, svuint16_t, + z6_res = svget3_u16 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_u16_z6_2: +** ret +*/ +TEST_GET (get3_u16_z6_2, svuint16x3_t, svuint16_t, + z6_res = svget3_u16 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u32.c new file mode 100644 index 00000000000..03b5f2616cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u32.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_u32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_u32_z0_0, svuint32x3_t, svuint32_t, + z0 = svget3_u32 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_u32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_u32_z0_1, svuint32x3_t, svuint32_t, + z0 = svget3_u32 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_u32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_u32_z0_2, svuint32x3_t, svuint32_t, + z0 = svget3_u32 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_u32_z4_0: +** ret +*/ +TEST_GET (get3_u32_z4_0, svuint32x3_t, svuint32_t, + z4_res = svget3_u32 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_u32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_u32_z4_1, svuint32x3_t, svuint32_t, + z4_res = svget3_u32 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_u32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_u32_z4_2, svuint32x3_t, svuint32_t, + z4_res = svget3_u32 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_u32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_u32_z5_0, svuint32x3_t, svuint32_t, + z5_res = svget3_u32 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_u32_z5_1: +** ret +*/ +TEST_GET (get3_u32_z5_1, svuint32x3_t, svuint32_t, + z5_res = svget3_u32 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_u32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_u32_z5_2, svuint32x3_t, svuint32_t, + z5_res = svget3_u32 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_u32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_u32_z6_0, svuint32x3_t, svuint32_t, + z6_res = svget3_u32 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_u32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_u32_z6_1, svuint32x3_t, svuint32_t, + z6_res = svget3_u32 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_u32_z6_2: +** ret +*/ +TEST_GET (get3_u32_z6_2, svuint32x3_t, svuint32_t, + z6_res = svget3_u32 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u64.c new file mode 100644 index 00000000000..ae4ef00240c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u64.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_u64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_u64_z0_0, svuint64x3_t, svuint64_t, + z0 = svget3_u64 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_u64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_u64_z0_1, svuint64x3_t, svuint64_t, + z0 = svget3_u64 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_u64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_u64_z0_2, svuint64x3_t, svuint64_t, + z0 = svget3_u64 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_u64_z4_0: +** ret +*/ +TEST_GET (get3_u64_z4_0, svuint64x3_t, svuint64_t, + z4_res = svget3_u64 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_u64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_u64_z4_1, svuint64x3_t, svuint64_t, + z4_res = svget3_u64 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_u64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_u64_z4_2, svuint64x3_t, svuint64_t, + z4_res = svget3_u64 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_u64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_u64_z5_0, svuint64x3_t, svuint64_t, + z5_res = svget3_u64 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_u64_z5_1: +** ret +*/ +TEST_GET (get3_u64_z5_1, svuint64x3_t, svuint64_t, + z5_res = svget3_u64 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_u64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_u64_z5_2, svuint64x3_t, svuint64_t, + z5_res = svget3_u64 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_u64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_u64_z6_0, svuint64x3_t, svuint64_t, + z6_res = svget3_u64 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_u64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_u64_z6_1, svuint64x3_t, svuint64_t, + z6_res = svget3_u64 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_u64_z6_2: +** ret +*/ +TEST_GET (get3_u64_z6_2, svuint64x3_t, svuint64_t, + z6_res = svget3_u64 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u8.c new file mode 100644 index 00000000000..497dcbbae06 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get3_u8.c @@ -0,0 +1,108 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get3_u8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get3_u8_z0_0, svuint8x3_t, svuint8_t, + z0 = svget3_u8 (z4, 0), + z0 = svget3 (z4, 0)) + +/* +** get3_u8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get3_u8_z0_1, svuint8x3_t, svuint8_t, + z0 = svget3_u8 (z4, 1), + z0 = svget3 (z4, 1)) + +/* +** get3_u8_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get3_u8_z0_2, svuint8x3_t, svuint8_t, + z0 = svget3_u8 (z4, 2), + z0 = svget3 (z4, 2)) + +/* +** get3_u8_z4_0: +** ret +*/ +TEST_GET (get3_u8_z4_0, svuint8x3_t, svuint8_t, + z4_res = svget3_u8 (z4, 0), + z4_res = svget3 (z4, 0)) + +/* +** get3_u8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get3_u8_z4_1, svuint8x3_t, svuint8_t, + z4_res = svget3_u8 (z4, 1), + z4_res = svget3 (z4, 1)) + +/* +** get3_u8_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get3_u8_z4_2, svuint8x3_t, svuint8_t, + z4_res = svget3_u8 (z4, 2), + z4_res = svget3 (z4, 2)) + +/* +** get3_u8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get3_u8_z5_0, svuint8x3_t, svuint8_t, + z5_res = svget3_u8 (z4, 0), + z5_res = svget3 (z4, 0)) + +/* +** get3_u8_z5_1: +** ret +*/ +TEST_GET (get3_u8_z5_1, svuint8x3_t, svuint8_t, + z5_res = svget3_u8 (z4, 1), + z5_res = svget3 (z4, 1)) + +/* +** get3_u8_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get3_u8_z5_2, svuint8x3_t, svuint8_t, + z5_res = svget3_u8 (z4, 2), + z5_res = svget3 (z4, 2)) + +/* +** get3_u8_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get3_u8_z6_0, svuint8x3_t, svuint8_t, + z6_res = svget3_u8 (z4, 0), + z6_res = svget3 (z4, 0)) + +/* +** get3_u8_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get3_u8_z6_1, svuint8x3_t, svuint8_t, + z6_res = svget3_u8 (z4, 1), + z6_res = svget3 (z4, 1)) + +/* +** get3_u8_z6_2: +** ret +*/ +TEST_GET (get3_u8_z6_2, svuint8x3_t, svuint8_t, + z6_res = svget3_u8 (z4, 2), + z6_res = svget3 (z4, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f16.c new file mode 100644 index 00000000000..7871f6f4ed7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f16.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_f16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_f16_z0_0, svfloat16x4_t, svfloat16_t, + z0 = svget4_f16 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_f16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_f16_z0_1, svfloat16x4_t, svfloat16_t, + z0 = svget4_f16 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_f16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_f16_z0_2, svfloat16x4_t, svfloat16_t, + z0 = svget4_f16 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_f16_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_f16_z0_3, svfloat16x4_t, svfloat16_t, + z0 = svget4_f16 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_f16_z4_0: +** ret +*/ +TEST_GET (get4_f16_z4_0, svfloat16x4_t, svfloat16_t, + z4_res = svget4_f16 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_f16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_f16_z4_1, svfloat16x4_t, svfloat16_t, + z4_res = svget4_f16 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_f16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_f16_z4_2, svfloat16x4_t, svfloat16_t, + z4_res = svget4_f16 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_f16_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_f16_z4_3, svfloat16x4_t, svfloat16_t, + z4_res = svget4_f16 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_f16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_f16_z5_0, svfloat16x4_t, svfloat16_t, + z5_res = svget4_f16 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_f16_z5_1: +** ret +*/ +TEST_GET (get4_f16_z5_1, svfloat16x4_t, svfloat16_t, + z5_res = svget4_f16 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_f16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_f16_z5_2, svfloat16x4_t, svfloat16_t, + z5_res = svget4_f16 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_f16_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_f16_z5_3, svfloat16x4_t, svfloat16_t, + z5_res = svget4_f16 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_f16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_f16_z6_0, svfloat16x4_t, svfloat16_t, + z6_res = svget4_f16 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_f16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_f16_z6_1, svfloat16x4_t, svfloat16_t, + z6_res = svget4_f16 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_f16_z6_2: +** ret +*/ +TEST_GET (get4_f16_z6_2, svfloat16x4_t, svfloat16_t, + z6_res = svget4_f16 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_f16_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_f16_z6_3, svfloat16x4_t, svfloat16_t, + z6_res = svget4_f16 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_f16_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_f16_z7_0, svfloat16x4_t, svfloat16_t, + z7_res = svget4_f16 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_f16_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_f16_z7_1, svfloat16x4_t, svfloat16_t, + z7_res = svget4_f16 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_f16_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_f16_z7_2, svfloat16x4_t, svfloat16_t, + z7_res = svget4_f16 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_f16_z7_3: +** ret +*/ +TEST_GET (get4_f16_z7_3, svfloat16x4_t, svfloat16_t, + z7_res = svget4_f16 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f32.c new file mode 100644 index 00000000000..a290e026d6b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f32.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_f32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_f32_z0_0, svfloat32x4_t, svfloat32_t, + z0 = svget4_f32 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_f32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_f32_z0_1, svfloat32x4_t, svfloat32_t, + z0 = svget4_f32 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_f32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_f32_z0_2, svfloat32x4_t, svfloat32_t, + z0 = svget4_f32 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_f32_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_f32_z0_3, svfloat32x4_t, svfloat32_t, + z0 = svget4_f32 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_f32_z4_0: +** ret +*/ +TEST_GET (get4_f32_z4_0, svfloat32x4_t, svfloat32_t, + z4_res = svget4_f32 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_f32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_f32_z4_1, svfloat32x4_t, svfloat32_t, + z4_res = svget4_f32 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_f32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_f32_z4_2, svfloat32x4_t, svfloat32_t, + z4_res = svget4_f32 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_f32_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_f32_z4_3, svfloat32x4_t, svfloat32_t, + z4_res = svget4_f32 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_f32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_f32_z5_0, svfloat32x4_t, svfloat32_t, + z5_res = svget4_f32 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_f32_z5_1: +** ret +*/ +TEST_GET (get4_f32_z5_1, svfloat32x4_t, svfloat32_t, + z5_res = svget4_f32 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_f32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_f32_z5_2, svfloat32x4_t, svfloat32_t, + z5_res = svget4_f32 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_f32_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_f32_z5_3, svfloat32x4_t, svfloat32_t, + z5_res = svget4_f32 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_f32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_f32_z6_0, svfloat32x4_t, svfloat32_t, + z6_res = svget4_f32 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_f32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_f32_z6_1, svfloat32x4_t, svfloat32_t, + z6_res = svget4_f32 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_f32_z6_2: +** ret +*/ +TEST_GET (get4_f32_z6_2, svfloat32x4_t, svfloat32_t, + z6_res = svget4_f32 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_f32_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_f32_z6_3, svfloat32x4_t, svfloat32_t, + z6_res = svget4_f32 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_f32_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_f32_z7_0, svfloat32x4_t, svfloat32_t, + z7_res = svget4_f32 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_f32_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_f32_z7_1, svfloat32x4_t, svfloat32_t, + z7_res = svget4_f32 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_f32_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_f32_z7_2, svfloat32x4_t, svfloat32_t, + z7_res = svget4_f32 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_f32_z7_3: +** ret +*/ +TEST_GET (get4_f32_z7_3, svfloat32x4_t, svfloat32_t, + z7_res = svget4_f32 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f64.c new file mode 100644 index 00000000000..2c34dfef1f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_f64.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_f64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_f64_z0_0, svfloat64x4_t, svfloat64_t, + z0 = svget4_f64 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_f64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_f64_z0_1, svfloat64x4_t, svfloat64_t, + z0 = svget4_f64 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_f64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_f64_z0_2, svfloat64x4_t, svfloat64_t, + z0 = svget4_f64 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_f64_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_f64_z0_3, svfloat64x4_t, svfloat64_t, + z0 = svget4_f64 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_f64_z4_0: +** ret +*/ +TEST_GET (get4_f64_z4_0, svfloat64x4_t, svfloat64_t, + z4_res = svget4_f64 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_f64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_f64_z4_1, svfloat64x4_t, svfloat64_t, + z4_res = svget4_f64 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_f64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_f64_z4_2, svfloat64x4_t, svfloat64_t, + z4_res = svget4_f64 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_f64_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_f64_z4_3, svfloat64x4_t, svfloat64_t, + z4_res = svget4_f64 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_f64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_f64_z5_0, svfloat64x4_t, svfloat64_t, + z5_res = svget4_f64 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_f64_z5_1: +** ret +*/ +TEST_GET (get4_f64_z5_1, svfloat64x4_t, svfloat64_t, + z5_res = svget4_f64 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_f64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_f64_z5_2, svfloat64x4_t, svfloat64_t, + z5_res = svget4_f64 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_f64_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_f64_z5_3, svfloat64x4_t, svfloat64_t, + z5_res = svget4_f64 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_f64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_f64_z6_0, svfloat64x4_t, svfloat64_t, + z6_res = svget4_f64 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_f64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_f64_z6_1, svfloat64x4_t, svfloat64_t, + z6_res = svget4_f64 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_f64_z6_2: +** ret +*/ +TEST_GET (get4_f64_z6_2, svfloat64x4_t, svfloat64_t, + z6_res = svget4_f64 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_f64_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_f64_z6_3, svfloat64x4_t, svfloat64_t, + z6_res = svget4_f64 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_f64_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_f64_z7_0, svfloat64x4_t, svfloat64_t, + z7_res = svget4_f64 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_f64_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_f64_z7_1, svfloat64x4_t, svfloat64_t, + z7_res = svget4_f64 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_f64_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_f64_z7_2, svfloat64x4_t, svfloat64_t, + z7_res = svget4_f64 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_f64_z7_3: +** ret +*/ +TEST_GET (get4_f64_z7_3, svfloat64x4_t, svfloat64_t, + z7_res = svget4_f64 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s16.c new file mode 100644 index 00000000000..6a2280fea88 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s16.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_s16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_s16_z0_0, svint16x4_t, svint16_t, + z0 = svget4_s16 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_s16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_s16_z0_1, svint16x4_t, svint16_t, + z0 = svget4_s16 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_s16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_s16_z0_2, svint16x4_t, svint16_t, + z0 = svget4_s16 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_s16_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_s16_z0_3, svint16x4_t, svint16_t, + z0 = svget4_s16 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_s16_z4_0: +** ret +*/ +TEST_GET (get4_s16_z4_0, svint16x4_t, svint16_t, + z4_res = svget4_s16 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_s16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_s16_z4_1, svint16x4_t, svint16_t, + z4_res = svget4_s16 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_s16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_s16_z4_2, svint16x4_t, svint16_t, + z4_res = svget4_s16 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_s16_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_s16_z4_3, svint16x4_t, svint16_t, + z4_res = svget4_s16 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_s16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_s16_z5_0, svint16x4_t, svint16_t, + z5_res = svget4_s16 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_s16_z5_1: +** ret +*/ +TEST_GET (get4_s16_z5_1, svint16x4_t, svint16_t, + z5_res = svget4_s16 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_s16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_s16_z5_2, svint16x4_t, svint16_t, + z5_res = svget4_s16 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_s16_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_s16_z5_3, svint16x4_t, svint16_t, + z5_res = svget4_s16 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_s16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_s16_z6_0, svint16x4_t, svint16_t, + z6_res = svget4_s16 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_s16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_s16_z6_1, svint16x4_t, svint16_t, + z6_res = svget4_s16 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_s16_z6_2: +** ret +*/ +TEST_GET (get4_s16_z6_2, svint16x4_t, svint16_t, + z6_res = svget4_s16 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_s16_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_s16_z6_3, svint16x4_t, svint16_t, + z6_res = svget4_s16 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_s16_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_s16_z7_0, svint16x4_t, svint16_t, + z7_res = svget4_s16 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_s16_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_s16_z7_1, svint16x4_t, svint16_t, + z7_res = svget4_s16 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_s16_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_s16_z7_2, svint16x4_t, svint16_t, + z7_res = svget4_s16 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_s16_z7_3: +** ret +*/ +TEST_GET (get4_s16_z7_3, svint16x4_t, svint16_t, + z7_res = svget4_s16 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s32.c new file mode 100644 index 00000000000..41aca09d957 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s32.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_s32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_s32_z0_0, svint32x4_t, svint32_t, + z0 = svget4_s32 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_s32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_s32_z0_1, svint32x4_t, svint32_t, + z0 = svget4_s32 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_s32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_s32_z0_2, svint32x4_t, svint32_t, + z0 = svget4_s32 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_s32_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_s32_z0_3, svint32x4_t, svint32_t, + z0 = svget4_s32 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_s32_z4_0: +** ret +*/ +TEST_GET (get4_s32_z4_0, svint32x4_t, svint32_t, + z4_res = svget4_s32 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_s32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_s32_z4_1, svint32x4_t, svint32_t, + z4_res = svget4_s32 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_s32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_s32_z4_2, svint32x4_t, svint32_t, + z4_res = svget4_s32 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_s32_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_s32_z4_3, svint32x4_t, svint32_t, + z4_res = svget4_s32 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_s32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_s32_z5_0, svint32x4_t, svint32_t, + z5_res = svget4_s32 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_s32_z5_1: +** ret +*/ +TEST_GET (get4_s32_z5_1, svint32x4_t, svint32_t, + z5_res = svget4_s32 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_s32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_s32_z5_2, svint32x4_t, svint32_t, + z5_res = svget4_s32 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_s32_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_s32_z5_3, svint32x4_t, svint32_t, + z5_res = svget4_s32 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_s32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_s32_z6_0, svint32x4_t, svint32_t, + z6_res = svget4_s32 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_s32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_s32_z6_1, svint32x4_t, svint32_t, + z6_res = svget4_s32 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_s32_z6_2: +** ret +*/ +TEST_GET (get4_s32_z6_2, svint32x4_t, svint32_t, + z6_res = svget4_s32 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_s32_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_s32_z6_3, svint32x4_t, svint32_t, + z6_res = svget4_s32 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_s32_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_s32_z7_0, svint32x4_t, svint32_t, + z7_res = svget4_s32 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_s32_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_s32_z7_1, svint32x4_t, svint32_t, + z7_res = svget4_s32 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_s32_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_s32_z7_2, svint32x4_t, svint32_t, + z7_res = svget4_s32 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_s32_z7_3: +** ret +*/ +TEST_GET (get4_s32_z7_3, svint32x4_t, svint32_t, + z7_res = svget4_s32 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s64.c new file mode 100644 index 00000000000..a17e2779cb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s64.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_s64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_s64_z0_0, svint64x4_t, svint64_t, + z0 = svget4_s64 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_s64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_s64_z0_1, svint64x4_t, svint64_t, + z0 = svget4_s64 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_s64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_s64_z0_2, svint64x4_t, svint64_t, + z0 = svget4_s64 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_s64_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_s64_z0_3, svint64x4_t, svint64_t, + z0 = svget4_s64 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_s64_z4_0: +** ret +*/ +TEST_GET (get4_s64_z4_0, svint64x4_t, svint64_t, + z4_res = svget4_s64 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_s64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_s64_z4_1, svint64x4_t, svint64_t, + z4_res = svget4_s64 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_s64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_s64_z4_2, svint64x4_t, svint64_t, + z4_res = svget4_s64 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_s64_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_s64_z4_3, svint64x4_t, svint64_t, + z4_res = svget4_s64 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_s64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_s64_z5_0, svint64x4_t, svint64_t, + z5_res = svget4_s64 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_s64_z5_1: +** ret +*/ +TEST_GET (get4_s64_z5_1, svint64x4_t, svint64_t, + z5_res = svget4_s64 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_s64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_s64_z5_2, svint64x4_t, svint64_t, + z5_res = svget4_s64 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_s64_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_s64_z5_3, svint64x4_t, svint64_t, + z5_res = svget4_s64 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_s64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_s64_z6_0, svint64x4_t, svint64_t, + z6_res = svget4_s64 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_s64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_s64_z6_1, svint64x4_t, svint64_t, + z6_res = svget4_s64 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_s64_z6_2: +** ret +*/ +TEST_GET (get4_s64_z6_2, svint64x4_t, svint64_t, + z6_res = svget4_s64 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_s64_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_s64_z6_3, svint64x4_t, svint64_t, + z6_res = svget4_s64 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_s64_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_s64_z7_0, svint64x4_t, svint64_t, + z7_res = svget4_s64 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_s64_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_s64_z7_1, svint64x4_t, svint64_t, + z7_res = svget4_s64 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_s64_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_s64_z7_2, svint64x4_t, svint64_t, + z7_res = svget4_s64 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_s64_z7_3: +** ret +*/ +TEST_GET (get4_s64_z7_3, svint64x4_t, svint64_t, + z7_res = svget4_s64 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s8.c new file mode 100644 index 00000000000..9fa15959744 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_s8.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_s8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_s8_z0_0, svint8x4_t, svint8_t, + z0 = svget4_s8 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_s8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_s8_z0_1, svint8x4_t, svint8_t, + z0 = svget4_s8 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_s8_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_s8_z0_2, svint8x4_t, svint8_t, + z0 = svget4_s8 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_s8_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_s8_z0_3, svint8x4_t, svint8_t, + z0 = svget4_s8 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_s8_z4_0: +** ret +*/ +TEST_GET (get4_s8_z4_0, svint8x4_t, svint8_t, + z4_res = svget4_s8 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_s8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_s8_z4_1, svint8x4_t, svint8_t, + z4_res = svget4_s8 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_s8_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_s8_z4_2, svint8x4_t, svint8_t, + z4_res = svget4_s8 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_s8_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_s8_z4_3, svint8x4_t, svint8_t, + z4_res = svget4_s8 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_s8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_s8_z5_0, svint8x4_t, svint8_t, + z5_res = svget4_s8 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_s8_z5_1: +** ret +*/ +TEST_GET (get4_s8_z5_1, svint8x4_t, svint8_t, + z5_res = svget4_s8 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_s8_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_s8_z5_2, svint8x4_t, svint8_t, + z5_res = svget4_s8 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_s8_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_s8_z5_3, svint8x4_t, svint8_t, + z5_res = svget4_s8 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_s8_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_s8_z6_0, svint8x4_t, svint8_t, + z6_res = svget4_s8 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_s8_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_s8_z6_1, svint8x4_t, svint8_t, + z6_res = svget4_s8 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_s8_z6_2: +** ret +*/ +TEST_GET (get4_s8_z6_2, svint8x4_t, svint8_t, + z6_res = svget4_s8 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_s8_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_s8_z6_3, svint8x4_t, svint8_t, + z6_res = svget4_s8 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_s8_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_s8_z7_0, svint8x4_t, svint8_t, + z7_res = svget4_s8 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_s8_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_s8_z7_1, svint8x4_t, svint8_t, + z7_res = svget4_s8 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_s8_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_s8_z7_2, svint8x4_t, svint8_t, + z7_res = svget4_s8 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_s8_z7_3: +** ret +*/ +TEST_GET (get4_s8_z7_3, svint8x4_t, svint8_t, + z7_res = svget4_s8 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u16.c new file mode 100644 index 00000000000..8f17ad213a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u16.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_u16_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_u16_z0_0, svuint16x4_t, svuint16_t, + z0 = svget4_u16 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_u16_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_u16_z0_1, svuint16x4_t, svuint16_t, + z0 = svget4_u16 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_u16_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_u16_z0_2, svuint16x4_t, svuint16_t, + z0 = svget4_u16 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_u16_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_u16_z0_3, svuint16x4_t, svuint16_t, + z0 = svget4_u16 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_u16_z4_0: +** ret +*/ +TEST_GET (get4_u16_z4_0, svuint16x4_t, svuint16_t, + z4_res = svget4_u16 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_u16_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_u16_z4_1, svuint16x4_t, svuint16_t, + z4_res = svget4_u16 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_u16_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_u16_z4_2, svuint16x4_t, svuint16_t, + z4_res = svget4_u16 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_u16_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_u16_z4_3, svuint16x4_t, svuint16_t, + z4_res = svget4_u16 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_u16_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_u16_z5_0, svuint16x4_t, svuint16_t, + z5_res = svget4_u16 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_u16_z5_1: +** ret +*/ +TEST_GET (get4_u16_z5_1, svuint16x4_t, svuint16_t, + z5_res = svget4_u16 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_u16_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_u16_z5_2, svuint16x4_t, svuint16_t, + z5_res = svget4_u16 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_u16_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_u16_z5_3, svuint16x4_t, svuint16_t, + z5_res = svget4_u16 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_u16_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_u16_z6_0, svuint16x4_t, svuint16_t, + z6_res = svget4_u16 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_u16_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_u16_z6_1, svuint16x4_t, svuint16_t, + z6_res = svget4_u16 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_u16_z6_2: +** ret +*/ +TEST_GET (get4_u16_z6_2, svuint16x4_t, svuint16_t, + z6_res = svget4_u16 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_u16_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_u16_z6_3, svuint16x4_t, svuint16_t, + z6_res = svget4_u16 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_u16_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_u16_z7_0, svuint16x4_t, svuint16_t, + z7_res = svget4_u16 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_u16_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_u16_z7_1, svuint16x4_t, svuint16_t, + z7_res = svget4_u16 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_u16_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_u16_z7_2, svuint16x4_t, svuint16_t, + z7_res = svget4_u16 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_u16_z7_3: +** ret +*/ +TEST_GET (get4_u16_z7_3, svuint16x4_t, svuint16_t, + z7_res = svget4_u16 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u32.c new file mode 100644 index 00000000000..e6c94b39d94 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u32.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_u32_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_u32_z0_0, svuint32x4_t, svuint32_t, + z0 = svget4_u32 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_u32_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_u32_z0_1, svuint32x4_t, svuint32_t, + z0 = svget4_u32 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_u32_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_u32_z0_2, svuint32x4_t, svuint32_t, + z0 = svget4_u32 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_u32_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_u32_z0_3, svuint32x4_t, svuint32_t, + z0 = svget4_u32 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_u32_z4_0: +** ret +*/ +TEST_GET (get4_u32_z4_0, svuint32x4_t, svuint32_t, + z4_res = svget4_u32 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_u32_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_u32_z4_1, svuint32x4_t, svuint32_t, + z4_res = svget4_u32 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_u32_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_u32_z4_2, svuint32x4_t, svuint32_t, + z4_res = svget4_u32 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_u32_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_u32_z4_3, svuint32x4_t, svuint32_t, + z4_res = svget4_u32 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_u32_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_u32_z5_0, svuint32x4_t, svuint32_t, + z5_res = svget4_u32 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_u32_z5_1: +** ret +*/ +TEST_GET (get4_u32_z5_1, svuint32x4_t, svuint32_t, + z5_res = svget4_u32 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_u32_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_u32_z5_2, svuint32x4_t, svuint32_t, + z5_res = svget4_u32 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_u32_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_u32_z5_3, svuint32x4_t, svuint32_t, + z5_res = svget4_u32 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_u32_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_u32_z6_0, svuint32x4_t, svuint32_t, + z6_res = svget4_u32 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_u32_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_u32_z6_1, svuint32x4_t, svuint32_t, + z6_res = svget4_u32 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_u32_z6_2: +** ret +*/ +TEST_GET (get4_u32_z6_2, svuint32x4_t, svuint32_t, + z6_res = svget4_u32 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_u32_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_u32_z6_3, svuint32x4_t, svuint32_t, + z6_res = svget4_u32 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_u32_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_u32_z7_0, svuint32x4_t, svuint32_t, + z7_res = svget4_u32 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_u32_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_u32_z7_1, svuint32x4_t, svuint32_t, + z7_res = svget4_u32 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_u32_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_u32_z7_2, svuint32x4_t, svuint32_t, + z7_res = svget4_u32 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_u32_z7_3: +** ret +*/ +TEST_GET (get4_u32_z7_3, svuint32x4_t, svuint32_t, + z7_res = svget4_u32 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u64.c new file mode 100644 index 00000000000..79c293a2ceb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u64.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_u64_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_u64_z0_0, svuint64x4_t, svuint64_t, + z0 = svget4_u64 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_u64_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_u64_z0_1, svuint64x4_t, svuint64_t, + z0 = svget4_u64 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_u64_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_u64_z0_2, svuint64x4_t, svuint64_t, + z0 = svget4_u64 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_u64_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_u64_z0_3, svuint64x4_t, svuint64_t, + z0 = svget4_u64 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_u64_z4_0: +** ret +*/ +TEST_GET (get4_u64_z4_0, svuint64x4_t, svuint64_t, + z4_res = svget4_u64 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_u64_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_u64_z4_1, svuint64x4_t, svuint64_t, + z4_res = svget4_u64 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_u64_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_u64_z4_2, svuint64x4_t, svuint64_t, + z4_res = svget4_u64 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_u64_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_u64_z4_3, svuint64x4_t, svuint64_t, + z4_res = svget4_u64 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_u64_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_u64_z5_0, svuint64x4_t, svuint64_t, + z5_res = svget4_u64 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_u64_z5_1: +** ret +*/ +TEST_GET (get4_u64_z5_1, svuint64x4_t, svuint64_t, + z5_res = svget4_u64 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_u64_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_u64_z5_2, svuint64x4_t, svuint64_t, + z5_res = svget4_u64 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_u64_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_u64_z5_3, svuint64x4_t, svuint64_t, + z5_res = svget4_u64 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_u64_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_u64_z6_0, svuint64x4_t, svuint64_t, + z6_res = svget4_u64 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_u64_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_u64_z6_1, svuint64x4_t, svuint64_t, + z6_res = svget4_u64 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_u64_z6_2: +** ret +*/ +TEST_GET (get4_u64_z6_2, svuint64x4_t, svuint64_t, + z6_res = svget4_u64 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_u64_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_u64_z6_3, svuint64x4_t, svuint64_t, + z6_res = svget4_u64 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_u64_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_u64_z7_0, svuint64x4_t, svuint64_t, + z7_res = svget4_u64 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_u64_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_u64_z7_1, svuint64x4_t, svuint64_t, + z7_res = svget4_u64 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_u64_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_u64_z7_2, svuint64x4_t, svuint64_t, + z7_res = svget4_u64 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_u64_z7_3: +** ret +*/ +TEST_GET (get4_u64_z7_3, svuint64x4_t, svuint64_t, + z7_res = svget4_u64 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u8.c new file mode 100644 index 00000000000..f3ad9a85b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/get4_u8.c @@ -0,0 +1,179 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** get4_u8_z0_0: +** mov z0\.d, z4\.d +** ret +*/ +TEST_GET (get4_u8_z0_0, svuint8x4_t, svuint8_t, + z0 = svget4_u8 (z4, 0), + z0 = svget4 (z4, 0)) + +/* +** get4_u8_z0_1: +** mov z0\.d, z5\.d +** ret +*/ +TEST_GET (get4_u8_z0_1, svuint8x4_t, svuint8_t, + z0 = svget4_u8 (z4, 1), + z0 = svget4 (z4, 1)) + +/* +** get4_u8_z0_2: +** mov z0\.d, z6\.d +** ret +*/ +TEST_GET (get4_u8_z0_2, svuint8x4_t, svuint8_t, + z0 = svget4_u8 (z4, 2), + z0 = svget4 (z4, 2)) + +/* +** get4_u8_z0_3: +** mov z0\.d, z7\.d +** ret +*/ +TEST_GET (get4_u8_z0_3, svuint8x4_t, svuint8_t, + z0 = svget4_u8 (z4, 3), + z0 = svget4 (z4, 3)) + +/* +** get4_u8_z4_0: +** ret +*/ +TEST_GET (get4_u8_z4_0, svuint8x4_t, svuint8_t, + z4_res = svget4_u8 (z4, 0), + z4_res = svget4 (z4, 0)) + +/* +** get4_u8_z4_1: +** mov z4\.d, z5\.d +** ret +*/ +TEST_GET (get4_u8_z4_1, svuint8x4_t, svuint8_t, + z4_res = svget4_u8 (z4, 1), + z4_res = svget4 (z4, 1)) + +/* +** get4_u8_z4_2: +** mov z4\.d, z6\.d +** ret +*/ +TEST_GET (get4_u8_z4_2, svuint8x4_t, svuint8_t, + z4_res = svget4_u8 (z4, 2), + z4_res = svget4 (z4, 2)) + +/* +** get4_u8_z4_3: +** mov z4\.d, z7\.d +** ret +*/ +TEST_GET (get4_u8_z4_3, svuint8x4_t, svuint8_t, + z4_res = svget4_u8 (z4, 3), + z4_res = svget4 (z4, 3)) + +/* +** get4_u8_z5_0: +** mov z5\.d, z4\.d +** ret +*/ +TEST_GET (get4_u8_z5_0, svuint8x4_t, svuint8_t, + z5_res = svget4_u8 (z4, 0), + z5_res = svget4 (z4, 0)) + +/* +** get4_u8_z5_1: +** ret +*/ +TEST_GET (get4_u8_z5_1, svuint8x4_t, svuint8_t, + z5_res = svget4_u8 (z4, 1), + z5_res = svget4 (z4, 1)) + +/* +** get4_u8_z5_2: +** mov z5\.d, z6\.d +** ret +*/ +TEST_GET (get4_u8_z5_2, svuint8x4_t, svuint8_t, + z5_res = svget4_u8 (z4, 2), + z5_res = svget4 (z4, 2)) + +/* +** get4_u8_z5_3: +** mov z5\.d, z7\.d +** ret +*/ +TEST_GET (get4_u8_z5_3, svuint8x4_t, svuint8_t, + z5_res = svget4_u8 (z4, 3), + z5_res = svget4 (z4, 3)) + +/* +** get4_u8_z6_0: +** mov z6\.d, z4\.d +** ret +*/ +TEST_GET (get4_u8_z6_0, svuint8x4_t, svuint8_t, + z6_res = svget4_u8 (z4, 0), + z6_res = svget4 (z4, 0)) + +/* +** get4_u8_z6_1: +** mov z6\.d, z5\.d +** ret +*/ +TEST_GET (get4_u8_z6_1, svuint8x4_t, svuint8_t, + z6_res = svget4_u8 (z4, 1), + z6_res = svget4 (z4, 1)) + +/* +** get4_u8_z6_2: +** ret +*/ +TEST_GET (get4_u8_z6_2, svuint8x4_t, svuint8_t, + z6_res = svget4_u8 (z4, 2), + z6_res = svget4 (z4, 2)) + +/* +** get4_u8_z6_3: +** mov z6\.d, z7\.d +** ret +*/ +TEST_GET (get4_u8_z6_3, svuint8x4_t, svuint8_t, + z6_res = svget4_u8 (z4, 3), + z6_res = svget4 (z4, 3)) + +/* +** get4_u8_z7_0: +** mov z7\.d, z4\.d +** ret +*/ +TEST_GET (get4_u8_z7_0, svuint8x4_t, svuint8_t, + z7_res = svget4_u8 (z4, 0), + z7_res = svget4 (z4, 0)) + +/* +** get4_u8_z7_1: +** mov z7\.d, z5\.d +** ret +*/ +TEST_GET (get4_u8_z7_1, svuint8x4_t, svuint8_t, + z7_res = svget4_u8 (z4, 1), + z7_res = svget4 (z4, 1)) + +/* +** get4_u8_z7_2: +** mov z7\.d, z6\.d +** ret +*/ +TEST_GET (get4_u8_z7_2, svuint8x4_t, svuint8_t, + z7_res = svget4_u8 (z4, 2), + z7_res = svget4 (z4, 2)) + +/* +** get4_u8_z7_3: +** ret +*/ +TEST_GET (get4_u8_z7_3, svuint8x4_t, svuint8_t, + z7_res = svget4_u8 (z4, 3), + z7_res = svget4 (z4, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s16.c new file mode 100644 index 00000000000..90a1434f1e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s16.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_s16_w0_w1: +** index z0\.h, w0, w1 +** ret +*/ +TEST_S (index_s16_w0_w1, svint16_t, int16_t, + z0 = svindex_s16 (x0, x1)) + +/* +** index_s16_w0_2: +** index z0\.h, w0, #2 +** ret +*/ +TEST_S (index_s16_w0_2, svint16_t, int16_t, + z0 = svindex_s16 (x0, 2)) + +/* +** index_s16_50_2: +** mov (w[0-9]+), 50 +** index z0\.h, \1, #2 +** ret +*/ +TEST_S (index_s16_50_2, svint16_t, int16_t, + z0 = svindex_s16 (50, 2)) + +/* +** index_s16_0_m17: +** mov (w[0-9]+), -17 +** index z0\.h, #0, \1 +** ret +*/ +TEST_S (index_s16_0_m17, svint16_t, int16_t, + z0 = svindex_s16 (0, -17)) + +/* +** index_s16_0_m16: +** index z0\.h, #0, #-16 +** ret +*/ +TEST_S (index_s16_0_m16, svint16_t, int16_t, + z0 = svindex_s16 (0, -16)) + +/* +** index_s16_0_1: +** index z0\.h, #0, #1 +** ret +*/ +TEST_S (index_s16_0_1, svint16_t, int16_t, + z0 = svindex_s16 (0, 1)) + +/* +** index_s16_0_15: +** index z0\.h, #0, #15 +** ret +*/ +TEST_S (index_s16_0_15, svint16_t, int16_t, + z0 = svindex_s16 (0, 15)) + +/* +** index_s16_0_16: +** mov (w[0-9]+), 16 +** index z0\.h, #0, \1 +** ret +*/ +TEST_S (index_s16_0_16, svint16_t, int16_t, + z0 = svindex_s16 (0, 16)) + +/* +** index_s16_m17_1: +** mov (w[0-9]+), -17 +** index z0\.h, \1, #1 +** ret +*/ +TEST_S (index_s16_m17_1, svint16_t, int16_t, + z0 = svindex_s16 (-17, 1)) + +/* +** index_s16_m16_1: +** index z0\.h, #-16, #1 +** ret +*/ +TEST_S (index_s16_m16_1, svint16_t, int16_t, + z0 = svindex_s16 (-16, 1)) + +/* +** index_s16_m1_1: +** index z0\.h, #-1, #1 +** ret +*/ +TEST_S (index_s16_m1_1, svint16_t, int16_t, + z0 = svindex_s16 (-1, 1)) + +/* +** index_s16_1_1: +** index z0\.h, #1, #1 +** ret +*/ +TEST_S (index_s16_1_1, svint16_t, int16_t, + z0 = svindex_s16 (1, 1)) + +/* +** index_s16_15_1: +** index z0\.h, #15, #1 +** ret +*/ +TEST_S (index_s16_15_1, svint16_t, int16_t, + z0 = svindex_s16 (15, 1)) + +/* +** index_s16_16_1: +** mov (w[0-9]+), 16 +** index z0\.h, \1, #1 +** ret +*/ +TEST_S (index_s16_16_1, svint16_t, int16_t, + z0 = svindex_s16 (16, 1)) + +/* +** index_s16_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.h, \1, w0 +** ret +*/ +TEST_S (index_s16_m17_x0, svint16_t, int16_t, + z0 = svindex_s16 (-17, x0)) + +/* +** index_s16_m16_x0: +** index z0\.h, #-16, w0 +** ret +*/ +TEST_S (index_s16_m16_x0, svint16_t, int16_t, + z0 = svindex_s16 (-16, x0)) + +/* +** index_s16_m1_x0: +** index z0\.h, #-1, w0 +** ret +*/ +TEST_S (index_s16_m1_x0, svint16_t, int16_t, + z0 = svindex_s16 (-1, x0)) + +/* +** index_s16_0_x0: +** index z0\.h, #0, w0 +** ret +*/ +TEST_S (index_s16_0_x0, svint16_t, int16_t, + z0 = svindex_s16 (0, x0)) + +/* +** index_s16_1_x0: +** index z0\.h, #1, w0 +** ret +*/ +TEST_S (index_s16_1_x0, svint16_t, int16_t, + z0 = svindex_s16 (1, x0)) + +/* +** index_s16_15_x0: +** index z0\.h, #15, w0 +** ret +*/ +TEST_S (index_s16_15_x0, svint16_t, int16_t, + z0 = svindex_s16 (15, x0)) + +/* +** index_s16_16_x0: +** mov (w[0-9]+), 16 +** index z0\.h, \1, w0 +** ret +*/ +TEST_S (index_s16_16_x0, svint16_t, int16_t, + z0 = svindex_s16 (16, x0)) + +/* +** index_s16_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.h, w0, \1 +** ret +*/ +TEST_S (index_s16_x0_m17, svint16_t, int16_t, + z0 = svindex_s16 (x0, -17)) + +/* +** index_s16_x0_m16: +** index z0\.h, w0, #-16 +** ret +*/ +TEST_S (index_s16_x0_m16, svint16_t, int16_t, + z0 = svindex_s16 (x0, -16)) + +/* +** index_s16_x0_1: +** index z0\.h, w0, #1 +** ret +*/ +TEST_S (index_s16_x0_1, svint16_t, int16_t, + z0 = svindex_s16 (x0, 1)) + +/* +** index_s16_x0_15: +** index z0\.h, w0, #15 +** ret +*/ +TEST_S (index_s16_x0_15, svint16_t, int16_t, + z0 = svindex_s16 (x0, 15)) + +/* +** index_s16_x0_16: +** mov (w[0-9]+), 16 +** index z0\.h, w0, \1 +** ret +*/ +TEST_S (index_s16_x0_16, svint16_t, int16_t, + z0 = svindex_s16 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s32.c new file mode 100644 index 00000000000..18afedac029 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s32.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_s32_w0_w1: +** index z0\.s, w0, w1 +** ret +*/ +TEST_S (index_s32_w0_w1, svint32_t, int32_t, + z0 = svindex_s32 (x0, x1)) + +/* +** index_s32_w0_2: +** index z0\.s, w0, #2 +** ret +*/ +TEST_S (index_s32_w0_2, svint32_t, int32_t, + z0 = svindex_s32 (x0, 2)) + +/* +** index_s32_50_2: +** mov (w[0-9]+), 50 +** index z0\.s, \1, #2 +** ret +*/ +TEST_S (index_s32_50_2, svint32_t, int32_t, + z0 = svindex_s32 (50, 2)) + +/* +** index_s32_0_m17: +** mov (w[0-9]+), -17 +** index z0\.s, #0, \1 +** ret +*/ +TEST_S (index_s32_0_m17, svint32_t, int32_t, + z0 = svindex_s32 (0, -17)) + +/* +** index_s32_0_m16: +** index z0\.s, #0, #-16 +** ret +*/ +TEST_S (index_s32_0_m16, svint32_t, int32_t, + z0 = svindex_s32 (0, -16)) + +/* +** index_s32_0_1: +** index z0\.s, #0, #1 +** ret +*/ +TEST_S (index_s32_0_1, svint32_t, int32_t, + z0 = svindex_s32 (0, 1)) + +/* +** index_s32_0_15: +** index z0\.s, #0, #15 +** ret +*/ +TEST_S (index_s32_0_15, svint32_t, int32_t, + z0 = svindex_s32 (0, 15)) + +/* +** index_s32_0_16: +** mov (w[0-9]+), 16 +** index z0\.s, #0, \1 +** ret +*/ +TEST_S (index_s32_0_16, svint32_t, int32_t, + z0 = svindex_s32 (0, 16)) + +/* +** index_s32_m17_1: +** mov (w[0-9]+), -17 +** index z0\.s, \1, #1 +** ret +*/ +TEST_S (index_s32_m17_1, svint32_t, int32_t, + z0 = svindex_s32 (-17, 1)) + +/* +** index_s32_m16_1: +** index z0\.s, #-16, #1 +** ret +*/ +TEST_S (index_s32_m16_1, svint32_t, int32_t, + z0 = svindex_s32 (-16, 1)) + +/* +** index_s32_m1_1: +** index z0\.s, #-1, #1 +** ret +*/ +TEST_S (index_s32_m1_1, svint32_t, int32_t, + z0 = svindex_s32 (-1, 1)) + +/* +** index_s32_1_1: +** index z0\.s, #1, #1 +** ret +*/ +TEST_S (index_s32_1_1, svint32_t, int32_t, + z0 = svindex_s32 (1, 1)) + +/* +** index_s32_15_1: +** index z0\.s, #15, #1 +** ret +*/ +TEST_S (index_s32_15_1, svint32_t, int32_t, + z0 = svindex_s32 (15, 1)) + +/* +** index_s32_16_1: +** mov (w[0-9]+), 16 +** index z0\.s, \1, #1 +** ret +*/ +TEST_S (index_s32_16_1, svint32_t, int32_t, + z0 = svindex_s32 (16, 1)) + +/* +** index_s32_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.s, \1, w0 +** ret +*/ +TEST_S (index_s32_m17_x0, svint32_t, int32_t, + z0 = svindex_s32 (-17, x0)) + +/* +** index_s32_m16_x0: +** index z0\.s, #-16, w0 +** ret +*/ +TEST_S (index_s32_m16_x0, svint32_t, int32_t, + z0 = svindex_s32 (-16, x0)) + +/* +** index_s32_m1_x0: +** index z0\.s, #-1, w0 +** ret +*/ +TEST_S (index_s32_m1_x0, svint32_t, int32_t, + z0 = svindex_s32 (-1, x0)) + +/* +** index_s32_0_x0: +** index z0\.s, #0, w0 +** ret +*/ +TEST_S (index_s32_0_x0, svint32_t, int32_t, + z0 = svindex_s32 (0, x0)) + +/* +** index_s32_1_x0: +** index z0\.s, #1, w0 +** ret +*/ +TEST_S (index_s32_1_x0, svint32_t, int32_t, + z0 = svindex_s32 (1, x0)) + +/* +** index_s32_15_x0: +** index z0\.s, #15, w0 +** ret +*/ +TEST_S (index_s32_15_x0, svint32_t, int32_t, + z0 = svindex_s32 (15, x0)) + +/* +** index_s32_16_x0: +** mov (w[0-9]+), 16 +** index z0\.s, \1, w0 +** ret +*/ +TEST_S (index_s32_16_x0, svint32_t, int32_t, + z0 = svindex_s32 (16, x0)) + +/* +** index_s32_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.s, w0, \1 +** ret +*/ +TEST_S (index_s32_x0_m17, svint32_t, int32_t, + z0 = svindex_s32 (x0, -17)) + +/* +** index_s32_x0_m16: +** index z0\.s, w0, #-16 +** ret +*/ +TEST_S (index_s32_x0_m16, svint32_t, int32_t, + z0 = svindex_s32 (x0, -16)) + +/* +** index_s32_x0_1: +** index z0\.s, w0, #1 +** ret +*/ +TEST_S (index_s32_x0_1, svint32_t, int32_t, + z0 = svindex_s32 (x0, 1)) + +/* +** index_s32_x0_15: +** index z0\.s, w0, #15 +** ret +*/ +TEST_S (index_s32_x0_15, svint32_t, int32_t, + z0 = svindex_s32 (x0, 15)) + +/* +** index_s32_x0_16: +** mov (w[0-9]+), 16 +** index z0\.s, w0, \1 +** ret +*/ +TEST_S (index_s32_x0_16, svint32_t, int32_t, + z0 = svindex_s32 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s64.c new file mode 100644 index 00000000000..298eec9eaf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s64.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_s64_x0_x1: +** index z0\.d, x0, x1 +** ret +*/ +TEST_S (index_s64_x0_x1, svint64_t, int64_t, + z0 = svindex_s64 (x0, x1)) + +/* +** index_s64_x0_2: +** index z0\.d, x0, #2 +** ret +*/ +TEST_S (index_s64_x0_2, svint64_t, int64_t, + z0 = svindex_s64 (x0, 2)) + +/* +** index_s64_50_2: +** mov (x[0-9]+), 50 +** index z0\.d, \1, #2 +** ret +*/ +TEST_S (index_s64_50_2, svint64_t, int64_t, + z0 = svindex_s64 (50, 2)) + +/* +** index_s64_0_m17: +** mov (x[0-9]+), -17 +** index z0\.d, #0, \1 +** ret +*/ +TEST_S (index_s64_0_m17, svint64_t, int64_t, + z0 = svindex_s64 (0, -17)) + +/* +** index_s64_0_m16: +** index z0\.d, #0, #-16 +** ret +*/ +TEST_S (index_s64_0_m16, svint64_t, int64_t, + z0 = svindex_s64 (0, -16)) + +/* +** index_s64_0_1: +** index z0\.d, #0, #1 +** ret +*/ +TEST_S (index_s64_0_1, svint64_t, int64_t, + z0 = svindex_s64 (0, 1)) + +/* +** index_s64_0_15: +** index z0\.d, #0, #15 +** ret +*/ +TEST_S (index_s64_0_15, svint64_t, int64_t, + z0 = svindex_s64 (0, 15)) + +/* +** index_s64_0_16: +** mov (x[0-9]+), 16 +** index z0\.d, #0, \1 +** ret +*/ +TEST_S (index_s64_0_16, svint64_t, int64_t, + z0 = svindex_s64 (0, 16)) + +/* +** index_s64_m17_1: +** mov (x[0-9]+), -17 +** index z0\.d, \1, #1 +** ret +*/ +TEST_S (index_s64_m17_1, svint64_t, int64_t, + z0 = svindex_s64 (-17, 1)) + +/* +** index_s64_m16_1: +** index z0\.d, #-16, #1 +** ret +*/ +TEST_S (index_s64_m16_1, svint64_t, int64_t, + z0 = svindex_s64 (-16, 1)) + +/* +** index_s64_m1_1: +** index z0\.d, #-1, #1 +** ret +*/ +TEST_S (index_s64_m1_1, svint64_t, int64_t, + z0 = svindex_s64 (-1, 1)) + +/* +** index_s64_1_1: +** index z0\.d, #1, #1 +** ret +*/ +TEST_S (index_s64_1_1, svint64_t, int64_t, + z0 = svindex_s64 (1, 1)) + +/* +** index_s64_15_1: +** index z0\.d, #15, #1 +** ret +*/ +TEST_S (index_s64_15_1, svint64_t, int64_t, + z0 = svindex_s64 (15, 1)) + +/* +** index_s64_16_1: +** mov (x[0-9]+), 16 +** index z0\.d, \1, #1 +** ret +*/ +TEST_S (index_s64_16_1, svint64_t, int64_t, + z0 = svindex_s64 (16, 1)) + +/* +** index_s64_m17_x0: +** mov (x[0-9]+), -17 +** index z0\.d, \1, x0 +** ret +*/ +TEST_S (index_s64_m17_x0, svint64_t, int64_t, + z0 = svindex_s64 (-17, x0)) + +/* +** index_s64_m16_x0: +** index z0\.d, #-16, x0 +** ret +*/ +TEST_S (index_s64_m16_x0, svint64_t, int64_t, + z0 = svindex_s64 (-16, x0)) + +/* +** index_s64_m1_x0: +** index z0\.d, #-1, x0 +** ret +*/ +TEST_S (index_s64_m1_x0, svint64_t, int64_t, + z0 = svindex_s64 (-1, x0)) + +/* +** index_s64_0_x0: +** index z0\.d, #0, x0 +** ret +*/ +TEST_S (index_s64_0_x0, svint64_t, int64_t, + z0 = svindex_s64 (0, x0)) + +/* +** index_s64_1_x0: +** index z0\.d, #1, x0 +** ret +*/ +TEST_S (index_s64_1_x0, svint64_t, int64_t, + z0 = svindex_s64 (1, x0)) + +/* +** index_s64_15_x0: +** index z0\.d, #15, x0 +** ret +*/ +TEST_S (index_s64_15_x0, svint64_t, int64_t, + z0 = svindex_s64 (15, x0)) + +/* +** index_s64_16_x0: +** mov (x[0-9]+), 16 +** index z0\.d, \1, x0 +** ret +*/ +TEST_S (index_s64_16_x0, svint64_t, int64_t, + z0 = svindex_s64 (16, x0)) + +/* +** index_s64_x0_m17: +** mov (x[0-9]+), -17 +** index z0\.d, x0, \1 +** ret +*/ +TEST_S (index_s64_x0_m17, svint64_t, int64_t, + z0 = svindex_s64 (x0, -17)) + +/* +** index_s64_x0_m16: +** index z0\.d, x0, #-16 +** ret +*/ +TEST_S (index_s64_x0_m16, svint64_t, int64_t, + z0 = svindex_s64 (x0, -16)) + +/* +** index_s64_x0_1: +** index z0\.d, x0, #1 +** ret +*/ +TEST_S (index_s64_x0_1, svint64_t, int64_t, + z0 = svindex_s64 (x0, 1)) + +/* +** index_s64_x0_15: +** index z0\.d, x0, #15 +** ret +*/ +TEST_S (index_s64_x0_15, svint64_t, int64_t, + z0 = svindex_s64 (x0, 15)) + +/* +** index_s64_x0_16: +** mov (x[0-9]+), 16 +** index z0\.d, x0, \1 +** ret +*/ +TEST_S (index_s64_x0_16, svint64_t, int64_t, + z0 = svindex_s64 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s8.c new file mode 100644 index 00000000000..8a1f14f507e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_s8.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_s8_w0_w1: +** index z0\.b, w0, w1 +** ret +*/ +TEST_S (index_s8_w0_w1, svint8_t, int8_t, + z0 = svindex_s8 (x0, x1)) + +/* +** index_s8_w0_2: +** index z0\.b, w0, #2 +** ret +*/ +TEST_S (index_s8_w0_2, svint8_t, int8_t, + z0 = svindex_s8 (x0, 2)) + +/* +** index_s8_50_2: +** mov (w[0-9]+), 50 +** index z0\.b, \1, #2 +** ret +*/ +TEST_S (index_s8_50_2, svint8_t, int8_t, + z0 = svindex_s8 (50, 2)) + +/* +** index_s8_0_m17: +** mov (w[0-9]+), -17 +** index z0\.b, #0, \1 +** ret +*/ +TEST_S (index_s8_0_m17, svint8_t, int8_t, + z0 = svindex_s8 (0, -17)) + +/* +** index_s8_0_m16: +** index z0\.b, #0, #-16 +** ret +*/ +TEST_S (index_s8_0_m16, svint8_t, int8_t, + z0 = svindex_s8 (0, -16)) + +/* +** index_s8_0_1: +** index z0\.b, #0, #1 +** ret +*/ +TEST_S (index_s8_0_1, svint8_t, int8_t, + z0 = svindex_s8 (0, 1)) + +/* +** index_s8_0_15: +** index z0\.b, #0, #15 +** ret +*/ +TEST_S (index_s8_0_15, svint8_t, int8_t, + z0 = svindex_s8 (0, 15)) + +/* +** index_s8_0_16: +** mov (w[0-9]+), 16 +** index z0\.b, #0, \1 +** ret +*/ +TEST_S (index_s8_0_16, svint8_t, int8_t, + z0 = svindex_s8 (0, 16)) + +/* +** index_s8_m17_1: +** mov (w[0-9]+), -17 +** index z0\.b, \1, #1 +** ret +*/ +TEST_S (index_s8_m17_1, svint8_t, int8_t, + z0 = svindex_s8 (-17, 1)) + +/* +** index_s8_m16_1: +** index z0\.b, #-16, #1 +** ret +*/ +TEST_S (index_s8_m16_1, svint8_t, int8_t, + z0 = svindex_s8 (-16, 1)) + +/* +** index_s8_m1_1: +** index z0\.b, #-1, #1 +** ret +*/ +TEST_S (index_s8_m1_1, svint8_t, int8_t, + z0 = svindex_s8 (-1, 1)) + +/* +** index_s8_1_1: +** index z0\.b, #1, #1 +** ret +*/ +TEST_S (index_s8_1_1, svint8_t, int8_t, + z0 = svindex_s8 (1, 1)) + +/* +** index_s8_15_1: +** index z0\.b, #15, #1 +** ret +*/ +TEST_S (index_s8_15_1, svint8_t, int8_t, + z0 = svindex_s8 (15, 1)) + +/* +** index_s8_16_1: +** mov (w[0-9]+), 16 +** index z0\.b, \1, #1 +** ret +*/ +TEST_S (index_s8_16_1, svint8_t, int8_t, + z0 = svindex_s8 (16, 1)) + +/* +** index_s8_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.b, \1, w0 +** ret +*/ +TEST_S (index_s8_m17_x0, svint8_t, int8_t, + z0 = svindex_s8 (-17, x0)) + +/* +** index_s8_m16_x0: +** index z0\.b, #-16, w0 +** ret +*/ +TEST_S (index_s8_m16_x0, svint8_t, int8_t, + z0 = svindex_s8 (-16, x0)) + +/* +** index_s8_m1_x0: +** index z0\.b, #-1, w0 +** ret +*/ +TEST_S (index_s8_m1_x0, svint8_t, int8_t, + z0 = svindex_s8 (-1, x0)) + +/* +** index_s8_0_x0: +** index z0\.b, #0, w0 +** ret +*/ +TEST_S (index_s8_0_x0, svint8_t, int8_t, + z0 = svindex_s8 (0, x0)) + +/* +** index_s8_1_x0: +** index z0\.b, #1, w0 +** ret +*/ +TEST_S (index_s8_1_x0, svint8_t, int8_t, + z0 = svindex_s8 (1, x0)) + +/* +** index_s8_15_x0: +** index z0\.b, #15, w0 +** ret +*/ +TEST_S (index_s8_15_x0, svint8_t, int8_t, + z0 = svindex_s8 (15, x0)) + +/* +** index_s8_16_x0: +** mov (w[0-9]+), 16 +** index z0\.b, \1, w0 +** ret +*/ +TEST_S (index_s8_16_x0, svint8_t, int8_t, + z0 = svindex_s8 (16, x0)) + +/* +** index_s8_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.b, w0, \1 +** ret +*/ +TEST_S (index_s8_x0_m17, svint8_t, int8_t, + z0 = svindex_s8 (x0, -17)) + +/* +** index_s8_x0_m16: +** index z0\.b, w0, #-16 +** ret +*/ +TEST_S (index_s8_x0_m16, svint8_t, int8_t, + z0 = svindex_s8 (x0, -16)) + +/* +** index_s8_x0_1: +** index z0\.b, w0, #1 +** ret +*/ +TEST_S (index_s8_x0_1, svint8_t, int8_t, + z0 = svindex_s8 (x0, 1)) + +/* +** index_s8_x0_15: +** index z0\.b, w0, #15 +** ret +*/ +TEST_S (index_s8_x0_15, svint8_t, int8_t, + z0 = svindex_s8 (x0, 15)) + +/* +** index_s8_x0_16: +** mov (w[0-9]+), 16 +** index z0\.b, w0, \1 +** ret +*/ +TEST_S (index_s8_x0_16, svint8_t, int8_t, + z0 = svindex_s8 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u16.c new file mode 100644 index 00000000000..1c6631088f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u16.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_u16_w0_w1: +** index z0\.h, w0, w1 +** ret +*/ +TEST_S (index_u16_w0_w1, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, x1)) + +/* +** index_u16_w0_2: +** index z0\.h, w0, #2 +** ret +*/ +TEST_S (index_u16_w0_2, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, 2)) + +/* +** index_u16_50_2: +** mov (w[0-9]+), 50 +** index z0\.h, \1, #2 +** ret +*/ +TEST_S (index_u16_50_2, svuint16_t, uint16_t, + z0 = svindex_u16 (50, 2)) + +/* +** index_u16_0_m17: +** mov (w[0-9]+), -17 +** index z0\.h, #0, \1 +** ret +*/ +TEST_S (index_u16_0_m17, svuint16_t, uint16_t, + z0 = svindex_u16 (0, -17)) + +/* +** index_u16_0_m16: +** index z0\.h, #0, #-16 +** ret +*/ +TEST_S (index_u16_0_m16, svuint16_t, uint16_t, + z0 = svindex_u16 (0, -16)) + +/* +** index_u16_0_1: +** index z0\.h, #0, #1 +** ret +*/ +TEST_S (index_u16_0_1, svuint16_t, uint16_t, + z0 = svindex_u16 (0, 1)) + +/* +** index_u16_0_15: +** index z0\.h, #0, #15 +** ret +*/ +TEST_S (index_u16_0_15, svuint16_t, uint16_t, + z0 = svindex_u16 (0, 15)) + +/* +** index_u16_0_16: +** mov (w[0-9]+), 16 +** index z0\.h, #0, \1 +** ret +*/ +TEST_S (index_u16_0_16, svuint16_t, uint16_t, + z0 = svindex_u16 (0, 16)) + +/* +** index_u16_m17_1: +** mov (w[0-9]+), -17 +** index z0\.h, \1, #1 +** ret +*/ +TEST_S (index_u16_m17_1, svuint16_t, uint16_t, + z0 = svindex_u16 (-17, 1)) + +/* +** index_u16_m16_1: +** index z0\.h, #-16, #1 +** ret +*/ +TEST_S (index_u16_m16_1, svuint16_t, uint16_t, + z0 = svindex_u16 (-16, 1)) + +/* +** index_u16_m1_1: +** index z0\.h, #-1, #1 +** ret +*/ +TEST_S (index_u16_m1_1, svuint16_t, uint16_t, + z0 = svindex_u16 (-1, 1)) + +/* +** index_u16_1_1: +** index z0\.h, #1, #1 +** ret +*/ +TEST_S (index_u16_1_1, svuint16_t, uint16_t, + z0 = svindex_u16 (1, 1)) + +/* +** index_u16_15_1: +** index z0\.h, #15, #1 +** ret +*/ +TEST_S (index_u16_15_1, svuint16_t, uint16_t, + z0 = svindex_u16 (15, 1)) + +/* +** index_u16_16_1: +** mov (w[0-9]+), 16 +** index z0\.h, \1, #1 +** ret +*/ +TEST_S (index_u16_16_1, svuint16_t, uint16_t, + z0 = svindex_u16 (16, 1)) + +/* +** index_u16_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.h, \1, w0 +** ret +*/ +TEST_S (index_u16_m17_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (-17, x0)) + +/* +** index_u16_m16_x0: +** index z0\.h, #-16, w0 +** ret +*/ +TEST_S (index_u16_m16_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (-16, x0)) + +/* +** index_u16_m1_x0: +** index z0\.h, #-1, w0 +** ret +*/ +TEST_S (index_u16_m1_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (-1, x0)) + +/* +** index_u16_0_x0: +** index z0\.h, #0, w0 +** ret +*/ +TEST_S (index_u16_0_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (0, x0)) + +/* +** index_u16_1_x0: +** index z0\.h, #1, w0 +** ret +*/ +TEST_S (index_u16_1_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (1, x0)) + +/* +** index_u16_15_x0: +** index z0\.h, #15, w0 +** ret +*/ +TEST_S (index_u16_15_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (15, x0)) + +/* +** index_u16_16_x0: +** mov (w[0-9]+), 16 +** index z0\.h, \1, w0 +** ret +*/ +TEST_S (index_u16_16_x0, svuint16_t, uint16_t, + z0 = svindex_u16 (16, x0)) + +/* +** index_u16_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.h, w0, \1 +** ret +*/ +TEST_S (index_u16_x0_m17, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, -17)) + +/* +** index_u16_x0_m16: +** index z0\.h, w0, #-16 +** ret +*/ +TEST_S (index_u16_x0_m16, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, -16)) + +/* +** index_u16_x0_1: +** index z0\.h, w0, #1 +** ret +*/ +TEST_S (index_u16_x0_1, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, 1)) + +/* +** index_u16_x0_15: +** index z0\.h, w0, #15 +** ret +*/ +TEST_S (index_u16_x0_15, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, 15)) + +/* +** index_u16_x0_16: +** mov (w[0-9]+), 16 +** index z0\.h, w0, \1 +** ret +*/ +TEST_S (index_u16_x0_16, svuint16_t, uint16_t, + z0 = svindex_u16 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u32.c new file mode 100644 index 00000000000..c2badb05efe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u32.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_u32_w0_w1: +** index z0\.s, w0, w1 +** ret +*/ +TEST_S (index_u32_w0_w1, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, x1)) + +/* +** index_u32_w0_2: +** index z0\.s, w0, #2 +** ret +*/ +TEST_S (index_u32_w0_2, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, 2)) + +/* +** index_u32_50_2: +** mov (w[0-9]+), 50 +** index z0\.s, \1, #2 +** ret +*/ +TEST_S (index_u32_50_2, svuint32_t, uint32_t, + z0 = svindex_u32 (50, 2)) + +/* +** index_u32_0_m17: +** mov (w[0-9]+), -17 +** index z0\.s, #0, \1 +** ret +*/ +TEST_S (index_u32_0_m17, svuint32_t, uint32_t, + z0 = svindex_u32 (0, -17)) + +/* +** index_u32_0_m16: +** index z0\.s, #0, #-16 +** ret +*/ +TEST_S (index_u32_0_m16, svuint32_t, uint32_t, + z0 = svindex_u32 (0, -16)) + +/* +** index_u32_0_1: +** index z0\.s, #0, #1 +** ret +*/ +TEST_S (index_u32_0_1, svuint32_t, uint32_t, + z0 = svindex_u32 (0, 1)) + +/* +** index_u32_0_15: +** index z0\.s, #0, #15 +** ret +*/ +TEST_S (index_u32_0_15, svuint32_t, uint32_t, + z0 = svindex_u32 (0, 15)) + +/* +** index_u32_0_16: +** mov (w[0-9]+), 16 +** index z0\.s, #0, \1 +** ret +*/ +TEST_S (index_u32_0_16, svuint32_t, uint32_t, + z0 = svindex_u32 (0, 16)) + +/* +** index_u32_m17_1: +** mov (w[0-9]+), -17 +** index z0\.s, \1, #1 +** ret +*/ +TEST_S (index_u32_m17_1, svuint32_t, uint32_t, + z0 = svindex_u32 (-17, 1)) + +/* +** index_u32_m16_1: +** index z0\.s, #-16, #1 +** ret +*/ +TEST_S (index_u32_m16_1, svuint32_t, uint32_t, + z0 = svindex_u32 (-16, 1)) + +/* +** index_u32_m1_1: +** index z0\.s, #-1, #1 +** ret +*/ +TEST_S (index_u32_m1_1, svuint32_t, uint32_t, + z0 = svindex_u32 (-1, 1)) + +/* +** index_u32_1_1: +** index z0\.s, #1, #1 +** ret +*/ +TEST_S (index_u32_1_1, svuint32_t, uint32_t, + z0 = svindex_u32 (1, 1)) + +/* +** index_u32_15_1: +** index z0\.s, #15, #1 +** ret +*/ +TEST_S (index_u32_15_1, svuint32_t, uint32_t, + z0 = svindex_u32 (15, 1)) + +/* +** index_u32_16_1: +** mov (w[0-9]+), 16 +** index z0\.s, \1, #1 +** ret +*/ +TEST_S (index_u32_16_1, svuint32_t, uint32_t, + z0 = svindex_u32 (16, 1)) + +/* +** index_u32_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.s, \1, w0 +** ret +*/ +TEST_S (index_u32_m17_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (-17, x0)) + +/* +** index_u32_m16_x0: +** index z0\.s, #-16, w0 +** ret +*/ +TEST_S (index_u32_m16_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (-16, x0)) + +/* +** index_u32_m1_x0: +** index z0\.s, #-1, w0 +** ret +*/ +TEST_S (index_u32_m1_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (-1, x0)) + +/* +** index_u32_0_x0: +** index z0\.s, #0, w0 +** ret +*/ +TEST_S (index_u32_0_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (0, x0)) + +/* +** index_u32_1_x0: +** index z0\.s, #1, w0 +** ret +*/ +TEST_S (index_u32_1_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (1, x0)) + +/* +** index_u32_15_x0: +** index z0\.s, #15, w0 +** ret +*/ +TEST_S (index_u32_15_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (15, x0)) + +/* +** index_u32_16_x0: +** mov (w[0-9]+), 16 +** index z0\.s, \1, w0 +** ret +*/ +TEST_S (index_u32_16_x0, svuint32_t, uint32_t, + z0 = svindex_u32 (16, x0)) + +/* +** index_u32_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.s, w0, \1 +** ret +*/ +TEST_S (index_u32_x0_m17, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, -17)) + +/* +** index_u32_x0_m16: +** index z0\.s, w0, #-16 +** ret +*/ +TEST_S (index_u32_x0_m16, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, -16)) + +/* +** index_u32_x0_1: +** index z0\.s, w0, #1 +** ret +*/ +TEST_S (index_u32_x0_1, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, 1)) + +/* +** index_u32_x0_15: +** index z0\.s, w0, #15 +** ret +*/ +TEST_S (index_u32_x0_15, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, 15)) + +/* +** index_u32_x0_16: +** mov (w[0-9]+), 16 +** index z0\.s, w0, \1 +** ret +*/ +TEST_S (index_u32_x0_16, svuint32_t, uint32_t, + z0 = svindex_u32 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u64.c new file mode 100644 index 00000000000..526c5e80a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u64.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_u64_x0_x1: +** index z0\.d, x0, x1 +** ret +*/ +TEST_S (index_u64_x0_x1, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, x1)) + +/* +** index_u64_x0_2: +** index z0\.d, x0, #2 +** ret +*/ +TEST_S (index_u64_x0_2, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, 2)) + +/* +** index_u64_50_2: +** mov (x[0-9]+), 50 +** index z0\.d, \1, #2 +** ret +*/ +TEST_S (index_u64_50_2, svuint64_t, uint64_t, + z0 = svindex_u64 (50, 2)) + +/* +** index_u64_0_m17: +** mov (x[0-9]+), -17 +** index z0\.d, #0, \1 +** ret +*/ +TEST_S (index_u64_0_m17, svuint64_t, uint64_t, + z0 = svindex_u64 (0, -17)) + +/* +** index_u64_0_m16: +** index z0\.d, #0, #-16 +** ret +*/ +TEST_S (index_u64_0_m16, svuint64_t, uint64_t, + z0 = svindex_u64 (0, -16)) + +/* +** index_u64_0_1: +** index z0\.d, #0, #1 +** ret +*/ +TEST_S (index_u64_0_1, svuint64_t, uint64_t, + z0 = svindex_u64 (0, 1)) + +/* +** index_u64_0_15: +** index z0\.d, #0, #15 +** ret +*/ +TEST_S (index_u64_0_15, svuint64_t, uint64_t, + z0 = svindex_u64 (0, 15)) + +/* +** index_u64_0_16: +** mov (x[0-9]+), 16 +** index z0\.d, #0, \1 +** ret +*/ +TEST_S (index_u64_0_16, svuint64_t, uint64_t, + z0 = svindex_u64 (0, 16)) + +/* +** index_u64_m17_1: +** mov (x[0-9]+), -17 +** index z0\.d, \1, #1 +** ret +*/ +TEST_S (index_u64_m17_1, svuint64_t, uint64_t, + z0 = svindex_u64 (-17, 1)) + +/* +** index_u64_m16_1: +** index z0\.d, #-16, #1 +** ret +*/ +TEST_S (index_u64_m16_1, svuint64_t, uint64_t, + z0 = svindex_u64 (-16, 1)) + +/* +** index_u64_m1_1: +** index z0\.d, #-1, #1 +** ret +*/ +TEST_S (index_u64_m1_1, svuint64_t, uint64_t, + z0 = svindex_u64 (-1, 1)) + +/* +** index_u64_1_1: +** index z0\.d, #1, #1 +** ret +*/ +TEST_S (index_u64_1_1, svuint64_t, uint64_t, + z0 = svindex_u64 (1, 1)) + +/* +** index_u64_15_1: +** index z0\.d, #15, #1 +** ret +*/ +TEST_S (index_u64_15_1, svuint64_t, uint64_t, + z0 = svindex_u64 (15, 1)) + +/* +** index_u64_16_1: +** mov (x[0-9]+), 16 +** index z0\.d, \1, #1 +** ret +*/ +TEST_S (index_u64_16_1, svuint64_t, uint64_t, + z0 = svindex_u64 (16, 1)) + +/* +** index_u64_m17_x0: +** mov (x[0-9]+), -17 +** index z0\.d, \1, x0 +** ret +*/ +TEST_S (index_u64_m17_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (-17, x0)) + +/* +** index_u64_m16_x0: +** index z0\.d, #-16, x0 +** ret +*/ +TEST_S (index_u64_m16_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (-16, x0)) + +/* +** index_u64_m1_x0: +** index z0\.d, #-1, x0 +** ret +*/ +TEST_S (index_u64_m1_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (-1, x0)) + +/* +** index_u64_0_x0: +** index z0\.d, #0, x0 +** ret +*/ +TEST_S (index_u64_0_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (0, x0)) + +/* +** index_u64_1_x0: +** index z0\.d, #1, x0 +** ret +*/ +TEST_S (index_u64_1_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (1, x0)) + +/* +** index_u64_15_x0: +** index z0\.d, #15, x0 +** ret +*/ +TEST_S (index_u64_15_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (15, x0)) + +/* +** index_u64_16_x0: +** mov (x[0-9]+), 16 +** index z0\.d, \1, x0 +** ret +*/ +TEST_S (index_u64_16_x0, svuint64_t, uint64_t, + z0 = svindex_u64 (16, x0)) + +/* +** index_u64_x0_m17: +** mov (x[0-9]+), -17 +** index z0\.d, x0, \1 +** ret +*/ +TEST_S (index_u64_x0_m17, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, -17)) + +/* +** index_u64_x0_m16: +** index z0\.d, x0, #-16 +** ret +*/ +TEST_S (index_u64_x0_m16, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, -16)) + +/* +** index_u64_x0_1: +** index z0\.d, x0, #1 +** ret +*/ +TEST_S (index_u64_x0_1, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, 1)) + +/* +** index_u64_x0_15: +** index z0\.d, x0, #15 +** ret +*/ +TEST_S (index_u64_x0_15, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, 15)) + +/* +** index_u64_x0_16: +** mov (x[0-9]+), 16 +** index z0\.d, x0, \1 +** ret +*/ +TEST_S (index_u64_x0_16, svuint64_t, uint64_t, + z0 = svindex_u64 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u8.c new file mode 100644 index 00000000000..c6ce12ec8e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/index_u8.c @@ -0,0 +1,220 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** index_u8_w0_w1: +** index z0\.b, w0, w1 +** ret +*/ +TEST_S (index_u8_w0_w1, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, x1)) + +/* +** index_u8_w0_2: +** index z0\.b, w0, #2 +** ret +*/ +TEST_S (index_u8_w0_2, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, 2)) + +/* +** index_u8_50_2: +** mov (w[0-9]+), 50 +** index z0\.b, \1, #2 +** ret +*/ +TEST_S (index_u8_50_2, svuint8_t, uint8_t, + z0 = svindex_u8 (50, 2)) + +/* +** index_u8_0_m17: +** mov (w[0-9]+), -17 +** index z0\.b, #0, \1 +** ret +*/ +TEST_S (index_u8_0_m17, svuint8_t, uint8_t, + z0 = svindex_u8 (0, -17)) + +/* +** index_u8_0_m16: +** index z0\.b, #0, #-16 +** ret +*/ +TEST_S (index_u8_0_m16, svuint8_t, uint8_t, + z0 = svindex_u8 (0, -16)) + +/* +** index_u8_0_1: +** index z0\.b, #0, #1 +** ret +*/ +TEST_S (index_u8_0_1, svuint8_t, uint8_t, + z0 = svindex_u8 (0, 1)) + +/* +** index_u8_0_15: +** index z0\.b, #0, #15 +** ret +*/ +TEST_S (index_u8_0_15, svuint8_t, uint8_t, + z0 = svindex_u8 (0, 15)) + +/* +** index_u8_0_16: +** mov (w[0-9]+), 16 +** index z0\.b, #0, \1 +** ret +*/ +TEST_S (index_u8_0_16, svuint8_t, uint8_t, + z0 = svindex_u8 (0, 16)) + +/* +** index_u8_m17_1: +** mov (w[0-9]+), -17 +** index z0\.b, \1, #1 +** ret +*/ +TEST_S (index_u8_m17_1, svuint8_t, uint8_t, + z0 = svindex_u8 (-17, 1)) + +/* +** index_u8_m16_1: +** index z0\.b, #-16, #1 +** ret +*/ +TEST_S (index_u8_m16_1, svuint8_t, uint8_t, + z0 = svindex_u8 (-16, 1)) + +/* +** index_u8_m1_1: +** index z0\.b, #-1, #1 +** ret +*/ +TEST_S (index_u8_m1_1, svuint8_t, uint8_t, + z0 = svindex_u8 (-1, 1)) + +/* +** index_u8_1_1: +** index z0\.b, #1, #1 +** ret +*/ +TEST_S (index_u8_1_1, svuint8_t, uint8_t, + z0 = svindex_u8 (1, 1)) + +/* +** index_u8_15_1: +** index z0\.b, #15, #1 +** ret +*/ +TEST_S (index_u8_15_1, svuint8_t, uint8_t, + z0 = svindex_u8 (15, 1)) + +/* +** index_u8_16_1: +** mov (w[0-9]+), 16 +** index z0\.b, \1, #1 +** ret +*/ +TEST_S (index_u8_16_1, svuint8_t, uint8_t, + z0 = svindex_u8 (16, 1)) + +/* +** index_u8_m17_x0: +** mov (w[0-9]+), -17 +** index z0\.b, \1, w0 +** ret +*/ +TEST_S (index_u8_m17_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (-17, x0)) + +/* +** index_u8_m16_x0: +** index z0\.b, #-16, w0 +** ret +*/ +TEST_S (index_u8_m16_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (-16, x0)) + +/* +** index_u8_m1_x0: +** index z0\.b, #-1, w0 +** ret +*/ +TEST_S (index_u8_m1_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (-1, x0)) + +/* +** index_u8_0_x0: +** index z0\.b, #0, w0 +** ret +*/ +TEST_S (index_u8_0_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (0, x0)) + +/* +** index_u8_1_x0: +** index z0\.b, #1, w0 +** ret +*/ +TEST_S (index_u8_1_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (1, x0)) + +/* +** index_u8_15_x0: +** index z0\.b, #15, w0 +** ret +*/ +TEST_S (index_u8_15_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (15, x0)) + +/* +** index_u8_16_x0: +** mov (w[0-9]+), 16 +** index z0\.b, \1, w0 +** ret +*/ +TEST_S (index_u8_16_x0, svuint8_t, uint8_t, + z0 = svindex_u8 (16, x0)) + +/* +** index_u8_x0_m17: +** mov (w[0-9]+), -17 +** index z0\.b, w0, \1 +** ret +*/ +TEST_S (index_u8_x0_m17, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, -17)) + +/* +** index_u8_x0_m16: +** index z0\.b, w0, #-16 +** ret +*/ +TEST_S (index_u8_x0_m16, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, -16)) + +/* +** index_u8_x0_1: +** index z0\.b, w0, #1 +** ret +*/ +TEST_S (index_u8_x0_1, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, 1)) + +/* +** index_u8_x0_15: +** index z0\.b, w0, #15 +** ret +*/ +TEST_S (index_u8_x0_15, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, 15)) + +/* +** index_u8_x0_16: +** mov (w[0-9]+), 16 +** index z0\.b, w0, \1 +** ret +*/ +TEST_S (index_u8_x0_16, svuint8_t, uint8_t, + z0 = svindex_u8 (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f16.c new file mode 100644 index 00000000000..f01a3618965 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f16.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_h4_f16_tied1: +** insr z0\.h, h4 +** ret +*/ +TEST_UNIFORM_ZD (insr_h4_f16_tied1, svfloat16_t, __fp16, + z0 = svinsr_n_f16 (z0, d4), + z0 = svinsr (z0, d4)) + +/* +** insr_h4_f16_untied: +** movprfx z0, z1 +** insr z0\.h, h4 +** ret +*/ +TEST_UNIFORM_ZD (insr_h4_f16_untied, svfloat16_t, __fp16, + z0 = svinsr_n_f16 (z1, d4), + z0 = svinsr (z1, d4)) + +/* +** insr_0_f16_tied1: +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f16_tied1, svfloat16_t, + z0 = svinsr_n_f16 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_f16_untied: +** movprfx z0, z1 +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f16_untied, svfloat16_t, + z0 = svinsr_n_f16 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_f16: +** fmov (h[0-9]+), #?1\.0(?:e\+0)? +** insr z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (insr_1_f16, svfloat16_t, + z0 = svinsr_n_f16 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f32.c new file mode 100644 index 00000000000..e339727b11d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f32.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_s4_f32_tied1: +** insr z0\.s, s4 +** ret +*/ +TEST_UNIFORM_ZD (insr_s4_f32_tied1, svfloat32_t, float, + z0 = svinsr_n_f32 (z0, d4), + z0 = svinsr (z0, d4)) + +/* +** insr_s4_f32_untied: +** movprfx z0, z1 +** insr z0\.s, s4 +** ret +*/ +TEST_UNIFORM_ZD (insr_s4_f32_untied, svfloat32_t, float, + z0 = svinsr_n_f32 (z1, d4), + z0 = svinsr (z1, d4)) + +/* +** insr_0_f32_tied1: +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f32_tied1, svfloat32_t, + z0 = svinsr_n_f32 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_f32_untied: +** movprfx z0, z1 +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f32_untied, svfloat32_t, + z0 = svinsr_n_f32 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_f32: +** fmov (s[0-9]+), #?1\.0(?:e\+0)? +** insr z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (insr_1_f32, svfloat32_t, + z0 = svinsr_n_f32 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f64.c new file mode 100644 index 00000000000..9400225a546 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_f64.c @@ -0,0 +1,51 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_d4_f64_tied1: +** insr z0\.d, d4 +** ret +*/ +TEST_UNIFORM_ZD (insr_d4_f64_tied1, svfloat64_t, double, + z0 = svinsr_n_f64 (z0, d4), + z0 = svinsr (z0, d4)) + +/* +** insr_d4_f64_untied: +** movprfx z0, z1 +** insr z0\.d, d4 +** ret +*/ +TEST_UNIFORM_ZD (insr_d4_f64_untied, svfloat64_t, double, + z0 = svinsr_n_f64 (z1, d4), + z0 = svinsr (z1, d4)) + +/* +** insr_0_f64_tied1: +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f64_tied1, svfloat64_t, + z0 = svinsr_n_f64 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_f64_untied: +** movprfx z0, z1 +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_f64_untied, svfloat64_t, + z0 = svinsr_n_f64 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_f64: +** fmov (d[0-9]+), #?1\.0(?:e\+0)? +** insr z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (insr_1_f64, svfloat64_t, + z0 = svinsr_n_f64 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s16.c new file mode 100644 index 00000000000..651977a9de9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s16.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_s16_tied1: +** insr z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s16_tied1, svint16_t, int16_t, + z0 = svinsr_n_s16 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_s16_untied: +** movprfx z0, z1 +** insr z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s16_untied, svint16_t, int16_t, + z0 = svinsr_n_s16 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_s16_tied1: +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s16_tied1, svint16_t, + z0 = svinsr_n_s16 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_s16_untied: +** movprfx z0, z1 +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s16_untied, svint16_t, + z0 = svinsr_n_s16 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_s16: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.h, \1 +** | +** movi v([0-9]+)\.4h, 0x1 +** insr z0\.h, h\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_s16, svint16_t, + z0 = svinsr_n_s16 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s32.c new file mode 100644 index 00000000000..a1dcfc090df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s32.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_s32_tied1: +** insr z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s32_tied1, svint32_t, int32_t, + z0 = svinsr_n_s32 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_s32_untied: +** movprfx z0, z1 +** insr z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s32_untied, svint32_t, int32_t, + z0 = svinsr_n_s32 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_s32_tied1: +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s32_tied1, svint32_t, + z0 = svinsr_n_s32 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_s32_untied: +** movprfx z0, z1 +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s32_untied, svint32_t, + z0 = svinsr_n_s32 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_s32: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.s, \1 +** | +** movi v([0-9]+)\.2s, 0x1 +** insr z0\.s, s\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_s32, svint32_t, + z0 = svinsr_n_s32 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s64.c new file mode 100644 index 00000000000..32cdc8263d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s64.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_x0_s64_tied1: +** insr z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (insr_x0_s64_tied1, svint64_t, int64_t, + z0 = svinsr_n_s64 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_x0_s64_untied: +** movprfx z0, z1 +** insr z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (insr_x0_s64_untied, svint64_t, int64_t, + z0 = svinsr_n_s64 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_s64_tied1: +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s64_tied1, svint64_t, + z0 = svinsr_n_s64 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_s64_untied: +** movprfx z0, z1 +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s64_untied, svint64_t, + z0 = svinsr_n_s64 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_s64: +** ( +** mov (x[0-9]+), #?1 +** insr z0\.d, \1 +** | +** movi v([0-9]+)\.2d, 0x1 +** insr z0\.d, d\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_s64, svint64_t, + z0 = svinsr_n_s64 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s8.c new file mode 100644 index 00000000000..cb69b09fac7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_s8.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_s8_tied1: +** insr z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s8_tied1, svint8_t, int8_t, + z0 = svinsr_n_s8 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_s8_untied: +** movprfx z0, z1 +** insr z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_s8_untied, svint8_t, int8_t, + z0 = svinsr_n_s8 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_s8_tied1: +** insr z0\.b, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s8_tied1, svint8_t, + z0 = svinsr_n_s8 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_s8_untied: +** movprfx z0, z1 +** insr z0\.b, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_s8_untied, svint8_t, + z0 = svinsr_n_s8 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_s8: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.b, \1 +** | +** movi v([0-9]+)\.8b, 0x1 +** insr z0\.b, b\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_s8, svint8_t, + z0 = svinsr_n_s8 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u16.c new file mode 100644 index 00000000000..35af7740269 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u16.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_u16_tied1: +** insr z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svinsr_n_u16 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_u16_untied: +** movprfx z0, z1 +** insr z0\.h, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u16_untied, svuint16_t, uint16_t, + z0 = svinsr_n_u16 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_u16_tied1: +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u16_tied1, svuint16_t, + z0 = svinsr_n_u16 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_u16_untied: +** movprfx z0, z1 +** insr z0\.h, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u16_untied, svuint16_t, + z0 = svinsr_n_u16 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_u16: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.h, \1 +** | +** movi v([0-9]+)\.4h, 0x1 +** insr z0\.h, h\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_u16, svuint16_t, + z0 = svinsr_n_u16 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u32.c new file mode 100644 index 00000000000..8a72e7f2a99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u32.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_u32_tied1: +** insr z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svinsr_n_u32 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_u32_untied: +** movprfx z0, z1 +** insr z0\.s, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u32_untied, svuint32_t, uint32_t, + z0 = svinsr_n_u32 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_u32_tied1: +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u32_tied1, svuint32_t, + z0 = svinsr_n_u32 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_u32_untied: +** movprfx z0, z1 +** insr z0\.s, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u32_untied, svuint32_t, + z0 = svinsr_n_u32 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_u32: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.s, \1 +** | +** movi v([0-9]+)\.2s, 0x1 +** insr z0\.s, s\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_u32, svuint32_t, + z0 = svinsr_n_u32 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u64.c new file mode 100644 index 00000000000..ab23f677d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u64.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_x0_u64_tied1: +** insr z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (insr_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svinsr_n_u64 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_x0_u64_untied: +** movprfx z0, z1 +** insr z0\.d, x0 +** ret +*/ +TEST_UNIFORM_ZX (insr_x0_u64_untied, svuint64_t, uint64_t, + z0 = svinsr_n_u64 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_u64_tied1: +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u64_tied1, svuint64_t, + z0 = svinsr_n_u64 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_u64_untied: +** movprfx z0, z1 +** insr z0\.d, xzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u64_untied, svuint64_t, + z0 = svinsr_n_u64 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_u64: +** ( +** mov (x[0-9]+), #?1 +** insr z0\.d, \1 +** | +** movi v([0-9]+)\.2d, 0x1 +** insr z0\.d, d\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_u64, svuint64_t, + z0 = svinsr_n_u64 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u8.c new file mode 100644 index 00000000000..549d71882c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/insr_u8.c @@ -0,0 +1,56 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** insr_w0_u8_tied1: +** insr z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svinsr_n_u8 (z0, x0), + z0 = svinsr (z0, x0)) + +/* +** insr_w0_u8_untied: +** movprfx z0, z1 +** insr z0\.b, w0 +** ret +*/ +TEST_UNIFORM_ZX (insr_w0_u8_untied, svuint8_t, uint8_t, + z0 = svinsr_n_u8 (z1, x0), + z0 = svinsr (z1, x0)) + +/* +** insr_0_u8_tied1: +** insr z0\.b, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u8_tied1, svuint8_t, + z0 = svinsr_n_u8 (z0, 0), + z0 = svinsr (z0, 0)) + +/* +** insr_0_u8_untied: +** movprfx z0, z1 +** insr z0\.b, wzr +** ret +*/ +TEST_UNIFORM_Z (insr_0_u8_untied, svuint8_t, + z0 = svinsr_n_u8 (z1, 0), + z0 = svinsr (z1, 0)) + +/* +** insr_1_u8: +** ( +** mov (w[0-9]+), #?1 +** insr z0\.b, \1 +** | +** movi v([0-9]+)\.8b, 0x1 +** insr z0\.b, b\2 +** ) +** ret +*/ +TEST_UNIFORM_Z (insr_1_u8, svuint8_t, + z0 = svinsr_n_u8 (z0, 1), + z0 = svinsr (z0, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f16.c new file mode 100644 index 00000000000..972b55ab6b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_d0_f16_tied: +** lasta h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f16_tied, float16_t, svfloat16_t, + d0 = svlasta_f16 (p0, z0), + d0 = svlasta (p0, z0)) + +/* +** lasta_d0_f16_untied: +** lasta h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f16_untied, float16_t, svfloat16_t, + d0 = svlasta_f16 (p0, z1), + d0 = svlasta (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f32.c new file mode 100644 index 00000000000..cfb537f2ffe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_d0_f32_tied: +** lasta s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f32_tied, float32_t, svfloat32_t, + d0 = svlasta_f32 (p0, z0), + d0 = svlasta (p0, z0)) + +/* +** lasta_d0_f32_untied: +** lasta s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f32_untied, float32_t, svfloat32_t, + d0 = svlasta_f32 (p0, z1), + d0 = svlasta (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f64.c new file mode 100644 index 00000000000..a4a8a74c987 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_d0_f64_tied: +** lasta d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f64_tied, float64_t, svfloat64_t, + d0 = svlasta_f64 (p0, z0), + d0 = svlasta (p0, z0)) + +/* +** lasta_d0_f64_untied: +** lasta d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (lasta_d0_f64_untied, float64_t, svfloat64_t, + d0 = svlasta_f64 (p0, z1), + d0 = svlasta (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s16.c new file mode 100644 index 00000000000..54bd0248f16 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_s16: +** lasta w0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_X (lasta_x0_s16, int16_t, svint16_t, + x0 = svlasta_s16 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s32.c new file mode 100644 index 00000000000..18f852f94c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_s32: +** lasta w0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_X (lasta_x0_s32, int32_t, svint32_t, + x0 = svlasta_s32 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s64.c new file mode 100644 index 00000000000..6e45af3d4c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_s64: +** lasta x0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_X (lasta_x0_s64, int64_t, svint64_t, + x0 = svlasta_s64 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s8.c new file mode 100644 index 00000000000..58e574f3086 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_s8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_s8: +** lasta w0, p0, z0\.b +** ret +*/ +TEST_REDUCTION_X (lasta_x0_s8, int8_t, svint8_t, + x0 = svlasta_s8 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u16.c new file mode 100644 index 00000000000..a0e14eca481 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_u16: +** lasta w0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_X (lasta_x0_u16, uint16_t, svuint16_t, + x0 = svlasta_u16 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u32.c new file mode 100644 index 00000000000..dab37c36a7b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_u32: +** lasta w0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_X (lasta_x0_u32, uint32_t, svuint32_t, + x0 = svlasta_u32 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u64.c new file mode 100644 index 00000000000..c766f36ecb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_u64: +** lasta x0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_X (lasta_x0_u64, uint64_t, svuint64_t, + x0 = svlasta_u64 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u8.c new file mode 100644 index 00000000000..a83f25fe486 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lasta_u8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lasta_x0_u8: +** lasta w0, p0, z0\.b +** ret +*/ +TEST_REDUCTION_X (lasta_x0_u8, uint8_t, svuint8_t, + x0 = svlasta_u8 (p0, z0), + x0 = svlasta (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f16.c new file mode 100644 index 00000000000..0bc7e9ef48a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_d0_f16_tied: +** lastb h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f16_tied, float16_t, svfloat16_t, + d0 = svlastb_f16 (p0, z0), + d0 = svlastb (p0, z0)) + +/* +** lastb_d0_f16_untied: +** lastb h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f16_untied, float16_t, svfloat16_t, + d0 = svlastb_f16 (p0, z1), + d0 = svlastb (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f32.c new file mode 100644 index 00000000000..b33d61eee61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_d0_f32_tied: +** lastb s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f32_tied, float32_t, svfloat32_t, + d0 = svlastb_f32 (p0, z0), + d0 = svlastb (p0, z0)) + +/* +** lastb_d0_f32_untied: +** lastb s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f32_untied, float32_t, svfloat32_t, + d0 = svlastb_f32 (p0, z1), + d0 = svlastb (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f64.c new file mode 100644 index 00000000000..9fa7de706d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_d0_f64_tied: +** lastb d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f64_tied, float64_t, svfloat64_t, + d0 = svlastb_f64 (p0, z0), + d0 = svlastb (p0, z0)) + +/* +** lastb_d0_f64_untied: +** lastb d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (lastb_d0_f64_untied, float64_t, svfloat64_t, + d0 = svlastb_f64 (p0, z1), + d0 = svlastb (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s16.c new file mode 100644 index 00000000000..6575f21cdca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_s16: +** lastb w0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_X (lastb_x0_s16, int16_t, svint16_t, + x0 = svlastb_s16 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s32.c new file mode 100644 index 00000000000..856e5bdc8fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_s32: +** lastb w0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_X (lastb_x0_s32, int32_t, svint32_t, + x0 = svlastb_s32 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s64.c new file mode 100644 index 00000000000..bd7de2ab2bb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_s64: +** lastb x0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_X (lastb_x0_s64, int64_t, svint64_t, + x0 = svlastb_s64 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s8.c new file mode 100644 index 00000000000..4c343a7056d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_s8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_s8: +** lastb w0, p0, z0\.b +** ret +*/ +TEST_REDUCTION_X (lastb_x0_s8, int8_t, svint8_t, + x0 = svlastb_s8 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u16.c new file mode 100644 index 00000000000..7f3db1bb167 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_u16: +** lastb w0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_X (lastb_x0_u16, uint16_t, svuint16_t, + x0 = svlastb_u16 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u32.c new file mode 100644 index 00000000000..c2eeacba028 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_u32: +** lastb w0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_X (lastb_x0_u32, uint32_t, svuint32_t, + x0 = svlastb_u32 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u64.c new file mode 100644 index 00000000000..1496ffa0e0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_u64: +** lastb x0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_X (lastb_x0_u64, uint64_t, svuint64_t, + x0 = svlastb_u64 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u8.c new file mode 100644 index 00000000000..25f036063aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lastb_u8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lastb_x0_u8: +** lastb w0, p0, z0\.b +** ret +*/ +TEST_REDUCTION_X (lastb_x0_u8, uint8_t, svuint8_t, + x0 = svlastb_u8 (p0, z0), + x0 = svlastb (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f16.c new file mode 100644 index 00000000000..e82eaf87c4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_f16_base: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f16_base, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_f16_index: +** ld1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1_f16_index, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_f16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f16_1, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 + svcnth ()), + z0 = svld1 (p0, x0 + svcnth ())) + +/* +** ld1_f16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f16_7, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 + svcnth () * 7), + z0 = svld1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f16_8, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 + svcnth () * 8), + z0 = svld1 (p0, x0 + svcnth () * 8)) + +/* +** ld1_f16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f16_m1, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 - svcnth ()), + z0 = svld1 (p0, x0 - svcnth ())) + +/* +** ld1_f16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f16_m8, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 - svcnth () * 8), + z0 = svld1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f16_m9, svfloat16_t, float16_t, + z0 = svld1_f16 (p0, x0 - svcnth () * 9), + z0 = svld1 (p0, x0 - svcnth () * 9)) + +/* +** ld1_vnum_f16_0: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_0, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_f16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_1, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_f16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_7, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_8, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_f16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_m1, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_f16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_m8, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_m9, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_f16_x1, svfloat16_t, float16_t, + z0 = svld1_vnum_f16 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f32.c new file mode 100644 index 00000000000..7fe026c9473 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_f32_base: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f32_base, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_f32_index: +** ld1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1_f32_index, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_f32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f32_1, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 + svcntw ()), + z0 = svld1 (p0, x0 + svcntw ())) + +/* +** ld1_f32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f32_7, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 + svcntw () * 7), + z0 = svld1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f32_8, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 + svcntw () * 8), + z0 = svld1 (p0, x0 + svcntw () * 8)) + +/* +** ld1_f32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f32_m1, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 - svcntw ()), + z0 = svld1 (p0, x0 - svcntw ())) + +/* +** ld1_f32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f32_m8, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 - svcntw () * 8), + z0 = svld1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f32_m9, svfloat32_t, float32_t, + z0 = svld1_f32 (p0, x0 - svcntw () * 9), + z0 = svld1 (p0, x0 - svcntw () * 9)) + +/* +** ld1_vnum_f32_0: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_0, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_f32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_1, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_f32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_7, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_8, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_f32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_m1, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_f32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_m8, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_m9, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_f32_x1, svfloat32_t, float32_t, + z0 = svld1_vnum_f32 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f64.c new file mode 100644 index 00000000000..ddafcc62a79 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_f64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_f64_base: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f64_base, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_f64_index: +** ld1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1_f64_index, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_f64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f64_1, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 + svcntd ()), + z0 = svld1 (p0, x0 + svcntd ())) + +/* +** ld1_f64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f64_7, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 + svcntd () * 7), + z0 = svld1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f64_8, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 + svcntd () * 8), + z0 = svld1 (p0, x0 + svcntd () * 8)) + +/* +** ld1_f64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f64_m1, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 - svcntd ()), + z0 = svld1 (p0, x0 - svcntd ())) + +/* +** ld1_f64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_f64_m8, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 - svcntd () * 8), + z0 = svld1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_f64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_f64_m9, svfloat64_t, float64_t, + z0 = svld1_f64 (p0, x0 - svcntd () * 9), + z0 = svld1 (p0, x0 - svcntd () * 9)) + +/* +** ld1_vnum_f64_0: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_0, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_f64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_1, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_f64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_7, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_8, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_f64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_m1, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_f64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_m8, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_f64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_m9, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_f64_x1, svfloat64_t, float64_t, + z0 = svld1_vnum_f64 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f32.c new file mode 100644 index 00000000000..e4edffc78df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_f32_tied1: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_f32_tied1, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_f32 (p0, z0), + z0_res = svld1_gather_f32 (p0, z0)) + +/* +** ld1_gather_f32_untied: +** ld1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_f32_untied, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_f32 (p0, z1), + z0_res = svld1_gather_f32 (p0, z1)) + +/* +** ld1_gather_x0_f32_offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, x0), + z0_res = svld1_gather_offset_f32 (p0, z0, x0)) + +/* +** ld1_gather_m4_f32_offset: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m4_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, -4), + z0_res = svld1_gather_offset_f32 (p0, z0, -4)) + +/* +** ld1_gather_0_f32_offset: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 0), + z0_res = svld1_gather_offset_f32 (p0, z0, 0)) + +/* +** ld1_gather_5_f32_offset: +** mov (x[0-9]+), #?5 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 5), + z0_res = svld1_gather_offset_f32 (p0, z0, 5)) + +/* +** ld1_gather_6_f32_offset: +** mov (x[0-9]+), #?6 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_6_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 6), + z0_res = svld1_gather_offset_f32 (p0, z0, 6)) + +/* +** ld1_gather_7_f32_offset: +** mov (x[0-9]+), #?7 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_7_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 7), + z0_res = svld1_gather_offset_f32 (p0, z0, 7)) + +/* +** ld1_gather_8_f32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_8_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 8), + z0_res = svld1_gather_offset_f32 (p0, z0, 8)) + +/* +** ld1_gather_124_f32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_124_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 124), + z0_res = svld1_gather_offset_f32 (p0, z0, 124)) + +/* +** ld1_gather_128_f32_offset: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_128_f32_offset, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_f32 (p0, z0, 128), + z0_res = svld1_gather_offset_f32 (p0, z0, 128)) + +/* +** ld1_gather_x0_f32_index: +** lsl (x[0-9]+), x0, #?2 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, x0), + z0_res = svld1_gather_index_f32 (p0, z0, x0)) + +/* +** ld1_gather_m1_f32_index: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, -1), + z0_res = svld1_gather_index_f32 (p0, z0, -1)) + +/* +** ld1_gather_0_f32_index: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, 0), + z0_res = svld1_gather_index_f32 (p0, z0, 0)) + +/* +** ld1_gather_5_f32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, 5), + z0_res = svld1_gather_index_f32 (p0, z0, 5)) + +/* +** ld1_gather_31_f32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, 31), + z0_res = svld1_gather_index_f32 (p0, z0, 31)) + +/* +** ld1_gather_32_f32_index: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_f32_index, svfloat32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_f32 (p0, z0, 32), + z0_res = svld1_gather_index_f32 (p0, z0, 32)) + +/* +** ld1_gather_x0_f32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32offset_f32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_f32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32offset_f32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_f32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32offset_f32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_f32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32offset_f32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_f32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32offset_f32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_f32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32offset_f32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_f32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32index_f32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_f32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32index_f32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_f32_s32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svld1_gather_s32index_f32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_x0_f32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32index_f32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_f32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32index_f32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_f32_u32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svld1_gather_u32index_f32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f64.c new file mode 100644 index 00000000000..685cc490b99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_f64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_f64_tied1: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_f64_tied1, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_f64 (p0, z0), + z0_res = svld1_gather_f64 (p0, z0)) + +/* +** ld1_gather_f64_untied: +** ld1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_f64_untied, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_f64 (p0, z1), + z0_res = svld1_gather_f64 (p0, z1)) + +/* +** ld1_gather_x0_f64_offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, x0), + z0_res = svld1_gather_offset_f64 (p0, z0, x0)) + +/* +** ld1_gather_m8_f64_offset: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m8_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, -8), + z0_res = svld1_gather_offset_f64 (p0, z0, -8)) + +/* +** ld1_gather_0_f64_offset: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 0), + z0_res = svld1_gather_offset_f64 (p0, z0, 0)) + +/* +** ld1_gather_9_f64_offset: +** mov (x[0-9]+), #?9 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_9_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 9), + z0_res = svld1_gather_offset_f64 (p0, z0, 9)) + +/* +** ld1_gather_10_f64_offset: +** mov (x[0-9]+), #?10 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_10_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 10), + z0_res = svld1_gather_offset_f64 (p0, z0, 10)) + +/* +** ld1_gather_11_f64_offset: +** mov (x[0-9]+), #?11 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_11_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 11), + z0_res = svld1_gather_offset_f64 (p0, z0, 11)) + +/* +** ld1_gather_12_f64_offset: +** mov (x[0-9]+), #?12 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_12_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 12), + z0_res = svld1_gather_offset_f64 (p0, z0, 12)) + +/* +** ld1_gather_13_f64_offset: +** mov (x[0-9]+), #?13 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_13_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 13), + z0_res = svld1_gather_offset_f64 (p0, z0, 13)) + +/* +** ld1_gather_14_f64_offset: +** mov (x[0-9]+), #?14 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_14_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 14), + z0_res = svld1_gather_offset_f64 (p0, z0, 14)) + +/* +** ld1_gather_15_f64_offset: +** mov (x[0-9]+), #?15 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_15_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 15), + z0_res = svld1_gather_offset_f64 (p0, z0, 15)) + +/* +** ld1_gather_16_f64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_16_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 16), + z0_res = svld1_gather_offset_f64 (p0, z0, 16)) + +/* +** ld1_gather_248_f64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_248_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 248), + z0_res = svld1_gather_offset_f64 (p0, z0, 248)) + +/* +** ld1_gather_256_f64_offset: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_256_f64_offset, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_f64 (p0, z0, 256), + z0_res = svld1_gather_offset_f64 (p0, z0, 256)) + +/* +** ld1_gather_x0_f64_index: +** lsl (x[0-9]+), x0, #?3 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, x0), + z0_res = svld1_gather_index_f64 (p0, z0, x0)) + +/* +** ld1_gather_m1_f64_index: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, -1), + z0_res = svld1_gather_index_f64 (p0, z0, -1)) + +/* +** ld1_gather_0_f64_index: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, 0), + z0_res = svld1_gather_index_f64 (p0, z0, 0)) + +/* +** ld1_gather_5_f64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, 5), + z0_res = svld1_gather_index_f64 (p0, z0, 5)) + +/* +** ld1_gather_31_f64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, 31), + z0_res = svld1_gather_index_f64 (p0, z0, 31)) + +/* +** ld1_gather_32_f64_index: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_f64_index, svfloat64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_f64 (p0, z0, 32), + z0_res = svld1_gather_index_f64 (p0, z0, 32)) + +/* +** ld1_gather_x0_f64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64offset_f64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_f64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64offset_f64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_f64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64offset_f64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_f64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64offset_f64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_f64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64offset_f64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_f64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64offset_f64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_f64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64offset_f64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_f64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64offset_f64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_f64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64index_f64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_f64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64index_f64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_f64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64index_f64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_f64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svld1_gather_s64index_f64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_f64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64index_f64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_f64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64index_f64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_f64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64index_f64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_f64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svld1_gather_u64index_f64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s32.c new file mode 100644 index 00000000000..caa804ff7b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_s32_tied1: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_s32 (p0, z0), + z0_res = svld1_gather_s32 (p0, z0)) + +/* +** ld1_gather_s32_untied: +** ld1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_s32 (p0, z1), + z0_res = svld1_gather_s32 (p0, z1)) + +/* +** ld1_gather_x0_s32_offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svld1_gather_offset_s32 (p0, z0, x0)) + +/* +** ld1_gather_m4_s32_offset: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m4_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, -4), + z0_res = svld1_gather_offset_s32 (p0, z0, -4)) + +/* +** ld1_gather_0_s32_offset: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svld1_gather_offset_s32 (p0, z0, 0)) + +/* +** ld1_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svld1_gather_offset_s32 (p0, z0, 5)) + +/* +** ld1_gather_6_s32_offset: +** mov (x[0-9]+), #?6 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svld1_gather_offset_s32 (p0, z0, 6)) + +/* +** ld1_gather_7_s32_offset: +** mov (x[0-9]+), #?7 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_7_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 7), + z0_res = svld1_gather_offset_s32 (p0, z0, 7)) + +/* +** ld1_gather_8_s32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_8_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 8), + z0_res = svld1_gather_offset_s32 (p0, z0, 8)) + +/* +** ld1_gather_124_s32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_124_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 124), + z0_res = svld1_gather_offset_s32 (p0, z0, 124)) + +/* +** ld1_gather_128_s32_offset: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_128_s32_offset, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_s32 (p0, z0, 128), + z0_res = svld1_gather_offset_s32 (p0, z0, 128)) + +/* +** ld1_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?2 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svld1_gather_index_s32 (p0, z0, x0)) + +/* +** ld1_gather_m1_s32_index: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svld1_gather_index_s32 (p0, z0, -1)) + +/* +** ld1_gather_0_s32_index: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svld1_gather_index_s32 (p0, z0, 0)) + +/* +** ld1_gather_5_s32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svld1_gather_index_s32 (p0, z0, 5)) + +/* +** ld1_gather_31_s32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svld1_gather_index_s32 (p0, z0, 31)) + +/* +** ld1_gather_32_s32_index: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svld1_gather_index_s32 (p0, z0, 32)) + +/* +** ld1_gather_x0_s32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_s32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_s32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32offset_s32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_s32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_s32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_s32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32offset_s32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_s32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_s32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_s32_s32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svld1_gather_s32index_s32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_x0_s32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_s32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_s32_u32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svld1_gather_u32index_s32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s64.c new file mode 100644 index 00000000000..f5100612f5e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_s64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_s64_tied1: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_s64 (p0, z0), + z0_res = svld1_gather_s64 (p0, z0)) + +/* +** ld1_gather_s64_untied: +** ld1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_s64 (p0, z1), + z0_res = svld1_gather_s64 (p0, z1)) + +/* +** ld1_gather_x0_s64_offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1_gather_m8_s64_offset: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m8_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, -8), + z0_res = svld1_gather_offset_s64 (p0, z0, -8)) + +/* +** ld1_gather_0_s64_offset: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1_gather_9_s64_offset: +** mov (x[0-9]+), #?9 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_9_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 9), + z0_res = svld1_gather_offset_s64 (p0, z0, 9)) + +/* +** ld1_gather_10_s64_offset: +** mov (x[0-9]+), #?10 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_10_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 10), + z0_res = svld1_gather_offset_s64 (p0, z0, 10)) + +/* +** ld1_gather_11_s64_offset: +** mov (x[0-9]+), #?11 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_11_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 11), + z0_res = svld1_gather_offset_s64 (p0, z0, 11)) + +/* +** ld1_gather_12_s64_offset: +** mov (x[0-9]+), #?12 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_12_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 12), + z0_res = svld1_gather_offset_s64 (p0, z0, 12)) + +/* +** ld1_gather_13_s64_offset: +** mov (x[0-9]+), #?13 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_13_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 13), + z0_res = svld1_gather_offset_s64 (p0, z0, 13)) + +/* +** ld1_gather_14_s64_offset: +** mov (x[0-9]+), #?14 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_14_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 14), + z0_res = svld1_gather_offset_s64 (p0, z0, 14)) + +/* +** ld1_gather_15_s64_offset: +** mov (x[0-9]+), #?15 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_15_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 15), + z0_res = svld1_gather_offset_s64 (p0, z0, 15)) + +/* +** ld1_gather_16_s64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_16_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 16), + z0_res = svld1_gather_offset_s64 (p0, z0, 16)) + +/* +** ld1_gather_248_s64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_248_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 248), + z0_res = svld1_gather_offset_s64 (p0, z0, 248)) + +/* +** ld1_gather_256_s64_offset: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_256_s64_offset, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_s64 (p0, z0, 256), + z0_res = svld1_gather_offset_s64 (p0, z0, 256)) + +/* +** ld1_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?3 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svld1_gather_index_s64 (p0, z0, x0)) + +/* +** ld1_gather_m1_s64_index: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svld1_gather_index_s64 (p0, z0, -1)) + +/* +** ld1_gather_0_s64_index: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svld1_gather_index_s64 (p0, z0, 0)) + +/* +** ld1_gather_5_s64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svld1_gather_index_s64 (p0, z0, 5)) + +/* +** ld1_gather_31_s64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svld1_gather_index_s64 (p0, z0, 31)) + +/* +** ld1_gather_32_s64_index: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svld1_gather_index_s64 (p0, z0, 32)) + +/* +** ld1_gather_x0_s64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_s64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_s64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_s64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_s64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_s64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_s64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_s64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_s64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_s64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_s64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64index_s64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_s64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svld1_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_s64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_s64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_s64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64index_s64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_s64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svld1_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u32.c new file mode 100644 index 00000000000..8039b49d8f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_u32_tied1: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_u32 (p0, z0), + z0_res = svld1_gather_u32 (p0, z0)) + +/* +** ld1_gather_u32_untied: +** ld1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_u32 (p0, z1), + z0_res = svld1_gather_u32 (p0, z1)) + +/* +** ld1_gather_x0_u32_offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svld1_gather_offset_u32 (p0, z0, x0)) + +/* +** ld1_gather_m4_u32_offset: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m4_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, -4), + z0_res = svld1_gather_offset_u32 (p0, z0, -4)) + +/* +** ld1_gather_0_u32_offset: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svld1_gather_offset_u32 (p0, z0, 0)) + +/* +** ld1_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svld1_gather_offset_u32 (p0, z0, 5)) + +/* +** ld1_gather_6_u32_offset: +** mov (x[0-9]+), #?6 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svld1_gather_offset_u32 (p0, z0, 6)) + +/* +** ld1_gather_7_u32_offset: +** mov (x[0-9]+), #?7 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_7_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 7), + z0_res = svld1_gather_offset_u32 (p0, z0, 7)) + +/* +** ld1_gather_8_u32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_8_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 8), + z0_res = svld1_gather_offset_u32 (p0, z0, 8)) + +/* +** ld1_gather_124_u32_offset: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_124_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 124), + z0_res = svld1_gather_offset_u32 (p0, z0, 124)) + +/* +** ld1_gather_128_u32_offset: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_128_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_offset_u32 (p0, z0, 128), + z0_res = svld1_gather_offset_u32 (p0, z0, 128)) + +/* +** ld1_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?2 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svld1_gather_index_u32 (p0, z0, x0)) + +/* +** ld1_gather_m1_u32_index: +** mov (x[0-9]+), #?-4 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svld1_gather_index_u32 (p0, z0, -1)) + +/* +** ld1_gather_0_u32_index: +** ld1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svld1_gather_index_u32 (p0, z0, 0)) + +/* +** ld1_gather_5_u32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svld1_gather_index_u32 (p0, z0, 5)) + +/* +** ld1_gather_31_u32_index: +** ld1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svld1_gather_index_u32 (p0, z0, 31)) + +/* +** ld1_gather_32_u32_index: +** mov (x[0-9]+), #?128 +** ld1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svld1_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svld1_gather_index_u32 (p0, z0, 32)) + +/* +** ld1_gather_x0_u32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_u32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_u32_s32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32offset_u32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_u32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_u32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_u32_u32offset: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32offset_u32 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_x0_u32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_u32_s32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_u32_s32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svld1_gather_s32index_u32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_x0_u32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_u32_u32index: +** ld1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_u32_u32index: +** ld1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svld1_gather_u32index_u32 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u64.c new file mode 100644 index 00000000000..a1a5117e150 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_gather_u64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_gather_u64_tied1: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_u64 (p0, z0), + z0_res = svld1_gather_u64 (p0, z0)) + +/* +** ld1_gather_u64_untied: +** ld1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_u64 (p0, z1), + z0_res = svld1_gather_u64 (p0, z1)) + +/* +** ld1_gather_x0_u64_offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1_gather_m8_u64_offset: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m8_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, -8), + z0_res = svld1_gather_offset_u64 (p0, z0, -8)) + +/* +** ld1_gather_0_u64_offset: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1_gather_9_u64_offset: +** mov (x[0-9]+), #?9 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_9_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 9), + z0_res = svld1_gather_offset_u64 (p0, z0, 9)) + +/* +** ld1_gather_10_u64_offset: +** mov (x[0-9]+), #?10 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_10_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 10), + z0_res = svld1_gather_offset_u64 (p0, z0, 10)) + +/* +** ld1_gather_11_u64_offset: +** mov (x[0-9]+), #?11 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_11_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 11), + z0_res = svld1_gather_offset_u64 (p0, z0, 11)) + +/* +** ld1_gather_12_u64_offset: +** mov (x[0-9]+), #?12 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_12_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 12), + z0_res = svld1_gather_offset_u64 (p0, z0, 12)) + +/* +** ld1_gather_13_u64_offset: +** mov (x[0-9]+), #?13 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_13_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 13), + z0_res = svld1_gather_offset_u64 (p0, z0, 13)) + +/* +** ld1_gather_14_u64_offset: +** mov (x[0-9]+), #?14 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_14_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 14), + z0_res = svld1_gather_offset_u64 (p0, z0, 14)) + +/* +** ld1_gather_15_u64_offset: +** mov (x[0-9]+), #?15 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_15_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 15), + z0_res = svld1_gather_offset_u64 (p0, z0, 15)) + +/* +** ld1_gather_16_u64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_16_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 16), + z0_res = svld1_gather_offset_u64 (p0, z0, 16)) + +/* +** ld1_gather_248_u64_offset: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_248_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 248), + z0_res = svld1_gather_offset_u64 (p0, z0, 248)) + +/* +** ld1_gather_256_u64_offset: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_256_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_offset_u64 (p0, z0, 256), + z0_res = svld1_gather_offset_u64 (p0, z0, 256)) + +/* +** ld1_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?3 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svld1_gather_index_u64 (p0, z0, x0)) + +/* +** ld1_gather_m1_u64_index: +** mov (x[0-9]+), #?-8 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svld1_gather_index_u64 (p0, z0, -1)) + +/* +** ld1_gather_0_u64_index: +** ld1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svld1_gather_index_u64 (p0, z0, 0)) + +/* +** ld1_gather_5_u64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svld1_gather_index_u64 (p0, z0, 5)) + +/* +** ld1_gather_31_u64_index: +** ld1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svld1_gather_index_u64 (p0, z0, 31)) + +/* +** ld1_gather_32_u64_index: +** mov (x[0-9]+), #?256 +** ld1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svld1_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svld1_gather_index_u64 (p0, z0, 32)) + +/* +** ld1_gather_x0_u64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_u64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_u64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_u64_s64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_u64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_tied1_u64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1_gather_offset (p0, x0, z0)) + +/* +** ld1_gather_untied_u64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1_gather_offset (p0, x0, z1)) + +/* +** ld1_gather_ext_u64_u64offset: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_u64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_u64_s64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_u64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64index_u64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_u64_s64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svld1_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ld1_gather_x0_u64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_x0_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_tied1_u64_u64index: +** ld1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_tied1_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1_gather_index (p0, x0, z0)) + +/* +** ld1_gather_untied_u64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_untied_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64index_u64 (p0, x0, z1), + z0_res = svld1_gather_index (p0, x0, z1)) + +/* +** ld1_gather_ext_u64_u64index: +** ld1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1_gather_ext_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svld1_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s16.c new file mode 100644 index 00000000000..0e01b711e2e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_s16_base: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s16_base, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_s16_index: +** ld1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1_s16_index, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_s16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s16_1, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 + svcnth ()), + z0 = svld1 (p0, x0 + svcnth ())) + +/* +** ld1_s16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s16_7, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 + svcnth () * 7), + z0 = svld1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s16_8, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 + svcnth () * 8), + z0 = svld1 (p0, x0 + svcnth () * 8)) + +/* +** ld1_s16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s16_m1, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 - svcnth ()), + z0 = svld1 (p0, x0 - svcnth ())) + +/* +** ld1_s16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s16_m8, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 - svcnth () * 8), + z0 = svld1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s16_m9, svint16_t, int16_t, + z0 = svld1_s16 (p0, x0 - svcnth () * 9), + z0 = svld1 (p0, x0 - svcnth () * 9)) + +/* +** ld1_vnum_s16_0: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_0, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_s16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_1, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_s16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_7, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_8, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_s16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_m1, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_s16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_m8, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_m9, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_s16_x1, svint16_t, int16_t, + z0 = svld1_vnum_s16 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s32.c new file mode 100644 index 00000000000..3002381671d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_s32_base: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s32_base, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_s32_index: +** ld1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1_s32_index, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_s32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s32_1, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 + svcntw ()), + z0 = svld1 (p0, x0 + svcntw ())) + +/* +** ld1_s32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s32_7, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 + svcntw () * 7), + z0 = svld1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s32_8, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 + svcntw () * 8), + z0 = svld1 (p0, x0 + svcntw () * 8)) + +/* +** ld1_s32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s32_m1, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 - svcntw ()), + z0 = svld1 (p0, x0 - svcntw ())) + +/* +** ld1_s32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s32_m8, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 - svcntw () * 8), + z0 = svld1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s32_m9, svint32_t, int32_t, + z0 = svld1_s32 (p0, x0 - svcntw () * 9), + z0 = svld1 (p0, x0 - svcntw () * 9)) + +/* +** ld1_vnum_s32_0: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_0, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_s32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_1, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_s32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_7, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_8, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_s32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_m1, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_s32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_m8, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_m9, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_s32_x1, svint32_t, int32_t, + z0 = svld1_vnum_s32 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s64.c new file mode 100644 index 00000000000..a854450d074 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_s64_base: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s64_base, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_s64_index: +** ld1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1_s64_index, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_s64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s64_1, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 + svcntd ()), + z0 = svld1 (p0, x0 + svcntd ())) + +/* +** ld1_s64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s64_7, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 + svcntd () * 7), + z0 = svld1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s64_8, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 + svcntd () * 8), + z0 = svld1 (p0, x0 + svcntd () * 8)) + +/* +** ld1_s64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s64_m1, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 - svcntd ()), + z0 = svld1 (p0, x0 - svcntd ())) + +/* +** ld1_s64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s64_m8, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 - svcntd () * 8), + z0 = svld1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s64_m9, svint64_t, int64_t, + z0 = svld1_s64 (p0, x0 - svcntd () * 9), + z0 = svld1 (p0, x0 - svcntd () * 9)) + +/* +** ld1_vnum_s64_0: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_0, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_s64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_1, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_s64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_7, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_8, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_s64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_m1, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_s64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_m8, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_m9, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_s64_x1, svint64_t, int64_t, + z0 = svld1_vnum_s64 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s8.c new file mode 100644 index 00000000000..8fc61cae635 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_s8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_s8_base: +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s8_base, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_s8_index: +** ld1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1_s8_index, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_s8_1: +** ld1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s8_1, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 + svcntb ()), + z0 = svld1 (p0, x0 + svcntb ())) + +/* +** ld1_s8_7: +** ld1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s8_7, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 + svcntb () * 7), + z0 = svld1 (p0, x0 + svcntb () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s8_8: +** incb x0, all, mul #8 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s8_8, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 + svcntb () * 8), + z0 = svld1 (p0, x0 + svcntb () * 8)) + +/* +** ld1_s8_m1: +** ld1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s8_m1, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 - svcntb ()), + z0 = svld1 (p0, x0 - svcntb ())) + +/* +** ld1_s8_m8: +** ld1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_s8_m8, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 - svcntb () * 8), + z0 = svld1 (p0, x0 - svcntb () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_s8_m9: +** decb x0, all, mul #9 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_s8_m9, svint8_t, int8_t, + z0 = svld1_s8 (p0, x0 - svcntb () * 9), + z0 = svld1 (p0, x0 - svcntb () * 9)) + +/* +** ld1_vnum_s8_0: +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_0, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_s8_1: +** ld1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_1, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_s8_7: +** ld1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_7, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s8_8: +** incb x0, all, mul #8 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_8, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_s8_m1: +** ld1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_m1, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_s8_m8: +** ld1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_m8, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_s8_m9: +** decb x0, all, mul #9 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_s8_m9, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* +** ld1_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1_vnum_s8_x1, svint8_t, int8_t, + z0 = svld1_vnum_s8 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u16.c new file mode 100644 index 00000000000..5caa9daf819 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_u16_base: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u16_base, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_u16_index: +** ld1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1_u16_index, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_u16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u16_1, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 + svcnth ()), + z0 = svld1 (p0, x0 + svcnth ())) + +/* +** ld1_u16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u16_7, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 + svcnth () * 7), + z0 = svld1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u16_8, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 + svcnth () * 8), + z0 = svld1 (p0, x0 + svcnth () * 8)) + +/* +** ld1_u16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u16_m1, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 - svcnth ()), + z0 = svld1 (p0, x0 - svcnth ())) + +/* +** ld1_u16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u16_m8, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 - svcnth () * 8), + z0 = svld1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u16_m9, svuint16_t, uint16_t, + z0 = svld1_u16 (p0, x0 - svcnth () * 9), + z0 = svld1 (p0, x0 - svcnth () * 9)) + +/* +** ld1_vnum_u16_0: +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_0, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_u16_1: +** ld1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_1, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_u16_7: +** ld1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_7, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u16_8: +** incb x0, all, mul #8 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_8, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_u16_m1: +** ld1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_m1, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_u16_m8: +** ld1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_m8, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u16_m9: +** decb x0, all, mul #9 +** ld1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_m9, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_u16_x1, svuint16_t, uint16_t, + z0 = svld1_vnum_u16 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u32.c new file mode 100644 index 00000000000..8c5077d60ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_u32_base: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u32_base, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_u32_index: +** ld1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1_u32_index, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_u32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u32_1, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 + svcntw ()), + z0 = svld1 (p0, x0 + svcntw ())) + +/* +** ld1_u32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u32_7, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 + svcntw () * 7), + z0 = svld1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u32_8, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 + svcntw () * 8), + z0 = svld1 (p0, x0 + svcntw () * 8)) + +/* +** ld1_u32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u32_m1, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 - svcntw ()), + z0 = svld1 (p0, x0 - svcntw ())) + +/* +** ld1_u32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u32_m8, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 - svcntw () * 8), + z0 = svld1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u32_m9, svuint32_t, uint32_t, + z0 = svld1_u32 (p0, x0 - svcntw () * 9), + z0 = svld1 (p0, x0 - svcntw () * 9)) + +/* +** ld1_vnum_u32_0: +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_0, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_u32_1: +** ld1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_1, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_u32_7: +** ld1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_7, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u32_8: +** incb x0, all, mul #8 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_8, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_u32_m1: +** ld1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_m1, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_u32_m8: +** ld1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_m8, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u32_m9: +** decb x0, all, mul #9 +** ld1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_m9, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_u32_x1, svuint32_t, uint32_t, + z0 = svld1_vnum_u32 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u64.c new file mode 100644 index 00000000000..1893b3ed340 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_u64_base: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u64_base, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_u64_index: +** ld1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1_u64_index, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_u64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u64_1, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 + svcntd ()), + z0 = svld1 (p0, x0 + svcntd ())) + +/* +** ld1_u64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u64_7, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 + svcntd () * 7), + z0 = svld1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u64_8, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 + svcntd () * 8), + z0 = svld1 (p0, x0 + svcntd () * 8)) + +/* +** ld1_u64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u64_m1, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 - svcntd ()), + z0 = svld1 (p0, x0 - svcntd ())) + +/* +** ld1_u64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u64_m8, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 - svcntd () * 8), + z0 = svld1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u64_m9, svuint64_t, uint64_t, + z0 = svld1_u64 (p0, x0 - svcntd () * 9), + z0 = svld1 (p0, x0 - svcntd () * 9)) + +/* +** ld1_vnum_u64_0: +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_0, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_u64_1: +** ld1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_1, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_u64_7: +** ld1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_7, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u64_8: +** incb x0, all, mul #8 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_8, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_u64_m1: +** ld1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_m1, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_u64_m8: +** ld1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_m8, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u64_m9: +** decb x0, all, mul #9 +** ld1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_m9, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1_vnum_u64_x1, svuint64_t, uint64_t, + z0 = svld1_vnum_u64 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u8.c new file mode 100644 index 00000000000..b17b4b7c6d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1_u8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1_u8_base: +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u8_base, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0), + z0 = svld1 (p0, x0)) + +/* +** ld1_u8_index: +** ld1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1_u8_index, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 + x1), + z0 = svld1 (p0, x0 + x1)) + +/* +** ld1_u8_1: +** ld1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u8_1, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 + svcntb ()), + z0 = svld1 (p0, x0 + svcntb ())) + +/* +** ld1_u8_7: +** ld1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u8_7, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 + svcntb () * 7), + z0 = svld1 (p0, x0 + svcntb () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u8_8: +** incb x0, all, mul #8 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u8_8, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 + svcntb () * 8), + z0 = svld1 (p0, x0 + svcntb () * 8)) + +/* +** ld1_u8_m1: +** ld1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u8_m1, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 - svcntb ()), + z0 = svld1 (p0, x0 - svcntb ())) + +/* +** ld1_u8_m8: +** ld1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_u8_m8, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 - svcntb () * 8), + z0 = svld1 (p0, x0 - svcntb () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_u8_m9: +** decb x0, all, mul #9 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_u8_m9, svuint8_t, uint8_t, + z0 = svld1_u8 (p0, x0 - svcntb () * 9), + z0 = svld1 (p0, x0 - svcntb () * 9)) + +/* +** ld1_vnum_u8_0: +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_0, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, 0), + z0 = svld1_vnum (p0, x0, 0)) + +/* +** ld1_vnum_u8_1: +** ld1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_1, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, 1), + z0 = svld1_vnum (p0, x0, 1)) + +/* +** ld1_vnum_u8_7: +** ld1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_7, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, 7), + z0 = svld1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u8_8: +** incb x0, all, mul #8 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_8, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, 8), + z0 = svld1_vnum (p0, x0, 8)) + +/* +** ld1_vnum_u8_m1: +** ld1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_m1, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, -1), + z0 = svld1_vnum (p0, x0, -1)) + +/* +** ld1_vnum_u8_m8: +** ld1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_m8, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, -8), + z0 = svld1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1_vnum_u8_m9: +** decb x0, all, mul #9 +** ld1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1_vnum_u8_m9, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, -9), + z0 = svld1_vnum (p0, x0, -9)) + +/* +** ld1_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1_vnum_u8_x1, svuint8_t, uint8_t, + z0 = svld1_vnum_u8 (p0, x0, x1), + z0 = svld1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c new file mode 100644 index 00000000000..4071b6d1ba3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f16.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_f16_base: +** ld1rqh z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_f16_base, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_f16_index: { xfail *-*-* } +** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_index, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_f16_1: +** add (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_1, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_f16_4: +** add (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_4, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_f16_7: +** add (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_7, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 7), + z0 = svld1rq (p0, x0 + 7)) + +/* +** ld1rq_f16_8: +** ld1rqh z0\.h, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_f16_8, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 8), + z0 = svld1rq (p0, x0 + 8)) + +/* +** ld1rq_f16_56: +** ld1rqh z0\.h, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_f16_56, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 56), + z0 = svld1rq (p0, x0 + 56)) + +/* +** ld1rq_f16_64: +** add (x[0-9]+), x0, #?128 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_64, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 + 64), + z0 = svld1rq (p0, x0 + 64)) + +/* +** ld1rq_f16_m1: +** sub (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m1, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_f16_m4: +** sub (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m4, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_f16_m7: +** sub (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m7, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 7), + z0 = svld1rq (p0, x0 - 7)) + +/* +** ld1rq_f16_m8: +** ld1rqh z0\.h, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m8, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 8), + z0 = svld1rq (p0, x0 - 8)) + +/* +** ld1rq_f16_m64: +** ld1rqh z0\.h, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m64, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 64), + z0 = svld1rq (p0, x0 - 64)) + +/* +** ld1rq_f16_m72: +** sub (x[0-9]+), x0, #?144 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f16_m72, svfloat16_t, float16_t, + z0 = svld1rq_f16 (p0, x0 - 72), + z0 = svld1rq (p0, x0 - 72)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c new file mode 100644 index 00000000000..25013fcf0c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f32.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_f32_base: +** ld1rqw z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_f32_base, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_f32_index: { xfail *-*-* } +** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1rq_f32_index, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_f32_1: +** add (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_1, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_f32_2: +** add (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_2, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_f32_3: +** add (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_3, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 3), + z0 = svld1rq (p0, x0 + 3)) + +/* +** ld1rq_f32_4: +** ld1rqw z0\.s, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_f32_4, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_f32_28: +** ld1rqw z0\.s, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_f32_28, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 28), + z0 = svld1rq (p0, x0 + 28)) + +/* +** ld1rq_f32_32: +** add (x[0-9]+), x0, #?128 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_32, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 + 32), + z0 = svld1rq (p0, x0 + 32)) + +/* +** ld1rq_f32_m1: +** sub (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m1, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_f32_m2: +** sub (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m2, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_f32_m3: +** sub (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m3, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 3), + z0 = svld1rq (p0, x0 - 3)) + +/* +** ld1rq_f32_m4: +** ld1rqw z0\.s, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m4, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_f32_m32: +** ld1rqw z0\.s, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m32, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 32), + z0 = svld1rq (p0, x0 - 32)) + +/* +** ld1rq_f32_m36: +** sub (x[0-9]+), x0, #?144 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f32_m36, svfloat32_t, float32_t, + z0 = svld1rq_f32 (p0, x0 - 36), + z0 = svld1rq (p0, x0 - 36)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c new file mode 100644 index 00000000000..49f8da0803f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_f64.c @@ -0,0 +1,97 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_f64_base: +** ld1rqd z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_f64_base, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_f64_index: { xfail *-*-* } +** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1rq_f64_index, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_f64_1: +** add (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f64_1, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_f64_2: +** ld1rqd z0\.d, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_f64_2, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_f64_14: +** ld1rqd z0\.d, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_f64_14, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 + 14), + z0 = svld1rq (p0, x0 + 14)) + +/* +** ld1rq_f64_16: +** add (x[0-9]+), x0, #?128 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f64_16, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 + 16), + z0 = svld1rq (p0, x0 + 16)) + +/* +** ld1rq_f64_m1: +** sub (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f64_m1, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_f64_m2: +** ld1rqd z0\.d, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_f64_m2, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_f64_m16: +** ld1rqd z0\.d, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_f64_m16, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 - 16), + z0 = svld1rq (p0, x0 - 16)) + +/* +** ld1rq_f64_m18: +** sub (x[0-9]+), x0, #?144 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_f64_m18, svfloat64_t, float64_t, + z0 = svld1rq_f64 (p0, x0 - 18), + z0 = svld1rq (p0, x0 - 18)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c new file mode 100644 index 00000000000..c12b659c20e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s16.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_s16_base: +** ld1rqh z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_s16_base, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_s16_index: { xfail *-*-* } +** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_index, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_s16_1: +** add (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_1, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_s16_4: +** add (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_4, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_s16_7: +** add (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_7, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 7), + z0 = svld1rq (p0, x0 + 7)) + +/* +** ld1rq_s16_8: +** ld1rqh z0\.h, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_s16_8, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 8), + z0 = svld1rq (p0, x0 + 8)) + +/* +** ld1rq_s16_56: +** ld1rqh z0\.h, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_s16_56, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 56), + z0 = svld1rq (p0, x0 + 56)) + +/* +** ld1rq_s16_64: +** add (x[0-9]+), x0, #?128 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_64, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 + 64), + z0 = svld1rq (p0, x0 + 64)) + +/* +** ld1rq_s16_m1: +** sub (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m1, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_s16_m4: +** sub (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m4, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_s16_m7: +** sub (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m7, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 7), + z0 = svld1rq (p0, x0 - 7)) + +/* +** ld1rq_s16_m8: +** ld1rqh z0\.h, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m8, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 8), + z0 = svld1rq (p0, x0 - 8)) + +/* +** ld1rq_s16_m64: +** ld1rqh z0\.h, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m64, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 64), + z0 = svld1rq (p0, x0 - 64)) + +/* +** ld1rq_s16_m72: +** sub (x[0-9]+), x0, #?144 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s16_m72, svint16_t, int16_t, + z0 = svld1rq_s16 (p0, x0 - 72), + z0 = svld1rq (p0, x0 - 72)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c new file mode 100644 index 00000000000..8184ab80011 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s32.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_s32_base: +** ld1rqw z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_s32_base, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_s32_index: { xfail *-*-* } +** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1rq_s32_index, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_s32_1: +** add (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_1, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_s32_2: +** add (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_2, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_s32_3: +** add (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_3, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 3), + z0 = svld1rq (p0, x0 + 3)) + +/* +** ld1rq_s32_4: +** ld1rqw z0\.s, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_s32_4, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_s32_28: +** ld1rqw z0\.s, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_s32_28, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 28), + z0 = svld1rq (p0, x0 + 28)) + +/* +** ld1rq_s32_32: +** add (x[0-9]+), x0, #?128 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_32, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 + 32), + z0 = svld1rq (p0, x0 + 32)) + +/* +** ld1rq_s32_m1: +** sub (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m1, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_s32_m2: +** sub (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m2, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_s32_m3: +** sub (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m3, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 3), + z0 = svld1rq (p0, x0 - 3)) + +/* +** ld1rq_s32_m4: +** ld1rqw z0\.s, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m4, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_s32_m32: +** ld1rqw z0\.s, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m32, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 32), + z0 = svld1rq (p0, x0 - 32)) + +/* +** ld1rq_s32_m36: +** sub (x[0-9]+), x0, #?144 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s32_m36, svint32_t, int32_t, + z0 = svld1rq_s32 (p0, x0 - 36), + z0 = svld1rq (p0, x0 - 36)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c new file mode 100644 index 00000000000..616ce0bfa80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s64.c @@ -0,0 +1,97 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_s64_base: +** ld1rqd z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_s64_base, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_s64_index: { xfail *-*-* } +** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1rq_s64_index, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_s64_1: +** add (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s64_1, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_s64_2: +** ld1rqd z0\.d, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_s64_2, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_s64_14: +** ld1rqd z0\.d, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_s64_14, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 + 14), + z0 = svld1rq (p0, x0 + 14)) + +/* +** ld1rq_s64_16: +** add (x[0-9]+), x0, #?128 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s64_16, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 + 16), + z0 = svld1rq (p0, x0 + 16)) + +/* +** ld1rq_s64_m1: +** sub (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s64_m1, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_s64_m2: +** ld1rqd z0\.d, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_s64_m2, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_s64_m16: +** ld1rqd z0\.d, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_s64_m16, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 - 16), + z0 = svld1rq (p0, x0 - 16)) + +/* +** ld1rq_s64_m18: +** sub (x[0-9]+), x0, #?144 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s64_m18, svint64_t, int64_t, + z0 = svld1rq_s64 (p0, x0 - 18), + z0 = svld1rq (p0, x0 - 18)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s8.c new file mode 100644 index 00000000000..72600574fb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_s8.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_s8_base: +** ld1rqb z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_s8_base, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_s8_index: +** ld1rqb z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_index, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_s8_1: +** add (x[0-9]+), x0, #?1 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_1, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_s8_8: +** add (x[0-9]+), x0, #?8 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_8, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 8), + z0 = svld1rq (p0, x0 + 8)) + +/* +** ld1rq_s8_15: +** add (x[0-9]+), x0, #?15 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_15, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 15), + z0 = svld1rq (p0, x0 + 15)) + +/* +** ld1rq_s8_16: +** ld1rqb z0\.b, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_s8_16, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 16), + z0 = svld1rq (p0, x0 + 16)) + +/* +** ld1rq_s8_112: +** ld1rqb z0\.b, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_s8_112, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 112), + z0 = svld1rq (p0, x0 + 112)) + +/* +** ld1rq_s8_128: +** add (x[0-9]+), x0, #?128 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_128, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 + 128), + z0 = svld1rq (p0, x0 + 128)) + +/* +** ld1rq_s8_m1: +** sub (x[0-9]+), x0, #?1 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m1, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_s8_m8: +** sub (x[0-9]+), x0, #?8 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m8, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 8), + z0 = svld1rq (p0, x0 - 8)) + +/* +** ld1rq_s8_m15: +** sub (x[0-9]+), x0, #?15 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m15, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 15), + z0 = svld1rq (p0, x0 - 15)) + +/* +** ld1rq_s8_m16: +** ld1rqb z0\.b, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m16, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 16), + z0 = svld1rq (p0, x0 - 16)) + +/* +** ld1rq_s8_m128: +** ld1rqb z0\.b, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m128, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 128), + z0 = svld1rq (p0, x0 - 128)) + +/* +** ld1rq_s8_m144: +** sub (x[0-9]+), x0, #?144 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_s8_m144, svint8_t, int8_t, + z0 = svld1rq_s8 (p0, x0 - 144), + z0 = svld1rq (p0, x0 - 144)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c new file mode 100644 index 00000000000..1f543006c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u16.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_u16_base: +** ld1rqh z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_u16_base, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_u16_index: { xfail *-*-* } +** ld1rqh z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_index, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_u16_1: +** add (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_1, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_u16_4: +** add (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_4, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_u16_7: +** add (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_7, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 7), + z0 = svld1rq (p0, x0 + 7)) + +/* +** ld1rq_u16_8: +** ld1rqh z0\.h, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_u16_8, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 8), + z0 = svld1rq (p0, x0 + 8)) + +/* +** ld1rq_u16_56: +** ld1rqh z0\.h, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_u16_56, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 56), + z0 = svld1rq (p0, x0 + 56)) + +/* +** ld1rq_u16_64: +** add (x[0-9]+), x0, #?128 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_64, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 + 64), + z0 = svld1rq (p0, x0 + 64)) + +/* +** ld1rq_u16_m1: +** sub (x[0-9]+), x0, #?2 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m1, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_u16_m4: +** sub (x[0-9]+), x0, #?8 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m4, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_u16_m7: +** sub (x[0-9]+), x0, #?14 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m7, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 7), + z0 = svld1rq (p0, x0 - 7)) + +/* +** ld1rq_u16_m8: +** ld1rqh z0\.h, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m8, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 8), + z0 = svld1rq (p0, x0 - 8)) + +/* +** ld1rq_u16_m64: +** ld1rqh z0\.h, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m64, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 64), + z0 = svld1rq (p0, x0 - 64)) + +/* +** ld1rq_u16_m72: +** sub (x[0-9]+), x0, #?144 +** ld1rqh z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u16_m72, svuint16_t, uint16_t, + z0 = svld1rq_u16 (p0, x0 - 72), + z0 = svld1rq (p0, x0 - 72)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c new file mode 100644 index 00000000000..e2a348d00ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u32.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_u32_base: +** ld1rqw z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_u32_base, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_u32_index: { xfail *-*-* } +** ld1rqw z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1rq_u32_index, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_u32_1: +** add (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_1, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_u32_2: +** add (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_2, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_u32_3: +** add (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_3, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 3), + z0 = svld1rq (p0, x0 + 3)) + +/* +** ld1rq_u32_4: +** ld1rqw z0\.s, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_u32_4, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 4), + z0 = svld1rq (p0, x0 + 4)) + +/* +** ld1rq_u32_28: +** ld1rqw z0\.s, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_u32_28, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 28), + z0 = svld1rq (p0, x0 + 28)) + +/* +** ld1rq_u32_32: +** add (x[0-9]+), x0, #?128 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_32, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 + 32), + z0 = svld1rq (p0, x0 + 32)) + +/* +** ld1rq_u32_m1: +** sub (x[0-9]+), x0, #?4 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m1, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_u32_m2: +** sub (x[0-9]+), x0, #?8 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m2, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_u32_m3: +** sub (x[0-9]+), x0, #?12 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m3, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 3), + z0 = svld1rq (p0, x0 - 3)) + +/* +** ld1rq_u32_m4: +** ld1rqw z0\.s, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m4, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 4), + z0 = svld1rq (p0, x0 - 4)) + +/* +** ld1rq_u32_m32: +** ld1rqw z0\.s, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m32, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 32), + z0 = svld1rq (p0, x0 - 32)) + +/* +** ld1rq_u32_m36: +** sub (x[0-9]+), x0, #?144 +** ld1rqw z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u32_m36, svuint32_t, uint32_t, + z0 = svld1rq_u32 (p0, x0 - 36), + z0 = svld1rq (p0, x0 - 36)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c new file mode 100644 index 00000000000..bf9d7201677 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u64.c @@ -0,0 +1,97 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_u64_base: +** ld1rqd z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_u64_base, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_u64_index: { xfail *-*-* } +** ld1rqd z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld1rq_u64_index, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_u64_1: +** add (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u64_1, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_u64_2: +** ld1rqd z0\.d, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_u64_2, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 + 2), + z0 = svld1rq (p0, x0 + 2)) + +/* +** ld1rq_u64_14: +** ld1rqd z0\.d, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_u64_14, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 + 14), + z0 = svld1rq (p0, x0 + 14)) + +/* +** ld1rq_u64_16: +** add (x[0-9]+), x0, #?128 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u64_16, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 + 16), + z0 = svld1rq (p0, x0 + 16)) + +/* +** ld1rq_u64_m1: +** sub (x[0-9]+), x0, #?8 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u64_m1, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_u64_m2: +** ld1rqd z0\.d, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_u64_m2, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 - 2), + z0 = svld1rq (p0, x0 - 2)) + +/* +** ld1rq_u64_m16: +** ld1rqd z0\.d, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_u64_m16, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 - 16), + z0 = svld1rq (p0, x0 - 16)) + +/* +** ld1rq_u64_m18: +** sub (x[0-9]+), x0, #?144 +** ld1rqd z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u64_m18, svuint64_t, uint64_t, + z0 = svld1rq_u64 (p0, x0 - 18), + z0 = svld1rq (p0, x0 - 18)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u8.c new file mode 100644 index 00000000000..69616622ce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1rq_u8.c @@ -0,0 +1,137 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1rq_u8_base: +** ld1rqb z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1rq_u8_base, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0), + z0 = svld1rq (p0, x0)) + +/* +** ld1rq_u8_index: +** ld1rqb z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_index, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + x1), + z0 = svld1rq (p0, x0 + x1)) + +/* +** ld1rq_u8_1: +** add (x[0-9]+), x0, #?1 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_1, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 1), + z0 = svld1rq (p0, x0 + 1)) + +/* +** ld1rq_u8_8: +** add (x[0-9]+), x0, #?8 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_8, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 8), + z0 = svld1rq (p0, x0 + 8)) + +/* +** ld1rq_u8_15: +** add (x[0-9]+), x0, #?15 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_15, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 15), + z0 = svld1rq (p0, x0 + 15)) + +/* +** ld1rq_u8_16: +** ld1rqb z0\.b, p0/z, \[x0, #?16\] +** ret +*/ +TEST_LOAD (ld1rq_u8_16, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 16), + z0 = svld1rq (p0, x0 + 16)) + +/* +** ld1rq_u8_112: +** ld1rqb z0\.b, p0/z, \[x0, #?112\] +** ret +*/ +TEST_LOAD (ld1rq_u8_112, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 112), + z0 = svld1rq (p0, x0 + 112)) + +/* +** ld1rq_u8_128: +** add (x[0-9]+), x0, #?128 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_128, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 + 128), + z0 = svld1rq (p0, x0 + 128)) + +/* +** ld1rq_u8_m1: +** sub (x[0-9]+), x0, #?1 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m1, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 1), + z0 = svld1rq (p0, x0 - 1)) + +/* +** ld1rq_u8_m8: +** sub (x[0-9]+), x0, #?8 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m8, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 8), + z0 = svld1rq (p0, x0 - 8)) + +/* +** ld1rq_u8_m15: +** sub (x[0-9]+), x0, #?15 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m15, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 15), + z0 = svld1rq (p0, x0 - 15)) + +/* +** ld1rq_u8_m16: +** ld1rqb z0\.b, p0/z, \[x0, #?-16\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m16, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 16), + z0 = svld1rq (p0, x0 - 16)) + +/* +** ld1rq_u8_m128: +** ld1rqb z0\.b, p0/z, \[x0, #?-128\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m128, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 128), + z0 = svld1rq (p0, x0 - 128)) + +/* +** ld1rq_u8_m144: +** sub (x[0-9]+), x0, #?144 +** ld1rqb z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld1rq_u8_m144, svuint8_t, uint8_t, + z0 = svld1rq_u8 (p0, x0 - 144), + z0 = svld1rq (p0, x0 - 144)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s32.c new file mode 100644 index 00000000000..a492d925b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_gather_s32_tied1: +** ld1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_s32 (p0, z0), + z0_res = svld1sb_gather_s32 (p0, z0)) + +/* +** ld1sb_gather_s32_untied: +** ld1sb z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_s32 (p0, z1), + z0_res = svld1sb_gather_s32 (p0, z1)) + +/* +** ld1sb_gather_x0_s32_offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svld1sb_gather_offset_s32 (p0, z0, x0)) + +/* +** ld1sb_gather_m1_s32_offset: +** mov (x[0-9]+), #?-1 +** ld1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_m1_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, -1), + z0_res = svld1sb_gather_offset_s32 (p0, z0, -1)) + +/* +** ld1sb_gather_0_s32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svld1sb_gather_offset_s32 (p0, z0, 0)) + +/* +** ld1sb_gather_5_s32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svld1sb_gather_offset_s32 (p0, z0, 5)) + +/* +** ld1sb_gather_31_s32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_31_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, 31), + z0_res = svld1sb_gather_offset_s32 (p0, z0, 31)) + +/* +** ld1sb_gather_32_s32_offset: +** mov (x[0-9]+), #?32 +** ld1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_32_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_s32 (p0, z0, 32), + z0_res = svld1sb_gather_offset_s32 (p0, z0, 32)) + +/* +** ld1sb_gather_x0_s32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_s32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_s32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_s32 (p0, x0, z1), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1sb_gather_x0_s32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_s32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_s32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_s32 (p0, x0, z1), + z0_res = svld1sb_gather_offset_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s64.c new file mode 100644 index 00000000000..611741b6c26 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_s64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_gather_s64_tied1: +** ld1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_s64 (p0, z0), + z0_res = svld1sb_gather_s64 (p0, z0)) + +/* +** ld1sb_gather_s64_untied: +** ld1sb z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_s64 (p0, z1), + z0_res = svld1sb_gather_s64 (p0, z1)) + +/* +** ld1sb_gather_x0_s64_offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1sb_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1sb_gather_m1_s64_offset: +** mov (x[0-9]+), #?-1 +** ld1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_m1_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, -1), + z0_res = svld1sb_gather_offset_s64 (p0, z0, -1)) + +/* +** ld1sb_gather_0_s64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1sb_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1sb_gather_5_s64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1sb_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1sb_gather_31_s64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_31_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, 31), + z0_res = svld1sb_gather_offset_s64 (p0, z0, 31)) + +/* +** ld1sb_gather_32_s64_offset: +** mov (x[0-9]+), #?32 +** ld1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_32_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_s64 (p0, z0, 32), + z0_res = svld1sb_gather_offset_s64 (p0, z0, 32)) + +/* +** ld1sb_gather_x0_s64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_s64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_s64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sb_gather_ext_s64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_ext_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sb_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sb_gather_x0_s64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_s64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_s64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1sb_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sb_gather_ext_s64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_ext_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sb_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u32.c new file mode 100644 index 00000000000..5388897d40e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_gather_u32_tied1: +** ld1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_u32 (p0, z0), + z0_res = svld1sb_gather_u32 (p0, z0)) + +/* +** ld1sb_gather_u32_untied: +** ld1sb z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_u32 (p0, z1), + z0_res = svld1sb_gather_u32 (p0, z1)) + +/* +** ld1sb_gather_x0_u32_offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svld1sb_gather_offset_u32 (p0, z0, x0)) + +/* +** ld1sb_gather_m1_u32_offset: +** mov (x[0-9]+), #?-1 +** ld1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_m1_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, -1), + z0_res = svld1sb_gather_offset_u32 (p0, z0, -1)) + +/* +** ld1sb_gather_0_u32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svld1sb_gather_offset_u32 (p0, z0, 0)) + +/* +** ld1sb_gather_5_u32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svld1sb_gather_offset_u32 (p0, z0, 5)) + +/* +** ld1sb_gather_31_u32_offset: +** ld1sb z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_31_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, 31), + z0_res = svld1sb_gather_offset_u32 (p0, z0, 31)) + +/* +** ld1sb_gather_32_u32_offset: +** mov (x[0-9]+), #?32 +** ld1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_32_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sb_gather_u32base_offset_u32 (p0, z0, 32), + z0_res = svld1sb_gather_offset_u32 (p0, z0, 32)) + +/* +** ld1sb_gather_x0_u32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_u32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_u32_s32offset: +** ld1sb z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svld1sb_gather_s32offset_u32 (p0, x0, z1), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1sb_gather_x0_u32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_u32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_u32_u32offset: +** ld1sb z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svld1sb_gather_u32offset_u32 (p0, x0, z1), + z0_res = svld1sb_gather_offset_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u64.c new file mode 100644 index 00000000000..7b3504bb133 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_gather_u64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_gather_u64_tied1: +** ld1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_u64 (p0, z0), + z0_res = svld1sb_gather_u64 (p0, z0)) + +/* +** ld1sb_gather_u64_untied: +** ld1sb z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_u64 (p0, z1), + z0_res = svld1sb_gather_u64 (p0, z1)) + +/* +** ld1sb_gather_x0_u64_offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1sb_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1sb_gather_m1_u64_offset: +** mov (x[0-9]+), #?-1 +** ld1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_m1_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, -1), + z0_res = svld1sb_gather_offset_u64 (p0, z0, -1)) + +/* +** ld1sb_gather_0_u64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1sb_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1sb_gather_5_u64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1sb_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1sb_gather_31_u64_offset: +** ld1sb z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_31_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, 31), + z0_res = svld1sb_gather_offset_u64 (p0, z0, 31)) + +/* +** ld1sb_gather_32_u64_offset: +** mov (x[0-9]+), #?32 +** ld1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sb_gather_32_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sb_gather_u64base_offset_u64 (p0, z0, 32), + z0_res = svld1sb_gather_offset_u64 (p0, z0, 32)) + +/* +** ld1sb_gather_x0_u64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_u64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_u64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sb_gather_ext_u64_s64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_ext_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svld1sb_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sb_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sb_gather_x0_u64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_x0_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sb_gather_tied1_u64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_tied1_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sb_gather_untied_u64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_untied_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1sb_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sb_gather_ext_u64_u64offset: +** ld1sb z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sb_gather_ext_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svld1sb_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sb_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s16.c new file mode 100644 index 00000000000..ad97398bc67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_s16_base: +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s16_base, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0), + z0 = svld1sb_s16 (p0, x0)) + +/* +** ld1sb_s16_index: +** ld1sb z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_s16_index, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 + x1), + z0 = svld1sb_s16 (p0, x0 + x1)) + +/* +** ld1sb_s16_1: +** ld1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s16_1, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 + svcnth ()), + z0 = svld1sb_s16 (p0, x0 + svcnth ())) + +/* +** ld1sb_s16_7: +** ld1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s16_7, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 + svcnth () * 7), + z0 = svld1sb_s16 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s16_8: +** incb x0, all, mul #4 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s16_8, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 + svcnth () * 8), + z0 = svld1sb_s16 (p0, x0 + svcnth () * 8)) + +/* +** ld1sb_s16_m1: +** ld1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s16_m1, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 - svcnth ()), + z0 = svld1sb_s16 (p0, x0 - svcnth ())) + +/* +** ld1sb_s16_m8: +** ld1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s16_m8, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 - svcnth () * 8), + z0 = svld1sb_s16 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s16_m9: +** dech x0, all, mul #9 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s16_m9, svint16_t, int8_t, + z0 = svld1sb_s16 (p0, x0 - svcnth () * 9), + z0 = svld1sb_s16 (p0, x0 - svcnth () * 9)) + +/* +** ld1sb_vnum_s16_0: +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_0, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, 0), + z0 = svld1sb_vnum_s16 (p0, x0, 0)) + +/* +** ld1sb_vnum_s16_1: +** ld1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_1, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, 1), + z0 = svld1sb_vnum_s16 (p0, x0, 1)) + +/* +** ld1sb_vnum_s16_7: +** ld1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_7, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, 7), + z0 = svld1sb_vnum_s16 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s16_8: +** incb x0, all, mul #4 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_8, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, 8), + z0 = svld1sb_vnum_s16 (p0, x0, 8)) + +/* +** ld1sb_vnum_s16_m1: +** ld1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_m1, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, -1), + z0 = svld1sb_vnum_s16 (p0, x0, -1)) + +/* +** ld1sb_vnum_s16_m8: +** ld1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_m8, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, -8), + z0 = svld1sb_vnum_s16 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s16_m9: +** dech x0, all, mul #9 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_m9, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, -9), + z0 = svld1sb_vnum_s16 (p0, x0, -9)) + +/* +** ld1sb_vnum_s16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_s16_x1, svint16_t, int8_t, + z0 = svld1sb_vnum_s16 (p0, x0, x1), + z0 = svld1sb_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s32.c new file mode 100644 index 00000000000..97b04fb8562 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_s32_base: +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s32_base, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0), + z0 = svld1sb_s32 (p0, x0)) + +/* +** ld1sb_s32_index: +** ld1sb z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_s32_index, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 + x1), + z0 = svld1sb_s32 (p0, x0 + x1)) + +/* +** ld1sb_s32_1: +** ld1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s32_1, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 + svcntw ()), + z0 = svld1sb_s32 (p0, x0 + svcntw ())) + +/* +** ld1sb_s32_7: +** ld1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s32_7, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 + svcntw () * 7), + z0 = svld1sb_s32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s32_8: +** incb x0, all, mul #2 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s32_8, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 + svcntw () * 8), + z0 = svld1sb_s32 (p0, x0 + svcntw () * 8)) + +/* +** ld1sb_s32_m1: +** ld1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s32_m1, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 - svcntw ()), + z0 = svld1sb_s32 (p0, x0 - svcntw ())) + +/* +** ld1sb_s32_m8: +** ld1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s32_m8, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 - svcntw () * 8), + z0 = svld1sb_s32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s32_m9: +** decw x0, all, mul #9 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s32_m9, svint32_t, int8_t, + z0 = svld1sb_s32 (p0, x0 - svcntw () * 9), + z0 = svld1sb_s32 (p0, x0 - svcntw () * 9)) + +/* +** ld1sb_vnum_s32_0: +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_0, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, 0), + z0 = svld1sb_vnum_s32 (p0, x0, 0)) + +/* +** ld1sb_vnum_s32_1: +** ld1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_1, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, 1), + z0 = svld1sb_vnum_s32 (p0, x0, 1)) + +/* +** ld1sb_vnum_s32_7: +** ld1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_7, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, 7), + z0 = svld1sb_vnum_s32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s32_8: +** incb x0, all, mul #2 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_8, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, 8), + z0 = svld1sb_vnum_s32 (p0, x0, 8)) + +/* +** ld1sb_vnum_s32_m1: +** ld1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_m1, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, -1), + z0 = svld1sb_vnum_s32 (p0, x0, -1)) + +/* +** ld1sb_vnum_s32_m8: +** ld1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_m8, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, -8), + z0 = svld1sb_vnum_s32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s32_m9: +** decw x0, all, mul #9 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_m9, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, -9), + z0 = svld1sb_vnum_s32 (p0, x0, -9)) + +/* +** ld1sb_vnum_s32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_s32_x1, svint32_t, int8_t, + z0 = svld1sb_vnum_s32 (p0, x0, x1), + z0 = svld1sb_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s64.c new file mode 100644 index 00000000000..ca7c2aee67a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_s64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_s64_base: +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s64_base, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0), + z0 = svld1sb_s64 (p0, x0)) + +/* +** ld1sb_s64_index: +** ld1sb z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_s64_index, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 + x1), + z0 = svld1sb_s64 (p0, x0 + x1)) + +/* +** ld1sb_s64_1: +** ld1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s64_1, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 + svcntd ()), + z0 = svld1sb_s64 (p0, x0 + svcntd ())) + +/* +** ld1sb_s64_7: +** ld1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s64_7, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 + svcntd () * 7), + z0 = svld1sb_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s64_8: +** incb x0 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s64_8, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 + svcntd () * 8), + z0 = svld1sb_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sb_s64_m1: +** ld1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s64_m1, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 - svcntd ()), + z0 = svld1sb_s64 (p0, x0 - svcntd ())) + +/* +** ld1sb_s64_m8: +** ld1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_s64_m8, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 - svcntd () * 8), + z0 = svld1sb_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_s64_m9: +** decd x0, all, mul #9 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_s64_m9, svint64_t, int8_t, + z0 = svld1sb_s64 (p0, x0 - svcntd () * 9), + z0 = svld1sb_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sb_vnum_s64_0: +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_0, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, 0), + z0 = svld1sb_vnum_s64 (p0, x0, 0)) + +/* +** ld1sb_vnum_s64_1: +** ld1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_1, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, 1), + z0 = svld1sb_vnum_s64 (p0, x0, 1)) + +/* +** ld1sb_vnum_s64_7: +** ld1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_7, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, 7), + z0 = svld1sb_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s64_8: +** incb x0 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_8, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, 8), + z0 = svld1sb_vnum_s64 (p0, x0, 8)) + +/* +** ld1sb_vnum_s64_m1: +** ld1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_m1, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, -1), + z0 = svld1sb_vnum_s64 (p0, x0, -1)) + +/* +** ld1sb_vnum_s64_m8: +** ld1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_m8, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, -8), + z0 = svld1sb_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_s64_m9: +** decd x0, all, mul #9 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_m9, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, -9), + z0 = svld1sb_vnum_s64 (p0, x0, -9)) + +/* +** ld1sb_vnum_s64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_s64_x1, svint64_t, int8_t, + z0 = svld1sb_vnum_s64 (p0, x0, x1), + z0 = svld1sb_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u16.c new file mode 100644 index 00000000000..2906ce8bf72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_u16_base: +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u16_base, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0), + z0 = svld1sb_u16 (p0, x0)) + +/* +** ld1sb_u16_index: +** ld1sb z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_u16_index, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 + x1), + z0 = svld1sb_u16 (p0, x0 + x1)) + +/* +** ld1sb_u16_1: +** ld1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u16_1, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 + svcnth ()), + z0 = svld1sb_u16 (p0, x0 + svcnth ())) + +/* +** ld1sb_u16_7: +** ld1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u16_7, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 + svcnth () * 7), + z0 = svld1sb_u16 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u16_8: +** incb x0, all, mul #4 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u16_8, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 + svcnth () * 8), + z0 = svld1sb_u16 (p0, x0 + svcnth () * 8)) + +/* +** ld1sb_u16_m1: +** ld1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u16_m1, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 - svcnth ()), + z0 = svld1sb_u16 (p0, x0 - svcnth ())) + +/* +** ld1sb_u16_m8: +** ld1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u16_m8, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 - svcnth () * 8), + z0 = svld1sb_u16 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u16_m9: +** dech x0, all, mul #9 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u16_m9, svuint16_t, int8_t, + z0 = svld1sb_u16 (p0, x0 - svcnth () * 9), + z0 = svld1sb_u16 (p0, x0 - svcnth () * 9)) + +/* +** ld1sb_vnum_u16_0: +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_0, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, 0), + z0 = svld1sb_vnum_u16 (p0, x0, 0)) + +/* +** ld1sb_vnum_u16_1: +** ld1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_1, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, 1), + z0 = svld1sb_vnum_u16 (p0, x0, 1)) + +/* +** ld1sb_vnum_u16_7: +** ld1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_7, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, 7), + z0 = svld1sb_vnum_u16 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u16_8: +** incb x0, all, mul #4 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_8, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, 8), + z0 = svld1sb_vnum_u16 (p0, x0, 8)) + +/* +** ld1sb_vnum_u16_m1: +** ld1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_m1, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, -1), + z0 = svld1sb_vnum_u16 (p0, x0, -1)) + +/* +** ld1sb_vnum_u16_m8: +** ld1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_m8, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, -8), + z0 = svld1sb_vnum_u16 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u16_m9: +** dech x0, all, mul #9 +** ld1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_m9, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, -9), + z0 = svld1sb_vnum_u16 (p0, x0, -9)) + +/* +** ld1sb_vnum_u16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_u16_x1, svuint16_t, int8_t, + z0 = svld1sb_vnum_u16 (p0, x0, x1), + z0 = svld1sb_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u32.c new file mode 100644 index 00000000000..3e898285b75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_u32_base: +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u32_base, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0), + z0 = svld1sb_u32 (p0, x0)) + +/* +** ld1sb_u32_index: +** ld1sb z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_u32_index, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 + x1), + z0 = svld1sb_u32 (p0, x0 + x1)) + +/* +** ld1sb_u32_1: +** ld1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u32_1, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 + svcntw ()), + z0 = svld1sb_u32 (p0, x0 + svcntw ())) + +/* +** ld1sb_u32_7: +** ld1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u32_7, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 + svcntw () * 7), + z0 = svld1sb_u32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u32_8: +** incb x0, all, mul #2 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u32_8, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 + svcntw () * 8), + z0 = svld1sb_u32 (p0, x0 + svcntw () * 8)) + +/* +** ld1sb_u32_m1: +** ld1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u32_m1, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 - svcntw ()), + z0 = svld1sb_u32 (p0, x0 - svcntw ())) + +/* +** ld1sb_u32_m8: +** ld1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u32_m8, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 - svcntw () * 8), + z0 = svld1sb_u32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u32_m9: +** decw x0, all, mul #9 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u32_m9, svuint32_t, int8_t, + z0 = svld1sb_u32 (p0, x0 - svcntw () * 9), + z0 = svld1sb_u32 (p0, x0 - svcntw () * 9)) + +/* +** ld1sb_vnum_u32_0: +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_0, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, 0), + z0 = svld1sb_vnum_u32 (p0, x0, 0)) + +/* +** ld1sb_vnum_u32_1: +** ld1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_1, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, 1), + z0 = svld1sb_vnum_u32 (p0, x0, 1)) + +/* +** ld1sb_vnum_u32_7: +** ld1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_7, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, 7), + z0 = svld1sb_vnum_u32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u32_8: +** incb x0, all, mul #2 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_8, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, 8), + z0 = svld1sb_vnum_u32 (p0, x0, 8)) + +/* +** ld1sb_vnum_u32_m1: +** ld1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_m1, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, -1), + z0 = svld1sb_vnum_u32 (p0, x0, -1)) + +/* +** ld1sb_vnum_u32_m8: +** ld1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_m8, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, -8), + z0 = svld1sb_vnum_u32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u32_m9: +** decw x0, all, mul #9 +** ld1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_m9, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, -9), + z0 = svld1sb_vnum_u32 (p0, x0, -9)) + +/* +** ld1sb_vnum_u32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_u32_x1, svuint32_t, int8_t, + z0 = svld1sb_vnum_u32 (p0, x0, x1), + z0 = svld1sb_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u64.c new file mode 100644 index 00000000000..1a2f9aaae31 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sb_u64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sb_u64_base: +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u64_base, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0), + z0 = svld1sb_u64 (p0, x0)) + +/* +** ld1sb_u64_index: +** ld1sb z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1sb_u64_index, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 + x1), + z0 = svld1sb_u64 (p0, x0 + x1)) + +/* +** ld1sb_u64_1: +** ld1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u64_1, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 + svcntd ()), + z0 = svld1sb_u64 (p0, x0 + svcntd ())) + +/* +** ld1sb_u64_7: +** ld1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u64_7, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 + svcntd () * 7), + z0 = svld1sb_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u64_8: +** incb x0 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u64_8, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 + svcntd () * 8), + z0 = svld1sb_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sb_u64_m1: +** ld1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u64_m1, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 - svcntd ()), + z0 = svld1sb_u64 (p0, x0 - svcntd ())) + +/* +** ld1sb_u64_m8: +** ld1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_u64_m8, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 - svcntd () * 8), + z0 = svld1sb_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_u64_m9: +** decd x0, all, mul #9 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_u64_m9, svuint64_t, int8_t, + z0 = svld1sb_u64 (p0, x0 - svcntd () * 9), + z0 = svld1sb_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sb_vnum_u64_0: +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_0, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, 0), + z0 = svld1sb_vnum_u64 (p0, x0, 0)) + +/* +** ld1sb_vnum_u64_1: +** ld1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_1, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, 1), + z0 = svld1sb_vnum_u64 (p0, x0, 1)) + +/* +** ld1sb_vnum_u64_7: +** ld1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_7, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, 7), + z0 = svld1sb_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u64_8: +** incb x0 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_8, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, 8), + z0 = svld1sb_vnum_u64 (p0, x0, 8)) + +/* +** ld1sb_vnum_u64_m1: +** ld1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_m1, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, -1), + z0 = svld1sb_vnum_u64 (p0, x0, -1)) + +/* +** ld1sb_vnum_u64_m8: +** ld1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_m8, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, -8), + z0 = svld1sb_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sb_vnum_u64_m9: +** decd x0, all, mul #9 +** ld1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_m9, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, -9), + z0 = svld1sb_vnum_u64 (p0, x0, -9)) + +/* +** ld1sb_vnum_u64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1sb z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1sb z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1sb_vnum_u64_x1, svuint64_t, int8_t, + z0 = svld1sb_vnum_u64 (p0, x0, x1), + z0 = svld1sb_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s32.c new file mode 100644 index 00000000000..03caf45ca2a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_gather_s32_tied1: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_s32 (p0, z0), + z0_res = svld1sh_gather_s32 (p0, z0)) + +/* +** ld1sh_gather_s32_untied: +** ld1sh z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_s32 (p0, z1), + z0_res = svld1sh_gather_s32 (p0, z1)) + +/* +** ld1sh_gather_x0_s32_offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svld1sh_gather_offset_s32 (p0, z0, x0)) + +/* +** ld1sh_gather_m2_s32_offset: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m2_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, -2), + z0_res = svld1sh_gather_offset_s32 (p0, z0, -2)) + +/* +** ld1sh_gather_0_s32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svld1sh_gather_offset_s32 (p0, z0, 0)) + +/* +** ld1sh_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svld1sh_gather_offset_s32 (p0, z0, 5)) + +/* +** ld1sh_gather_6_s32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svld1sh_gather_offset_s32 (p0, z0, 6)) + +/* +** ld1sh_gather_62_s32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_62_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, 62), + z0_res = svld1sh_gather_offset_s32 (p0, z0, 62)) + +/* +** ld1sh_gather_64_s32_offset: +** mov (x[0-9]+), #?64 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_64_s32_offset, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_s32 (p0, z0, 64), + z0_res = svld1sh_gather_offset_s32 (p0, z0, 64)) + +/* +** ld1sh_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?1 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svld1sh_gather_index_s32 (p0, z0, x0)) + +/* +** ld1sh_gather_m1_s32_index: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svld1sh_gather_index_s32 (p0, z0, -1)) + +/* +** ld1sh_gather_0_s32_index: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svld1sh_gather_index_s32 (p0, z0, 0)) + +/* +** ld1sh_gather_5_s32_index: +** ld1sh z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svld1sh_gather_index_s32 (p0, z0, 5)) + +/* +** ld1sh_gather_31_s32_index: +** ld1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svld1sh_gather_index_s32 (p0, z0, 31)) + +/* +** ld1sh_gather_32_s32_index: +** mov (x[0-9]+), #?64 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svld1sh_gather_index_s32 (p0, z0, 32)) + +/* +** ld1sh_gather_x0_s32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_s32 (p0, x0, z1), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_s32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_s32 (p0, x0, z1), + z0_res = svld1sh_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_s32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_s32 (p0, x0, z1), + z0_res = svld1sh_gather_index_s32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_s32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_s32 (p0, x0, z1), + z0_res = svld1sh_gather_index_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s64.c new file mode 100644 index 00000000000..6e39f45db4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_s64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_gather_s64_tied1: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_s64 (p0, z0), + z0_res = svld1sh_gather_s64 (p0, z0)) + +/* +** ld1sh_gather_s64_untied: +** ld1sh z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_s64 (p0, z1), + z0_res = svld1sh_gather_s64 (p0, z1)) + +/* +** ld1sh_gather_x0_s64_offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1sh_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1sh_gather_m2_s64_offset: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m2_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, -2), + z0_res = svld1sh_gather_offset_s64 (p0, z0, -2)) + +/* +** ld1sh_gather_0_s64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1sh_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1sh_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1sh_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1sh_gather_6_s64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svld1sh_gather_offset_s64 (p0, z0, 6)) + +/* +** ld1sh_gather_62_s64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_62_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, 62), + z0_res = svld1sh_gather_offset_s64 (p0, z0, 62)) + +/* +** ld1sh_gather_64_s64_offset: +** mov (x[0-9]+), #?64 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_64_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_s64 (p0, z0, 64), + z0_res = svld1sh_gather_offset_s64 (p0, z0, 64)) + +/* +** ld1sh_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?1 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svld1sh_gather_index_s64 (p0, z0, x0)) + +/* +** ld1sh_gather_m1_s64_index: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svld1sh_gather_index_s64 (p0, z0, -1)) + +/* +** ld1sh_gather_0_s64_index: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svld1sh_gather_index_s64 (p0, z0, 0)) + +/* +** ld1sh_gather_5_s64_index: +** ld1sh z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svld1sh_gather_index_s64 (p0, z0, 5)) + +/* +** ld1sh_gather_31_s64_index: +** ld1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svld1sh_gather_index_s64 (p0, z0, 31)) + +/* +** ld1sh_gather_32_s64_index: +** mov (x[0-9]+), #?64 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svld1sh_gather_index_s64 (p0, z0, 32)) + +/* +** ld1sh_gather_x0_s64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_s64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_s64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1sh_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_s64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_s64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_s64 (p0, x0, z1), + z0_res = svld1sh_gather_index_s64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_s64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_s64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_s64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_s64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_s64 (p0, x0, z1), + z0_res = svld1sh_gather_index_s64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_s64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u32.c new file mode 100644 index 00000000000..6be0cf29748 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_gather_u32_tied1: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_u32 (p0, z0), + z0_res = svld1sh_gather_u32 (p0, z0)) + +/* +** ld1sh_gather_u32_untied: +** ld1sh z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_u32 (p0, z1), + z0_res = svld1sh_gather_u32 (p0, z1)) + +/* +** ld1sh_gather_x0_u32_offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svld1sh_gather_offset_u32 (p0, z0, x0)) + +/* +** ld1sh_gather_m2_u32_offset: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m2_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, -2), + z0_res = svld1sh_gather_offset_u32 (p0, z0, -2)) + +/* +** ld1sh_gather_0_u32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svld1sh_gather_offset_u32 (p0, z0, 0)) + +/* +** ld1sh_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svld1sh_gather_offset_u32 (p0, z0, 5)) + +/* +** ld1sh_gather_6_u32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svld1sh_gather_offset_u32 (p0, z0, 6)) + +/* +** ld1sh_gather_62_u32_offset: +** ld1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_62_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, 62), + z0_res = svld1sh_gather_offset_u32 (p0, z0, 62)) + +/* +** ld1sh_gather_64_u32_offset: +** mov (x[0-9]+), #?64 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_64_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_offset_u32 (p0, z0, 64), + z0_res = svld1sh_gather_offset_u32 (p0, z0, 64)) + +/* +** ld1sh_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?1 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svld1sh_gather_index_u32 (p0, z0, x0)) + +/* +** ld1sh_gather_m1_u32_index: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svld1sh_gather_index_u32 (p0, z0, -1)) + +/* +** ld1sh_gather_0_u32_index: +** ld1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svld1sh_gather_index_u32 (p0, z0, 0)) + +/* +** ld1sh_gather_5_u32_index: +** ld1sh z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svld1sh_gather_index_u32 (p0, z0, 5)) + +/* +** ld1sh_gather_31_u32_index: +** ld1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svld1sh_gather_index_u32 (p0, z0, 31)) + +/* +** ld1sh_gather_32_u32_index: +** mov (x[0-9]+), #?64 +** ld1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svld1sh_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svld1sh_gather_index_u32 (p0, z0, 32)) + +/* +** ld1sh_gather_x0_u32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u32_s32offset: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32offset_u32 (p0, x0, z1), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_u32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u32_u32offset: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32offset_u32 (p0, x0, z1), + z0_res = svld1sh_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_u32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u32_s32index: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svld1sh_gather_s32index_u32 (p0, x0, z1), + z0_res = svld1sh_gather_index_u32 (p0, x0, z1)) + +/* +** ld1sh_gather_x0_u32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u32_u32index: +** ld1sh z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svld1sh_gather_u32index_u32 (p0, x0, z1), + z0_res = svld1sh_gather_index_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u64.c new file mode 100644 index 00000000000..a1f614e5574 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_gather_u64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_gather_u64_tied1: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_u64 (p0, z0), + z0_res = svld1sh_gather_u64 (p0, z0)) + +/* +** ld1sh_gather_u64_untied: +** ld1sh z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_u64 (p0, z1), + z0_res = svld1sh_gather_u64 (p0, z1)) + +/* +** ld1sh_gather_x0_u64_offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1sh_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1sh_gather_m2_u64_offset: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m2_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, -2), + z0_res = svld1sh_gather_offset_u64 (p0, z0, -2)) + +/* +** ld1sh_gather_0_u64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1sh_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1sh_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1sh_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1sh_gather_6_u64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svld1sh_gather_offset_u64 (p0, z0, 6)) + +/* +** ld1sh_gather_62_u64_offset: +** ld1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_62_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, 62), + z0_res = svld1sh_gather_offset_u64 (p0, z0, 62)) + +/* +** ld1sh_gather_64_u64_offset: +** mov (x[0-9]+), #?64 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_64_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_offset_u64 (p0, z0, 64), + z0_res = svld1sh_gather_offset_u64 (p0, z0, 64)) + +/* +** ld1sh_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?1 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svld1sh_gather_index_u64 (p0, z0, x0)) + +/* +** ld1sh_gather_m1_u64_index: +** mov (x[0-9]+), #?-2 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svld1sh_gather_index_u64 (p0, z0, -1)) + +/* +** ld1sh_gather_0_u64_index: +** ld1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svld1sh_gather_index_u64 (p0, z0, 0)) + +/* +** ld1sh_gather_5_u64_index: +** ld1sh z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svld1sh_gather_index_u64 (p0, z0, 5)) + +/* +** ld1sh_gather_31_u64_index: +** ld1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svld1sh_gather_index_u64 (p0, z0, 31)) + +/* +** ld1sh_gather_32_u64_index: +** mov (x[0-9]+), #?64 +** ld1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sh_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sh_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svld1sh_gather_index_u64 (p0, z0, 32)) + +/* +** ld1sh_gather_x0_u64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_u64_s64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_u64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1sh_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_u64_u64offset: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_u64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_u64 (p0, x0, z1), + z0_res = svld1sh_gather_index_u64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_u64_s64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svld1sh_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sh_gather_x0_u64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_x0_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_tied1_u64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_tied1_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sh_gather_untied_u64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_untied_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_u64 (p0, x0, z1), + z0_res = svld1sh_gather_index_u64 (p0, x0, z1)) + +/* +** ld1sh_gather_ext_u64_u64index: +** ld1sh z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sh_gather_ext_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svld1sh_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s32.c new file mode 100644 index 00000000000..e7b60cad7ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_s32_base: +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s32_base, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0), + z0 = svld1sh_s32 (p0, x0)) + +/* +** ld1sh_s32_index: +** ld1sh z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1sh_s32_index, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 + x1), + z0 = svld1sh_s32 (p0, x0 + x1)) + +/* +** ld1sh_s32_1: +** ld1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s32_1, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 + svcntw ()), + z0 = svld1sh_s32 (p0, x0 + svcntw ())) + +/* +** ld1sh_s32_7: +** ld1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s32_7, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 + svcntw () * 7), + z0 = svld1sh_s32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_s32_8: +** incb x0, all, mul #4 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s32_8, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 + svcntw () * 8), + z0 = svld1sh_s32 (p0, x0 + svcntw () * 8)) + +/* +** ld1sh_s32_m1: +** ld1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s32_m1, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 - svcntw ()), + z0 = svld1sh_s32 (p0, x0 - svcntw ())) + +/* +** ld1sh_s32_m8: +** ld1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s32_m8, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 - svcntw () * 8), + z0 = svld1sh_s32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_s32_m9: +** dech x0, all, mul #9 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s32_m9, svint32_t, int16_t, + z0 = svld1sh_s32 (p0, x0 - svcntw () * 9), + z0 = svld1sh_s32 (p0, x0 - svcntw () * 9)) + +/* +** ld1sh_vnum_s32_0: +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_0, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, 0), + z0 = svld1sh_vnum_s32 (p0, x0, 0)) + +/* +** ld1sh_vnum_s32_1: +** ld1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_1, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, 1), + z0 = svld1sh_vnum_s32 (p0, x0, 1)) + +/* +** ld1sh_vnum_s32_7: +** ld1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_7, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, 7), + z0 = svld1sh_vnum_s32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_s32_8: +** incb x0, all, mul #4 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_8, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, 8), + z0 = svld1sh_vnum_s32 (p0, x0, 8)) + +/* +** ld1sh_vnum_s32_m1: +** ld1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_m1, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, -1), + z0 = svld1sh_vnum_s32 (p0, x0, -1)) + +/* +** ld1sh_vnum_s32_m8: +** ld1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_m8, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, -8), + z0 = svld1sh_vnum_s32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_s32_m9: +** dech x0, all, mul #9 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_m9, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, -9), + z0 = svld1sh_vnum_s32 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s32_x1, svint32_t, int16_t, + z0 = svld1sh_vnum_s32 (p0, x0, x1), + z0 = svld1sh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s64.c new file mode 100644 index 00000000000..b91f365c08c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_s64_base: +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s64_base, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0), + z0 = svld1sh_s64 (p0, x0)) + +/* +** ld1sh_s64_index: +** ld1sh z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1sh_s64_index, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 + x1), + z0 = svld1sh_s64 (p0, x0 + x1)) + +/* +** ld1sh_s64_1: +** ld1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s64_1, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 + svcntd ()), + z0 = svld1sh_s64 (p0, x0 + svcntd ())) + +/* +** ld1sh_s64_7: +** ld1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s64_7, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 + svcntd () * 7), + z0 = svld1sh_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_s64_8: +** incb x0, all, mul #2 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s64_8, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 + svcntd () * 8), + z0 = svld1sh_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sh_s64_m1: +** ld1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s64_m1, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 - svcntd ()), + z0 = svld1sh_s64 (p0, x0 - svcntd ())) + +/* +** ld1sh_s64_m8: +** ld1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_s64_m8, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 - svcntd () * 8), + z0 = svld1sh_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_s64_m9: +** decw x0, all, mul #9 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_s64_m9, svint64_t, int16_t, + z0 = svld1sh_s64 (p0, x0 - svcntd () * 9), + z0 = svld1sh_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sh_vnum_s64_0: +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_0, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, 0), + z0 = svld1sh_vnum_s64 (p0, x0, 0)) + +/* +** ld1sh_vnum_s64_1: +** ld1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_1, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, 1), + z0 = svld1sh_vnum_s64 (p0, x0, 1)) + +/* +** ld1sh_vnum_s64_7: +** ld1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_7, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, 7), + z0 = svld1sh_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_s64_8: +** incb x0, all, mul #2 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_8, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, 8), + z0 = svld1sh_vnum_s64 (p0, x0, 8)) + +/* +** ld1sh_vnum_s64_m1: +** ld1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_m1, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, -1), + z0 = svld1sh_vnum_s64 (p0, x0, -1)) + +/* +** ld1sh_vnum_s64_m8: +** ld1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_m8, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, -8), + z0 = svld1sh_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_s64_m9: +** decw x0, all, mul #9 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_m9, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, -9), + z0 = svld1sh_vnum_s64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_s64_x1, svint64_t, int16_t, + z0 = svld1sh_vnum_s64 (p0, x0, x1), + z0 = svld1sh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u32.c new file mode 100644 index 00000000000..6dfe6e821bb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_u32_base: +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u32_base, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0), + z0 = svld1sh_u32 (p0, x0)) + +/* +** ld1sh_u32_index: +** ld1sh z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1sh_u32_index, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 + x1), + z0 = svld1sh_u32 (p0, x0 + x1)) + +/* +** ld1sh_u32_1: +** ld1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u32_1, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 + svcntw ()), + z0 = svld1sh_u32 (p0, x0 + svcntw ())) + +/* +** ld1sh_u32_7: +** ld1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u32_7, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 + svcntw () * 7), + z0 = svld1sh_u32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_u32_8: +** incb x0, all, mul #4 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u32_8, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 + svcntw () * 8), + z0 = svld1sh_u32 (p0, x0 + svcntw () * 8)) + +/* +** ld1sh_u32_m1: +** ld1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u32_m1, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 - svcntw ()), + z0 = svld1sh_u32 (p0, x0 - svcntw ())) + +/* +** ld1sh_u32_m8: +** ld1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u32_m8, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 - svcntw () * 8), + z0 = svld1sh_u32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_u32_m9: +** dech x0, all, mul #9 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u32_m9, svuint32_t, int16_t, + z0 = svld1sh_u32 (p0, x0 - svcntw () * 9), + z0 = svld1sh_u32 (p0, x0 - svcntw () * 9)) + +/* +** ld1sh_vnum_u32_0: +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_0, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, 0), + z0 = svld1sh_vnum_u32 (p0, x0, 0)) + +/* +** ld1sh_vnum_u32_1: +** ld1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_1, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, 1), + z0 = svld1sh_vnum_u32 (p0, x0, 1)) + +/* +** ld1sh_vnum_u32_7: +** ld1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_7, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, 7), + z0 = svld1sh_vnum_u32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_u32_8: +** incb x0, all, mul #4 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_8, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, 8), + z0 = svld1sh_vnum_u32 (p0, x0, 8)) + +/* +** ld1sh_vnum_u32_m1: +** ld1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_m1, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, -1), + z0 = svld1sh_vnum_u32 (p0, x0, -1)) + +/* +** ld1sh_vnum_u32_m8: +** ld1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_m8, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, -8), + z0 = svld1sh_vnum_u32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_u32_m9: +** dech x0, all, mul #9 +** ld1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_m9, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, -9), + z0 = svld1sh_vnum_u32 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u32_x1, svuint32_t, int16_t, + z0 = svld1sh_vnum_u32 (p0, x0, x1), + z0 = svld1sh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u64.c new file mode 100644 index 00000000000..9cfce394e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sh_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sh_u64_base: +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u64_base, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0), + z0 = svld1sh_u64 (p0, x0)) + +/* +** ld1sh_u64_index: +** ld1sh z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1sh_u64_index, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 + x1), + z0 = svld1sh_u64 (p0, x0 + x1)) + +/* +** ld1sh_u64_1: +** ld1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u64_1, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 + svcntd ()), + z0 = svld1sh_u64 (p0, x0 + svcntd ())) + +/* +** ld1sh_u64_7: +** ld1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u64_7, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 + svcntd () * 7), + z0 = svld1sh_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_u64_8: +** incb x0, all, mul #2 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u64_8, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 + svcntd () * 8), + z0 = svld1sh_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sh_u64_m1: +** ld1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u64_m1, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 - svcntd ()), + z0 = svld1sh_u64 (p0, x0 - svcntd ())) + +/* +** ld1sh_u64_m8: +** ld1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_u64_m8, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 - svcntd () * 8), + z0 = svld1sh_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_u64_m9: +** decw x0, all, mul #9 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_u64_m9, svuint64_t, int16_t, + z0 = svld1sh_u64 (p0, x0 - svcntd () * 9), + z0 = svld1sh_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sh_vnum_u64_0: +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_0, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, 0), + z0 = svld1sh_vnum_u64 (p0, x0, 0)) + +/* +** ld1sh_vnum_u64_1: +** ld1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_1, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, 1), + z0 = svld1sh_vnum_u64 (p0, x0, 1)) + +/* +** ld1sh_vnum_u64_7: +** ld1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_7, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, 7), + z0 = svld1sh_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_u64_8: +** incb x0, all, mul #2 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_8, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, 8), + z0 = svld1sh_vnum_u64 (p0, x0, 8)) + +/* +** ld1sh_vnum_u64_m1: +** ld1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_m1, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, -1), + z0 = svld1sh_vnum_u64 (p0, x0, -1)) + +/* +** ld1sh_vnum_u64_m8: +** ld1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_m8, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, -8), + z0 = svld1sh_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sh_vnum_u64_m9: +** decw x0, all, mul #9 +** ld1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_m9, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, -9), + z0 = svld1sh_vnum_u64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sh_vnum_u64_x1, svuint64_t, int16_t, + z0 = svld1sh_vnum_u64 (p0, x0, x1), + z0 = svld1sh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_s64.c new file mode 100644 index 00000000000..cda2a6481d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_s64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sw_gather_s64_tied1: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_s64 (p0, z0), + z0_res = svld1sw_gather_s64 (p0, z0)) + +/* +** ld1sw_gather_s64_untied: +** ld1sw z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_s64 (p0, z1), + z0_res = svld1sw_gather_s64 (p0, z1)) + +/* +** ld1sw_gather_x0_s64_offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1sw_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1sw_gather_m4_s64_offset: +** mov (x[0-9]+), #?-4 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_m4_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, -4), + z0_res = svld1sw_gather_offset_s64 (p0, z0, -4)) + +/* +** ld1sw_gather_0_s64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1sw_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1sw_gather_6_s64_offset: +** mov (x[0-9]+), #?6 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 6)) + +/* +** ld1sw_gather_7_s64_offset: +** mov (x[0-9]+), #?7 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_7_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 7), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 7)) + +/* +** ld1sw_gather_8_s64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_8_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 8), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 8)) + +/* +** ld1sw_gather_124_s64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_124_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 124), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 124)) + +/* +** ld1sw_gather_128_s64_offset: +** mov (x[0-9]+), #?128 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_128_s64_offset, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_s64 (p0, z0, 128), + z0_res = svld1sw_gather_offset_s64 (p0, z0, 128)) + +/* +** ld1sw_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?2 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svld1sw_gather_index_s64 (p0, z0, x0)) + +/* +** ld1sw_gather_m1_s64_index: +** mov (x[0-9]+), #?-4 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svld1sw_gather_index_s64 (p0, z0, -1)) + +/* +** ld1sw_gather_0_s64_index: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svld1sw_gather_index_s64 (p0, z0, 0)) + +/* +** ld1sw_gather_5_s64_index: +** ld1sw z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svld1sw_gather_index_s64 (p0, z0, 5)) + +/* +** ld1sw_gather_31_s64_index: +** ld1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svld1sw_gather_index_s64 (p0, z0, 31)) + +/* +** ld1sw_gather_32_s64_index: +** mov (x[0-9]+), #?128 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svld1sw_gather_index_s64 (p0, z0, 32)) + +/* +** ld1sw_gather_x0_s64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_s64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_s64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_s64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_s64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_s64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_s64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1sw_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_s64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_s64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_s64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_s64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_s64 (p0, x0, z1), + z0_res = svld1sw_gather_index_s64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_s64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_s64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_s64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_s64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_s64 (p0, x0, z1), + z0_res = svld1sw_gather_index_s64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_s64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_u64.c new file mode 100644 index 00000000000..518d60ea161 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_gather_u64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sw_gather_u64_tied1: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_u64 (p0, z0), + z0_res = svld1sw_gather_u64 (p0, z0)) + +/* +** ld1sw_gather_u64_untied: +** ld1sw z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_u64 (p0, z1), + z0_res = svld1sw_gather_u64 (p0, z1)) + +/* +** ld1sw_gather_x0_u64_offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1sw_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1sw_gather_m4_u64_offset: +** mov (x[0-9]+), #?-4 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_m4_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, -4), + z0_res = svld1sw_gather_offset_u64 (p0, z0, -4)) + +/* +** ld1sw_gather_0_u64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1sw_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1sw_gather_6_u64_offset: +** mov (x[0-9]+), #?6 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 6)) + +/* +** ld1sw_gather_7_u64_offset: +** mov (x[0-9]+), #?7 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_7_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 7), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 7)) + +/* +** ld1sw_gather_8_u64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_8_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 8), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 8)) + +/* +** ld1sw_gather_124_u64_offset: +** ld1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_124_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 124), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 124)) + +/* +** ld1sw_gather_128_u64_offset: +** mov (x[0-9]+), #?128 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_128_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_offset_u64 (p0, z0, 128), + z0_res = svld1sw_gather_offset_u64 (p0, z0, 128)) + +/* +** ld1sw_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?2 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svld1sw_gather_index_u64 (p0, z0, x0)) + +/* +** ld1sw_gather_m1_u64_index: +** mov (x[0-9]+), #?-4 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svld1sw_gather_index_u64 (p0, z0, -1)) + +/* +** ld1sw_gather_0_u64_index: +** ld1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svld1sw_gather_index_u64 (p0, z0, 0)) + +/* +** ld1sw_gather_5_u64_index: +** ld1sw z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svld1sw_gather_index_u64 (p0, z0, 5)) + +/* +** ld1sw_gather_31_u64_index: +** ld1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svld1sw_gather_index_u64 (p0, z0, 31)) + +/* +** ld1sw_gather_32_u64_index: +** mov (x[0-9]+), #?128 +** ld1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1sw_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svld1sw_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svld1sw_gather_index_u64 (p0, z0, 32)) + +/* +** ld1sw_gather_x0_u64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_u64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_u64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_u64_s64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_u64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_u64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_u64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1sw_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_u64_u64offset: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_u64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_u64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_u64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_u64 (p0, x0, z1), + z0_res = svld1sw_gather_index_u64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_u64_s64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svld1sw_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1sw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1sw_gather_x0_u64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_x0_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_tied1_u64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_tied1_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1sw_gather_untied_u64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_untied_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_u64 (p0, x0, z1), + z0_res = svld1sw_gather_index_u64 (p0, x0, z1)) + +/* +** ld1sw_gather_ext_u64_u64index: +** ld1sw z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1sw_gather_ext_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svld1sw_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1sw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_s64.c new file mode 100644 index 00000000000..62cae18888d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sw_s64_base: +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_s64_base, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0), + z0 = svld1sw_s64 (p0, x0)) + +/* +** ld1sw_s64_index: +** ld1sw z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1sw_s64_index, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 + x1), + z0 = svld1sw_s64 (p0, x0 + x1)) + +/* +** ld1sw_s64_1: +** ld1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_s64_1, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 + svcntd ()), + z0 = svld1sw_s64 (p0, x0 + svcntd ())) + +/* +** ld1sw_s64_7: +** ld1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_s64_7, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 + svcntd () * 7), + z0 = svld1sw_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_s64_8: +** incb x0, all, mul #4 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_s64_8, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 + svcntd () * 8), + z0 = svld1sw_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sw_s64_m1: +** ld1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_s64_m1, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 - svcntd ()), + z0 = svld1sw_s64 (p0, x0 - svcntd ())) + +/* +** ld1sw_s64_m8: +** ld1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_s64_m8, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 - svcntd () * 8), + z0 = svld1sw_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_s64_m9: +** dech x0, all, mul #9 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_s64_m9, svint64_t, int32_t, + z0 = svld1sw_s64 (p0, x0 - svcntd () * 9), + z0 = svld1sw_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sw_vnum_s64_0: +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_0, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, 0), + z0 = svld1sw_vnum_s64 (p0, x0, 0)) + +/* +** ld1sw_vnum_s64_1: +** ld1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_1, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, 1), + z0 = svld1sw_vnum_s64 (p0, x0, 1)) + +/* +** ld1sw_vnum_s64_7: +** ld1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_7, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, 7), + z0 = svld1sw_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_vnum_s64_8: +** incb x0, all, mul #4 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_8, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, 8), + z0 = svld1sw_vnum_s64 (p0, x0, 8)) + +/* +** ld1sw_vnum_s64_m1: +** ld1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_m1, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, -1), + z0 = svld1sw_vnum_s64 (p0, x0, -1)) + +/* +** ld1sw_vnum_s64_m8: +** ld1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_m8, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, -8), + z0 = svld1sw_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_vnum_s64_m9: +** dech x0, all, mul #9 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_m9, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, -9), + z0 = svld1sw_vnum_s64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_s64_x1, svint64_t, int32_t, + z0 = svld1sw_vnum_s64 (p0, x0, x1), + z0 = svld1sw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_u64.c new file mode 100644 index 00000000000..37fdd016ddc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1sw_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1sw_u64_base: +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_u64_base, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0), + z0 = svld1sw_u64 (p0, x0)) + +/* +** ld1sw_u64_index: +** ld1sw z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1sw_u64_index, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 + x1), + z0 = svld1sw_u64 (p0, x0 + x1)) + +/* +** ld1sw_u64_1: +** ld1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_u64_1, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 + svcntd ()), + z0 = svld1sw_u64 (p0, x0 + svcntd ())) + +/* +** ld1sw_u64_7: +** ld1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_u64_7, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 + svcntd () * 7), + z0 = svld1sw_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_u64_8: +** incb x0, all, mul #4 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_u64_8, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 + svcntd () * 8), + z0 = svld1sw_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1sw_u64_m1: +** ld1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_u64_m1, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 - svcntd ()), + z0 = svld1sw_u64 (p0, x0 - svcntd ())) + +/* +** ld1sw_u64_m8: +** ld1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_u64_m8, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 - svcntd () * 8), + z0 = svld1sw_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_u64_m9: +** dech x0, all, mul #9 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_u64_m9, svuint64_t, int32_t, + z0 = svld1sw_u64 (p0, x0 - svcntd () * 9), + z0 = svld1sw_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1sw_vnum_u64_0: +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_0, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, 0), + z0 = svld1sw_vnum_u64 (p0, x0, 0)) + +/* +** ld1sw_vnum_u64_1: +** ld1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_1, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, 1), + z0 = svld1sw_vnum_u64 (p0, x0, 1)) + +/* +** ld1sw_vnum_u64_7: +** ld1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_7, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, 7), + z0 = svld1sw_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_vnum_u64_8: +** incb x0, all, mul #4 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_8, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, 8), + z0 = svld1sw_vnum_u64 (p0, x0, 8)) + +/* +** ld1sw_vnum_u64_m1: +** ld1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_m1, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, -1), + z0 = svld1sw_vnum_u64 (p0, x0, -1)) + +/* +** ld1sw_vnum_u64_m8: +** ld1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_m8, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, -8), + z0 = svld1sw_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1sw_vnum_u64_m9: +** dech x0, all, mul #9 +** ld1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_m9, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, -9), + z0 = svld1sw_vnum_u64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1sw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1sw_vnum_u64_x1, svuint64_t, int32_t, + z0 = svld1sw_vnum_u64 (p0, x0, x1), + z0 = svld1sw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s32.c new file mode 100644 index 00000000000..283b80a75d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_gather_s32_tied1: +** ld1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_s32 (p0, z0), + z0_res = svld1ub_gather_s32 (p0, z0)) + +/* +** ld1ub_gather_s32_untied: +** ld1b z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_s32 (p0, z1), + z0_res = svld1ub_gather_s32 (p0, z1)) + +/* +** ld1ub_gather_x0_s32_offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svld1ub_gather_offset_s32 (p0, z0, x0)) + +/* +** ld1ub_gather_m1_s32_offset: +** mov (x[0-9]+), #?-1 +** ld1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_m1_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, -1), + z0_res = svld1ub_gather_offset_s32 (p0, z0, -1)) + +/* +** ld1ub_gather_0_s32_offset: +** ld1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svld1ub_gather_offset_s32 (p0, z0, 0)) + +/* +** ld1ub_gather_5_s32_offset: +** ld1b z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svld1ub_gather_offset_s32 (p0, z0, 5)) + +/* +** ld1ub_gather_31_s32_offset: +** ld1b z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_31_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, 31), + z0_res = svld1ub_gather_offset_s32 (p0, z0, 31)) + +/* +** ld1ub_gather_32_s32_offset: +** mov (x[0-9]+), #?32 +** ld1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_32_s32_offset, svint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_s32 (p0, z0, 32), + z0_res = svld1ub_gather_offset_s32 (p0, z0, 32)) + +/* +** ld1ub_gather_x0_s32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_s32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_s32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_s32 (p0, x0, z1), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1ub_gather_x0_s32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_s32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_s32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_s32 (p0, x0, z1), + z0_res = svld1ub_gather_offset_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s64.c new file mode 100644 index 00000000000..1de92a134cc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_s64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_gather_s64_tied1: +** ld1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_s64 (p0, z0), + z0_res = svld1ub_gather_s64 (p0, z0)) + +/* +** ld1ub_gather_s64_untied: +** ld1b z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_s64 (p0, z1), + z0_res = svld1ub_gather_s64 (p0, z1)) + +/* +** ld1ub_gather_x0_s64_offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1ub_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1ub_gather_m1_s64_offset: +** mov (x[0-9]+), #?-1 +** ld1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_m1_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, -1), + z0_res = svld1ub_gather_offset_s64 (p0, z0, -1)) + +/* +** ld1ub_gather_0_s64_offset: +** ld1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1ub_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1ub_gather_5_s64_offset: +** ld1b z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1ub_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1ub_gather_31_s64_offset: +** ld1b z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_31_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, 31), + z0_res = svld1ub_gather_offset_s64 (p0, z0, 31)) + +/* +** ld1ub_gather_32_s64_offset: +** mov (x[0-9]+), #?32 +** ld1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_32_s64_offset, svint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_s64 (p0, z0, 32), + z0_res = svld1ub_gather_offset_s64 (p0, z0, 32)) + +/* +** ld1ub_gather_x0_s64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_s64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_s64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1ub_gather_ext_s64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_ext_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1ub_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1ub_gather_x0_s64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_s64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_s64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1ub_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1ub_gather_ext_s64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_ext_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1ub_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u32.c new file mode 100644 index 00000000000..28aa39b12ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_gather_u32_tied1: +** ld1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_u32 (p0, z0), + z0_res = svld1ub_gather_u32 (p0, z0)) + +/* +** ld1ub_gather_u32_untied: +** ld1b z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_u32 (p0, z1), + z0_res = svld1ub_gather_u32 (p0, z1)) + +/* +** ld1ub_gather_x0_u32_offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svld1ub_gather_offset_u32 (p0, z0, x0)) + +/* +** ld1ub_gather_m1_u32_offset: +** mov (x[0-9]+), #?-1 +** ld1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_m1_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, -1), + z0_res = svld1ub_gather_offset_u32 (p0, z0, -1)) + +/* +** ld1ub_gather_0_u32_offset: +** ld1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svld1ub_gather_offset_u32 (p0, z0, 0)) + +/* +** ld1ub_gather_5_u32_offset: +** ld1b z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svld1ub_gather_offset_u32 (p0, z0, 5)) + +/* +** ld1ub_gather_31_u32_offset: +** ld1b z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_31_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, 31), + z0_res = svld1ub_gather_offset_u32 (p0, z0, 31)) + +/* +** ld1ub_gather_32_u32_offset: +** mov (x[0-9]+), #?32 +** ld1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_32_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1ub_gather_u32base_offset_u32 (p0, z0, 32), + z0_res = svld1ub_gather_offset_u32 (p0, z0, 32)) + +/* +** ld1ub_gather_x0_u32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_u32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_u32_s32offset: +** ld1b z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svld1ub_gather_s32offset_u32 (p0, x0, z1), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1ub_gather_x0_u32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_u32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_u32_u32offset: +** ld1b z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svld1ub_gather_u32offset_u32 (p0, x0, z1), + z0_res = svld1ub_gather_offset_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u64.c new file mode 100644 index 00000000000..08c8cc7de01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_gather_u64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_gather_u64_tied1: +** ld1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_u64 (p0, z0), + z0_res = svld1ub_gather_u64 (p0, z0)) + +/* +** ld1ub_gather_u64_untied: +** ld1b z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_u64 (p0, z1), + z0_res = svld1ub_gather_u64 (p0, z1)) + +/* +** ld1ub_gather_x0_u64_offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1ub_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1ub_gather_m1_u64_offset: +** mov (x[0-9]+), #?-1 +** ld1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_m1_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, -1), + z0_res = svld1ub_gather_offset_u64 (p0, z0, -1)) + +/* +** ld1ub_gather_0_u64_offset: +** ld1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1ub_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1ub_gather_5_u64_offset: +** ld1b z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1ub_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1ub_gather_31_u64_offset: +** ld1b z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_31_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, 31), + z0_res = svld1ub_gather_offset_u64 (p0, z0, 31)) + +/* +** ld1ub_gather_32_u64_offset: +** mov (x[0-9]+), #?32 +** ld1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1ub_gather_32_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1ub_gather_u64base_offset_u64 (p0, z0, 32), + z0_res = svld1ub_gather_offset_u64 (p0, z0, 32)) + +/* +** ld1ub_gather_x0_u64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_u64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_u64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1ub_gather_ext_u64_s64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_ext_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svld1ub_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1ub_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1ub_gather_x0_u64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_x0_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1ub_gather_tied1_u64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_tied1_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1ub_gather_untied_u64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_untied_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1ub_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1ub_gather_ext_u64_u64offset: +** ld1b z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1ub_gather_ext_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svld1ub_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1ub_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s16.c new file mode 100644 index 00000000000..f6b78677bd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_s16_base: +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s16_base, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0), + z0 = svld1ub_s16 (p0, x0)) + +/* +** ld1ub_s16_index: +** ld1b z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_s16_index, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 + x1), + z0 = svld1ub_s16 (p0, x0 + x1)) + +/* +** ld1ub_s16_1: +** ld1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s16_1, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 + svcnth ()), + z0 = svld1ub_s16 (p0, x0 + svcnth ())) + +/* +** ld1ub_s16_7: +** ld1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s16_7, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 + svcnth () * 7), + z0 = svld1ub_s16 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s16_8: +** incb x0, all, mul #4 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s16_8, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 + svcnth () * 8), + z0 = svld1ub_s16 (p0, x0 + svcnth () * 8)) + +/* +** ld1ub_s16_m1: +** ld1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s16_m1, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 - svcnth ()), + z0 = svld1ub_s16 (p0, x0 - svcnth ())) + +/* +** ld1ub_s16_m8: +** ld1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s16_m8, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 - svcnth () * 8), + z0 = svld1ub_s16 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s16_m9: +** dech x0, all, mul #9 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s16_m9, svint16_t, uint8_t, + z0 = svld1ub_s16 (p0, x0 - svcnth () * 9), + z0 = svld1ub_s16 (p0, x0 - svcnth () * 9)) + +/* +** ld1ub_vnum_s16_0: +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_0, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, 0), + z0 = svld1ub_vnum_s16 (p0, x0, 0)) + +/* +** ld1ub_vnum_s16_1: +** ld1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_1, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, 1), + z0 = svld1ub_vnum_s16 (p0, x0, 1)) + +/* +** ld1ub_vnum_s16_7: +** ld1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_7, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, 7), + z0 = svld1ub_vnum_s16 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s16_8: +** incb x0, all, mul #4 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_8, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, 8), + z0 = svld1ub_vnum_s16 (p0, x0, 8)) + +/* +** ld1ub_vnum_s16_m1: +** ld1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_m1, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, -1), + z0 = svld1ub_vnum_s16 (p0, x0, -1)) + +/* +** ld1ub_vnum_s16_m8: +** ld1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_m8, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, -8), + z0 = svld1ub_vnum_s16 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s16_m9: +** dech x0, all, mul #9 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_m9, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, -9), + z0 = svld1ub_vnum_s16 (p0, x0, -9)) + +/* +** ld1ub_vnum_s16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_s16_x1, svint16_t, uint8_t, + z0 = svld1ub_vnum_s16 (p0, x0, x1), + z0 = svld1ub_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s32.c new file mode 100644 index 00000000000..5ac49535139 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_s32_base: +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s32_base, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0), + z0 = svld1ub_s32 (p0, x0)) + +/* +** ld1ub_s32_index: +** ld1b z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_s32_index, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 + x1), + z0 = svld1ub_s32 (p0, x0 + x1)) + +/* +** ld1ub_s32_1: +** ld1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s32_1, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 + svcntw ()), + z0 = svld1ub_s32 (p0, x0 + svcntw ())) + +/* +** ld1ub_s32_7: +** ld1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s32_7, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 + svcntw () * 7), + z0 = svld1ub_s32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s32_8: +** incb x0, all, mul #2 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s32_8, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 + svcntw () * 8), + z0 = svld1ub_s32 (p0, x0 + svcntw () * 8)) + +/* +** ld1ub_s32_m1: +** ld1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s32_m1, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 - svcntw ()), + z0 = svld1ub_s32 (p0, x0 - svcntw ())) + +/* +** ld1ub_s32_m8: +** ld1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s32_m8, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 - svcntw () * 8), + z0 = svld1ub_s32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s32_m9: +** decw x0, all, mul #9 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s32_m9, svint32_t, uint8_t, + z0 = svld1ub_s32 (p0, x0 - svcntw () * 9), + z0 = svld1ub_s32 (p0, x0 - svcntw () * 9)) + +/* +** ld1ub_vnum_s32_0: +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_0, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, 0), + z0 = svld1ub_vnum_s32 (p0, x0, 0)) + +/* +** ld1ub_vnum_s32_1: +** ld1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_1, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, 1), + z0 = svld1ub_vnum_s32 (p0, x0, 1)) + +/* +** ld1ub_vnum_s32_7: +** ld1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_7, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, 7), + z0 = svld1ub_vnum_s32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s32_8: +** incb x0, all, mul #2 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_8, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, 8), + z0 = svld1ub_vnum_s32 (p0, x0, 8)) + +/* +** ld1ub_vnum_s32_m1: +** ld1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_m1, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, -1), + z0 = svld1ub_vnum_s32 (p0, x0, -1)) + +/* +** ld1ub_vnum_s32_m8: +** ld1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_m8, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, -8), + z0 = svld1ub_vnum_s32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s32_m9: +** decw x0, all, mul #9 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_m9, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, -9), + z0 = svld1ub_vnum_s32 (p0, x0, -9)) + +/* +** ld1ub_vnum_s32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_s32_x1, svint32_t, uint8_t, + z0 = svld1ub_vnum_s32 (p0, x0, x1), + z0 = svld1ub_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s64.c new file mode 100644 index 00000000000..86d794da0b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_s64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_s64_base: +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s64_base, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0), + z0 = svld1ub_s64 (p0, x0)) + +/* +** ld1ub_s64_index: +** ld1b z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_s64_index, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 + x1), + z0 = svld1ub_s64 (p0, x0 + x1)) + +/* +** ld1ub_s64_1: +** ld1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s64_1, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 + svcntd ()), + z0 = svld1ub_s64 (p0, x0 + svcntd ())) + +/* +** ld1ub_s64_7: +** ld1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s64_7, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 + svcntd () * 7), + z0 = svld1ub_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s64_8: +** incb x0 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s64_8, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 + svcntd () * 8), + z0 = svld1ub_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1ub_s64_m1: +** ld1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s64_m1, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 - svcntd ()), + z0 = svld1ub_s64 (p0, x0 - svcntd ())) + +/* +** ld1ub_s64_m8: +** ld1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_s64_m8, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 - svcntd () * 8), + z0 = svld1ub_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_s64_m9: +** decd x0, all, mul #9 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_s64_m9, svint64_t, uint8_t, + z0 = svld1ub_s64 (p0, x0 - svcntd () * 9), + z0 = svld1ub_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1ub_vnum_s64_0: +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_0, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, 0), + z0 = svld1ub_vnum_s64 (p0, x0, 0)) + +/* +** ld1ub_vnum_s64_1: +** ld1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_1, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, 1), + z0 = svld1ub_vnum_s64 (p0, x0, 1)) + +/* +** ld1ub_vnum_s64_7: +** ld1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_7, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, 7), + z0 = svld1ub_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s64_8: +** incb x0 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_8, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, 8), + z0 = svld1ub_vnum_s64 (p0, x0, 8)) + +/* +** ld1ub_vnum_s64_m1: +** ld1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_m1, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, -1), + z0 = svld1ub_vnum_s64 (p0, x0, -1)) + +/* +** ld1ub_vnum_s64_m8: +** ld1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_m8, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, -8), + z0 = svld1ub_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_s64_m9: +** decd x0, all, mul #9 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_m9, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, -9), + z0 = svld1ub_vnum_s64 (p0, x0, -9)) + +/* +** ld1ub_vnum_s64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_s64_x1, svint64_t, uint8_t, + z0 = svld1ub_vnum_s64 (p0, x0, x1), + z0 = svld1ub_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u16.c new file mode 100644 index 00000000000..f1a3f458244 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_u16_base: +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u16_base, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0), + z0 = svld1ub_u16 (p0, x0)) + +/* +** ld1ub_u16_index: +** ld1b z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_u16_index, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 + x1), + z0 = svld1ub_u16 (p0, x0 + x1)) + +/* +** ld1ub_u16_1: +** ld1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u16_1, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 + svcnth ()), + z0 = svld1ub_u16 (p0, x0 + svcnth ())) + +/* +** ld1ub_u16_7: +** ld1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u16_7, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 + svcnth () * 7), + z0 = svld1ub_u16 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u16_8: +** incb x0, all, mul #4 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u16_8, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 + svcnth () * 8), + z0 = svld1ub_u16 (p0, x0 + svcnth () * 8)) + +/* +** ld1ub_u16_m1: +** ld1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u16_m1, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 - svcnth ()), + z0 = svld1ub_u16 (p0, x0 - svcnth ())) + +/* +** ld1ub_u16_m8: +** ld1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u16_m8, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 - svcnth () * 8), + z0 = svld1ub_u16 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u16_m9: +** dech x0, all, mul #9 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u16_m9, svuint16_t, uint8_t, + z0 = svld1ub_u16 (p0, x0 - svcnth () * 9), + z0 = svld1ub_u16 (p0, x0 - svcnth () * 9)) + +/* +** ld1ub_vnum_u16_0: +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_0, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, 0), + z0 = svld1ub_vnum_u16 (p0, x0, 0)) + +/* +** ld1ub_vnum_u16_1: +** ld1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_1, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, 1), + z0 = svld1ub_vnum_u16 (p0, x0, 1)) + +/* +** ld1ub_vnum_u16_7: +** ld1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_7, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, 7), + z0 = svld1ub_vnum_u16 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u16_8: +** incb x0, all, mul #4 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_8, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, 8), + z0 = svld1ub_vnum_u16 (p0, x0, 8)) + +/* +** ld1ub_vnum_u16_m1: +** ld1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_m1, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, -1), + z0 = svld1ub_vnum_u16 (p0, x0, -1)) + +/* +** ld1ub_vnum_u16_m8: +** ld1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_m8, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, -8), + z0 = svld1ub_vnum_u16 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u16_m9: +** dech x0, all, mul #9 +** ld1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_m9, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, -9), + z0 = svld1ub_vnum_u16 (p0, x0, -9)) + +/* +** ld1ub_vnum_u16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_u16_x1, svuint16_t, uint8_t, + z0 = svld1ub_vnum_u16 (p0, x0, x1), + z0 = svld1ub_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u32.c new file mode 100644 index 00000000000..9c841ed31f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_u32_base: +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u32_base, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0), + z0 = svld1ub_u32 (p0, x0)) + +/* +** ld1ub_u32_index: +** ld1b z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_u32_index, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 + x1), + z0 = svld1ub_u32 (p0, x0 + x1)) + +/* +** ld1ub_u32_1: +** ld1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u32_1, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 + svcntw ()), + z0 = svld1ub_u32 (p0, x0 + svcntw ())) + +/* +** ld1ub_u32_7: +** ld1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u32_7, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 + svcntw () * 7), + z0 = svld1ub_u32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u32_8: +** incb x0, all, mul #2 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u32_8, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 + svcntw () * 8), + z0 = svld1ub_u32 (p0, x0 + svcntw () * 8)) + +/* +** ld1ub_u32_m1: +** ld1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u32_m1, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 - svcntw ()), + z0 = svld1ub_u32 (p0, x0 - svcntw ())) + +/* +** ld1ub_u32_m8: +** ld1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u32_m8, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 - svcntw () * 8), + z0 = svld1ub_u32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u32_m9: +** decw x0, all, mul #9 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u32_m9, svuint32_t, uint8_t, + z0 = svld1ub_u32 (p0, x0 - svcntw () * 9), + z0 = svld1ub_u32 (p0, x0 - svcntw () * 9)) + +/* +** ld1ub_vnum_u32_0: +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_0, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, 0), + z0 = svld1ub_vnum_u32 (p0, x0, 0)) + +/* +** ld1ub_vnum_u32_1: +** ld1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_1, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, 1), + z0 = svld1ub_vnum_u32 (p0, x0, 1)) + +/* +** ld1ub_vnum_u32_7: +** ld1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_7, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, 7), + z0 = svld1ub_vnum_u32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u32_8: +** incb x0, all, mul #2 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_8, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, 8), + z0 = svld1ub_vnum_u32 (p0, x0, 8)) + +/* +** ld1ub_vnum_u32_m1: +** ld1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_m1, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, -1), + z0 = svld1ub_vnum_u32 (p0, x0, -1)) + +/* +** ld1ub_vnum_u32_m8: +** ld1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_m8, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, -8), + z0 = svld1ub_vnum_u32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u32_m9: +** decw x0, all, mul #9 +** ld1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_m9, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, -9), + z0 = svld1ub_vnum_u32 (p0, x0, -9)) + +/* +** ld1ub_vnum_u32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_u32_x1, svuint32_t, uint8_t, + z0 = svld1ub_vnum_u32 (p0, x0, x1), + z0 = svld1ub_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u64.c new file mode 100644 index 00000000000..2936b63b4b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ub_u64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1ub_u64_base: +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u64_base, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0), + z0 = svld1ub_u64 (p0, x0)) + +/* +** ld1ub_u64_index: +** ld1b z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld1ub_u64_index, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 + x1), + z0 = svld1ub_u64 (p0, x0 + x1)) + +/* +** ld1ub_u64_1: +** ld1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u64_1, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 + svcntd ()), + z0 = svld1ub_u64 (p0, x0 + svcntd ())) + +/* +** ld1ub_u64_7: +** ld1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u64_7, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 + svcntd () * 7), + z0 = svld1ub_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u64_8: +** incb x0 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u64_8, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 + svcntd () * 8), + z0 = svld1ub_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1ub_u64_m1: +** ld1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u64_m1, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 - svcntd ()), + z0 = svld1ub_u64 (p0, x0 - svcntd ())) + +/* +** ld1ub_u64_m8: +** ld1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_u64_m8, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 - svcntd () * 8), + z0 = svld1ub_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_u64_m9: +** decd x0, all, mul #9 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_u64_m9, svuint64_t, uint8_t, + z0 = svld1ub_u64 (p0, x0 - svcntd () * 9), + z0 = svld1ub_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1ub_vnum_u64_0: +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_0, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, 0), + z0 = svld1ub_vnum_u64 (p0, x0, 0)) + +/* +** ld1ub_vnum_u64_1: +** ld1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_1, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, 1), + z0 = svld1ub_vnum_u64 (p0, x0, 1)) + +/* +** ld1ub_vnum_u64_7: +** ld1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_7, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, 7), + z0 = svld1ub_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u64_8: +** incb x0 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_8, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, 8), + z0 = svld1ub_vnum_u64 (p0, x0, 8)) + +/* +** ld1ub_vnum_u64_m1: +** ld1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_m1, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, -1), + z0 = svld1ub_vnum_u64 (p0, x0, -1)) + +/* +** ld1ub_vnum_u64_m8: +** ld1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_m8, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, -8), + z0 = svld1ub_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1ub_vnum_u64_m9: +** decd x0, all, mul #9 +** ld1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_m9, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, -9), + z0 = svld1ub_vnum_u64 (p0, x0, -9)) + +/* +** ld1ub_vnum_u64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld1b z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld1b z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld1ub_vnum_u64_x1, svuint64_t, uint8_t, + z0 = svld1ub_vnum_u64 (p0, x0, x1), + z0 = svld1ub_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s32.c new file mode 100644 index 00000000000..440ae5c6e0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_gather_s32_tied1: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_s32 (p0, z0), + z0_res = svld1uh_gather_s32 (p0, z0)) + +/* +** ld1uh_gather_s32_untied: +** ld1h z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_s32 (p0, z1), + z0_res = svld1uh_gather_s32 (p0, z1)) + +/* +** ld1uh_gather_x0_s32_offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svld1uh_gather_offset_s32 (p0, z0, x0)) + +/* +** ld1uh_gather_m2_s32_offset: +** mov (x[0-9]+), #?-2 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m2_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, -2), + z0_res = svld1uh_gather_offset_s32 (p0, z0, -2)) + +/* +** ld1uh_gather_0_s32_offset: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svld1uh_gather_offset_s32 (p0, z0, 0)) + +/* +** ld1uh_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svld1uh_gather_offset_s32 (p0, z0, 5)) + +/* +** ld1uh_gather_6_s32_offset: +** ld1h z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svld1uh_gather_offset_s32 (p0, z0, 6)) + +/* +** ld1uh_gather_62_s32_offset: +** ld1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_62_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, 62), + z0_res = svld1uh_gather_offset_s32 (p0, z0, 62)) + +/* +** ld1uh_gather_64_s32_offset: +** mov (x[0-9]+), #?64 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_64_s32_offset, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_s32 (p0, z0, 64), + z0_res = svld1uh_gather_offset_s32 (p0, z0, 64)) + +/* +** ld1uh_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?1 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svld1uh_gather_index_s32 (p0, z0, x0)) + +/* +** ld1uh_gather_m1_s32_index: +** mov (x[0-9]+), #?-2 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svld1uh_gather_index_s32 (p0, z0, -1)) + +/* +** ld1uh_gather_0_s32_index: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svld1uh_gather_index_s32 (p0, z0, 0)) + +/* +** ld1uh_gather_5_s32_index: +** ld1h z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svld1uh_gather_index_s32 (p0, z0, 5)) + +/* +** ld1uh_gather_31_s32_index: +** ld1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svld1uh_gather_index_s32 (p0, z0, 31)) + +/* +** ld1uh_gather_32_s32_index: +** mov (x[0-9]+), #?64 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svld1uh_gather_index_s32 (p0, z0, 32)) + +/* +** ld1uh_gather_x0_s32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_s32 (p0, x0, z1), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_s32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_s32 (p0, x0, z1), + z0_res = svld1uh_gather_offset_s32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_s32_s32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s32_s32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_s32 (p0, x0, z0), + z0_res = svld1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s32_s32index: +** ld1h z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_s32 (p0, x0, z1), + z0_res = svld1uh_gather_index_s32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_s32_u32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s32_u32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_s32 (p0, x0, z0), + z0_res = svld1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s32_u32index: +** ld1h z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_s32 (p0, x0, z1), + z0_res = svld1uh_gather_index_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s64.c new file mode 100644 index 00000000000..ddd7b89c761 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_s64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_gather_s64_tied1: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_s64 (p0, z0), + z0_res = svld1uh_gather_s64 (p0, z0)) + +/* +** ld1uh_gather_s64_untied: +** ld1h z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_s64 (p0, z1), + z0_res = svld1uh_gather_s64 (p0, z1)) + +/* +** ld1uh_gather_x0_s64_offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1uh_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1uh_gather_m2_s64_offset: +** mov (x[0-9]+), #?-2 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m2_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, -2), + z0_res = svld1uh_gather_offset_s64 (p0, z0, -2)) + +/* +** ld1uh_gather_0_s64_offset: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1uh_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1uh_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1uh_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1uh_gather_6_s64_offset: +** ld1h z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svld1uh_gather_offset_s64 (p0, z0, 6)) + +/* +** ld1uh_gather_62_s64_offset: +** ld1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_62_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, 62), + z0_res = svld1uh_gather_offset_s64 (p0, z0, 62)) + +/* +** ld1uh_gather_64_s64_offset: +** mov (x[0-9]+), #?64 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_64_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_s64 (p0, z0, 64), + z0_res = svld1uh_gather_offset_s64 (p0, z0, 64)) + +/* +** ld1uh_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?1 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svld1uh_gather_index_s64 (p0, z0, x0)) + +/* +** ld1uh_gather_m1_s64_index: +** mov (x[0-9]+), #?-2 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svld1uh_gather_index_s64 (p0, z0, -1)) + +/* +** ld1uh_gather_0_s64_index: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svld1uh_gather_index_s64 (p0, z0, 0)) + +/* +** ld1uh_gather_5_s64_index: +** ld1h z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svld1uh_gather_index_s64 (p0, z0, 5)) + +/* +** ld1uh_gather_31_s64_index: +** ld1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svld1uh_gather_index_s64 (p0, z0, 31)) + +/* +** ld1uh_gather_32_s64_index: +** mov (x[0-9]+), #?64 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svld1uh_gather_index_s64 (p0, z0, 32)) + +/* +** ld1uh_gather_x0_s64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_s64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_s64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1uh_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_s64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_s64_s64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s64_s64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s64_s64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_s64 (p0, x0, z1), + z0_res = svld1uh_gather_index_s64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_s64_s64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_s64_u64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_s64_u64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_s64_u64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_s64 (p0, x0, z1), + z0_res = svld1uh_gather_index_s64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_s64_u64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u32.c new file mode 100644 index 00000000000..1077ebba78d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_gather_u32_tied1: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_u32 (p0, z0), + z0_res = svld1uh_gather_u32 (p0, z0)) + +/* +** ld1uh_gather_u32_untied: +** ld1h z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_u32 (p0, z1), + z0_res = svld1uh_gather_u32 (p0, z1)) + +/* +** ld1uh_gather_x0_u32_offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svld1uh_gather_offset_u32 (p0, z0, x0)) + +/* +** ld1uh_gather_m2_u32_offset: +** mov (x[0-9]+), #?-2 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m2_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, -2), + z0_res = svld1uh_gather_offset_u32 (p0, z0, -2)) + +/* +** ld1uh_gather_0_u32_offset: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svld1uh_gather_offset_u32 (p0, z0, 0)) + +/* +** ld1uh_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svld1uh_gather_offset_u32 (p0, z0, 5)) + +/* +** ld1uh_gather_6_u32_offset: +** ld1h z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svld1uh_gather_offset_u32 (p0, z0, 6)) + +/* +** ld1uh_gather_62_u32_offset: +** ld1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_62_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, 62), + z0_res = svld1uh_gather_offset_u32 (p0, z0, 62)) + +/* +** ld1uh_gather_64_u32_offset: +** mov (x[0-9]+), #?64 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_64_u32_offset, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_offset_u32 (p0, z0, 64), + z0_res = svld1uh_gather_offset_u32 (p0, z0, 64)) + +/* +** ld1uh_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?1 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svld1uh_gather_index_u32 (p0, z0, x0)) + +/* +** ld1uh_gather_m1_u32_index: +** mov (x[0-9]+), #?-2 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svld1uh_gather_index_u32 (p0, z0, -1)) + +/* +** ld1uh_gather_0_u32_index: +** ld1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svld1uh_gather_index_u32 (p0, z0, 0)) + +/* +** ld1uh_gather_5_u32_index: +** ld1h z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svld1uh_gather_index_u32 (p0, z0, 5)) + +/* +** ld1uh_gather_31_u32_index: +** ld1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svld1uh_gather_index_u32 (p0, z0, 31)) + +/* +** ld1uh_gather_32_u32_index: +** mov (x[0-9]+), #?64 +** ld1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svld1uh_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svld1uh_gather_index_u32 (p0, z0, 32)) + +/* +** ld1uh_gather_x0_u32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u32_s32offset: +** ld1h z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32offset_u32 (p0, x0, z1), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_u32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u32_u32offset: +** ld1h z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32offset_u32 (p0, x0, z1), + z0_res = svld1uh_gather_offset_u32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_u32_s32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u32_s32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_u32 (p0, x0, z0), + z0_res = svld1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u32_s32index: +** ld1h z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svld1uh_gather_s32index_u32 (p0, x0, z1), + z0_res = svld1uh_gather_index_u32 (p0, x0, z1)) + +/* +** ld1uh_gather_x0_u32_u32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u32_u32index: +** ld1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_u32 (p0, x0, z0), + z0_res = svld1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u32_u32index: +** ld1h z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svld1uh_gather_u32index_u32 (p0, x0, z1), + z0_res = svld1uh_gather_index_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u64.c new file mode 100644 index 00000000000..f0b60964ff4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_gather_u64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_gather_u64_tied1: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_u64 (p0, z0), + z0_res = svld1uh_gather_u64 (p0, z0)) + +/* +** ld1uh_gather_u64_untied: +** ld1h z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_u64 (p0, z1), + z0_res = svld1uh_gather_u64 (p0, z1)) + +/* +** ld1uh_gather_x0_u64_offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1uh_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1uh_gather_m2_u64_offset: +** mov (x[0-9]+), #?-2 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m2_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, -2), + z0_res = svld1uh_gather_offset_u64 (p0, z0, -2)) + +/* +** ld1uh_gather_0_u64_offset: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1uh_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1uh_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1uh_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1uh_gather_6_u64_offset: +** ld1h z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svld1uh_gather_offset_u64 (p0, z0, 6)) + +/* +** ld1uh_gather_62_u64_offset: +** ld1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_62_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, 62), + z0_res = svld1uh_gather_offset_u64 (p0, z0, 62)) + +/* +** ld1uh_gather_64_u64_offset: +** mov (x[0-9]+), #?64 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_64_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_offset_u64 (p0, z0, 64), + z0_res = svld1uh_gather_offset_u64 (p0, z0, 64)) + +/* +** ld1uh_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?1 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svld1uh_gather_index_u64 (p0, z0, x0)) + +/* +** ld1uh_gather_m1_u64_index: +** mov (x[0-9]+), #?-2 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svld1uh_gather_index_u64 (p0, z0, -1)) + +/* +** ld1uh_gather_0_u64_index: +** ld1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svld1uh_gather_index_u64 (p0, z0, 0)) + +/* +** ld1uh_gather_5_u64_index: +** ld1h z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svld1uh_gather_index_u64 (p0, z0, 5)) + +/* +** ld1uh_gather_31_u64_index: +** ld1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svld1uh_gather_index_u64 (p0, z0, 31)) + +/* +** ld1uh_gather_32_u64_index: +** mov (x[0-9]+), #?64 +** ld1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uh_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uh_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svld1uh_gather_index_u64 (p0, z0, 32)) + +/* +** ld1uh_gather_x0_u64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_u64_s64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_u64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1uh_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_u64_u64offset: +** ld1h z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_u64_s64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u64_s64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u64_s64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_u64 (p0, x0, z1), + z0_res = svld1uh_gather_index_u64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_u64_s64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svld1uh_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uh_gather_x0_u64_u64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_x0_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_tied1_u64_u64index: +** ld1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_tied1_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uh_gather_untied_u64_u64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_untied_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_u64 (p0, x0, z1), + z0_res = svld1uh_gather_index_u64 (p0, x0, z1)) + +/* +** ld1uh_gather_ext_u64_u64index: +** ld1h z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uh_gather_ext_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svld1uh_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s32.c new file mode 100644 index 00000000000..1c8a9e1806f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_s32_base: +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s32_base, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0), + z0 = svld1uh_s32 (p0, x0)) + +/* +** ld1uh_s32_index: +** ld1h z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1uh_s32_index, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 + x1), + z0 = svld1uh_s32 (p0, x0 + x1)) + +/* +** ld1uh_s32_1: +** ld1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s32_1, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 + svcntw ()), + z0 = svld1uh_s32 (p0, x0 + svcntw ())) + +/* +** ld1uh_s32_7: +** ld1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s32_7, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 + svcntw () * 7), + z0 = svld1uh_s32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_s32_8: +** incb x0, all, mul #4 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s32_8, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 + svcntw () * 8), + z0 = svld1uh_s32 (p0, x0 + svcntw () * 8)) + +/* +** ld1uh_s32_m1: +** ld1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s32_m1, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 - svcntw ()), + z0 = svld1uh_s32 (p0, x0 - svcntw ())) + +/* +** ld1uh_s32_m8: +** ld1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s32_m8, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 - svcntw () * 8), + z0 = svld1uh_s32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_s32_m9: +** dech x0, all, mul #9 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s32_m9, svint32_t, uint16_t, + z0 = svld1uh_s32 (p0, x0 - svcntw () * 9), + z0 = svld1uh_s32 (p0, x0 - svcntw () * 9)) + +/* +** ld1uh_vnum_s32_0: +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_0, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, 0), + z0 = svld1uh_vnum_s32 (p0, x0, 0)) + +/* +** ld1uh_vnum_s32_1: +** ld1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_1, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, 1), + z0 = svld1uh_vnum_s32 (p0, x0, 1)) + +/* +** ld1uh_vnum_s32_7: +** ld1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_7, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, 7), + z0 = svld1uh_vnum_s32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_s32_8: +** incb x0, all, mul #4 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_8, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, 8), + z0 = svld1uh_vnum_s32 (p0, x0, 8)) + +/* +** ld1uh_vnum_s32_m1: +** ld1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_m1, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, -1), + z0 = svld1uh_vnum_s32 (p0, x0, -1)) + +/* +** ld1uh_vnum_s32_m8: +** ld1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_m8, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, -8), + z0 = svld1uh_vnum_s32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_s32_m9: +** dech x0, all, mul #9 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_m9, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, -9), + z0 = svld1uh_vnum_s32 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s32_x1, svint32_t, uint16_t, + z0 = svld1uh_vnum_s32 (p0, x0, x1), + z0 = svld1uh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s64.c new file mode 100644 index 00000000000..09b1faf1c3d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_s64_base: +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s64_base, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0), + z0 = svld1uh_s64 (p0, x0)) + +/* +** ld1uh_s64_index: +** ld1h z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1uh_s64_index, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 + x1), + z0 = svld1uh_s64 (p0, x0 + x1)) + +/* +** ld1uh_s64_1: +** ld1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s64_1, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 + svcntd ()), + z0 = svld1uh_s64 (p0, x0 + svcntd ())) + +/* +** ld1uh_s64_7: +** ld1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s64_7, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 + svcntd () * 7), + z0 = svld1uh_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_s64_8: +** incb x0, all, mul #2 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s64_8, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 + svcntd () * 8), + z0 = svld1uh_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1uh_s64_m1: +** ld1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s64_m1, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 - svcntd ()), + z0 = svld1uh_s64 (p0, x0 - svcntd ())) + +/* +** ld1uh_s64_m8: +** ld1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_s64_m8, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 - svcntd () * 8), + z0 = svld1uh_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_s64_m9: +** decw x0, all, mul #9 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_s64_m9, svint64_t, uint16_t, + z0 = svld1uh_s64 (p0, x0 - svcntd () * 9), + z0 = svld1uh_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1uh_vnum_s64_0: +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_0, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, 0), + z0 = svld1uh_vnum_s64 (p0, x0, 0)) + +/* +** ld1uh_vnum_s64_1: +** ld1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_1, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, 1), + z0 = svld1uh_vnum_s64 (p0, x0, 1)) + +/* +** ld1uh_vnum_s64_7: +** ld1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_7, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, 7), + z0 = svld1uh_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_s64_8: +** incb x0, all, mul #2 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_8, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, 8), + z0 = svld1uh_vnum_s64 (p0, x0, 8)) + +/* +** ld1uh_vnum_s64_m1: +** ld1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_m1, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, -1), + z0 = svld1uh_vnum_s64 (p0, x0, -1)) + +/* +** ld1uh_vnum_s64_m8: +** ld1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_m8, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, -8), + z0 = svld1uh_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_s64_m9: +** decw x0, all, mul #9 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_m9, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, -9), + z0 = svld1uh_vnum_s64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_s64_x1, svint64_t, uint16_t, + z0 = svld1uh_vnum_s64 (p0, x0, x1), + z0 = svld1uh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u32.c new file mode 100644 index 00000000000..b1c35206c04 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_u32_base: +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u32_base, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0), + z0 = svld1uh_u32 (p0, x0)) + +/* +** ld1uh_u32_index: +** ld1h z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1uh_u32_index, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 + x1), + z0 = svld1uh_u32 (p0, x0 + x1)) + +/* +** ld1uh_u32_1: +** ld1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u32_1, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 + svcntw ()), + z0 = svld1uh_u32 (p0, x0 + svcntw ())) + +/* +** ld1uh_u32_7: +** ld1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u32_7, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 + svcntw () * 7), + z0 = svld1uh_u32 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_u32_8: +** incb x0, all, mul #4 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u32_8, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 + svcntw () * 8), + z0 = svld1uh_u32 (p0, x0 + svcntw () * 8)) + +/* +** ld1uh_u32_m1: +** ld1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u32_m1, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 - svcntw ()), + z0 = svld1uh_u32 (p0, x0 - svcntw ())) + +/* +** ld1uh_u32_m8: +** ld1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u32_m8, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 - svcntw () * 8), + z0 = svld1uh_u32 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_u32_m9: +** dech x0, all, mul #9 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u32_m9, svuint32_t, uint16_t, + z0 = svld1uh_u32 (p0, x0 - svcntw () * 9), + z0 = svld1uh_u32 (p0, x0 - svcntw () * 9)) + +/* +** ld1uh_vnum_u32_0: +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_0, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, 0), + z0 = svld1uh_vnum_u32 (p0, x0, 0)) + +/* +** ld1uh_vnum_u32_1: +** ld1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_1, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, 1), + z0 = svld1uh_vnum_u32 (p0, x0, 1)) + +/* +** ld1uh_vnum_u32_7: +** ld1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_7, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, 7), + z0 = svld1uh_vnum_u32 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_u32_8: +** incb x0, all, mul #4 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_8, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, 8), + z0 = svld1uh_vnum_u32 (p0, x0, 8)) + +/* +** ld1uh_vnum_u32_m1: +** ld1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_m1, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, -1), + z0 = svld1uh_vnum_u32 (p0, x0, -1)) + +/* +** ld1uh_vnum_u32_m8: +** ld1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_m8, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, -8), + z0 = svld1uh_vnum_u32 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_u32_m9: +** dech x0, all, mul #9 +** ld1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_m9, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, -9), + z0 = svld1uh_vnum_u32 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u32_x1, svuint32_t, uint16_t, + z0 = svld1uh_vnum_u32 (p0, x0, x1), + z0 = svld1uh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u64.c new file mode 100644 index 00000000000..9f26a57148b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uh_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uh_u64_base: +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u64_base, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0), + z0 = svld1uh_u64 (p0, x0)) + +/* +** ld1uh_u64_index: +** ld1h z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld1uh_u64_index, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 + x1), + z0 = svld1uh_u64 (p0, x0 + x1)) + +/* +** ld1uh_u64_1: +** ld1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u64_1, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 + svcntd ()), + z0 = svld1uh_u64 (p0, x0 + svcntd ())) + +/* +** ld1uh_u64_7: +** ld1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u64_7, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 + svcntd () * 7), + z0 = svld1uh_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_u64_8: +** incb x0, all, mul #2 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u64_8, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 + svcntd () * 8), + z0 = svld1uh_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1uh_u64_m1: +** ld1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u64_m1, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 - svcntd ()), + z0 = svld1uh_u64 (p0, x0 - svcntd ())) + +/* +** ld1uh_u64_m8: +** ld1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_u64_m8, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 - svcntd () * 8), + z0 = svld1uh_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_u64_m9: +** decw x0, all, mul #9 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_u64_m9, svuint64_t, uint16_t, + z0 = svld1uh_u64 (p0, x0 - svcntd () * 9), + z0 = svld1uh_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1uh_vnum_u64_0: +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_0, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, 0), + z0 = svld1uh_vnum_u64 (p0, x0, 0)) + +/* +** ld1uh_vnum_u64_1: +** ld1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_1, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, 1), + z0 = svld1uh_vnum_u64 (p0, x0, 1)) + +/* +** ld1uh_vnum_u64_7: +** ld1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_7, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, 7), + z0 = svld1uh_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_u64_8: +** incb x0, all, mul #2 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_8, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, 8), + z0 = svld1uh_vnum_u64 (p0, x0, 8)) + +/* +** ld1uh_vnum_u64_m1: +** ld1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_m1, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, -1), + z0 = svld1uh_vnum_u64 (p0, x0, -1)) + +/* +** ld1uh_vnum_u64_m8: +** ld1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_m8, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, -8), + z0 = svld1uh_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uh_vnum_u64_m9: +** decw x0, all, mul #9 +** ld1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_m9, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, -9), + z0 = svld1uh_vnum_u64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uh_vnum_u64_x1, svuint64_t, uint16_t, + z0 = svld1uh_vnum_u64 (p0, x0, x1), + z0 = svld1uh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_s64.c new file mode 100644 index 00000000000..b9d6c26863c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_s64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uw_gather_s64_tied1: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_s64 (p0, z0), + z0_res = svld1uw_gather_s64 (p0, z0)) + +/* +** ld1uw_gather_s64_untied: +** ld1w z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_s64 (p0, z1), + z0_res = svld1uw_gather_s64 (p0, z1)) + +/* +** ld1uw_gather_x0_s64_offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svld1uw_gather_offset_s64 (p0, z0, x0)) + +/* +** ld1uw_gather_m4_s64_offset: +** mov (x[0-9]+), #?-4 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_m4_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, -4), + z0_res = svld1uw_gather_offset_s64 (p0, z0, -4)) + +/* +** ld1uw_gather_0_s64_offset: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 0)) + +/* +** ld1uw_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 5)) + +/* +** ld1uw_gather_6_s64_offset: +** mov (x[0-9]+), #?6 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 6)) + +/* +** ld1uw_gather_7_s64_offset: +** mov (x[0-9]+), #?7 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_7_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 7), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 7)) + +/* +** ld1uw_gather_8_s64_offset: +** ld1w z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_8_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 8), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 8)) + +/* +** ld1uw_gather_124_s64_offset: +** ld1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_124_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 124), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 124)) + +/* +** ld1uw_gather_128_s64_offset: +** mov (x[0-9]+), #?128 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_128_s64_offset, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_s64 (p0, z0, 128), + z0_res = svld1uw_gather_offset_s64 (p0, z0, 128)) + +/* +** ld1uw_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?2 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svld1uw_gather_index_s64 (p0, z0, x0)) + +/* +** ld1uw_gather_m1_s64_index: +** mov (x[0-9]+), #?-4 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svld1uw_gather_index_s64 (p0, z0, -1)) + +/* +** ld1uw_gather_0_s64_index: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svld1uw_gather_index_s64 (p0, z0, 0)) + +/* +** ld1uw_gather_5_s64_index: +** ld1w z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svld1uw_gather_index_s64 (p0, z0, 5)) + +/* +** ld1uw_gather_31_s64_index: +** ld1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svld1uw_gather_index_s64 (p0, z0, 31)) + +/* +** ld1uw_gather_32_s64_index: +** mov (x[0-9]+), #?128 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svld1uw_gather_index_s64 (p0, z0, 32)) + +/* +** ld1uw_gather_x0_s64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_s64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_s64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_s64 (p0, x0, z1), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_s64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_s64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_s64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_s64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_s64 (p0, x0, z1), + z0_res = svld1uw_gather_offset_s64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_s64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_s64_s64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_s64_s64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_s64 (p0, x0, z0), + z0_res = svld1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_s64_s64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_s64 (p0, x0, z1), + z0_res = svld1uw_gather_index_s64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_s64_s64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_s64_u64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_s64_u64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_s64 (p0, x0, z0), + z0_res = svld1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_s64_u64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_s64 (p0, x0, z1), + z0_res = svld1uw_gather_index_s64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_s64_u64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_u64.c new file mode 100644 index 00000000000..43ee33618ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_gather_u64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uw_gather_u64_tied1: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_u64 (p0, z0), + z0_res = svld1uw_gather_u64 (p0, z0)) + +/* +** ld1uw_gather_u64_untied: +** ld1w z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_u64 (p0, z1), + z0_res = svld1uw_gather_u64 (p0, z1)) + +/* +** ld1uw_gather_x0_u64_offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svld1uw_gather_offset_u64 (p0, z0, x0)) + +/* +** ld1uw_gather_m4_u64_offset: +** mov (x[0-9]+), #?-4 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_m4_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, -4), + z0_res = svld1uw_gather_offset_u64 (p0, z0, -4)) + +/* +** ld1uw_gather_0_u64_offset: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 0)) + +/* +** ld1uw_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 5)) + +/* +** ld1uw_gather_6_u64_offset: +** mov (x[0-9]+), #?6 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 6)) + +/* +** ld1uw_gather_7_u64_offset: +** mov (x[0-9]+), #?7 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_7_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 7), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 7)) + +/* +** ld1uw_gather_8_u64_offset: +** ld1w z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_8_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 8), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 8)) + +/* +** ld1uw_gather_124_u64_offset: +** ld1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_124_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 124), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 124)) + +/* +** ld1uw_gather_128_u64_offset: +** mov (x[0-9]+), #?128 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_128_u64_offset, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_offset_u64 (p0, z0, 128), + z0_res = svld1uw_gather_offset_u64 (p0, z0, 128)) + +/* +** ld1uw_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?2 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svld1uw_gather_index_u64 (p0, z0, x0)) + +/* +** ld1uw_gather_m1_u64_index: +** mov (x[0-9]+), #?-4 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svld1uw_gather_index_u64 (p0, z0, -1)) + +/* +** ld1uw_gather_0_u64_index: +** ld1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svld1uw_gather_index_u64 (p0, z0, 0)) + +/* +** ld1uw_gather_5_u64_index: +** ld1w z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svld1uw_gather_index_u64 (p0, z0, 5)) + +/* +** ld1uw_gather_31_u64_index: +** ld1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svld1uw_gather_index_u64 (p0, z0, 31)) + +/* +** ld1uw_gather_32_u64_index: +** mov (x[0-9]+), #?128 +** ld1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ld1uw_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svld1uw_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svld1uw_gather_index_u64 (p0, z0, 32)) + +/* +** ld1uw_gather_x0_u64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_u64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_u64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_u64 (p0, x0, z1), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_u64_s64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_u64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_u64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_u64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_u64 (p0, x0, z1), + z0_res = svld1uw_gather_offset_u64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_u64_u64offset: +** ld1w z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_u64_s64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_u64_s64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_u64 (p0, x0, z0), + z0_res = svld1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_u64_s64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_u64 (p0, x0, z1), + z0_res = svld1uw_gather_index_u64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_u64_s64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svld1uw_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svld1uw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ld1uw_gather_x0_u64_u64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_x0_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_tied1_u64_u64index: +** ld1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_tied1_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_u64 (p0, x0, z0), + z0_res = svld1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ld1uw_gather_untied_u64_u64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_untied_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_u64 (p0, x0, z1), + z0_res = svld1uw_gather_index_u64 (p0, x0, z1)) + +/* +** ld1uw_gather_ext_u64_u64index: +** ld1w z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ld1uw_gather_ext_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svld1uw_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svld1uw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_s64.c new file mode 100644 index 00000000000..951fc5ea09b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uw_s64_base: +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_s64_base, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0), + z0 = svld1uw_s64 (p0, x0)) + +/* +** ld1uw_s64_index: +** ld1w z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1uw_s64_index, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 + x1), + z0 = svld1uw_s64 (p0, x0 + x1)) + +/* +** ld1uw_s64_1: +** ld1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_s64_1, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 + svcntd ()), + z0 = svld1uw_s64 (p0, x0 + svcntd ())) + +/* +** ld1uw_s64_7: +** ld1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_s64_7, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 + svcntd () * 7), + z0 = svld1uw_s64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_s64_8: +** incb x0, all, mul #4 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_s64_8, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 + svcntd () * 8), + z0 = svld1uw_s64 (p0, x0 + svcntd () * 8)) + +/* +** ld1uw_s64_m1: +** ld1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_s64_m1, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 - svcntd ()), + z0 = svld1uw_s64 (p0, x0 - svcntd ())) + +/* +** ld1uw_s64_m8: +** ld1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_s64_m8, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 - svcntd () * 8), + z0 = svld1uw_s64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_s64_m9: +** dech x0, all, mul #9 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_s64_m9, svint64_t, uint32_t, + z0 = svld1uw_s64 (p0, x0 - svcntd () * 9), + z0 = svld1uw_s64 (p0, x0 - svcntd () * 9)) + +/* +** ld1uw_vnum_s64_0: +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_0, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, 0), + z0 = svld1uw_vnum_s64 (p0, x0, 0)) + +/* +** ld1uw_vnum_s64_1: +** ld1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_1, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, 1), + z0 = svld1uw_vnum_s64 (p0, x0, 1)) + +/* +** ld1uw_vnum_s64_7: +** ld1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_7, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, 7), + z0 = svld1uw_vnum_s64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_vnum_s64_8: +** incb x0, all, mul #4 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_8, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, 8), + z0 = svld1uw_vnum_s64 (p0, x0, 8)) + +/* +** ld1uw_vnum_s64_m1: +** ld1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_m1, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, -1), + z0 = svld1uw_vnum_s64 (p0, x0, -1)) + +/* +** ld1uw_vnum_s64_m8: +** ld1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_m8, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, -8), + z0 = svld1uw_vnum_s64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_vnum_s64_m9: +** dech x0, all, mul #9 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_m9, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, -9), + z0 = svld1uw_vnum_s64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_s64_x1, svint64_t, uint32_t, + z0 = svld1uw_vnum_s64 (p0, x0, x1), + z0 = svld1uw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_u64.c new file mode 100644 index 00000000000..68ba618feac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1uw_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld1uw_u64_base: +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_u64_base, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0), + z0 = svld1uw_u64 (p0, x0)) + +/* +** ld1uw_u64_index: +** ld1w z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld1uw_u64_index, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 + x1), + z0 = svld1uw_u64 (p0, x0 + x1)) + +/* +** ld1uw_u64_1: +** ld1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_u64_1, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 + svcntd ()), + z0 = svld1uw_u64 (p0, x0 + svcntd ())) + +/* +** ld1uw_u64_7: +** ld1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_u64_7, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 + svcntd () * 7), + z0 = svld1uw_u64 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_u64_8: +** incb x0, all, mul #4 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_u64_8, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 + svcntd () * 8), + z0 = svld1uw_u64 (p0, x0 + svcntd () * 8)) + +/* +** ld1uw_u64_m1: +** ld1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_u64_m1, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 - svcntd ()), + z0 = svld1uw_u64 (p0, x0 - svcntd ())) + +/* +** ld1uw_u64_m8: +** ld1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_u64_m8, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 - svcntd () * 8), + z0 = svld1uw_u64 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_u64_m9: +** dech x0, all, mul #9 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_u64_m9, svuint64_t, uint32_t, + z0 = svld1uw_u64 (p0, x0 - svcntd () * 9), + z0 = svld1uw_u64 (p0, x0 - svcntd () * 9)) + +/* +** ld1uw_vnum_u64_0: +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_0, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, 0), + z0 = svld1uw_vnum_u64 (p0, x0, 0)) + +/* +** ld1uw_vnum_u64_1: +** ld1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_1, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, 1), + z0 = svld1uw_vnum_u64 (p0, x0, 1)) + +/* +** ld1uw_vnum_u64_7: +** ld1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_7, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, 7), + z0 = svld1uw_vnum_u64 (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_vnum_u64_8: +** incb x0, all, mul #4 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_8, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, 8), + z0 = svld1uw_vnum_u64 (p0, x0, 8)) + +/* +** ld1uw_vnum_u64_m1: +** ld1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_m1, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, -1), + z0 = svld1uw_vnum_u64 (p0, x0, -1)) + +/* +** ld1uw_vnum_u64_m8: +** ld1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_m8, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, -8), + z0 = svld1uw_vnum_u64 (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld1uw_vnum_u64_m9: +** dech x0, all, mul #9 +** ld1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_m9, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, -9), + z0 = svld1uw_vnum_u64 (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld1uw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld1uw_vnum_u64_x1, svuint64_t, uint32_t, + z0 = svld1uw_vnum_u64 (p0, x0, x1), + z0 = svld1uw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f16.c new file mode 100644 index 00000000000..b44c13c7d8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_f16_base: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f16_base, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_f16_index: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld2_f16_index, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f16_1, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 + svcnth ()), + z0 = svld2 (p0, x0 + svcnth ())) + +/* +** ld2_f16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f16_2, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 + svcnth () * 2), + z0 = svld2 (p0, x0 + svcnth () * 2)) + +/* +** ld2_f16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f16_14, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 + svcnth () * 14), + z0 = svld2 (p0, x0 + svcnth () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f16_16, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 + svcnth () * 16), + z0 = svld2 (p0, x0 + svcnth () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f16_m1, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 - svcnth ()), + z0 = svld2 (p0, x0 - svcnth ())) + +/* +** ld2_f16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f16_m2, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 - svcnth () * 2), + z0 = svld2 (p0, x0 - svcnth () * 2)) + +/* +** ld2_f16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f16_m16, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 - svcnth () * 16), + z0 = svld2 (p0, x0 - svcnth () * 16)) + +/* +** ld2_f16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_f16_m18, svfloat16x2_t, float16_t, + z0 = svld2_f16 (p0, x0 - svcnth () * 18), + z0 = svld2 (p0, x0 - svcnth () * 18)) + +/* +** ld2_vnum_f16_0: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_0, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_1, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_f16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_2, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_f16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_14, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_16, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_m1, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_f16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_m2, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_f16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_m16, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_f16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_m18, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_f16_x1, svfloat16x2_t, float16_t, + z0 = svld2_vnum_f16 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f32.c new file mode 100644 index 00000000000..1d665c221eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_f32_base: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f32_base, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_f32_index: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld2_f32_index, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f32_1, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 + svcntw ()), + z0 = svld2 (p0, x0 + svcntw ())) + +/* +** ld2_f32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f32_2, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 + svcntw () * 2), + z0 = svld2 (p0, x0 + svcntw () * 2)) + +/* +** ld2_f32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f32_14, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 + svcntw () * 14), + z0 = svld2 (p0, x0 + svcntw () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f32_16, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 + svcntw () * 16), + z0 = svld2 (p0, x0 + svcntw () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f32_m1, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 - svcntw ()), + z0 = svld2 (p0, x0 - svcntw ())) + +/* +** ld2_f32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f32_m2, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 - svcntw () * 2), + z0 = svld2 (p0, x0 - svcntw () * 2)) + +/* +** ld2_f32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f32_m16, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 - svcntw () * 16), + z0 = svld2 (p0, x0 - svcntw () * 16)) + +/* +** ld2_f32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_f32_m18, svfloat32x2_t, float32_t, + z0 = svld2_f32 (p0, x0 - svcntw () * 18), + z0 = svld2 (p0, x0 - svcntw () * 18)) + +/* +** ld2_vnum_f32_0: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_0, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_1, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_f32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_2, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_f32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_14, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_16, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_m1, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_f32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_m2, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_f32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_m16, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_f32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_m18, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_f32_x1, svfloat32x2_t, float32_t, + z0 = svld2_vnum_f32 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f64.c new file mode 100644 index 00000000000..db46a1e1ee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_f64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_f64_base: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f64_base, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_f64_index: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld2_f64_index, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f64_1, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 + svcntd ()), + z0 = svld2 (p0, x0 + svcntd ())) + +/* +** ld2_f64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f64_2, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 + svcntd () * 2), + z0 = svld2 (p0, x0 + svcntd () * 2)) + +/* +** ld2_f64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f64_14, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 + svcntd () * 14), + z0 = svld2 (p0, x0 + svcntd () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f64_16, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 + svcntd () * 16), + z0 = svld2 (p0, x0 + svcntd () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_f64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_f64_m1, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 - svcntd ()), + z0 = svld2 (p0, x0 - svcntd ())) + +/* +** ld2_f64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f64_m2, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 - svcntd () * 2), + z0 = svld2 (p0, x0 - svcntd () * 2)) + +/* +** ld2_f64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_f64_m16, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 - svcntd () * 16), + z0 = svld2 (p0, x0 - svcntd () * 16)) + +/* +** ld2_f64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_f64_m18, svfloat64x2_t, float64_t, + z0 = svld2_f64 (p0, x0 - svcntd () * 18), + z0 = svld2 (p0, x0 - svcntd () * 18)) + +/* +** ld2_vnum_f64_0: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_0, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_1, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_f64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_2, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_f64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_14, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_16, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_f64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_m1, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_f64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_m2, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_f64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_m16, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_f64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_m18, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_f64_x1, svfloat64x2_t, float64_t, + z0 = svld2_vnum_f64 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s16.c new file mode 100644 index 00000000000..5f5fd6aa5d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_s16_base: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s16_base, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_s16_index: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld2_s16_index, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s16_1, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 + svcnth ()), + z0 = svld2 (p0, x0 + svcnth ())) + +/* +** ld2_s16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s16_2, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 + svcnth () * 2), + z0 = svld2 (p0, x0 + svcnth () * 2)) + +/* +** ld2_s16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s16_14, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 + svcnth () * 14), + z0 = svld2 (p0, x0 + svcnth () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s16_16, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 + svcnth () * 16), + z0 = svld2 (p0, x0 + svcnth () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s16_m1, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 - svcnth ()), + z0 = svld2 (p0, x0 - svcnth ())) + +/* +** ld2_s16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s16_m2, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 - svcnth () * 2), + z0 = svld2 (p0, x0 - svcnth () * 2)) + +/* +** ld2_s16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s16_m16, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 - svcnth () * 16), + z0 = svld2 (p0, x0 - svcnth () * 16)) + +/* +** ld2_s16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_s16_m18, svint16x2_t, int16_t, + z0 = svld2_s16 (p0, x0 - svcnth () * 18), + z0 = svld2 (p0, x0 - svcnth () * 18)) + +/* +** ld2_vnum_s16_0: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_0, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_1, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_s16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_2, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_s16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_14, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_16, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_m1, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_s16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_m2, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_s16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_m16, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_s16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_m18, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_s16_x1, svint16x2_t, int16_t, + z0 = svld2_vnum_s16 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s32.c new file mode 100644 index 00000000000..25a67a33911 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_s32_base: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s32_base, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_s32_index: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld2_s32_index, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s32_1, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 + svcntw ()), + z0 = svld2 (p0, x0 + svcntw ())) + +/* +** ld2_s32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s32_2, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 + svcntw () * 2), + z0 = svld2 (p0, x0 + svcntw () * 2)) + +/* +** ld2_s32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s32_14, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 + svcntw () * 14), + z0 = svld2 (p0, x0 + svcntw () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s32_16, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 + svcntw () * 16), + z0 = svld2 (p0, x0 + svcntw () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s32_m1, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 - svcntw ()), + z0 = svld2 (p0, x0 - svcntw ())) + +/* +** ld2_s32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s32_m2, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 - svcntw () * 2), + z0 = svld2 (p0, x0 - svcntw () * 2)) + +/* +** ld2_s32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s32_m16, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 - svcntw () * 16), + z0 = svld2 (p0, x0 - svcntw () * 16)) + +/* +** ld2_s32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_s32_m18, svint32x2_t, int32_t, + z0 = svld2_s32 (p0, x0 - svcntw () * 18), + z0 = svld2 (p0, x0 - svcntw () * 18)) + +/* +** ld2_vnum_s32_0: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_0, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_1, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_s32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_2, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_s32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_14, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_16, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_m1, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_s32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_m2, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_s32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_m16, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_s32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_m18, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_s32_x1, svint32x2_t, int32_t, + z0 = svld2_vnum_s32 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s64.c new file mode 100644 index 00000000000..9f606016d6c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_s64_base: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s64_base, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_s64_index: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld2_s64_index, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s64_1, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 + svcntd ()), + z0 = svld2 (p0, x0 + svcntd ())) + +/* +** ld2_s64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s64_2, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 + svcntd () * 2), + z0 = svld2 (p0, x0 + svcntd () * 2)) + +/* +** ld2_s64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s64_14, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 + svcntd () * 14), + z0 = svld2 (p0, x0 + svcntd () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s64_16, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 + svcntd () * 16), + z0 = svld2 (p0, x0 + svcntd () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s64_m1, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 - svcntd ()), + z0 = svld2 (p0, x0 - svcntd ())) + +/* +** ld2_s64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s64_m2, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 - svcntd () * 2), + z0 = svld2 (p0, x0 - svcntd () * 2)) + +/* +** ld2_s64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s64_m16, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 - svcntd () * 16), + z0 = svld2 (p0, x0 - svcntd () * 16)) + +/* +** ld2_s64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_s64_m18, svint64x2_t, int64_t, + z0 = svld2_s64 (p0, x0 - svcntd () * 18), + z0 = svld2 (p0, x0 - svcntd () * 18)) + +/* +** ld2_vnum_s64_0: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_0, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_1, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_s64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_2, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_s64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_14, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_16, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_m1, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_s64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_m2, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_s64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_m16, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_s64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_m18, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_s64_x1, svint64x2_t, int64_t, + z0 = svld2_vnum_s64 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s8.c new file mode 100644 index 00000000000..01ec1f15ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_s8.c @@ -0,0 +1,204 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_s8_base: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s8_base, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_s8_index: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld2_s8_index, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s8_1: +** incb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s8_1, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 + svcntb ()), + z0 = svld2 (p0, x0 + svcntb ())) + +/* +** ld2_s8_2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s8_2, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 + svcntb () * 2), + z0 = svld2 (p0, x0 + svcntb () * 2)) + +/* +** ld2_s8_14: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s8_14, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 + svcntb () * 14), + z0 = svld2 (p0, x0 + svcntb () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s8_16: +** incb x0, all, mul #16 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s8_16, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 + svcntb () * 16), + z0 = svld2 (p0, x0 + svcntb () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_s8_m1: +** decb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_s8_m1, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 - svcntb ()), + z0 = svld2 (p0, x0 - svcntb ())) + +/* +** ld2_s8_m2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s8_m2, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 - svcntb () * 2), + z0 = svld2 (p0, x0 - svcntb () * 2)) + +/* +** ld2_s8_m16: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_s8_m16, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 - svcntb () * 16), + z0 = svld2 (p0, x0 - svcntb () * 16)) + +/* +** ld2_s8_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_s8_m18, svint8x2_t, int8_t, + z0 = svld2_s8 (p0, x0 - svcntb () * 18), + z0 = svld2 (p0, x0 - svcntb () * 18)) + +/* +** ld2_vnum_s8_0: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_0, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s8_1: +** incb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_1, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_s8_2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_2, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_s8_14: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_14, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s8_16: +** incb x0, all, mul #16 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_16, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_s8_m1: +** decb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_m1, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_s8_m2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_m2, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_s8_m16: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_m16, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_s8_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_s8_m18, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* +** ld2_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld2_vnum_s8_x1, svint8x2_t, int8_t, + z0 = svld2_vnum_s8 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u16.c new file mode 100644 index 00000000000..e99ff88765c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_u16_base: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u16_base, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_u16_index: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld2_u16_index, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u16_1, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 + svcnth ()), + z0 = svld2 (p0, x0 + svcnth ())) + +/* +** ld2_u16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u16_2, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 + svcnth () * 2), + z0 = svld2 (p0, x0 + svcnth () * 2)) + +/* +** ld2_u16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u16_14, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 + svcnth () * 14), + z0 = svld2 (p0, x0 + svcnth () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u16_16, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 + svcnth () * 16), + z0 = svld2 (p0, x0 + svcnth () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u16_m1, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 - svcnth ()), + z0 = svld2 (p0, x0 - svcnth ())) + +/* +** ld2_u16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u16_m2, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 - svcnth () * 2), + z0 = svld2 (p0, x0 - svcnth () * 2)) + +/* +** ld2_u16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u16_m16, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 - svcnth () * 16), + z0 = svld2 (p0, x0 - svcnth () * 16)) + +/* +** ld2_u16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_u16_m18, svuint16x2_t, uint16_t, + z0 = svld2_u16 (p0, x0 - svcnth () * 18), + z0 = svld2 (p0, x0 - svcnth () * 18)) + +/* +** ld2_vnum_u16_0: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_0, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u16_1: +** incb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_1, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_u16_2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_2, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_u16_14: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_14, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u16_16: +** incb x0, all, mul #16 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_16, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u16_m1: +** decb x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_m1, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_u16_m2: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_m2, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_u16_m16: +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_m16, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_u16_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_m18, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2h {z0\.h(?: - |, )z1\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_u16_x1, svuint16x2_t, uint16_t, + z0 = svld2_vnum_u16 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u32.c new file mode 100644 index 00000000000..4f7d783c77e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_u32_base: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u32_base, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_u32_index: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld2_u32_index, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u32_1, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 + svcntw ()), + z0 = svld2 (p0, x0 + svcntw ())) + +/* +** ld2_u32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u32_2, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 + svcntw () * 2), + z0 = svld2 (p0, x0 + svcntw () * 2)) + +/* +** ld2_u32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u32_14, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 + svcntw () * 14), + z0 = svld2 (p0, x0 + svcntw () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u32_16, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 + svcntw () * 16), + z0 = svld2 (p0, x0 + svcntw () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u32_m1, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 - svcntw ()), + z0 = svld2 (p0, x0 - svcntw ())) + +/* +** ld2_u32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u32_m2, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 - svcntw () * 2), + z0 = svld2 (p0, x0 - svcntw () * 2)) + +/* +** ld2_u32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u32_m16, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 - svcntw () * 16), + z0 = svld2 (p0, x0 - svcntw () * 16)) + +/* +** ld2_u32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_u32_m18, svuint32x2_t, uint32_t, + z0 = svld2_u32 (p0, x0 - svcntw () * 18), + z0 = svld2 (p0, x0 - svcntw () * 18)) + +/* +** ld2_vnum_u32_0: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_0, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u32_1: +** incb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_1, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_u32_2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_2, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_u32_14: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_14, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u32_16: +** incb x0, all, mul #16 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_16, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u32_m1: +** decb x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_m1, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_u32_m2: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_m2, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_u32_m16: +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_m16, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_u32_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_m18, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2w {z0\.s(?: - |, )z1\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_u32_x1, svuint32x2_t, uint32_t, + z0 = svld2_vnum_u32 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u64.c new file mode 100644 index 00000000000..600a9421670 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_u64_base: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u64_base, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_u64_index: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld2_u64_index, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u64_1, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 + svcntd ()), + z0 = svld2 (p0, x0 + svcntd ())) + +/* +** ld2_u64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u64_2, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 + svcntd () * 2), + z0 = svld2 (p0, x0 + svcntd () * 2)) + +/* +** ld2_u64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u64_14, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 + svcntd () * 14), + z0 = svld2 (p0, x0 + svcntd () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u64_16, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 + svcntd () * 16), + z0 = svld2 (p0, x0 + svcntd () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u64_m1, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 - svcntd ()), + z0 = svld2 (p0, x0 - svcntd ())) + +/* +** ld2_u64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u64_m2, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 - svcntd () * 2), + z0 = svld2 (p0, x0 - svcntd () * 2)) + +/* +** ld2_u64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u64_m16, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 - svcntd () * 16), + z0 = svld2 (p0, x0 - svcntd () * 16)) + +/* +** ld2_u64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_u64_m18, svuint64x2_t, uint64_t, + z0 = svld2_u64 (p0, x0 - svcntd () * 18), + z0 = svld2 (p0, x0 - svcntd () * 18)) + +/* +** ld2_vnum_u64_0: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_0, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u64_1: +** incb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_1, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_u64_2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_2, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_u64_14: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_14, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u64_16: +** incb x0, all, mul #16 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_16, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u64_m1: +** decb x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_m1, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_u64_m2: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_m2, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_u64_m16: +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_m16, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_u64_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_m18, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld2_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld2d {z0\.d(?: - |, )z1\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld2_vnum_u64_x1, svuint64x2_t, uint64_t, + z0 = svld2_vnum_u64 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u8.c new file mode 100644 index 00000000000..88b12bfbda8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld2_u8.c @@ -0,0 +1,204 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld2_u8_base: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u8_base, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0), + z0 = svld2 (p0, x0)) + +/* +** ld2_u8_index: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld2_u8_index, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 + x1), + z0 = svld2 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u8_1: +** incb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u8_1, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 + svcntb ()), + z0 = svld2 (p0, x0 + svcntb ())) + +/* +** ld2_u8_2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u8_2, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 + svcntb () * 2), + z0 = svld2 (p0, x0 + svcntb () * 2)) + +/* +** ld2_u8_14: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u8_14, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 + svcntb () * 14), + z0 = svld2 (p0, x0 + svcntb () * 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u8_16: +** incb x0, all, mul #16 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u8_16, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 + svcntb () * 16), + z0 = svld2 (p0, x0 + svcntb () * 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_u8_m1: +** decb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_u8_m1, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 - svcntb ()), + z0 = svld2 (p0, x0 - svcntb ())) + +/* +** ld2_u8_m2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u8_m2, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 - svcntb () * 2), + z0 = svld2 (p0, x0 - svcntb () * 2)) + +/* +** ld2_u8_m16: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_u8_m16, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 - svcntb () * 16), + z0 = svld2 (p0, x0 - svcntb () * 16)) + +/* +** ld2_u8_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_u8_m18, svuint8x2_t, uint8_t, + z0 = svld2_u8 (p0, x0 - svcntb () * 18), + z0 = svld2 (p0, x0 - svcntb () * 18)) + +/* +** ld2_vnum_u8_0: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_0, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, 0), + z0 = svld2_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u8_1: +** incb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_1, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, 1), + z0 = svld2_vnum (p0, x0, 1)) + +/* +** ld2_vnum_u8_2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_2, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, 2), + z0 = svld2_vnum (p0, x0, 2)) + +/* +** ld2_vnum_u8_14: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #14, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_14, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, 14), + z0 = svld2_vnum (p0, x0, 14)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u8_16: +** incb x0, all, mul #16 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_16, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, 16), + z0 = svld2_vnum (p0, x0, 16)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld2_vnum_u8_m1: +** decb x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_m1, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, -1), + z0 = svld2_vnum (p0, x0, -1)) + +/* +** ld2_vnum_u8_m2: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-2, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_m2, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, -2), + z0 = svld2_vnum (p0, x0, -2)) + +/* +** ld2_vnum_u8_m16: +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, #-16, mul vl\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_m16, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, -16), + z0 = svld2_vnum (p0, x0, -16)) + +/* +** ld2_vnum_u8_m18: +** addvl (x[0-9]+), x0, #-18 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld2_vnum_u8_m18, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, -18), + z0 = svld2_vnum (p0, x0, -18)) + +/* +** ld2_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld2b {z0\.b(?: - |, )z1\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld2_vnum_u8_x1, svuint8x2_t, uint8_t, + z0 = svld2_vnum_u8 (p0, x0, x1), + z0 = svld2_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f16.c new file mode 100644 index 00000000000..3bfa2ce942b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_f16_base: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f16_base, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_f16_index: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld3_f16_index, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f16_1, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + svcnth ()), + z0 = svld3 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f16_2, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + svcnth () * 2), + z0 = svld3 (p0, x0 + svcnth () * 2)) + +/* +** ld3_f16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f16_3, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + svcnth () * 3), + z0 = svld3 (p0, x0 + svcnth () * 3)) + +/* +** ld3_f16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f16_21, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + svcnth () * 21), + z0 = svld3 (p0, x0 + svcnth () * 21)) + +/* +** ld3_f16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f16_24, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 + svcnth () * 24), + z0 = svld3 (p0, x0 + svcnth () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f16_m1, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 - svcnth ()), + z0 = svld3 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f16_m2, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 - svcnth () * 2), + z0 = svld3 (p0, x0 - svcnth () * 2)) + +/* +** ld3_f16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f16_m3, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 - svcnth () * 3), + z0 = svld3 (p0, x0 - svcnth () * 3)) + +/* +** ld3_f16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f16_m24, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 - svcnth () * 24), + z0 = svld3 (p0, x0 - svcnth () * 24)) + +/* +** ld3_f16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f16_m27, svfloat16x3_t, float16_t, + z0 = svld3_f16 (p0, x0 - svcnth () * 27), + z0 = svld3 (p0, x0 - svcnth () * 27)) + +/* +** ld3_vnum_f16_0: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_0, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_1, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_2, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_f16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_3, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_f16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_21, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_f16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_24, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_m1, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_m2, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_f16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_m3, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_f16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_m24, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_f16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_m27, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_f16_x1, svfloat16x3_t, float16_t, + z0 = svld3_vnum_f16 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f32.c new file mode 100644 index 00000000000..0de941d814b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_f32_base: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f32_base, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_f32_index: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld3_f32_index, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f32_1, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + svcntw ()), + z0 = svld3 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f32_2, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + svcntw () * 2), + z0 = svld3 (p0, x0 + svcntw () * 2)) + +/* +** ld3_f32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f32_3, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + svcntw () * 3), + z0 = svld3 (p0, x0 + svcntw () * 3)) + +/* +** ld3_f32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f32_21, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + svcntw () * 21), + z0 = svld3 (p0, x0 + svcntw () * 21)) + +/* +** ld3_f32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f32_24, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 + svcntw () * 24), + z0 = svld3 (p0, x0 + svcntw () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f32_m1, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 - svcntw ()), + z0 = svld3 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f32_m2, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 - svcntw () * 2), + z0 = svld3 (p0, x0 - svcntw () * 2)) + +/* +** ld3_f32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f32_m3, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 - svcntw () * 3), + z0 = svld3 (p0, x0 - svcntw () * 3)) + +/* +** ld3_f32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f32_m24, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 - svcntw () * 24), + z0 = svld3 (p0, x0 - svcntw () * 24)) + +/* +** ld3_f32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f32_m27, svfloat32x3_t, float32_t, + z0 = svld3_f32 (p0, x0 - svcntw () * 27), + z0 = svld3 (p0, x0 - svcntw () * 27)) + +/* +** ld3_vnum_f32_0: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_0, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_1, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_2, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_f32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_3, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_f32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_21, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_f32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_24, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_m1, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_m2, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_f32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_m3, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_f32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_m24, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_f32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_m27, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_f32_x1, svfloat32x3_t, float32_t, + z0 = svld3_vnum_f32 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f64.c new file mode 100644 index 00000000000..e913379455d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_f64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_f64_base: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f64_base, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_f64_index: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld3_f64_index, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f64_1, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + svcntd ()), + z0 = svld3 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f64_2, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + svcntd () * 2), + z0 = svld3 (p0, x0 + svcntd () * 2)) + +/* +** ld3_f64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f64_3, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + svcntd () * 3), + z0 = svld3 (p0, x0 + svcntd () * 3)) + +/* +** ld3_f64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f64_21, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + svcntd () * 21), + z0 = svld3 (p0, x0 + svcntd () * 21)) + +/* +** ld3_f64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f64_24, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 + svcntd () * 24), + z0 = svld3 (p0, x0 + svcntd () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f64_m1, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 - svcntd ()), + z0 = svld3 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_f64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_f64_m2, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 - svcntd () * 2), + z0 = svld3 (p0, x0 - svcntd () * 2)) + +/* +** ld3_f64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f64_m3, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 - svcntd () * 3), + z0 = svld3 (p0, x0 - svcntd () * 3)) + +/* +** ld3_f64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_f64_m24, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 - svcntd () * 24), + z0 = svld3 (p0, x0 - svcntd () * 24)) + +/* +** ld3_f64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_f64_m27, svfloat64x3_t, float64_t, + z0 = svld3_f64 (p0, x0 - svcntd () * 27), + z0 = svld3 (p0, x0 - svcntd () * 27)) + +/* +** ld3_vnum_f64_0: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_0, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_1, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_2, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_f64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_3, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_f64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_21, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_f64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_24, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_m1, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_f64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_m2, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_f64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_m3, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_f64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_m24, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_f64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_m27, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_f64_x1, svfloat64x3_t, float64_t, + z0 = svld3_vnum_f64 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s16.c new file mode 100644 index 00000000000..9021ccf5caa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_s16_base: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s16_base, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_s16_index: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld3_s16_index, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s16_1, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + svcnth ()), + z0 = svld3 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s16_2, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + svcnth () * 2), + z0 = svld3 (p0, x0 + svcnth () * 2)) + +/* +** ld3_s16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s16_3, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + svcnth () * 3), + z0 = svld3 (p0, x0 + svcnth () * 3)) + +/* +** ld3_s16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s16_21, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + svcnth () * 21), + z0 = svld3 (p0, x0 + svcnth () * 21)) + +/* +** ld3_s16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s16_24, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 + svcnth () * 24), + z0 = svld3 (p0, x0 + svcnth () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s16_m1, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 - svcnth ()), + z0 = svld3 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s16_m2, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 - svcnth () * 2), + z0 = svld3 (p0, x0 - svcnth () * 2)) + +/* +** ld3_s16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s16_m3, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 - svcnth () * 3), + z0 = svld3 (p0, x0 - svcnth () * 3)) + +/* +** ld3_s16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s16_m24, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 - svcnth () * 24), + z0 = svld3 (p0, x0 - svcnth () * 24)) + +/* +** ld3_s16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s16_m27, svint16x3_t, int16_t, + z0 = svld3_s16 (p0, x0 - svcnth () * 27), + z0 = svld3 (p0, x0 - svcnth () * 27)) + +/* +** ld3_vnum_s16_0: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_0, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_1, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_2, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_s16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_3, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_s16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_21, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_s16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_24, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_m1, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_m2, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_s16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_m3, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_s16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_m24, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_s16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_m27, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_s16_x1, svint16x3_t, int16_t, + z0 = svld3_vnum_s16 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s32.c new file mode 100644 index 00000000000..5d73def8b74 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_s32_base: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s32_base, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_s32_index: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld3_s32_index, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s32_1, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + svcntw ()), + z0 = svld3 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s32_2, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + svcntw () * 2), + z0 = svld3 (p0, x0 + svcntw () * 2)) + +/* +** ld3_s32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s32_3, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + svcntw () * 3), + z0 = svld3 (p0, x0 + svcntw () * 3)) + +/* +** ld3_s32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s32_21, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + svcntw () * 21), + z0 = svld3 (p0, x0 + svcntw () * 21)) + +/* +** ld3_s32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s32_24, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 + svcntw () * 24), + z0 = svld3 (p0, x0 + svcntw () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s32_m1, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 - svcntw ()), + z0 = svld3 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s32_m2, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 - svcntw () * 2), + z0 = svld3 (p0, x0 - svcntw () * 2)) + +/* +** ld3_s32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s32_m3, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 - svcntw () * 3), + z0 = svld3 (p0, x0 - svcntw () * 3)) + +/* +** ld3_s32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s32_m24, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 - svcntw () * 24), + z0 = svld3 (p0, x0 - svcntw () * 24)) + +/* +** ld3_s32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s32_m27, svint32x3_t, int32_t, + z0 = svld3_s32 (p0, x0 - svcntw () * 27), + z0 = svld3 (p0, x0 - svcntw () * 27)) + +/* +** ld3_vnum_s32_0: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_0, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_1, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_2, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_s32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_3, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_s32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_21, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_s32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_24, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_m1, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_m2, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_s32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_m3, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_s32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_m24, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_s32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_m27, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_s32_x1, svint32x3_t, int32_t, + z0 = svld3_vnum_s32 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s64.c new file mode 100644 index 00000000000..d1741964ee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_s64_base: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s64_base, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_s64_index: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld3_s64_index, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s64_1, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + svcntd ()), + z0 = svld3 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s64_2, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + svcntd () * 2), + z0 = svld3 (p0, x0 + svcntd () * 2)) + +/* +** ld3_s64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s64_3, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + svcntd () * 3), + z0 = svld3 (p0, x0 + svcntd () * 3)) + +/* +** ld3_s64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s64_21, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + svcntd () * 21), + z0 = svld3 (p0, x0 + svcntd () * 21)) + +/* +** ld3_s64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s64_24, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 + svcntd () * 24), + z0 = svld3 (p0, x0 + svcntd () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s64_m1, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 - svcntd ()), + z0 = svld3 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s64_m2, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 - svcntd () * 2), + z0 = svld3 (p0, x0 - svcntd () * 2)) + +/* +** ld3_s64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s64_m3, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 - svcntd () * 3), + z0 = svld3 (p0, x0 - svcntd () * 3)) + +/* +** ld3_s64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s64_m24, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 - svcntd () * 24), + z0 = svld3 (p0, x0 - svcntd () * 24)) + +/* +** ld3_s64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s64_m27, svint64x3_t, int64_t, + z0 = svld3_s64 (p0, x0 - svcntd () * 27), + z0 = svld3 (p0, x0 - svcntd () * 27)) + +/* +** ld3_vnum_s64_0: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_0, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_1, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_2, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_s64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_3, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_s64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_21, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_s64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_24, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_m1, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_m2, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_s64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_m3, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_s64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_m24, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_s64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_m27, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_s64_x1, svint64x3_t, int64_t, + z0 = svld3_vnum_s64 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s8.c new file mode 100644 index 00000000000..8d0fc0d82e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_s8.c @@ -0,0 +1,246 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_s8_base: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s8_base, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_s8_index: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld3_s8_index, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s8_1: +** incb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s8_1, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + svcntb ()), + z0 = svld3 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s8_2: +** incb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s8_2, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + svcntb () * 2), + z0 = svld3 (p0, x0 + svcntb () * 2)) + +/* +** ld3_s8_3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s8_3, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + svcntb () * 3), + z0 = svld3 (p0, x0 + svcntb () * 3)) + +/* +** ld3_s8_21: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s8_21, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + svcntb () * 21), + z0 = svld3 (p0, x0 + svcntb () * 21)) + +/* +** ld3_s8_24: +** addvl (x[0-9]+), x0, #24 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s8_24, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 + svcntb () * 24), + z0 = svld3 (p0, x0 + svcntb () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s8_m1: +** decb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s8_m1, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 - svcntb ()), + z0 = svld3 (p0, x0 - svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_s8_m2: +** decb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_s8_m2, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 - svcntb () * 2), + z0 = svld3 (p0, x0 - svcntb () * 2)) + +/* +** ld3_s8_m3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s8_m3, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 - svcntb () * 3), + z0 = svld3 (p0, x0 - svcntb () * 3)) + +/* +** ld3_s8_m24: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_s8_m24, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 - svcntb () * 24), + z0 = svld3 (p0, x0 - svcntb () * 24)) + +/* +** ld3_s8_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_s8_m27, svint8x3_t, int8_t, + z0 = svld3_s8 (p0, x0 - svcntb () * 27), + z0 = svld3 (p0, x0 - svcntb () * 27)) + +/* +** ld3_vnum_s8_0: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_0, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s8_1: +** incb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_1, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s8_2: +** incb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_2, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_s8_3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_3, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_s8_21: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_21, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_s8_24: +** addvl (x[0-9]+), x0, #24 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_24, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s8_m1: +** decb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_m1, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_s8_m2: +** decb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_m2, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_s8_m3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_m3, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_s8_m24: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_m24, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_s8_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_s8_m27, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* +** ld3_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld3_vnum_s8_x1, svint8x3_t, int8_t, + z0 = svld3_vnum_s8 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u16.c new file mode 100644 index 00000000000..e3e36b864c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_u16_base: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u16_base, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_u16_index: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld3_u16_index, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u16_1, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + svcnth ()), + z0 = svld3 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u16_2, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + svcnth () * 2), + z0 = svld3 (p0, x0 + svcnth () * 2)) + +/* +** ld3_u16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u16_3, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + svcnth () * 3), + z0 = svld3 (p0, x0 + svcnth () * 3)) + +/* +** ld3_u16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u16_21, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + svcnth () * 21), + z0 = svld3 (p0, x0 + svcnth () * 21)) + +/* +** ld3_u16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u16_24, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 + svcnth () * 24), + z0 = svld3 (p0, x0 + svcnth () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u16_m1, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 - svcnth ()), + z0 = svld3 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u16_m2, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 - svcnth () * 2), + z0 = svld3 (p0, x0 - svcnth () * 2)) + +/* +** ld3_u16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u16_m3, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 - svcnth () * 3), + z0 = svld3 (p0, x0 - svcnth () * 3)) + +/* +** ld3_u16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u16_m24, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 - svcnth () * 24), + z0 = svld3 (p0, x0 - svcnth () * 24)) + +/* +** ld3_u16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u16_m27, svuint16x3_t, uint16_t, + z0 = svld3_u16 (p0, x0 - svcnth () * 27), + z0 = svld3 (p0, x0 - svcnth () * 27)) + +/* +** ld3_vnum_u16_0: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_0, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u16_1: +** incb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_1, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u16_2: +** incb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_2, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_u16_3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_3, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_u16_21: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_21, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_u16_24: +** addvl (x[0-9]+), x0, #24 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_24, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u16_m1: +** decb x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_m1, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u16_m2: +** decb x0, all, mul #2 +** ld3h {z0\.h - z2\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_m2, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_u16_m3: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_m3, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_u16_m24: +** ld3h {z0\.h - z2\.h}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_m24, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_u16_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3h {z0\.h - z2\.h}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_m27, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3h {z0\.h - z2\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_u16_x1, svuint16x3_t, uint16_t, + z0 = svld3_vnum_u16 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u32.c new file mode 100644 index 00000000000..31bda9075b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_u32_base: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u32_base, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_u32_index: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld3_u32_index, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u32_1, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + svcntw ()), + z0 = svld3 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u32_2, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + svcntw () * 2), + z0 = svld3 (p0, x0 + svcntw () * 2)) + +/* +** ld3_u32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u32_3, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + svcntw () * 3), + z0 = svld3 (p0, x0 + svcntw () * 3)) + +/* +** ld3_u32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u32_21, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + svcntw () * 21), + z0 = svld3 (p0, x0 + svcntw () * 21)) + +/* +** ld3_u32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u32_24, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 + svcntw () * 24), + z0 = svld3 (p0, x0 + svcntw () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u32_m1, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 - svcntw ()), + z0 = svld3 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u32_m2, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 - svcntw () * 2), + z0 = svld3 (p0, x0 - svcntw () * 2)) + +/* +** ld3_u32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u32_m3, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 - svcntw () * 3), + z0 = svld3 (p0, x0 - svcntw () * 3)) + +/* +** ld3_u32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u32_m24, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 - svcntw () * 24), + z0 = svld3 (p0, x0 - svcntw () * 24)) + +/* +** ld3_u32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u32_m27, svuint32x3_t, uint32_t, + z0 = svld3_u32 (p0, x0 - svcntw () * 27), + z0 = svld3 (p0, x0 - svcntw () * 27)) + +/* +** ld3_vnum_u32_0: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_0, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u32_1: +** incb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_1, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u32_2: +** incb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_2, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_u32_3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_3, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_u32_21: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_21, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_u32_24: +** addvl (x[0-9]+), x0, #24 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_24, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u32_m1: +** decb x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_m1, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u32_m2: +** decb x0, all, mul #2 +** ld3w {z0\.s - z2\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_m2, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_u32_m3: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_m3, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_u32_m24: +** ld3w {z0\.s - z2\.s}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_m24, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_u32_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3w {z0\.s - z2\.s}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_m27, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3w {z0\.s - z2\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_u32_x1, svuint32x3_t, uint32_t, + z0 = svld3_vnum_u32 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u64.c new file mode 100644 index 00000000000..48fbbdce9da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_u64_base: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u64_base, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_u64_index: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld3_u64_index, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u64_1, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + svcntd ()), + z0 = svld3 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u64_2, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + svcntd () * 2), + z0 = svld3 (p0, x0 + svcntd () * 2)) + +/* +** ld3_u64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u64_3, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + svcntd () * 3), + z0 = svld3 (p0, x0 + svcntd () * 3)) + +/* +** ld3_u64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u64_21, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + svcntd () * 21), + z0 = svld3 (p0, x0 + svcntd () * 21)) + +/* +** ld3_u64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u64_24, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 + svcntd () * 24), + z0 = svld3 (p0, x0 + svcntd () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u64_m1, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 - svcntd ()), + z0 = svld3 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u64_m2, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 - svcntd () * 2), + z0 = svld3 (p0, x0 - svcntd () * 2)) + +/* +** ld3_u64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u64_m3, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 - svcntd () * 3), + z0 = svld3 (p0, x0 - svcntd () * 3)) + +/* +** ld3_u64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u64_m24, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 - svcntd () * 24), + z0 = svld3 (p0, x0 - svcntd () * 24)) + +/* +** ld3_u64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u64_m27, svuint64x3_t, uint64_t, + z0 = svld3_u64 (p0, x0 - svcntd () * 27), + z0 = svld3 (p0, x0 - svcntd () * 27)) + +/* +** ld3_vnum_u64_0: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_0, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u64_1: +** incb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_1, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u64_2: +** incb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_2, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_u64_3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_3, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_u64_21: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_21, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_u64_24: +** addvl (x[0-9]+), x0, #24 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_24, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u64_m1: +** decb x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_m1, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u64_m2: +** decb x0, all, mul #2 +** ld3d {z0\.d - z2\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_m2, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_u64_m3: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_m3, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_u64_m24: +** ld3d {z0\.d - z2\.d}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_m24, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_u64_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3d {z0\.d - z2\.d}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_m27, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld3_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld3d {z0\.d - z2\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld3_vnum_u64_x1, svuint64x3_t, uint64_t, + z0 = svld3_vnum_u64 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u8.c new file mode 100644 index 00000000000..a8d5e0aacb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld3_u8.c @@ -0,0 +1,246 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld3_u8_base: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u8_base, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0), + z0 = svld3 (p0, x0)) + +/* +** ld3_u8_index: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld3_u8_index, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + x1), + z0 = svld3 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u8_1: +** incb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u8_1, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + svcntb ()), + z0 = svld3 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u8_2: +** incb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u8_2, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + svcntb () * 2), + z0 = svld3 (p0, x0 + svcntb () * 2)) + +/* +** ld3_u8_3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u8_3, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + svcntb () * 3), + z0 = svld3 (p0, x0 + svcntb () * 3)) + +/* +** ld3_u8_21: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u8_21, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + svcntb () * 21), + z0 = svld3 (p0, x0 + svcntb () * 21)) + +/* +** ld3_u8_24: +** addvl (x[0-9]+), x0, #24 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u8_24, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 + svcntb () * 24), + z0 = svld3 (p0, x0 + svcntb () * 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u8_m1: +** decb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u8_m1, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 - svcntb ()), + z0 = svld3 (p0, x0 - svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_u8_m2: +** decb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_u8_m2, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 - svcntb () * 2), + z0 = svld3 (p0, x0 - svcntb () * 2)) + +/* +** ld3_u8_m3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u8_m3, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 - svcntb () * 3), + z0 = svld3 (p0, x0 - svcntb () * 3)) + +/* +** ld3_u8_m24: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_u8_m24, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 - svcntb () * 24), + z0 = svld3 (p0, x0 - svcntb () * 24)) + +/* +** ld3_u8_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_u8_m27, svuint8x3_t, uint8_t, + z0 = svld3_u8 (p0, x0 - svcntb () * 27), + z0 = svld3 (p0, x0 - svcntb () * 27)) + +/* +** ld3_vnum_u8_0: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_0, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 0), + z0 = svld3_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u8_1: +** incb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_1, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 1), + z0 = svld3_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u8_2: +** incb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_2, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 2), + z0 = svld3_vnum (p0, x0, 2)) + +/* +** ld3_vnum_u8_3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_3, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 3), + z0 = svld3_vnum (p0, x0, 3)) + +/* +** ld3_vnum_u8_21: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #21, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_21, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 21), + z0 = svld3_vnum (p0, x0, 21)) + +/* +** ld3_vnum_u8_24: +** addvl (x[0-9]+), x0, #24 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_24, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, 24), + z0 = svld3_vnum (p0, x0, 24)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u8_m1: +** decb x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_m1, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, -1), + z0 = svld3_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld3_vnum_u8_m2: +** decb x0, all, mul #2 +** ld3b {z0\.b - z2\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_m2, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, -2), + z0 = svld3_vnum (p0, x0, -2)) + +/* +** ld3_vnum_u8_m3: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-3, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_m3, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, -3), + z0 = svld3_vnum (p0, x0, -3)) + +/* +** ld3_vnum_u8_m24: +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, #-24, mul vl\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_m24, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, -24), + z0 = svld3_vnum (p0, x0, -24)) + +/* +** ld3_vnum_u8_m27: +** addvl (x[0-9]+), x0, #-27 +** ld3b {z0\.b - z2\.b}, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ld3_vnum_u8_m27, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, -27), + z0 = svld3_vnum (p0, x0, -27)) + +/* +** ld3_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld3b {z0\.b - z2\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld3b {z0\.b - z2\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld3_vnum_u8_x1, svuint8x3_t, uint8_t, + z0 = svld3_vnum_u8 (p0, x0, x1), + z0 = svld3_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f16.c new file mode 100644 index 00000000000..697ea9dab98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_f16_base: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_base, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_f16_index: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld4_f16_index, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_1, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth ()), + z0 = svld4 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_2, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth () * 2), + z0 = svld4 (p0, x0 + svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_3, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth () * 3), + z0 = svld4 (p0, x0 + svcnth () * 3)) + +/* +** ld4_f16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f16_4, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth () * 4), + z0 = svld4 (p0, x0 + svcnth () * 4)) + +/* +** ld4_f16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f16_28, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth () * 28), + z0 = svld4 (p0, x0 + svcnth () * 28)) + +/* +** ld4_f16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f16_32, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 + svcnth () * 32), + z0 = svld4 (p0, x0 + svcnth () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_m1, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth ()), + z0 = svld4 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_m2, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth () * 2), + z0 = svld4 (p0, x0 - svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f16_m3, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth () * 3), + z0 = svld4 (p0, x0 - svcnth () * 3)) + +/* +** ld4_f16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f16_m4, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth () * 4), + z0 = svld4 (p0, x0 - svcnth () * 4)) + +/* +** ld4_f16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f16_m32, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth () * 32), + z0 = svld4 (p0, x0 - svcnth () * 32)) + +/* +** ld4_f16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f16_m36, svfloat16x4_t, float16_t, + z0 = svld4_f16 (p0, x0 - svcnth () * 36), + z0 = svld4 (p0, x0 - svcnth () * 36)) + +/* +** ld4_vnum_f16_0: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_0, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_1, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_2, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_3, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_f16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_4, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_f16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_28, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_f16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_32, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m1, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m2, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m3, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_f16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m4, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_f16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m32, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_f16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_m36, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_f16_x1, svfloat16x4_t, float16_t, + z0 = svld4_vnum_f16 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f32.c new file mode 100644 index 00000000000..e124eb09d59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_f32_base: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_base, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_f32_index: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld4_f32_index, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_1, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw ()), + z0 = svld4 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_2, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw () * 2), + z0 = svld4 (p0, x0 + svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_3, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw () * 3), + z0 = svld4 (p0, x0 + svcntw () * 3)) + +/* +** ld4_f32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f32_4, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw () * 4), + z0 = svld4 (p0, x0 + svcntw () * 4)) + +/* +** ld4_f32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f32_28, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw () * 28), + z0 = svld4 (p0, x0 + svcntw () * 28)) + +/* +** ld4_f32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f32_32, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 + svcntw () * 32), + z0 = svld4 (p0, x0 + svcntw () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_m1, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw ()), + z0 = svld4 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_m2, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw () * 2), + z0 = svld4 (p0, x0 - svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f32_m3, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw () * 3), + z0 = svld4 (p0, x0 - svcntw () * 3)) + +/* +** ld4_f32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f32_m4, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw () * 4), + z0 = svld4 (p0, x0 - svcntw () * 4)) + +/* +** ld4_f32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f32_m32, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw () * 32), + z0 = svld4 (p0, x0 - svcntw () * 32)) + +/* +** ld4_f32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f32_m36, svfloat32x4_t, float32_t, + z0 = svld4_f32 (p0, x0 - svcntw () * 36), + z0 = svld4 (p0, x0 - svcntw () * 36)) + +/* +** ld4_vnum_f32_0: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_0, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_1, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_2, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_3, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_f32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_4, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_f32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_28, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_f32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_32, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m1, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m2, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m3, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_f32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m4, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_f32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m32, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_f32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_m36, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_f32_x1, svfloat32x4_t, float32_t, + z0 = svld4_vnum_f32 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f64.c new file mode 100644 index 00000000000..303bbeb0c41 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_f64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_f64_base: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_base, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_f64_index: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld4_f64_index, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_1, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd ()), + z0 = svld4 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_2, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd () * 2), + z0 = svld4 (p0, x0 + svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_3, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd () * 3), + z0 = svld4 (p0, x0 + svcntd () * 3)) + +/* +** ld4_f64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f64_4, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd () * 4), + z0 = svld4 (p0, x0 + svcntd () * 4)) + +/* +** ld4_f64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f64_28, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd () * 28), + z0 = svld4 (p0, x0 + svcntd () * 28)) + +/* +** ld4_f64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f64_32, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 + svcntd () * 32), + z0 = svld4 (p0, x0 + svcntd () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_m1, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd ()), + z0 = svld4 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_m2, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd () * 2), + z0 = svld4 (p0, x0 - svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_f64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_f64_m3, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd () * 3), + z0 = svld4 (p0, x0 - svcntd () * 3)) + +/* +** ld4_f64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f64_m4, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd () * 4), + z0 = svld4 (p0, x0 - svcntd () * 4)) + +/* +** ld4_f64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_f64_m32, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd () * 32), + z0 = svld4 (p0, x0 - svcntd () * 32)) + +/* +** ld4_f64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_f64_m36, svfloat64x4_t, float64_t, + z0 = svld4_f64 (p0, x0 - svcntd () * 36), + z0 = svld4 (p0, x0 - svcntd () * 36)) + +/* +** ld4_vnum_f64_0: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_0, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_1, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_2, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_3, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_f64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_4, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_f64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_28, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_f64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_32, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m1, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m2, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_f64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m3, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_f64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m4, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_f64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m32, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_f64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_m36, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_f64_x1, svfloat64x4_t, float64_t, + z0 = svld4_vnum_f64 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s16.c new file mode 100644 index 00000000000..a6c01d1675d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_s16_base: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_base, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_s16_index: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld4_s16_index, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_1, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth ()), + z0 = svld4 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_2, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth () * 2), + z0 = svld4 (p0, x0 + svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_3, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth () * 3), + z0 = svld4 (p0, x0 + svcnth () * 3)) + +/* +** ld4_s16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s16_4, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth () * 4), + z0 = svld4 (p0, x0 + svcnth () * 4)) + +/* +** ld4_s16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s16_28, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth () * 28), + z0 = svld4 (p0, x0 + svcnth () * 28)) + +/* +** ld4_s16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s16_32, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 + svcnth () * 32), + z0 = svld4 (p0, x0 + svcnth () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_m1, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth ()), + z0 = svld4 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_m2, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth () * 2), + z0 = svld4 (p0, x0 - svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s16_m3, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth () * 3), + z0 = svld4 (p0, x0 - svcnth () * 3)) + +/* +** ld4_s16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s16_m4, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth () * 4), + z0 = svld4 (p0, x0 - svcnth () * 4)) + +/* +** ld4_s16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s16_m32, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth () * 32), + z0 = svld4 (p0, x0 - svcnth () * 32)) + +/* +** ld4_s16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s16_m36, svint16x4_t, int16_t, + z0 = svld4_s16 (p0, x0 - svcnth () * 36), + z0 = svld4 (p0, x0 - svcnth () * 36)) + +/* +** ld4_vnum_s16_0: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_0, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_1, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_2, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_3, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_s16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_4, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_s16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_28, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_s16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_32, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m1, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m2, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m3, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_s16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m4, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_s16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m32, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_s16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_m36, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_s16_x1, svint16x4_t, int16_t, + z0 = svld4_vnum_s16 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s32.c new file mode 100644 index 00000000000..4f356ecb468 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_s32_base: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_base, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_s32_index: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld4_s32_index, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_1, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw ()), + z0 = svld4 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_2, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw () * 2), + z0 = svld4 (p0, x0 + svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_3, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw () * 3), + z0 = svld4 (p0, x0 + svcntw () * 3)) + +/* +** ld4_s32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s32_4, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw () * 4), + z0 = svld4 (p0, x0 + svcntw () * 4)) + +/* +** ld4_s32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s32_28, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw () * 28), + z0 = svld4 (p0, x0 + svcntw () * 28)) + +/* +** ld4_s32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s32_32, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 + svcntw () * 32), + z0 = svld4 (p0, x0 + svcntw () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_m1, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw ()), + z0 = svld4 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_m2, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw () * 2), + z0 = svld4 (p0, x0 - svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s32_m3, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw () * 3), + z0 = svld4 (p0, x0 - svcntw () * 3)) + +/* +** ld4_s32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s32_m4, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw () * 4), + z0 = svld4 (p0, x0 - svcntw () * 4)) + +/* +** ld4_s32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s32_m32, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw () * 32), + z0 = svld4 (p0, x0 - svcntw () * 32)) + +/* +** ld4_s32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s32_m36, svint32x4_t, int32_t, + z0 = svld4_s32 (p0, x0 - svcntw () * 36), + z0 = svld4 (p0, x0 - svcntw () * 36)) + +/* +** ld4_vnum_s32_0: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_0, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_1, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_2, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_3, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_s32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_4, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_s32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_28, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_s32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_32, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m1, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m2, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m3, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_s32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m4, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_s32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m32, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_s32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_m36, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_s32_x1, svint32x4_t, int32_t, + z0 = svld4_vnum_s32 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s64.c new file mode 100644 index 00000000000..f4f85228cea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_s64_base: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_base, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_s64_index: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld4_s64_index, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_1, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd ()), + z0 = svld4 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_2, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd () * 2), + z0 = svld4 (p0, x0 + svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_3, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd () * 3), + z0 = svld4 (p0, x0 + svcntd () * 3)) + +/* +** ld4_s64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s64_4, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd () * 4), + z0 = svld4 (p0, x0 + svcntd () * 4)) + +/* +** ld4_s64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s64_28, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd () * 28), + z0 = svld4 (p0, x0 + svcntd () * 28)) + +/* +** ld4_s64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s64_32, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 + svcntd () * 32), + z0 = svld4 (p0, x0 + svcntd () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_m1, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd ()), + z0 = svld4 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_m2, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd () * 2), + z0 = svld4 (p0, x0 - svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s64_m3, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd () * 3), + z0 = svld4 (p0, x0 - svcntd () * 3)) + +/* +** ld4_s64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s64_m4, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd () * 4), + z0 = svld4 (p0, x0 - svcntd () * 4)) + +/* +** ld4_s64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s64_m32, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd () * 32), + z0 = svld4 (p0, x0 - svcntd () * 32)) + +/* +** ld4_s64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s64_m36, svint64x4_t, int64_t, + z0 = svld4_s64 (p0, x0 - svcntd () * 36), + z0 = svld4 (p0, x0 - svcntd () * 36)) + +/* +** ld4_vnum_s64_0: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_0, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_1, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_2, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_3, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_s64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_4, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_s64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_28, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_s64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_32, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m1, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m2, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m3, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_s64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m4, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_s64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m32, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_s64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_m36, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_s64_x1, svint64x4_t, int64_t, + z0 = svld4_vnum_s64 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s8.c new file mode 100644 index 00000000000..d00f1c4b581 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_s8.c @@ -0,0 +1,290 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_s8_base: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_base, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_s8_index: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld4_s8_index, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_1: +** incb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_1, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb ()), + z0 = svld4 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_2: +** incb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_2, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb () * 2), + z0 = svld4 (p0, x0 + svcntb () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_3: +** incb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_3, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb () * 3), + z0 = svld4 (p0, x0 + svcntb () * 3)) + +/* +** ld4_s8_4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s8_4, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb () * 4), + z0 = svld4 (p0, x0 + svcntb () * 4)) + +/* +** ld4_s8_28: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s8_28, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb () * 28), + z0 = svld4 (p0, x0 + svcntb () * 28)) + +/* +** ld4_s8_32: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s8_32, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 + svcntb () * 32), + z0 = svld4 (p0, x0 + svcntb () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_m1: +** decb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_m1, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb ()), + z0 = svld4 (p0, x0 - svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_m2: +** decb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_m2, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb () * 2), + z0 = svld4 (p0, x0 - svcntb () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_s8_m3: +** decb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_s8_m3, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb () * 3), + z0 = svld4 (p0, x0 - svcntb () * 3)) + +/* +** ld4_s8_m4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s8_m4, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb () * 4), + z0 = svld4 (p0, x0 - svcntb () * 4)) + +/* +** ld4_s8_m32: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_s8_m32, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb () * 32), + z0 = svld4 (p0, x0 - svcntb () * 32)) + +/* +** ld4_s8_m36: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_s8_m36, svint8x4_t, int8_t, + z0 = svld4_s8 (p0, x0 - svcntb () * 36), + z0 = svld4 (p0, x0 - svcntb () * 36)) + +/* +** ld4_vnum_s8_0: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_0, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_1: +** incb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_1, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_2: +** incb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_2, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_3: +** incb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_3, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_s8_4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_4, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_s8_28: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_28, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_s8_32: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_32, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_m1: +** decb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m1, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_m2: +** decb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m2, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_s8_m3: +** decb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m3, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_s8_m4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m4, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_s8_m32: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m32, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_s8_m36: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_s8_m36, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* +** ld4_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld4_vnum_s8_x1, svint8x4_t, int8_t, + z0 = svld4_vnum_s8 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u16.c new file mode 100644 index 00000000000..4e78c42d415 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_u16_base: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_base, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_u16_index: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ld4_u16_index, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_1, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth ()), + z0 = svld4 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_2, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth () * 2), + z0 = svld4 (p0, x0 + svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_3, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth () * 3), + z0 = svld4 (p0, x0 + svcnth () * 3)) + +/* +** ld4_u16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u16_4, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth () * 4), + z0 = svld4 (p0, x0 + svcnth () * 4)) + +/* +** ld4_u16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u16_28, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth () * 28), + z0 = svld4 (p0, x0 + svcnth () * 28)) + +/* +** ld4_u16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u16_32, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 + svcnth () * 32), + z0 = svld4 (p0, x0 + svcnth () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_m1, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth ()), + z0 = svld4 (p0, x0 - svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_m2, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth () * 2), + z0 = svld4 (p0, x0 - svcnth () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u16_m3, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth () * 3), + z0 = svld4 (p0, x0 - svcnth () * 3)) + +/* +** ld4_u16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u16_m4, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth () * 4), + z0 = svld4 (p0, x0 - svcnth () * 4)) + +/* +** ld4_u16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u16_m32, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth () * 32), + z0 = svld4 (p0, x0 - svcnth () * 32)) + +/* +** ld4_u16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u16_m36, svuint16x4_t, uint16_t, + z0 = svld4_u16 (p0, x0 - svcnth () * 36), + z0 = svld4 (p0, x0 - svcnth () * 36)) + +/* +** ld4_vnum_u16_0: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_0, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_1: +** incb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_1, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_2: +** incb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_2, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_3: +** incb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_3, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_u16_4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_4, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_u16_28: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_28, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_u16_32: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_32, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_m1: +** decb x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m1, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_m2: +** decb x0, all, mul #2 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m2, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u16_m3: +** decb x0, all, mul #3 +** ld4h {z0\.h - z3\.h}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m3, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_u16_m4: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m4, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_u16_m32: +** ld4h {z0\.h - z3\.h}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m32, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_u16_m36: +** [^{]* +** ld4h {z0\.h - z3\.h}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_m36, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4h {z0\.h - z3\.h}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_u16_x1, svuint16x4_t, uint16_t, + z0 = svld4_vnum_u16 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u32.c new file mode 100644 index 00000000000..19931b687c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_u32_base: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_base, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_u32_index: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ld4_u32_index, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_1, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw ()), + z0 = svld4 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_2, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw () * 2), + z0 = svld4 (p0, x0 + svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_3, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw () * 3), + z0 = svld4 (p0, x0 + svcntw () * 3)) + +/* +** ld4_u32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u32_4, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw () * 4), + z0 = svld4 (p0, x0 + svcntw () * 4)) + +/* +** ld4_u32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u32_28, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw () * 28), + z0 = svld4 (p0, x0 + svcntw () * 28)) + +/* +** ld4_u32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u32_32, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 + svcntw () * 32), + z0 = svld4 (p0, x0 + svcntw () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_m1, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw ()), + z0 = svld4 (p0, x0 - svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_m2, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw () * 2), + z0 = svld4 (p0, x0 - svcntw () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u32_m3, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw () * 3), + z0 = svld4 (p0, x0 - svcntw () * 3)) + +/* +** ld4_u32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u32_m4, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw () * 4), + z0 = svld4 (p0, x0 - svcntw () * 4)) + +/* +** ld4_u32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u32_m32, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw () * 32), + z0 = svld4 (p0, x0 - svcntw () * 32)) + +/* +** ld4_u32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u32_m36, svuint32x4_t, uint32_t, + z0 = svld4_u32 (p0, x0 - svcntw () * 36), + z0 = svld4 (p0, x0 - svcntw () * 36)) + +/* +** ld4_vnum_u32_0: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_0, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_1: +** incb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_1, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_2: +** incb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_2, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_3: +** incb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_3, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_u32_4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_4, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_u32_28: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_28, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_u32_32: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_32, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_m1: +** decb x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m1, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_m2: +** decb x0, all, mul #2 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m2, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u32_m3: +** decb x0, all, mul #3 +** ld4w {z0\.s - z3\.s}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m3, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_u32_m4: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m4, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_u32_m32: +** ld4w {z0\.s - z3\.s}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m32, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_u32_m36: +** [^{]* +** ld4w {z0\.s - z3\.s}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_m36, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4w {z0\.s - z3\.s}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_u32_x1, svuint32x4_t, uint32_t, + z0 = svld4_vnum_u32 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u64.c new file mode 100644 index 00000000000..1bed2e7e244 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_u64_base: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_base, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_u64_index: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ld4_u64_index, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_1, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd ()), + z0 = svld4 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_2, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd () * 2), + z0 = svld4 (p0, x0 + svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_3, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd () * 3), + z0 = svld4 (p0, x0 + svcntd () * 3)) + +/* +** ld4_u64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u64_4, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd () * 4), + z0 = svld4 (p0, x0 + svcntd () * 4)) + +/* +** ld4_u64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u64_28, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd () * 28), + z0 = svld4 (p0, x0 + svcntd () * 28)) + +/* +** ld4_u64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u64_32, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 + svcntd () * 32), + z0 = svld4 (p0, x0 + svcntd () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_m1, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd ()), + z0 = svld4 (p0, x0 - svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_m2, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd () * 2), + z0 = svld4 (p0, x0 - svcntd () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u64_m3, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd () * 3), + z0 = svld4 (p0, x0 - svcntd () * 3)) + +/* +** ld4_u64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u64_m4, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd () * 4), + z0 = svld4 (p0, x0 - svcntd () * 4)) + +/* +** ld4_u64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u64_m32, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd () * 32), + z0 = svld4 (p0, x0 - svcntd () * 32)) + +/* +** ld4_u64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u64_m36, svuint64x4_t, uint64_t, + z0 = svld4_u64 (p0, x0 - svcntd () * 36), + z0 = svld4 (p0, x0 - svcntd () * 36)) + +/* +** ld4_vnum_u64_0: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_0, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_1: +** incb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_1, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_2: +** incb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_2, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_3: +** incb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_3, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_u64_4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_4, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_u64_28: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_28, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_u64_32: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_32, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_m1: +** decb x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m1, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_m2: +** decb x0, all, mul #2 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m2, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u64_m3: +** decb x0, all, mul #3 +** ld4d {z0\.d - z3\.d}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m3, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_u64_m4: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m4, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_u64_m32: +** ld4d {z0\.d - z3\.d}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m32, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_u64_m36: +** [^{]* +** ld4d {z0\.d - z3\.d}, p0/z, \[x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_m36, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ld4_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ld4d {z0\.d - z3\.d}, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ld4_vnum_u64_x1, svuint64x4_t, uint64_t, + z0 = svld4_vnum_u64 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u8.c new file mode 100644 index 00000000000..d731dbb7b53 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld4_u8.c @@ -0,0 +1,290 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ld4_u8_base: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_base, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0), + z0 = svld4 (p0, x0)) + +/* +** ld4_u8_index: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ld4_u8_index, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + x1), + z0 = svld4 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_1: +** incb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_1, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb ()), + z0 = svld4 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_2: +** incb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_2, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb () * 2), + z0 = svld4 (p0, x0 + svcntb () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_3: +** incb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_3, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb () * 3), + z0 = svld4 (p0, x0 + svcntb () * 3)) + +/* +** ld4_u8_4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u8_4, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb () * 4), + z0 = svld4 (p0, x0 + svcntb () * 4)) + +/* +** ld4_u8_28: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u8_28, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb () * 28), + z0 = svld4 (p0, x0 + svcntb () * 28)) + +/* +** ld4_u8_32: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u8_32, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 + svcntb () * 32), + z0 = svld4 (p0, x0 + svcntb () * 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_m1: +** decb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_m1, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb ()), + z0 = svld4 (p0, x0 - svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_m2: +** decb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_m2, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb () * 2), + z0 = svld4 (p0, x0 - svcntb () * 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_u8_m3: +** decb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_u8_m3, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb () * 3), + z0 = svld4 (p0, x0 - svcntb () * 3)) + +/* +** ld4_u8_m4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u8_m4, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb () * 4), + z0 = svld4 (p0, x0 - svcntb () * 4)) + +/* +** ld4_u8_m32: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_u8_m32, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb () * 32), + z0 = svld4 (p0, x0 - svcntb () * 32)) + +/* +** ld4_u8_m36: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_u8_m36, svuint8x4_t, uint8_t, + z0 = svld4_u8 (p0, x0 - svcntb () * 36), + z0 = svld4 (p0, x0 - svcntb () * 36)) + +/* +** ld4_vnum_u8_0: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_0, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 0), + z0 = svld4_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_1: +** incb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_1, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 1), + z0 = svld4_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_2: +** incb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_2, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 2), + z0 = svld4_vnum (p0, x0, 2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_3: +** incb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_3, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 3), + z0 = svld4_vnum (p0, x0, 3)) + +/* +** ld4_vnum_u8_4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_4, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 4), + z0 = svld4_vnum (p0, x0, 4)) + +/* +** ld4_vnum_u8_28: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #28, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_28, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 28), + z0 = svld4_vnum (p0, x0, 28)) + +/* +** ld4_vnum_u8_32: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_32, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, 32), + z0 = svld4_vnum (p0, x0, 32)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_m1: +** decb x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m1, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -1), + z0 = svld4_vnum (p0, x0, -1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_m2: +** decb x0, all, mul #2 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m2, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -2), + z0 = svld4_vnum (p0, x0, -2)) + +/* Moving the constant into a register would also be OK. */ +/* +** ld4_vnum_u8_m3: +** decb x0, all, mul #3 +** ld4b {z0\.b - z3\.b}, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m3, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -3), + z0 = svld4_vnum (p0, x0, -3)) + +/* +** ld4_vnum_u8_m4: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-4, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m4, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -4), + z0 = svld4_vnum (p0, x0, -4)) + +/* +** ld4_vnum_u8_m32: +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, #-32, mul vl\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m32, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -32), + z0 = svld4_vnum (p0, x0, -32)) + +/* +** ld4_vnum_u8_m36: +** [^{]* +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, x[0-9]+\] +** ret +*/ +TEST_LOAD (ld4_vnum_u8_m36, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, -36), + z0 = svld4_vnum (p0, x0, -36)) + +/* +** ld4_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ld4b {z0\.b - z3\.b}, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ld4b {z0\.b - z3\.b}, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ld4_vnum_u8_x1, svuint8x4_t, uint8_t, + z0 = svld4_vnum_u8 (p0, x0, x1), + z0 = svld4_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f16.c new file mode 100644 index 00000000000..b73d5cbbe4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f16.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_f16_base: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f16_base, svfloat16_t, float16_t, + z0 = svldff1_f16 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_f16_index: +** ldff1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1_f16_index, svfloat16_t, float16_t, + z0 = svldff1_f16 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f16_1, svfloat16_t, float16_t, + z0 = svldff1_f16 (p0, x0 + svcnth ()), + z0 = svldff1 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f16_m1, svfloat16_t, float16_t, + z0 = svldff1_f16 (p0, x0 - svcnth ()), + z0 = svldff1 (p0, x0 - svcnth ())) + +/* +** ldff1_vnum_f16_0: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f16_0, svfloat16_t, float16_t, + z0 = svldff1_vnum_f16 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f16_1, svfloat16_t, float16_t, + z0 = svldff1_vnum_f16 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f16_m1, svfloat16_t, float16_t, + z0 = svldff1_vnum_f16 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f16_x1, svfloat16_t, float16_t, + z0 = svldff1_vnum_f16 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f32.c new file mode 100644 index 00000000000..c7e2b62ea6e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_f32_base: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f32_base, svfloat32_t, float32_t, + z0 = svldff1_f32 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_f32_index: +** ldff1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1_f32_index, svfloat32_t, float32_t, + z0 = svldff1_f32 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f32_1, svfloat32_t, float32_t, + z0 = svldff1_f32 (p0, x0 + svcntw ()), + z0 = svldff1 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f32_m1, svfloat32_t, float32_t, + z0 = svldff1_f32 (p0, x0 - svcntw ()), + z0 = svldff1 (p0, x0 - svcntw ())) + +/* +** ldff1_vnum_f32_0: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f32_0, svfloat32_t, float32_t, + z0 = svldff1_vnum_f32 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f32_1, svfloat32_t, float32_t, + z0 = svldff1_vnum_f32 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f32_m1, svfloat32_t, float32_t, + z0 = svldff1_vnum_f32 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f32_x1, svfloat32_t, float32_t, + z0 = svldff1_vnum_f32 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f64.c new file mode 100644 index 00000000000..1c0ac4a2c11 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_f64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_f64_base: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f64_base, svfloat64_t, float64_t, + z0 = svldff1_f64 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_f64_index: +** ldff1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldff1_f64_index, svfloat64_t, float64_t, + z0 = svldff1_f64 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f64_1, svfloat64_t, float64_t, + z0 = svldff1_f64 (p0, x0 + svcntd ()), + z0 = svldff1 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_f64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_f64_m1, svfloat64_t, float64_t, + z0 = svldff1_f64 (p0, x0 - svcntd ()), + z0 = svldff1 (p0, x0 - svcntd ())) + +/* +** ldff1_vnum_f64_0: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f64_0, svfloat64_t, float64_t, + z0 = svldff1_vnum_f64 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f64_1, svfloat64_t, float64_t, + z0 = svldff1_vnum_f64 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_f64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f64_m1, svfloat64_t, float64_t, + z0 = svldff1_vnum_f64 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_f64_x1, svfloat64_t, float64_t, + z0 = svldff1_vnum_f64 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f32.c new file mode 100644 index 00000000000..316fc8461c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_f32_tied1: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_f32_tied1, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_f32 (p0, z0), + z0_res = svldff1_gather_f32 (p0, z0)) + +/* +** ldff1_gather_f32_untied: +** ldff1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_f32_untied, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_f32 (p0, z1), + z0_res = svldff1_gather_f32 (p0, z1)) + +/* +** ldff1_gather_x0_f32_offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, x0), + z0_res = svldff1_gather_offset_f32 (p0, z0, x0)) + +/* +** ldff1_gather_m4_f32_offset: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m4_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, -4), + z0_res = svldff1_gather_offset_f32 (p0, z0, -4)) + +/* +** ldff1_gather_0_f32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 0), + z0_res = svldff1_gather_offset_f32 (p0, z0, 0)) + +/* +** ldff1_gather_5_f32_offset: +** mov (x[0-9]+), #?5 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 5), + z0_res = svldff1_gather_offset_f32 (p0, z0, 5)) + +/* +** ldff1_gather_6_f32_offset: +** mov (x[0-9]+), #?6 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_6_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 6), + z0_res = svldff1_gather_offset_f32 (p0, z0, 6)) + +/* +** ldff1_gather_7_f32_offset: +** mov (x[0-9]+), #?7 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_7_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 7), + z0_res = svldff1_gather_offset_f32 (p0, z0, 7)) + +/* +** ldff1_gather_8_f32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_8_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 8), + z0_res = svldff1_gather_offset_f32 (p0, z0, 8)) + +/* +** ldff1_gather_124_f32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_124_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 124), + z0_res = svldff1_gather_offset_f32 (p0, z0, 124)) + +/* +** ldff1_gather_128_f32_offset: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_128_f32_offset, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_f32 (p0, z0, 128), + z0_res = svldff1_gather_offset_f32 (p0, z0, 128)) + +/* +** ldff1_gather_x0_f32_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, x0), + z0_res = svldff1_gather_index_f32 (p0, z0, x0)) + +/* +** ldff1_gather_m1_f32_index: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, -1), + z0_res = svldff1_gather_index_f32 (p0, z0, -1)) + +/* +** ldff1_gather_0_f32_index: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, 0), + z0_res = svldff1_gather_index_f32 (p0, z0, 0)) + +/* +** ldff1_gather_5_f32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, 5), + z0_res = svldff1_gather_index_f32 (p0, z0, 5)) + +/* +** ldff1_gather_31_f32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, 31), + z0_res = svldff1_gather_index_f32 (p0, z0, 31)) + +/* +** ldff1_gather_32_f32_index: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_f32_index, svfloat32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_f32 (p0, z0, 32), + z0_res = svldff1_gather_index_f32 (p0, z0, 32)) + +/* +** ldff1_gather_x0_f32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32offset_f32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32offset_f32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_f32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f32_s32offset, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32offset_f32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_f32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_f32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_f32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_f32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_f32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_f32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32index_f32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32index_f32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_f32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f32_s32index, svfloat32_t, float32_t, svint32_t, + z0_res = svldff1_gather_s32index_f32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_x0_f32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32index_f32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32index_f32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_f32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f32_u32index, svfloat32_t, float32_t, svuint32_t, + z0_res = svldff1_gather_u32index_f32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f64.c new file mode 100644 index 00000000000..972142a934c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_f64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_f64_tied1: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_f64_tied1, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_f64 (p0, z0), + z0_res = svldff1_gather_f64 (p0, z0)) + +/* +** ldff1_gather_f64_untied: +** ldff1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_f64_untied, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_f64 (p0, z1), + z0_res = svldff1_gather_f64 (p0, z1)) + +/* +** ldff1_gather_x0_f64_offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, x0), + z0_res = svldff1_gather_offset_f64 (p0, z0, x0)) + +/* +** ldff1_gather_m8_f64_offset: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m8_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, -8), + z0_res = svldff1_gather_offset_f64 (p0, z0, -8)) + +/* +** ldff1_gather_0_f64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 0), + z0_res = svldff1_gather_offset_f64 (p0, z0, 0)) + +/* +** ldff1_gather_9_f64_offset: +** mov (x[0-9]+), #?9 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_9_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 9), + z0_res = svldff1_gather_offset_f64 (p0, z0, 9)) + +/* +** ldff1_gather_10_f64_offset: +** mov (x[0-9]+), #?10 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_10_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 10), + z0_res = svldff1_gather_offset_f64 (p0, z0, 10)) + +/* +** ldff1_gather_11_f64_offset: +** mov (x[0-9]+), #?11 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_11_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 11), + z0_res = svldff1_gather_offset_f64 (p0, z0, 11)) + +/* +** ldff1_gather_12_f64_offset: +** mov (x[0-9]+), #?12 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_12_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 12), + z0_res = svldff1_gather_offset_f64 (p0, z0, 12)) + +/* +** ldff1_gather_13_f64_offset: +** mov (x[0-9]+), #?13 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_13_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 13), + z0_res = svldff1_gather_offset_f64 (p0, z0, 13)) + +/* +** ldff1_gather_14_f64_offset: +** mov (x[0-9]+), #?14 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_14_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 14), + z0_res = svldff1_gather_offset_f64 (p0, z0, 14)) + +/* +** ldff1_gather_15_f64_offset: +** mov (x[0-9]+), #?15 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_15_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 15), + z0_res = svldff1_gather_offset_f64 (p0, z0, 15)) + +/* +** ldff1_gather_16_f64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_16_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 16), + z0_res = svldff1_gather_offset_f64 (p0, z0, 16)) + +/* +** ldff1_gather_248_f64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_248_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 248), + z0_res = svldff1_gather_offset_f64 (p0, z0, 248)) + +/* +** ldff1_gather_256_f64_offset: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_256_f64_offset, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_f64 (p0, z0, 256), + z0_res = svldff1_gather_offset_f64 (p0, z0, 256)) + +/* +** ldff1_gather_x0_f64_index: +** lsl (x[0-9]+), x0, #?3 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, x0), + z0_res = svldff1_gather_index_f64 (p0, z0, x0)) + +/* +** ldff1_gather_m1_f64_index: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, -1), + z0_res = svldff1_gather_index_f64 (p0, z0, -1)) + +/* +** ldff1_gather_0_f64_index: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, 0), + z0_res = svldff1_gather_index_f64 (p0, z0, 0)) + +/* +** ldff1_gather_5_f64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, 5), + z0_res = svldff1_gather_index_f64 (p0, z0, 5)) + +/* +** ldff1_gather_31_f64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, 31), + z0_res = svldff1_gather_index_f64 (p0, z0, 31)) + +/* +** ldff1_gather_32_f64_index: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_f64_index, svfloat64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_f64 (p0, z0, 32), + z0_res = svldff1_gather_index_f64 (p0, z0, 32)) + +/* +** ldff1_gather_x0_f64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64offset_f64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64offset_f64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_f64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64offset_f64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_f64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_f64_s64offset, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64offset_f64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_f64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_f64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_f64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_f64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_f64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_f64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_f64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_f64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64index_f64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64index_f64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_f64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64index_f64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_f64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_f64_s64index, svfloat64_t, float64_t, svint64_t, + z0_res = svldff1_gather_s64index_f64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_f64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64index_f64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_f64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64index_f64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_f64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64index_f64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_f64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_f64_u64index, svfloat64_t, float64_t, svuint64_t, + z0_res = svldff1_gather_u64index_f64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s32.c new file mode 100644 index 00000000000..60a4aec53bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_s32_tied1: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_s32 (p0, z0), + z0_res = svldff1_gather_s32 (p0, z0)) + +/* +** ldff1_gather_s32_untied: +** ldff1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_s32 (p0, z1), + z0_res = svldff1_gather_s32 (p0, z1)) + +/* +** ldff1_gather_x0_s32_offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svldff1_gather_offset_s32 (p0, z0, x0)) + +/* +** ldff1_gather_m4_s32_offset: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m4_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, -4), + z0_res = svldff1_gather_offset_s32 (p0, z0, -4)) + +/* +** ldff1_gather_0_s32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svldff1_gather_offset_s32 (p0, z0, 0)) + +/* +** ldff1_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svldff1_gather_offset_s32 (p0, z0, 5)) + +/* +** ldff1_gather_6_s32_offset: +** mov (x[0-9]+), #?6 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svldff1_gather_offset_s32 (p0, z0, 6)) + +/* +** ldff1_gather_7_s32_offset: +** mov (x[0-9]+), #?7 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_7_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 7), + z0_res = svldff1_gather_offset_s32 (p0, z0, 7)) + +/* +** ldff1_gather_8_s32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_8_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 8), + z0_res = svldff1_gather_offset_s32 (p0, z0, 8)) + +/* +** ldff1_gather_124_s32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_124_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 124), + z0_res = svldff1_gather_offset_s32 (p0, z0, 124)) + +/* +** ldff1_gather_128_s32_offset: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_128_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_s32 (p0, z0, 128), + z0_res = svldff1_gather_offset_s32 (p0, z0, 128)) + +/* +** ldff1_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svldff1_gather_index_s32 (p0, z0, x0)) + +/* +** ldff1_gather_m1_s32_index: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svldff1_gather_index_s32 (p0, z0, -1)) + +/* +** ldff1_gather_0_s32_index: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svldff1_gather_index_s32 (p0, z0, 0)) + +/* +** ldff1_gather_5_s32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svldff1_gather_index_s32 (p0, z0, 5)) + +/* +** ldff1_gather_31_s32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svldff1_gather_index_s32 (p0, z0, 31)) + +/* +** ldff1_gather_32_s32_index: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svldff1_gather_index_s32 (p0, z0, 32)) + +/* +** ldff1_gather_x0_s32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_s32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s32_s32offset, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32offset_s32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_s32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_s32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s32_u32offset, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_s32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_s32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_s32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s32_s32index, svint32_t, int32_t, svint32_t, + z0_res = svldff1_gather_s32index_s32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_x0_s32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_s32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s32_u32index, svint32_t, int32_t, svuint32_t, + z0_res = svldff1_gather_u32index_s32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s64.c new file mode 100644 index 00000000000..0c4fcb02485 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_s64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_s64_tied1: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_s64 (p0, z0), + z0_res = svldff1_gather_s64 (p0, z0)) + +/* +** ldff1_gather_s64_untied: +** ldff1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_s64 (p0, z1), + z0_res = svldff1_gather_s64 (p0, z1)) + +/* +** ldff1_gather_x0_s64_offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1_gather_m8_s64_offset: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m8_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, -8), + z0_res = svldff1_gather_offset_s64 (p0, z0, -8)) + +/* +** ldff1_gather_0_s64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1_gather_9_s64_offset: +** mov (x[0-9]+), #?9 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_9_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 9), + z0_res = svldff1_gather_offset_s64 (p0, z0, 9)) + +/* +** ldff1_gather_10_s64_offset: +** mov (x[0-9]+), #?10 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_10_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 10), + z0_res = svldff1_gather_offset_s64 (p0, z0, 10)) + +/* +** ldff1_gather_11_s64_offset: +** mov (x[0-9]+), #?11 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_11_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 11), + z0_res = svldff1_gather_offset_s64 (p0, z0, 11)) + +/* +** ldff1_gather_12_s64_offset: +** mov (x[0-9]+), #?12 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_12_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 12), + z0_res = svldff1_gather_offset_s64 (p0, z0, 12)) + +/* +** ldff1_gather_13_s64_offset: +** mov (x[0-9]+), #?13 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_13_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 13), + z0_res = svldff1_gather_offset_s64 (p0, z0, 13)) + +/* +** ldff1_gather_14_s64_offset: +** mov (x[0-9]+), #?14 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_14_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 14), + z0_res = svldff1_gather_offset_s64 (p0, z0, 14)) + +/* +** ldff1_gather_15_s64_offset: +** mov (x[0-9]+), #?15 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_15_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 15), + z0_res = svldff1_gather_offset_s64 (p0, z0, 15)) + +/* +** ldff1_gather_16_s64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_16_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 16), + z0_res = svldff1_gather_offset_s64 (p0, z0, 16)) + +/* +** ldff1_gather_248_s64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_248_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 248), + z0_res = svldff1_gather_offset_s64 (p0, z0, 248)) + +/* +** ldff1_gather_256_s64_offset: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_256_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_s64 (p0, z0, 256), + z0_res = svldff1_gather_offset_s64 (p0, z0, 256)) + +/* +** ldff1_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?3 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svldff1_gather_index_s64 (p0, z0, x0)) + +/* +** ldff1_gather_m1_s64_index: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svldff1_gather_index_s64 (p0, z0, -1)) + +/* +** ldff1_gather_0_s64_index: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svldff1_gather_index_s64 (p0, z0, 0)) + +/* +** ldff1_gather_5_s64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svldff1_gather_index_s64 (p0, z0, 5)) + +/* +** ldff1_gather_31_s64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svldff1_gather_index_s64 (p0, z0, 31)) + +/* +** ldff1_gather_32_s64_index: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svldff1_gather_index_s64 (p0, z0, 32)) + +/* +** ldff1_gather_x0_s64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_s64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_s64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_s64_s64offset, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_s64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_s64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_s64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_s64_u64offset, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_s64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_s64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64index_s64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_s64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_s64_s64index, svint64_t, int64_t, svint64_t, + z0_res = svldff1_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_s64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_s64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_s64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64index_s64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_s64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_s64_u64index, svint64_t, int64_t, svuint64_t, + z0_res = svldff1_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u32.c new file mode 100644 index 00000000000..05307f744ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u32.c @@ -0,0 +1,272 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_u32_tied1: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_u32 (p0, z0), + z0_res = svldff1_gather_u32 (p0, z0)) + +/* +** ldff1_gather_u32_untied: +** ldff1w z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_u32 (p0, z1), + z0_res = svldff1_gather_u32 (p0, z1)) + +/* +** ldff1_gather_x0_u32_offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svldff1_gather_offset_u32 (p0, z0, x0)) + +/* +** ldff1_gather_m4_u32_offset: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m4_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, -4), + z0_res = svldff1_gather_offset_u32 (p0, z0, -4)) + +/* +** ldff1_gather_0_u32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svldff1_gather_offset_u32 (p0, z0, 0)) + +/* +** ldff1_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svldff1_gather_offset_u32 (p0, z0, 5)) + +/* +** ldff1_gather_6_u32_offset: +** mov (x[0-9]+), #?6 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svldff1_gather_offset_u32 (p0, z0, 6)) + +/* +** ldff1_gather_7_u32_offset: +** mov (x[0-9]+), #?7 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_7_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 7), + z0_res = svldff1_gather_offset_u32 (p0, z0, 7)) + +/* +** ldff1_gather_8_u32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_8_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 8), + z0_res = svldff1_gather_offset_u32 (p0, z0, 8)) + +/* +** ldff1_gather_124_u32_offset: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_124_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 124), + z0_res = svldff1_gather_offset_u32 (p0, z0, 124)) + +/* +** ldff1_gather_128_u32_offset: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_128_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_offset_u32 (p0, z0, 128), + z0_res = svldff1_gather_offset_u32 (p0, z0, 128)) + +/* +** ldff1_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svldff1_gather_index_u32 (p0, z0, x0)) + +/* +** ldff1_gather_m1_u32_index: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svldff1_gather_index_u32 (p0, z0, -1)) + +/* +** ldff1_gather_0_u32_index: +** ldff1w z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svldff1_gather_index_u32 (p0, z0, 0)) + +/* +** ldff1_gather_5_u32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svldff1_gather_index_u32 (p0, z0, 5)) + +/* +** ldff1_gather_31_u32_index: +** ldff1w z0\.s, p0/z, \[z0\.s, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svldff1_gather_index_u32 (p0, z0, 31)) + +/* +** ldff1_gather_32_u32_index: +** mov (x[0-9]+), #?128 +** ldff1w z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svldff1_gather_index_u32 (p0, z0, 32)) + +/* +** ldff1_gather_x0_u32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_u32_s32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u32_s32offset, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32offset_u32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_u32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_u32_u32offset: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32offset_u32 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_x0_u32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_u32_s32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u32_s32index, svuint32_t, uint32_t, svint32_t, + z0_res = svldff1_gather_s32index_u32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_x0_u32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_u32_u32index: +** ldff1w z0\.s, p0/z, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u32_u32index, svuint32_t, uint32_t, svuint32_t, + z0_res = svldff1_gather_u32index_u32 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u64.c new file mode 100644 index 00000000000..b5dc1fbaeb5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_gather_u64.c @@ -0,0 +1,348 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_gather_u64_tied1: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_u64 (p0, z0), + z0_res = svldff1_gather_u64 (p0, z0)) + +/* +** ldff1_gather_u64_untied: +** ldff1d z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_u64 (p0, z1), + z0_res = svldff1_gather_u64 (p0, z1)) + +/* +** ldff1_gather_x0_u64_offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1_gather_m8_u64_offset: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m8_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, -8), + z0_res = svldff1_gather_offset_u64 (p0, z0, -8)) + +/* +** ldff1_gather_0_u64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1_gather_9_u64_offset: +** mov (x[0-9]+), #?9 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_9_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 9), + z0_res = svldff1_gather_offset_u64 (p0, z0, 9)) + +/* +** ldff1_gather_10_u64_offset: +** mov (x[0-9]+), #?10 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_10_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 10), + z0_res = svldff1_gather_offset_u64 (p0, z0, 10)) + +/* +** ldff1_gather_11_u64_offset: +** mov (x[0-9]+), #?11 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_11_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 11), + z0_res = svldff1_gather_offset_u64 (p0, z0, 11)) + +/* +** ldff1_gather_12_u64_offset: +** mov (x[0-9]+), #?12 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_12_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 12), + z0_res = svldff1_gather_offset_u64 (p0, z0, 12)) + +/* +** ldff1_gather_13_u64_offset: +** mov (x[0-9]+), #?13 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_13_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 13), + z0_res = svldff1_gather_offset_u64 (p0, z0, 13)) + +/* +** ldff1_gather_14_u64_offset: +** mov (x[0-9]+), #?14 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_14_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 14), + z0_res = svldff1_gather_offset_u64 (p0, z0, 14)) + +/* +** ldff1_gather_15_u64_offset: +** mov (x[0-9]+), #?15 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_15_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 15), + z0_res = svldff1_gather_offset_u64 (p0, z0, 15)) + +/* +** ldff1_gather_16_u64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #16\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_16_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 16), + z0_res = svldff1_gather_offset_u64 (p0, z0, 16)) + +/* +** ldff1_gather_248_u64_offset: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_248_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 248), + z0_res = svldff1_gather_offset_u64 (p0, z0, 248)) + +/* +** ldff1_gather_256_u64_offset: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_256_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_offset_u64 (p0, z0, 256), + z0_res = svldff1_gather_offset_u64 (p0, z0, 256)) + +/* +** ldff1_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?3 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svldff1_gather_index_u64 (p0, z0, x0)) + +/* +** ldff1_gather_m1_u64_index: +** mov (x[0-9]+), #?-8 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svldff1_gather_index_u64 (p0, z0, -1)) + +/* +** ldff1_gather_0_u64_index: +** ldff1d z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svldff1_gather_index_u64 (p0, z0, 0)) + +/* +** ldff1_gather_5_u64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #40\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svldff1_gather_index_u64 (p0, z0, 5)) + +/* +** ldff1_gather_31_u64_index: +** ldff1d z0\.d, p0/z, \[z0\.d, #248\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svldff1_gather_index_u64 (p0, z0, 31)) + +/* +** ldff1_gather_32_u64_index: +** mov (x[0-9]+), #?256 +** ldff1d z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svldff1_gather_index_u64 (p0, z0, 32)) + +/* +** ldff1_gather_x0_u64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_u64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_u64_s64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_u64_s64offset, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_u64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1_gather_offset (p0, x0, z0)) + +/* +** ldff1_gather_untied_u64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1_gather_offset (p0, x0, z1)) + +/* +** ldff1_gather_ext_u64_u64offset: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_offset (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_u64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_u64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64index_u64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_u64_s64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_u64_s64index, svuint64_t, uint64_t, svint64_t, + z0_res = svldff1_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1_gather_x0_u64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_x0_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_tied1_u64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_tied1_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1_gather_index (p0, x0, z0)) + +/* +** ldff1_gather_untied_u64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_untied_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64index_u64 (p0, x0, z1), + z0_res = svldff1_gather_index (p0, x0, z1)) + +/* +** ldff1_gather_ext_u64_u64index: +** ldff1d z0\.d, p0/z, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1_gather_ext_u64_u64index, svuint64_t, uint64_t, svuint64_t, + z0_res = svldff1_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1_gather_index (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s16.c new file mode 100644 index 00000000000..092ac20a976 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s16.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_s16_base: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s16_base, svint16_t, int16_t, + z0 = svldff1_s16 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_s16_index: +** ldff1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1_s16_index, svint16_t, int16_t, + z0 = svldff1_s16 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s16_1, svint16_t, int16_t, + z0 = svldff1_s16 (p0, x0 + svcnth ()), + z0 = svldff1 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s16_m1, svint16_t, int16_t, + z0 = svldff1_s16 (p0, x0 - svcnth ()), + z0 = svldff1 (p0, x0 - svcnth ())) + +/* +** ldff1_vnum_s16_0: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s16_0, svint16_t, int16_t, + z0 = svldff1_vnum_s16 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s16_1, svint16_t, int16_t, + z0 = svldff1_vnum_s16 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s16_m1, svint16_t, int16_t, + z0 = svldff1_vnum_s16 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s16_x1, svint16_t, int16_t, + z0 = svldff1_vnum_s16 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s32.c new file mode 100644 index 00000000000..9c2a4ec03bc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_s32_base: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s32_base, svint32_t, int32_t, + z0 = svldff1_s32 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_s32_index: +** ldff1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1_s32_index, svint32_t, int32_t, + z0 = svldff1_s32 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s32_1, svint32_t, int32_t, + z0 = svldff1_s32 (p0, x0 + svcntw ()), + z0 = svldff1 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s32_m1, svint32_t, int32_t, + z0 = svldff1_s32 (p0, x0 - svcntw ()), + z0 = svldff1 (p0, x0 - svcntw ())) + +/* +** ldff1_vnum_s32_0: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s32_0, svint32_t, int32_t, + z0 = svldff1_vnum_s32 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s32_1, svint32_t, int32_t, + z0 = svldff1_vnum_s32 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s32_m1, svint32_t, int32_t, + z0 = svldff1_vnum_s32 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s32_x1, svint32_t, int32_t, + z0 = svldff1_vnum_s32 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s64.c new file mode 100644 index 00000000000..057b52495d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_s64_base: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s64_base, svint64_t, int64_t, + z0 = svldff1_s64 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_s64_index: +** ldff1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldff1_s64_index, svint64_t, int64_t, + z0 = svldff1_s64 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s64_1, svint64_t, int64_t, + z0 = svldff1_s64 (p0, x0 + svcntd ()), + z0 = svldff1 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s64_m1, svint64_t, int64_t, + z0 = svldff1_s64 (p0, x0 - svcntd ()), + z0 = svldff1 (p0, x0 - svcntd ())) + +/* +** ldff1_vnum_s64_0: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s64_0, svint64_t, int64_t, + z0 = svldff1_vnum_s64 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s64_1, svint64_t, int64_t, + z0 = svldff1_vnum_s64 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s64_m1, svint64_t, int64_t, + z0 = svldff1_vnum_s64 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s64_x1, svint64_t, int64_t, + z0 = svldff1_vnum_s64 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s8.c new file mode 100644 index 00000000000..767b660160f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_s8.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_s8_base: +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s8_base, svint8_t, int8_t, + z0 = svldff1_s8 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_s8_index: +** ldff1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1_s8_index, svint8_t, int8_t, + z0 = svldff1_s8 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s8_1: +** incb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s8_1, svint8_t, int8_t, + z0 = svldff1_s8 (p0, x0 + svcntb ()), + z0 = svldff1 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_s8_m1: +** decb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_s8_m1, svint8_t, int8_t, + z0 = svldff1_s8 (p0, x0 - svcntb ()), + z0 = svldff1 (p0, x0 - svcntb ())) + +/* +** ldff1_vnum_s8_0: +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s8_0, svint8_t, int8_t, + z0 = svldff1_vnum_s8 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s8_1: +** incb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s8_1, svint8_t, int8_t, + z0 = svldff1_vnum_s8 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_s8_m1: +** decb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_s8_m1, svint8_t, int8_t, + z0 = svldff1_vnum_s8 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* +** ldff1_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1_vnum_s8_x1, svint8_t, int8_t, + z0 = svldff1_vnum_s8 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u16.c new file mode 100644 index 00000000000..39a191f7a73 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u16.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_u16_base: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u16_base, svuint16_t, uint16_t, + z0 = svldff1_u16 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_u16_index: +** ldff1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1_u16_index, svuint16_t, uint16_t, + z0 = svldff1_u16 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u16_1, svuint16_t, uint16_t, + z0 = svldff1_u16 (p0, x0 + svcnth ()), + z0 = svldff1 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u16_m1, svuint16_t, uint16_t, + z0 = svldff1_u16 (p0, x0 - svcnth ()), + z0 = svldff1 (p0, x0 - svcnth ())) + +/* +** ldff1_vnum_u16_0: +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u16_0, svuint16_t, uint16_t, + z0 = svldff1_vnum_u16 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u16_1: +** incb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u16_1, svuint16_t, uint16_t, + z0 = svldff1_vnum_u16 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u16_m1: +** decb x0 +** ldff1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u16_m1, svuint16_t, uint16_t, + z0 = svldff1_vnum_u16 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u16_x1, svuint16_t, uint16_t, + z0 = svldff1_vnum_u16 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u32.c new file mode 100644 index 00000000000..835fe84095f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_u32_base: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u32_base, svuint32_t, uint32_t, + z0 = svldff1_u32 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_u32_index: +** ldff1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1_u32_index, svuint32_t, uint32_t, + z0 = svldff1_u32 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u32_1, svuint32_t, uint32_t, + z0 = svldff1_u32 (p0, x0 + svcntw ()), + z0 = svldff1 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u32_m1, svuint32_t, uint32_t, + z0 = svldff1_u32 (p0, x0 - svcntw ()), + z0 = svldff1 (p0, x0 - svcntw ())) + +/* +** ldff1_vnum_u32_0: +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u32_0, svuint32_t, uint32_t, + z0 = svldff1_vnum_u32 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u32_1: +** incb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u32_1, svuint32_t, uint32_t, + z0 = svldff1_vnum_u32 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u32_m1: +** decb x0 +** ldff1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u32_m1, svuint32_t, uint32_t, + z0 = svldff1_vnum_u32 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u32_x1, svuint32_t, uint32_t, + z0 = svldff1_vnum_u32 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u64.c new file mode 100644 index 00000000000..1bb5fc375c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_u64_base: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u64_base, svuint64_t, uint64_t, + z0 = svldff1_u64 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_u64_index: +** ldff1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldff1_u64_index, svuint64_t, uint64_t, + z0 = svldff1_u64 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u64_1, svuint64_t, uint64_t, + z0 = svldff1_u64 (p0, x0 + svcntd ()), + z0 = svldff1 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u64_m1, svuint64_t, uint64_t, + z0 = svldff1_u64 (p0, x0 - svcntd ()), + z0 = svldff1 (p0, x0 - svcntd ())) + +/* +** ldff1_vnum_u64_0: +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u64_0, svuint64_t, uint64_t, + z0 = svldff1_vnum_u64 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u64_1: +** incb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u64_1, svuint64_t, uint64_t, + z0 = svldff1_vnum_u64 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u64_m1: +** decb x0 +** ldff1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u64_m1, svuint64_t, uint64_t, + z0 = svldff1_vnum_u64 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u64_x1, svuint64_t, uint64_t, + z0 = svldff1_vnum_u64 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u8.c new file mode 100644 index 00000000000..1ec531472e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1_u8.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1_u8_base: +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u8_base, svuint8_t, uint8_t, + z0 = svldff1_u8 (p0, x0), + z0 = svldff1 (p0, x0)) + +/* +** ldff1_u8_index: +** ldff1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1_u8_index, svuint8_t, uint8_t, + z0 = svldff1_u8 (p0, x0 + x1), + z0 = svldff1 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u8_1: +** incb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u8_1, svuint8_t, uint8_t, + z0 = svldff1_u8 (p0, x0 + svcntb ()), + z0 = svldff1 (p0, x0 + svcntb ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_u8_m1: +** decb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_u8_m1, svuint8_t, uint8_t, + z0 = svldff1_u8 (p0, x0 - svcntb ()), + z0 = svldff1 (p0, x0 - svcntb ())) + +/* +** ldff1_vnum_u8_0: +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u8_0, svuint8_t, uint8_t, + z0 = svldff1_vnum_u8 (p0, x0, 0), + z0 = svldff1_vnum (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u8_1: +** incb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u8_1, svuint8_t, uint8_t, + z0 = svldff1_vnum_u8 (p0, x0, 1), + z0 = svldff1_vnum (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1_vnum_u8_m1: +** decb x0 +** ldff1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1_vnum_u8_m1, svuint8_t, uint8_t, + z0 = svldff1_vnum_u8 (p0, x0, -1), + z0 = svldff1_vnum (p0, x0, -1)) + +/* +** ldff1_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1_vnum_u8_x1, svuint8_t, uint8_t, + z0 = svldff1_vnum_u8 (p0, x0, x1), + z0 = svldff1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s32.c new file mode 100644 index 00000000000..5f1979e8057 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_gather_s32_tied1: +** ldff1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_s32 (p0, z0), + z0_res = svldff1sb_gather_s32 (p0, z0)) + +/* +** ldff1sb_gather_s32_untied: +** ldff1sb z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_s32 (p0, z1), + z0_res = svldff1sb_gather_s32 (p0, z1)) + +/* +** ldff1sb_gather_x0_s32_offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, x0)) + +/* +** ldff1sb_gather_m1_s32_offset: +** mov (x[0-9]+), #?-1 +** ldff1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_m1_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, -1), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, -1)) + +/* +** ldff1sb_gather_0_s32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, 0)) + +/* +** ldff1sb_gather_5_s32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, 5)) + +/* +** ldff1sb_gather_31_s32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_31_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, 31), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, 31)) + +/* +** ldff1sb_gather_32_s32_offset: +** mov (x[0-9]+), #?32 +** ldff1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_32_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_s32 (p0, z0, 32), + z0_res = svldff1sb_gather_offset_s32 (p0, z0, 32)) + +/* +** ldff1sb_gather_x0_s32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_s32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_s32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_s32_s32offset, svint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_s32 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1sb_gather_x0_s32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_s32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_s32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_s32_u32offset, svint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_s32 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s64.c new file mode 100644 index 00000000000..31f2bc5020e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_s64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_gather_s64_tied1: +** ldff1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_s64 (p0, z0), + z0_res = svldff1sb_gather_s64 (p0, z0)) + +/* +** ldff1sb_gather_s64_untied: +** ldff1sb z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_s64 (p0, z1), + z0_res = svldff1sb_gather_s64 (p0, z1)) + +/* +** ldff1sb_gather_x0_s64_offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1sb_gather_m1_s64_offset: +** mov (x[0-9]+), #?-1 +** ldff1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_m1_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, -1), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, -1)) + +/* +** ldff1sb_gather_0_s64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1sb_gather_5_s64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1sb_gather_31_s64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_31_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, 31), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, 31)) + +/* +** ldff1sb_gather_32_s64_offset: +** mov (x[0-9]+), #?32 +** ldff1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_32_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_s64 (p0, z0, 32), + z0_res = svldff1sb_gather_offset_s64 (p0, z0, 32)) + +/* +** ldff1sb_gather_x0_s64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_s64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_s64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sb_gather_ext_s64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_ext_s64_s64offset, svint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sb_gather_x0_s64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_s64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_s64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sb_gather_ext_s64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_ext_s64_u64offset, svint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sb_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u32.c new file mode 100644 index 00000000000..975050f0579 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_gather_u32_tied1: +** ldff1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_u32 (p0, z0), + z0_res = svldff1sb_gather_u32 (p0, z0)) + +/* +** ldff1sb_gather_u32_untied: +** ldff1sb z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_u32 (p0, z1), + z0_res = svldff1sb_gather_u32 (p0, z1)) + +/* +** ldff1sb_gather_x0_u32_offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, x0)) + +/* +** ldff1sb_gather_m1_u32_offset: +** mov (x[0-9]+), #?-1 +** ldff1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_m1_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, -1), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, -1)) + +/* +** ldff1sb_gather_0_u32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, 0)) + +/* +** ldff1sb_gather_5_u32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, 5)) + +/* +** ldff1sb_gather_31_u32_offset: +** ldff1sb z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_31_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, 31), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, 31)) + +/* +** ldff1sb_gather_32_u32_offset: +** mov (x[0-9]+), #?32 +** ldff1sb z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_32_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sb_gather_u32base_offset_u32 (p0, z0, 32), + z0_res = svldff1sb_gather_offset_u32 (p0, z0, 32)) + +/* +** ldff1sb_gather_x0_u32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_u32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_u32_s32offset: +** ldff1sb z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_u32_s32offset, svuint32_t, int8_t, svint32_t, + z0_res = svldff1sb_gather_s32offset_u32 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1sb_gather_x0_u32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_u32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_u32_u32offset: +** ldff1sb z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_u32_u32offset, svuint32_t, int8_t, svuint32_t, + z0_res = svldff1sb_gather_u32offset_u32 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u64.c new file mode 100644 index 00000000000..834828b4ed7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_gather_u64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_gather_u64_tied1: +** ldff1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_u64 (p0, z0), + z0_res = svldff1sb_gather_u64 (p0, z0)) + +/* +** ldff1sb_gather_u64_untied: +** ldff1sb z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_u64 (p0, z1), + z0_res = svldff1sb_gather_u64 (p0, z1)) + +/* +** ldff1sb_gather_x0_u64_offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1sb_gather_m1_u64_offset: +** mov (x[0-9]+), #?-1 +** ldff1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_m1_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, -1), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, -1)) + +/* +** ldff1sb_gather_0_u64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1sb_gather_5_u64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1sb_gather_31_u64_offset: +** ldff1sb z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_31_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, 31), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, 31)) + +/* +** ldff1sb_gather_32_u64_offset: +** mov (x[0-9]+), #?32 +** ldff1sb z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sb_gather_32_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sb_gather_u64base_offset_u64 (p0, z0, 32), + z0_res = svldff1sb_gather_offset_u64 (p0, z0, 32)) + +/* +** ldff1sb_gather_x0_u64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_u64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_u64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sb_gather_ext_u64_s64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_ext_u64_s64offset, svuint64_t, int8_t, svint64_t, + z0_res = svldff1sb_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sb_gather_x0_u64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_x0_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sb_gather_tied1_u64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_tied1_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sb_gather_untied_u64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_untied_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sb_gather_ext_u64_u64offset: +** ldff1sb z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sb_gather_ext_u64_u64offset, svuint64_t, int8_t, svuint64_t, + z0_res = svldff1sb_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sb_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s16.c new file mode 100644 index 00000000000..6456709afb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s16.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_s16_base: +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s16_base, svint16_t, int8_t, + z0 = svldff1sb_s16 (p0, x0), + z0 = svldff1sb_s16 (p0, x0)) + +/* +** ldff1sb_s16_index: +** ldff1sb z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_s16_index, svint16_t, int8_t, + z0 = svldff1sb_s16 (p0, x0 + x1), + z0 = svldff1sb_s16 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s16_1: +** inch x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s16_1, svint16_t, int8_t, + z0 = svldff1sb_s16 (p0, x0 + svcnth ()), + z0 = svldff1sb_s16 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s16_m1: +** dech x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s16_m1, svint16_t, int8_t, + z0 = svldff1sb_s16 (p0, x0 - svcnth ()), + z0 = svldff1sb_s16 (p0, x0 - svcnth ())) + +/* +** ldff1sb_vnum_s16_0: +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s16_0, svint16_t, int8_t, + z0 = svldff1sb_vnum_s16 (p0, x0, 0), + z0 = svldff1sb_vnum_s16 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s16_1: +** inch x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s16_1, svint16_t, int8_t, + z0 = svldff1sb_vnum_s16 (p0, x0, 1), + z0 = svldff1sb_vnum_s16 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s16_m1: +** dech x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s16_m1, svint16_t, int8_t, + z0 = svldff1sb_vnum_s16 (p0, x0, -1), + z0 = svldff1sb_vnum_s16 (p0, x0, -1)) + +/* +** ldff1sb_vnum_s16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s16_x1, svint16_t, int8_t, + z0 = svldff1sb_vnum_s16 (p0, x0, x1), + z0 = svldff1sb_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s32.c new file mode 100644 index 00000000000..53a6ad20e95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s32.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_s32_base: +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s32_base, svint32_t, int8_t, + z0 = svldff1sb_s32 (p0, x0), + z0 = svldff1sb_s32 (p0, x0)) + +/* +** ldff1sb_s32_index: +** ldff1sb z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_s32_index, svint32_t, int8_t, + z0 = svldff1sb_s32 (p0, x0 + x1), + z0 = svldff1sb_s32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s32_1: +** incw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s32_1, svint32_t, int8_t, + z0 = svldff1sb_s32 (p0, x0 + svcntw ()), + z0 = svldff1sb_s32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s32_m1: +** decw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s32_m1, svint32_t, int8_t, + z0 = svldff1sb_s32 (p0, x0 - svcntw ()), + z0 = svldff1sb_s32 (p0, x0 - svcntw ())) + +/* +** ldff1sb_vnum_s32_0: +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s32_0, svint32_t, int8_t, + z0 = svldff1sb_vnum_s32 (p0, x0, 0), + z0 = svldff1sb_vnum_s32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s32_1: +** incw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s32_1, svint32_t, int8_t, + z0 = svldff1sb_vnum_s32 (p0, x0, 1), + z0 = svldff1sb_vnum_s32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s32_m1: +** decw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s32_m1, svint32_t, int8_t, + z0 = svldff1sb_vnum_s32 (p0, x0, -1), + z0 = svldff1sb_vnum_s32 (p0, x0, -1)) + +/* +** ldff1sb_vnum_s32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s32_x1, svint32_t, int8_t, + z0 = svldff1sb_vnum_s32 (p0, x0, x1), + z0 = svldff1sb_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s64.c new file mode 100644 index 00000000000..9c86e50352c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_s64.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_s64_base: +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s64_base, svint64_t, int8_t, + z0 = svldff1sb_s64 (p0, x0), + z0 = svldff1sb_s64 (p0, x0)) + +/* +** ldff1sb_s64_index: +** ldff1sb z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_s64_index, svint64_t, int8_t, + z0 = svldff1sb_s64 (p0, x0 + x1), + z0 = svldff1sb_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s64_1: +** incd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s64_1, svint64_t, int8_t, + z0 = svldff1sb_s64 (p0, x0 + svcntd ()), + z0 = svldff1sb_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_s64_m1: +** decd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_s64_m1, svint64_t, int8_t, + z0 = svldff1sb_s64 (p0, x0 - svcntd ()), + z0 = svldff1sb_s64 (p0, x0 - svcntd ())) + +/* +** ldff1sb_vnum_s64_0: +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s64_0, svint64_t, int8_t, + z0 = svldff1sb_vnum_s64 (p0, x0, 0), + z0 = svldff1sb_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s64_1: +** incd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s64_1, svint64_t, int8_t, + z0 = svldff1sb_vnum_s64 (p0, x0, 1), + z0 = svldff1sb_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_s64_m1: +** decd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s64_m1, svint64_t, int8_t, + z0 = svldff1sb_vnum_s64 (p0, x0, -1), + z0 = svldff1sb_vnum_s64 (p0, x0, -1)) + +/* +** ldff1sb_vnum_s64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_s64_x1, svint64_t, int8_t, + z0 = svldff1sb_vnum_s64 (p0, x0, x1), + z0 = svldff1sb_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u16.c new file mode 100644 index 00000000000..3854988c4d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u16.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_u16_base: +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u16_base, svuint16_t, int8_t, + z0 = svldff1sb_u16 (p0, x0), + z0 = svldff1sb_u16 (p0, x0)) + +/* +** ldff1sb_u16_index: +** ldff1sb z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_u16_index, svuint16_t, int8_t, + z0 = svldff1sb_u16 (p0, x0 + x1), + z0 = svldff1sb_u16 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u16_1: +** inch x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u16_1, svuint16_t, int8_t, + z0 = svldff1sb_u16 (p0, x0 + svcnth ()), + z0 = svldff1sb_u16 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u16_m1: +** dech x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u16_m1, svuint16_t, int8_t, + z0 = svldff1sb_u16 (p0, x0 - svcnth ()), + z0 = svldff1sb_u16 (p0, x0 - svcnth ())) + +/* +** ldff1sb_vnum_u16_0: +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u16_0, svuint16_t, int8_t, + z0 = svldff1sb_vnum_u16 (p0, x0, 0), + z0 = svldff1sb_vnum_u16 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u16_1: +** inch x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u16_1, svuint16_t, int8_t, + z0 = svldff1sb_vnum_u16 (p0, x0, 1), + z0 = svldff1sb_vnum_u16 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u16_m1: +** dech x0 +** ldff1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u16_m1, svuint16_t, int8_t, + z0 = svldff1sb_vnum_u16 (p0, x0, -1), + z0 = svldff1sb_vnum_u16 (p0, x0, -1)) + +/* +** ldff1sb_vnum_u16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u16_x1, svuint16_t, int8_t, + z0 = svldff1sb_vnum_u16 (p0, x0, x1), + z0 = svldff1sb_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u32.c new file mode 100644 index 00000000000..1f4a4bf2aca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u32.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_u32_base: +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u32_base, svuint32_t, int8_t, + z0 = svldff1sb_u32 (p0, x0), + z0 = svldff1sb_u32 (p0, x0)) + +/* +** ldff1sb_u32_index: +** ldff1sb z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_u32_index, svuint32_t, int8_t, + z0 = svldff1sb_u32 (p0, x0 + x1), + z0 = svldff1sb_u32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u32_1: +** incw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u32_1, svuint32_t, int8_t, + z0 = svldff1sb_u32 (p0, x0 + svcntw ()), + z0 = svldff1sb_u32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u32_m1: +** decw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u32_m1, svuint32_t, int8_t, + z0 = svldff1sb_u32 (p0, x0 - svcntw ()), + z0 = svldff1sb_u32 (p0, x0 - svcntw ())) + +/* +** ldff1sb_vnum_u32_0: +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u32_0, svuint32_t, int8_t, + z0 = svldff1sb_vnum_u32 (p0, x0, 0), + z0 = svldff1sb_vnum_u32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u32_1: +** incw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u32_1, svuint32_t, int8_t, + z0 = svldff1sb_vnum_u32 (p0, x0, 1), + z0 = svldff1sb_vnum_u32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u32_m1: +** decw x0 +** ldff1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u32_m1, svuint32_t, int8_t, + z0 = svldff1sb_vnum_u32 (p0, x0, -1), + z0 = svldff1sb_vnum_u32 (p0, x0, -1)) + +/* +** ldff1sb_vnum_u32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u32_x1, svuint32_t, int8_t, + z0 = svldff1sb_vnum_u32 (p0, x0, x1), + z0 = svldff1sb_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u64.c new file mode 100644 index 00000000000..d877580d604 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sb_u64.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sb_u64_base: +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u64_base, svuint64_t, int8_t, + z0 = svldff1sb_u64 (p0, x0), + z0 = svldff1sb_u64 (p0, x0)) + +/* +** ldff1sb_u64_index: +** ldff1sb z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1sb_u64_index, svuint64_t, int8_t, + z0 = svldff1sb_u64 (p0, x0 + x1), + z0 = svldff1sb_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u64_1: +** incd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u64_1, svuint64_t, int8_t, + z0 = svldff1sb_u64 (p0, x0 + svcntd ()), + z0 = svldff1sb_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_u64_m1: +** decd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_u64_m1, svuint64_t, int8_t, + z0 = svldff1sb_u64 (p0, x0 - svcntd ()), + z0 = svldff1sb_u64 (p0, x0 - svcntd ())) + +/* +** ldff1sb_vnum_u64_0: +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u64_0, svuint64_t, int8_t, + z0 = svldff1sb_vnum_u64 (p0, x0, 0), + z0 = svldff1sb_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u64_1: +** incd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u64_1, svuint64_t, int8_t, + z0 = svldff1sb_vnum_u64 (p0, x0, 1), + z0 = svldff1sb_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sb_vnum_u64_m1: +** decd x0 +** ldff1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u64_m1, svuint64_t, int8_t, + z0 = svldff1sb_vnum_u64 (p0, x0, -1), + z0 = svldff1sb_vnum_u64 (p0, x0, -1)) + +/* +** ldff1sb_vnum_u64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1sb z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1sb z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1sb_vnum_u64_x1, svuint64_t, int8_t, + z0 = svldff1sb_vnum_u64 (p0, x0, x1), + z0 = svldff1sb_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s32.c new file mode 100644 index 00000000000..180a7854362 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_gather_s32_tied1: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_s32 (p0, z0), + z0_res = svldff1sh_gather_s32 (p0, z0)) + +/* +** ldff1sh_gather_s32_untied: +** ldff1sh z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_s32 (p0, z1), + z0_res = svldff1sh_gather_s32 (p0, z1)) + +/* +** ldff1sh_gather_x0_s32_offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, x0)) + +/* +** ldff1sh_gather_m2_s32_offset: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m2_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, -2), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, -2)) + +/* +** ldff1sh_gather_0_s32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, 5)) + +/* +** ldff1sh_gather_6_s32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, 6)) + +/* +** ldff1sh_gather_62_s32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_62_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, 62), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, 62)) + +/* +** ldff1sh_gather_64_s32_offset: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_64_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_s32 (p0, z0, 64), + z0_res = svldff1sh_gather_offset_s32 (p0, z0, 64)) + +/* +** ldff1sh_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svldff1sh_gather_index_s32 (p0, z0, x0)) + +/* +** ldff1sh_gather_m1_s32_index: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svldff1sh_gather_index_s32 (p0, z0, -1)) + +/* +** ldff1sh_gather_0_s32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svldff1sh_gather_index_s32 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_s32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svldff1sh_gather_index_s32 (p0, z0, 5)) + +/* +** ldff1sh_gather_31_s32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svldff1sh_gather_index_s32 (p0, z0, 31)) + +/* +** ldff1sh_gather_32_s32_index: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svldff1sh_gather_index_s32 (p0, z0, 32)) + +/* +** ldff1sh_gather_x0_s32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s32_s32offset, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_s32 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_s32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s32_u32offset, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_s32 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_s32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s32_s32index, svint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_s32 (p0, x0, z1), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_s32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s32_u32index, svint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_s32 (p0, x0, z1), + z0_res = svldff1sh_gather_index_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s64.c new file mode 100644 index 00000000000..e41b45e30ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_s64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_gather_s64_tied1: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_s64 (p0, z0), + z0_res = svldff1sh_gather_s64 (p0, z0)) + +/* +** ldff1sh_gather_s64_untied: +** ldff1sh z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_s64 (p0, z1), + z0_res = svldff1sh_gather_s64 (p0, z1)) + +/* +** ldff1sh_gather_x0_s64_offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1sh_gather_m2_s64_offset: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m2_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, -2), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, -2)) + +/* +** ldff1sh_gather_0_s64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1sh_gather_6_s64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, 6)) + +/* +** ldff1sh_gather_62_s64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_62_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, 62), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, 62)) + +/* +** ldff1sh_gather_64_s64_offset: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_64_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_s64 (p0, z0, 64), + z0_res = svldff1sh_gather_offset_s64 (p0, z0, 64)) + +/* +** ldff1sh_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svldff1sh_gather_index_s64 (p0, z0, x0)) + +/* +** ldff1sh_gather_m1_s64_index: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svldff1sh_gather_index_s64 (p0, z0, -1)) + +/* +** ldff1sh_gather_0_s64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svldff1sh_gather_index_s64 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_s64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svldff1sh_gather_index_s64 (p0, z0, 5)) + +/* +** ldff1sh_gather_31_s64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svldff1sh_gather_index_s64 (p0, z0, 31)) + +/* +** ldff1sh_gather_32_s64_index: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svldff1sh_gather_index_s64 (p0, z0, 32)) + +/* +** ldff1sh_gather_x0_s64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_s64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_s64_s64offset, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_s64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_s64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_s64_u64offset, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_s64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_s64 (p0, x0, z1), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_s64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_s64_s64index, svint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_s64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_s64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_s64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_s64 (p0, x0, z1), + z0_res = svldff1sh_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_s64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_s64_u64index, svint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u32.c new file mode 100644 index 00000000000..4714ceac325 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_gather_u32_tied1: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_u32 (p0, z0), + z0_res = svldff1sh_gather_u32 (p0, z0)) + +/* +** ldff1sh_gather_u32_untied: +** ldff1sh z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_u32 (p0, z1), + z0_res = svldff1sh_gather_u32 (p0, z1)) + +/* +** ldff1sh_gather_x0_u32_offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, x0)) + +/* +** ldff1sh_gather_m2_u32_offset: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m2_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, -2), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, -2)) + +/* +** ldff1sh_gather_0_u32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, 5)) + +/* +** ldff1sh_gather_6_u32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, 6)) + +/* +** ldff1sh_gather_62_u32_offset: +** ldff1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_62_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, 62), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, 62)) + +/* +** ldff1sh_gather_64_u32_offset: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_64_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_offset_u32 (p0, z0, 64), + z0_res = svldff1sh_gather_offset_u32 (p0, z0, 64)) + +/* +** ldff1sh_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svldff1sh_gather_index_u32 (p0, z0, x0)) + +/* +** ldff1sh_gather_m1_u32_index: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svldff1sh_gather_index_u32 (p0, z0, -1)) + +/* +** ldff1sh_gather_0_u32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svldff1sh_gather_index_u32 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_u32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svldff1sh_gather_index_u32 (p0, z0, 5)) + +/* +** ldff1sh_gather_31_u32_index: +** ldff1sh z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svldff1sh_gather_index_u32 (p0, z0, 31)) + +/* +** ldff1sh_gather_32_u32_index: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1sh_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svldff1sh_gather_index_u32 (p0, z0, 32)) + +/* +** ldff1sh_gather_x0_u32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u32_s32offset: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u32_s32offset, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32offset_u32 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_u32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u32_u32offset: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u32_u32offset, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32offset_u32 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_u32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u32_s32index: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u32_s32index, svuint32_t, int16_t, svint32_t, + z0_res = svldff1sh_gather_s32index_u32 (p0, x0, z1), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z1)) + +/* +** ldff1sh_gather_x0_u32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u32_u32index: +** ldff1sh z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u32_u32index, svuint32_t, int16_t, svuint32_t, + z0_res = svldff1sh_gather_u32index_u32 (p0, x0, z1), + z0_res = svldff1sh_gather_index_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u64.c new file mode 100644 index 00000000000..bd695563b93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_gather_u64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_gather_u64_tied1: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_u64 (p0, z0), + z0_res = svldff1sh_gather_u64 (p0, z0)) + +/* +** ldff1sh_gather_u64_untied: +** ldff1sh z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_u64 (p0, z1), + z0_res = svldff1sh_gather_u64 (p0, z1)) + +/* +** ldff1sh_gather_x0_u64_offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1sh_gather_m2_u64_offset: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m2_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, -2), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, -2)) + +/* +** ldff1sh_gather_0_u64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1sh_gather_6_u64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, 6)) + +/* +** ldff1sh_gather_62_u64_offset: +** ldff1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_62_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, 62), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, 62)) + +/* +** ldff1sh_gather_64_u64_offset: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_64_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_offset_u64 (p0, z0, 64), + z0_res = svldff1sh_gather_offset_u64 (p0, z0, 64)) + +/* +** ldff1sh_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svldff1sh_gather_index_u64 (p0, z0, x0)) + +/* +** ldff1sh_gather_m1_u64_index: +** mov (x[0-9]+), #?-2 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svldff1sh_gather_index_u64 (p0, z0, -1)) + +/* +** ldff1sh_gather_0_u64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svldff1sh_gather_index_u64 (p0, z0, 0)) + +/* +** ldff1sh_gather_5_u64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svldff1sh_gather_index_u64 (p0, z0, 5)) + +/* +** ldff1sh_gather_31_u64_index: +** ldff1sh z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svldff1sh_gather_index_u64 (p0, z0, 31)) + +/* +** ldff1sh_gather_32_u64_index: +** mov (x[0-9]+), #?64 +** ldff1sh z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sh_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sh_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svldff1sh_gather_index_u64 (p0, z0, 32)) + +/* +** ldff1sh_gather_x0_u64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_u64_s64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_u64_s64offset, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_u64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_u64_u64offset: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_u64_u64offset, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_u64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_u64 (p0, x0, z1), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_u64_s64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_u64_s64index, svuint64_t, int16_t, svint64_t, + z0_res = svldff1sh_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sh_gather_x0_u64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_x0_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_tied1_u64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_tied1_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sh_gather_untied_u64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_untied_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_u64 (p0, x0, z1), + z0_res = svldff1sh_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1sh_gather_ext_u64_u64index: +** ldff1sh z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sh_gather_ext_u64_u64index, svuint64_t, int16_t, svuint64_t, + z0_res = svldff1sh_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s32.c new file mode 100644 index 00000000000..8cba05e2965 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_s32_base: +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s32_base, svint32_t, int16_t, + z0 = svldff1sh_s32 (p0, x0), + z0 = svldff1sh_s32 (p0, x0)) + +/* +** ldff1sh_s32_index: +** ldff1sh z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1sh_s32_index, svint32_t, int16_t, + z0 = svldff1sh_s32 (p0, x0 + x1), + z0 = svldff1sh_s32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_s32_1: +** inch x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s32_1, svint32_t, int16_t, + z0 = svldff1sh_s32 (p0, x0 + svcntw ()), + z0 = svldff1sh_s32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_s32_m1: +** dech x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s32_m1, svint32_t, int16_t, + z0 = svldff1sh_s32 (p0, x0 - svcntw ()), + z0 = svldff1sh_s32 (p0, x0 - svcntw ())) + +/* +** ldff1sh_vnum_s32_0: +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s32_0, svint32_t, int16_t, + z0 = svldff1sh_vnum_s32 (p0, x0, 0), + z0 = svldff1sh_vnum_s32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_s32_1: +** inch x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s32_1, svint32_t, int16_t, + z0 = svldff1sh_vnum_s32 (p0, x0, 1), + z0 = svldff1sh_vnum_s32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_s32_m1: +** dech x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s32_m1, svint32_t, int16_t, + z0 = svldff1sh_vnum_s32 (p0, x0, -1), + z0 = svldff1sh_vnum_s32 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s32_x1, svint32_t, int16_t, + z0 = svldff1sh_vnum_s32 (p0, x0, x1), + z0 = svldff1sh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s64.c new file mode 100644 index 00000000000..86a67c4e076 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_s64_base: +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s64_base, svint64_t, int16_t, + z0 = svldff1sh_s64 (p0, x0), + z0 = svldff1sh_s64 (p0, x0)) + +/* +** ldff1sh_s64_index: +** ldff1sh z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1sh_s64_index, svint64_t, int16_t, + z0 = svldff1sh_s64 (p0, x0 + x1), + z0 = svldff1sh_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_s64_1: +** incw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s64_1, svint64_t, int16_t, + z0 = svldff1sh_s64 (p0, x0 + svcntd ()), + z0 = svldff1sh_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_s64_m1: +** decw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_s64_m1, svint64_t, int16_t, + z0 = svldff1sh_s64 (p0, x0 - svcntd ()), + z0 = svldff1sh_s64 (p0, x0 - svcntd ())) + +/* +** ldff1sh_vnum_s64_0: +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s64_0, svint64_t, int16_t, + z0 = svldff1sh_vnum_s64 (p0, x0, 0), + z0 = svldff1sh_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_s64_1: +** incw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s64_1, svint64_t, int16_t, + z0 = svldff1sh_vnum_s64 (p0, x0, 1), + z0 = svldff1sh_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_s64_m1: +** decw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s64_m1, svint64_t, int16_t, + z0 = svldff1sh_vnum_s64 (p0, x0, -1), + z0 = svldff1sh_vnum_s64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_s64_x1, svint64_t, int16_t, + z0 = svldff1sh_vnum_s64 (p0, x0, x1), + z0 = svldff1sh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u32.c new file mode 100644 index 00000000000..cb20cdb19d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_u32_base: +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u32_base, svuint32_t, int16_t, + z0 = svldff1sh_u32 (p0, x0), + z0 = svldff1sh_u32 (p0, x0)) + +/* +** ldff1sh_u32_index: +** ldff1sh z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1sh_u32_index, svuint32_t, int16_t, + z0 = svldff1sh_u32 (p0, x0 + x1), + z0 = svldff1sh_u32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_u32_1: +** inch x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u32_1, svuint32_t, int16_t, + z0 = svldff1sh_u32 (p0, x0 + svcntw ()), + z0 = svldff1sh_u32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_u32_m1: +** dech x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u32_m1, svuint32_t, int16_t, + z0 = svldff1sh_u32 (p0, x0 - svcntw ()), + z0 = svldff1sh_u32 (p0, x0 - svcntw ())) + +/* +** ldff1sh_vnum_u32_0: +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u32_0, svuint32_t, int16_t, + z0 = svldff1sh_vnum_u32 (p0, x0, 0), + z0 = svldff1sh_vnum_u32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_u32_1: +** inch x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u32_1, svuint32_t, int16_t, + z0 = svldff1sh_vnum_u32 (p0, x0, 1), + z0 = svldff1sh_vnum_u32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_u32_m1: +** dech x0 +** ldff1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u32_m1, svuint32_t, int16_t, + z0 = svldff1sh_vnum_u32 (p0, x0, -1), + z0 = svldff1sh_vnum_u32 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u32_x1, svuint32_t, int16_t, + z0 = svldff1sh_vnum_u32 (p0, x0, x1), + z0 = svldff1sh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u64.c new file mode 100644 index 00000000000..84ca6e56dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sh_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sh_u64_base: +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u64_base, svuint64_t, int16_t, + z0 = svldff1sh_u64 (p0, x0), + z0 = svldff1sh_u64 (p0, x0)) + +/* +** ldff1sh_u64_index: +** ldff1sh z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1sh_u64_index, svuint64_t, int16_t, + z0 = svldff1sh_u64 (p0, x0 + x1), + z0 = svldff1sh_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_u64_1: +** incw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u64_1, svuint64_t, int16_t, + z0 = svldff1sh_u64 (p0, x0 + svcntd ()), + z0 = svldff1sh_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_u64_m1: +** decw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_u64_m1, svuint64_t, int16_t, + z0 = svldff1sh_u64 (p0, x0 - svcntd ()), + z0 = svldff1sh_u64 (p0, x0 - svcntd ())) + +/* +** ldff1sh_vnum_u64_0: +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u64_0, svuint64_t, int16_t, + z0 = svldff1sh_vnum_u64 (p0, x0, 0), + z0 = svldff1sh_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_u64_1: +** incw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u64_1, svuint64_t, int16_t, + z0 = svldff1sh_vnum_u64 (p0, x0, 1), + z0 = svldff1sh_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sh_vnum_u64_m1: +** decw x0 +** ldff1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u64_m1, svuint64_t, int16_t, + z0 = svldff1sh_vnum_u64 (p0, x0, -1), + z0 = svldff1sh_vnum_u64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sh_vnum_u64_x1, svuint64_t, int16_t, + z0 = svldff1sh_vnum_u64 (p0, x0, x1), + z0 = svldff1sh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_s64.c new file mode 100644 index 00000000000..73e8747a72c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_s64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sw_gather_s64_tied1: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_s64 (p0, z0), + z0_res = svldff1sw_gather_s64 (p0, z0)) + +/* +** ldff1sw_gather_s64_untied: +** ldff1sw z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_s64 (p0, z1), + z0_res = svldff1sw_gather_s64 (p0, z1)) + +/* +** ldff1sw_gather_x0_s64_offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1sw_gather_m4_s64_offset: +** mov (x[0-9]+), #?-4 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_m4_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, -4), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, -4)) + +/* +** ldff1sw_gather_0_s64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1sw_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1sw_gather_6_s64_offset: +** mov (x[0-9]+), #?6 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 6)) + +/* +** ldff1sw_gather_7_s64_offset: +** mov (x[0-9]+), #?7 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_7_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 7), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 7)) + +/* +** ldff1sw_gather_8_s64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_8_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 8), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 8)) + +/* +** ldff1sw_gather_124_s64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_124_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 124), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 124)) + +/* +** ldff1sw_gather_128_s64_offset: +** mov (x[0-9]+), #?128 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_128_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_s64 (p0, z0, 128), + z0_res = svldff1sw_gather_offset_s64 (p0, z0, 128)) + +/* +** ldff1sw_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svldff1sw_gather_index_s64 (p0, z0, x0)) + +/* +** ldff1sw_gather_m1_s64_index: +** mov (x[0-9]+), #?-4 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svldff1sw_gather_index_s64 (p0, z0, -1)) + +/* +** ldff1sw_gather_0_s64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svldff1sw_gather_index_s64 (p0, z0, 0)) + +/* +** ldff1sw_gather_5_s64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svldff1sw_gather_index_s64 (p0, z0, 5)) + +/* +** ldff1sw_gather_31_s64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svldff1sw_gather_index_s64 (p0, z0, 31)) + +/* +** ldff1sw_gather_32_s64_index: +** mov (x[0-9]+), #?128 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svldff1sw_gather_index_s64 (p0, z0, 32)) + +/* +** ldff1sw_gather_x0_s64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_s64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_s64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_s64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_s64_s64offset, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_s64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_s64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_s64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_s64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_s64_u64offset, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_s64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_s64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_s64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_s64 (p0, x0, z1), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_s64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_s64_s64index, svint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_s64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_s64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_s64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_s64 (p0, x0, z1), + z0_res = svldff1sw_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_s64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_s64_u64index, svint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_u64.c new file mode 100644 index 00000000000..86a90d6f824 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_gather_u64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sw_gather_u64_tied1: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_u64 (p0, z0), + z0_res = svldff1sw_gather_u64 (p0, z0)) + +/* +** ldff1sw_gather_u64_untied: +** ldff1sw z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_u64 (p0, z1), + z0_res = svldff1sw_gather_u64 (p0, z1)) + +/* +** ldff1sw_gather_x0_u64_offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1sw_gather_m4_u64_offset: +** mov (x[0-9]+), #?-4 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_m4_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, -4), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, -4)) + +/* +** ldff1sw_gather_0_u64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1sw_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1sw_gather_6_u64_offset: +** mov (x[0-9]+), #?6 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 6)) + +/* +** ldff1sw_gather_7_u64_offset: +** mov (x[0-9]+), #?7 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_7_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 7), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 7)) + +/* +** ldff1sw_gather_8_u64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_8_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 8), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 8)) + +/* +** ldff1sw_gather_124_u64_offset: +** ldff1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_124_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 124), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 124)) + +/* +** ldff1sw_gather_128_u64_offset: +** mov (x[0-9]+), #?128 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_128_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_offset_u64 (p0, z0, 128), + z0_res = svldff1sw_gather_offset_u64 (p0, z0, 128)) + +/* +** ldff1sw_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svldff1sw_gather_index_u64 (p0, z0, x0)) + +/* +** ldff1sw_gather_m1_u64_index: +** mov (x[0-9]+), #?-4 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svldff1sw_gather_index_u64 (p0, z0, -1)) + +/* +** ldff1sw_gather_0_u64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svldff1sw_gather_index_u64 (p0, z0, 0)) + +/* +** ldff1sw_gather_5_u64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svldff1sw_gather_index_u64 (p0, z0, 5)) + +/* +** ldff1sw_gather_31_u64_index: +** ldff1sw z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svldff1sw_gather_index_u64 (p0, z0, 31)) + +/* +** ldff1sw_gather_32_u64_index: +** mov (x[0-9]+), #?128 +** ldff1sw z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1sw_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1sw_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svldff1sw_gather_index_u64 (p0, z0, 32)) + +/* +** ldff1sw_gather_x0_u64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_u64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_u64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_u64_s64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_u64_s64offset, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_u64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_u64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_u64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_u64_u64offset: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_u64_u64offset, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_u64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_u64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_u64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_u64 (p0, x0, z1), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_u64_s64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_u64_s64index, svuint64_t, int32_t, svint64_t, + z0_res = svldff1sw_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1sw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1sw_gather_x0_u64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_x0_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_tied1_u64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_tied1_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1sw_gather_untied_u64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_untied_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_u64 (p0, x0, z1), + z0_res = svldff1sw_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1sw_gather_ext_u64_u64index: +** ldff1sw z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1sw_gather_ext_u64_u64index, svuint64_t, int32_t, svuint64_t, + z0_res = svldff1sw_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1sw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_s64.c new file mode 100644 index 00000000000..38158466488 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sw_s64_base: +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_s64_base, svint64_t, int32_t, + z0 = svldff1sw_s64 (p0, x0), + z0 = svldff1sw_s64 (p0, x0)) + +/* +** ldff1sw_s64_index: +** ldff1sw z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1sw_s64_index, svint64_t, int32_t, + z0 = svldff1sw_s64 (p0, x0 + x1), + z0 = svldff1sw_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_s64_1: +** inch x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_s64_1, svint64_t, int32_t, + z0 = svldff1sw_s64 (p0, x0 + svcntd ()), + z0 = svldff1sw_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_s64_m1: +** dech x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_s64_m1, svint64_t, int32_t, + z0 = svldff1sw_s64 (p0, x0 - svcntd ()), + z0 = svldff1sw_s64 (p0, x0 - svcntd ())) + +/* +** ldff1sw_vnum_s64_0: +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_s64_0, svint64_t, int32_t, + z0 = svldff1sw_vnum_s64 (p0, x0, 0), + z0 = svldff1sw_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_vnum_s64_1: +** inch x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_s64_1, svint64_t, int32_t, + z0 = svldff1sw_vnum_s64 (p0, x0, 1), + z0 = svldff1sw_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_vnum_s64_m1: +** dech x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_s64_m1, svint64_t, int32_t, + z0 = svldff1sw_vnum_s64 (p0, x0, -1), + z0 = svldff1sw_vnum_s64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_s64_x1, svint64_t, int32_t, + z0 = svldff1sw_vnum_s64 (p0, x0, x1), + z0 = svldff1sw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_u64.c new file mode 100644 index 00000000000..1644e10350e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1sw_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1sw_u64_base: +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_u64_base, svuint64_t, int32_t, + z0 = svldff1sw_u64 (p0, x0), + z0 = svldff1sw_u64 (p0, x0)) + +/* +** ldff1sw_u64_index: +** ldff1sw z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1sw_u64_index, svuint64_t, int32_t, + z0 = svldff1sw_u64 (p0, x0 + x1), + z0 = svldff1sw_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_u64_1: +** inch x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_u64_1, svuint64_t, int32_t, + z0 = svldff1sw_u64 (p0, x0 + svcntd ()), + z0 = svldff1sw_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_u64_m1: +** dech x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_u64_m1, svuint64_t, int32_t, + z0 = svldff1sw_u64 (p0, x0 - svcntd ()), + z0 = svldff1sw_u64 (p0, x0 - svcntd ())) + +/* +** ldff1sw_vnum_u64_0: +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_u64_0, svuint64_t, int32_t, + z0 = svldff1sw_vnum_u64 (p0, x0, 0), + z0 = svldff1sw_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_vnum_u64_1: +** inch x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_u64_1, svuint64_t, int32_t, + z0 = svldff1sw_vnum_u64 (p0, x0, 1), + z0 = svldff1sw_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1sw_vnum_u64_m1: +** dech x0 +** ldff1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_u64_m1, svuint64_t, int32_t, + z0 = svldff1sw_vnum_u64 (p0, x0, -1), + z0 = svldff1sw_vnum_u64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1sw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1sw_vnum_u64_x1, svuint64_t, int32_t, + z0 = svldff1sw_vnum_u64 (p0, x0, x1), + z0 = svldff1sw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s32.c new file mode 100644 index 00000000000..703adbd1f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_gather_s32_tied1: +** ldff1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_s32 (p0, z0), + z0_res = svldff1ub_gather_s32 (p0, z0)) + +/* +** ldff1ub_gather_s32_untied: +** ldff1b z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_s32 (p0, z1), + z0_res = svldff1ub_gather_s32 (p0, z1)) + +/* +** ldff1ub_gather_x0_s32_offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, x0)) + +/* +** ldff1ub_gather_m1_s32_offset: +** mov (x[0-9]+), #?-1 +** ldff1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_m1_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, -1), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, -1)) + +/* +** ldff1ub_gather_0_s32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, 0)) + +/* +** ldff1ub_gather_5_s32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, 5)) + +/* +** ldff1ub_gather_31_s32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_31_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, 31), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, 31)) + +/* +** ldff1ub_gather_32_s32_offset: +** mov (x[0-9]+), #?32 +** ldff1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_32_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_s32 (p0, z0, 32), + z0_res = svldff1ub_gather_offset_s32 (p0, z0, 32)) + +/* +** ldff1ub_gather_x0_s32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_s32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_s32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_s32_s32offset, svint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_s32 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1ub_gather_x0_s32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_s32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_s32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_s32_u32offset, svint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_s32 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s64.c new file mode 100644 index 00000000000..0820ff2bb2d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_s64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_gather_s64_tied1: +** ldff1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_s64 (p0, z0), + z0_res = svldff1ub_gather_s64 (p0, z0)) + +/* +** ldff1ub_gather_s64_untied: +** ldff1b z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_s64 (p0, z1), + z0_res = svldff1ub_gather_s64 (p0, z1)) + +/* +** ldff1ub_gather_x0_s64_offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1ub_gather_m1_s64_offset: +** mov (x[0-9]+), #?-1 +** ldff1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_m1_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, -1), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, -1)) + +/* +** ldff1ub_gather_0_s64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1ub_gather_5_s64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1ub_gather_31_s64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_31_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, 31), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, 31)) + +/* +** ldff1ub_gather_32_s64_offset: +** mov (x[0-9]+), #?32 +** ldff1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_32_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_s64 (p0, z0, 32), + z0_res = svldff1ub_gather_offset_s64 (p0, z0, 32)) + +/* +** ldff1ub_gather_x0_s64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_s64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_s64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1ub_gather_ext_s64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_ext_s64_s64offset, svint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1ub_gather_x0_s64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_s64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_s64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1ub_gather_ext_s64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_ext_s64_u64offset, svint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1ub_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u32.c new file mode 100644 index 00000000000..1efe9083397 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u32.c @@ -0,0 +1,131 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_gather_u32_tied1: +** ldff1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_u32 (p0, z0), + z0_res = svldff1ub_gather_u32 (p0, z0)) + +/* +** ldff1ub_gather_u32_untied: +** ldff1b z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_u32 (p0, z1), + z0_res = svldff1ub_gather_u32 (p0, z1)) + +/* +** ldff1ub_gather_x0_u32_offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, x0)) + +/* +** ldff1ub_gather_m1_u32_offset: +** mov (x[0-9]+), #?-1 +** ldff1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_m1_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, -1), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, -1)) + +/* +** ldff1ub_gather_0_u32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, 0)) + +/* +** ldff1ub_gather_5_u32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, 5)) + +/* +** ldff1ub_gather_31_u32_offset: +** ldff1b z0\.s, p0/z, \[z0\.s, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_31_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, 31), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, 31)) + +/* +** ldff1ub_gather_32_u32_offset: +** mov (x[0-9]+), #?32 +** ldff1b z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_32_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1ub_gather_u32base_offset_u32 (p0, z0, 32), + z0_res = svldff1ub_gather_offset_u32 (p0, z0, 32)) + +/* +** ldff1ub_gather_x0_u32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_u32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_u32_s32offset: +** ldff1b z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_u32_s32offset, svuint32_t, uint8_t, svint32_t, + z0_res = svldff1ub_gather_s32offset_u32 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1ub_gather_x0_u32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_u32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_u32_u32offset: +** ldff1b z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + z0_res = svldff1ub_gather_u32offset_u32 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u64.c new file mode 100644 index 00000000000..a29c7b8fb8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_gather_u64.c @@ -0,0 +1,149 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_gather_u64_tied1: +** ldff1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_u64 (p0, z0), + z0_res = svldff1ub_gather_u64 (p0, z0)) + +/* +** ldff1ub_gather_u64_untied: +** ldff1b z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_u64 (p0, z1), + z0_res = svldff1ub_gather_u64 (p0, z1)) + +/* +** ldff1ub_gather_x0_u64_offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1ub_gather_m1_u64_offset: +** mov (x[0-9]+), #?-1 +** ldff1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_m1_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, -1), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, -1)) + +/* +** ldff1ub_gather_0_u64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1ub_gather_5_u64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d, #5\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1ub_gather_31_u64_offset: +** ldff1b z0\.d, p0/z, \[z0\.d, #31\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_31_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, 31), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, 31)) + +/* +** ldff1ub_gather_32_u64_offset: +** mov (x[0-9]+), #?32 +** ldff1b z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1ub_gather_32_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1ub_gather_u64base_offset_u64 (p0, z0, 32), + z0_res = svldff1ub_gather_offset_u64 (p0, z0, 32)) + +/* +** ldff1ub_gather_x0_u64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_u64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_u64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1ub_gather_ext_u64_s64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_ext_u64_s64offset, svuint64_t, uint8_t, svint64_t, + z0_res = svldff1ub_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1ub_gather_x0_u64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_x0_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1ub_gather_tied1_u64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_tied1_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1ub_gather_untied_u64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_untied_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1ub_gather_ext_u64_u64offset: +** ldff1b z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1ub_gather_ext_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + z0_res = svldff1ub_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1ub_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s16.c new file mode 100644 index 00000000000..16a8b415cf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s16.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_s16_base: +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s16_base, svint16_t, uint8_t, + z0 = svldff1ub_s16 (p0, x0), + z0 = svldff1ub_s16 (p0, x0)) + +/* +** ldff1ub_s16_index: +** ldff1b z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_s16_index, svint16_t, uint8_t, + z0 = svldff1ub_s16 (p0, x0 + x1), + z0 = svldff1ub_s16 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s16_1: +** inch x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s16_1, svint16_t, uint8_t, + z0 = svldff1ub_s16 (p0, x0 + svcnth ()), + z0 = svldff1ub_s16 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s16_m1: +** dech x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s16_m1, svint16_t, uint8_t, + z0 = svldff1ub_s16 (p0, x0 - svcnth ()), + z0 = svldff1ub_s16 (p0, x0 - svcnth ())) + +/* +** ldff1ub_vnum_s16_0: +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s16_0, svint16_t, uint8_t, + z0 = svldff1ub_vnum_s16 (p0, x0, 0), + z0 = svldff1ub_vnum_s16 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s16_1: +** inch x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s16_1, svint16_t, uint8_t, + z0 = svldff1ub_vnum_s16 (p0, x0, 1), + z0 = svldff1ub_vnum_s16 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s16_m1: +** dech x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s16_m1, svint16_t, uint8_t, + z0 = svldff1ub_vnum_s16 (p0, x0, -1), + z0 = svldff1ub_vnum_s16 (p0, x0, -1)) + +/* +** ldff1ub_vnum_s16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s16_x1, svint16_t, uint8_t, + z0 = svldff1ub_vnum_s16 (p0, x0, x1), + z0 = svldff1ub_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s32.c new file mode 100644 index 00000000000..caf83429f4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s32.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_s32_base: +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s32_base, svint32_t, uint8_t, + z0 = svldff1ub_s32 (p0, x0), + z0 = svldff1ub_s32 (p0, x0)) + +/* +** ldff1ub_s32_index: +** ldff1b z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_s32_index, svint32_t, uint8_t, + z0 = svldff1ub_s32 (p0, x0 + x1), + z0 = svldff1ub_s32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s32_1: +** incw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s32_1, svint32_t, uint8_t, + z0 = svldff1ub_s32 (p0, x0 + svcntw ()), + z0 = svldff1ub_s32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s32_m1: +** decw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s32_m1, svint32_t, uint8_t, + z0 = svldff1ub_s32 (p0, x0 - svcntw ()), + z0 = svldff1ub_s32 (p0, x0 - svcntw ())) + +/* +** ldff1ub_vnum_s32_0: +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s32_0, svint32_t, uint8_t, + z0 = svldff1ub_vnum_s32 (p0, x0, 0), + z0 = svldff1ub_vnum_s32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s32_1: +** incw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s32_1, svint32_t, uint8_t, + z0 = svldff1ub_vnum_s32 (p0, x0, 1), + z0 = svldff1ub_vnum_s32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s32_m1: +** decw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s32_m1, svint32_t, uint8_t, + z0 = svldff1ub_vnum_s32 (p0, x0, -1), + z0 = svldff1ub_vnum_s32 (p0, x0, -1)) + +/* +** ldff1ub_vnum_s32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s32_x1, svint32_t, uint8_t, + z0 = svldff1ub_vnum_s32 (p0, x0, x1), + z0 = svldff1ub_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s64.c new file mode 100644 index 00000000000..72b0bc1ea5e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_s64.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_s64_base: +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s64_base, svint64_t, uint8_t, + z0 = svldff1ub_s64 (p0, x0), + z0 = svldff1ub_s64 (p0, x0)) + +/* +** ldff1ub_s64_index: +** ldff1b z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_s64_index, svint64_t, uint8_t, + z0 = svldff1ub_s64 (p0, x0 + x1), + z0 = svldff1ub_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s64_1: +** incd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s64_1, svint64_t, uint8_t, + z0 = svldff1ub_s64 (p0, x0 + svcntd ()), + z0 = svldff1ub_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_s64_m1: +** decd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_s64_m1, svint64_t, uint8_t, + z0 = svldff1ub_s64 (p0, x0 - svcntd ()), + z0 = svldff1ub_s64 (p0, x0 - svcntd ())) + +/* +** ldff1ub_vnum_s64_0: +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s64_0, svint64_t, uint8_t, + z0 = svldff1ub_vnum_s64 (p0, x0, 0), + z0 = svldff1ub_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s64_1: +** incd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s64_1, svint64_t, uint8_t, + z0 = svldff1ub_vnum_s64 (p0, x0, 1), + z0 = svldff1ub_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_s64_m1: +** decd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s64_m1, svint64_t, uint8_t, + z0 = svldff1ub_vnum_s64 (p0, x0, -1), + z0 = svldff1ub_vnum_s64 (p0, x0, -1)) + +/* +** ldff1ub_vnum_s64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_s64_x1, svint64_t, uint8_t, + z0 = svldff1ub_vnum_s64 (p0, x0, x1), + z0 = svldff1ub_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u16.c new file mode 100644 index 00000000000..134d79301c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u16.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_u16_base: +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u16_base, svuint16_t, uint8_t, + z0 = svldff1ub_u16 (p0, x0), + z0 = svldff1ub_u16 (p0, x0)) + +/* +** ldff1ub_u16_index: +** ldff1b z0\.h, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_u16_index, svuint16_t, uint8_t, + z0 = svldff1ub_u16 (p0, x0 + x1), + z0 = svldff1ub_u16 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u16_1: +** inch x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u16_1, svuint16_t, uint8_t, + z0 = svldff1ub_u16 (p0, x0 + svcnth ()), + z0 = svldff1ub_u16 (p0, x0 + svcnth ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u16_m1: +** dech x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u16_m1, svuint16_t, uint8_t, + z0 = svldff1ub_u16 (p0, x0 - svcnth ()), + z0 = svldff1ub_u16 (p0, x0 - svcnth ())) + +/* +** ldff1ub_vnum_u16_0: +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u16_0, svuint16_t, uint8_t, + z0 = svldff1ub_vnum_u16 (p0, x0, 0), + z0 = svldff1ub_vnum_u16 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u16_1: +** inch x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u16_1, svuint16_t, uint8_t, + z0 = svldff1ub_vnum_u16 (p0, x0, 1), + z0 = svldff1ub_vnum_u16 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u16_m1: +** dech x0 +** ldff1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u16_m1, svuint16_t, uint8_t, + z0 = svldff1ub_vnum_u16 (p0, x0, -1), + z0 = svldff1ub_vnum_u16 (p0, x0, -1)) + +/* +** ldff1ub_vnum_u16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.h, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.h, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u16_x1, svuint16_t, uint8_t, + z0 = svldff1ub_vnum_u16 (p0, x0, x1), + z0 = svldff1ub_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u32.c new file mode 100644 index 00000000000..73ab574b859 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u32.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_u32_base: +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u32_base, svuint32_t, uint8_t, + z0 = svldff1ub_u32 (p0, x0), + z0 = svldff1ub_u32 (p0, x0)) + +/* +** ldff1ub_u32_index: +** ldff1b z0\.s, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_u32_index, svuint32_t, uint8_t, + z0 = svldff1ub_u32 (p0, x0 + x1), + z0 = svldff1ub_u32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u32_1: +** incw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u32_1, svuint32_t, uint8_t, + z0 = svldff1ub_u32 (p0, x0 + svcntw ()), + z0 = svldff1ub_u32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u32_m1: +** decw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u32_m1, svuint32_t, uint8_t, + z0 = svldff1ub_u32 (p0, x0 - svcntw ()), + z0 = svldff1ub_u32 (p0, x0 - svcntw ())) + +/* +** ldff1ub_vnum_u32_0: +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u32_0, svuint32_t, uint8_t, + z0 = svldff1ub_vnum_u32 (p0, x0, 0), + z0 = svldff1ub_vnum_u32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u32_1: +** incw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u32_1, svuint32_t, uint8_t, + z0 = svldff1ub_vnum_u32 (p0, x0, 1), + z0 = svldff1ub_vnum_u32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u32_m1: +** decw x0 +** ldff1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u32_m1, svuint32_t, uint8_t, + z0 = svldff1ub_vnum_u32 (p0, x0, -1), + z0 = svldff1ub_vnum_u32 (p0, x0, -1)) + +/* +** ldff1ub_vnum_u32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.s, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.s, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u32_x1, svuint32_t, uint8_t, + z0 = svldff1ub_vnum_u32 (p0, x0, x1), + z0 = svldff1ub_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u64.c new file mode 100644 index 00000000000..985b601f1c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1ub_u64.c @@ -0,0 +1,90 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1ub_u64_base: +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u64_base, svuint64_t, uint8_t, + z0 = svldff1ub_u64 (p0, x0), + z0 = svldff1ub_u64 (p0, x0)) + +/* +** ldff1ub_u64_index: +** ldff1b z0\.d, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldff1ub_u64_index, svuint64_t, uint8_t, + z0 = svldff1ub_u64 (p0, x0 + x1), + z0 = svldff1ub_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u64_1: +** incd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u64_1, svuint64_t, uint8_t, + z0 = svldff1ub_u64 (p0, x0 + svcntd ()), + z0 = svldff1ub_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_u64_m1: +** decd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_u64_m1, svuint64_t, uint8_t, + z0 = svldff1ub_u64 (p0, x0 - svcntd ()), + z0 = svldff1ub_u64 (p0, x0 - svcntd ())) + +/* +** ldff1ub_vnum_u64_0: +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u64_0, svuint64_t, uint8_t, + z0 = svldff1ub_vnum_u64 (p0, x0, 0), + z0 = svldff1ub_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u64_1: +** incd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u64_1, svuint64_t, uint8_t, + z0 = svldff1ub_vnum_u64 (p0, x0, 1), + z0 = svldff1ub_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1ub_vnum_u64_m1: +** decd x0 +** ldff1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u64_m1, svuint64_t, uint8_t, + z0 = svldff1ub_vnum_u64 (p0, x0, -1), + z0 = svldff1ub_vnum_u64 (p0, x0, -1)) + +/* +** ldff1ub_vnum_u64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldff1b z0\.d, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldff1b z0\.d, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldff1ub_vnum_u64_x1, svuint64_t, uint8_t, + z0 = svldff1ub_vnum_u64 (p0, x0, x1), + z0 = svldff1ub_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s32.c new file mode 100644 index 00000000000..d2857934be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_gather_s32_tied1: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_s32_tied1, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_s32 (p0, z0), + z0_res = svldff1uh_gather_s32 (p0, z0)) + +/* +** ldff1uh_gather_s32_untied: +** ldff1h z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_s32_untied, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_s32 (p0, z1), + z0_res = svldff1uh_gather_s32 (p0, z1)) + +/* +** ldff1uh_gather_x0_s32_offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, x0), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, x0)) + +/* +** ldff1uh_gather_m2_s32_offset: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m2_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, -2), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, -2)) + +/* +** ldff1uh_gather_0_s32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, 0), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_s32_offset: +** mov (x[0-9]+), #?5 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, 5), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, 5)) + +/* +** ldff1uh_gather_6_s32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_6_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, 6), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, 6)) + +/* +** ldff1uh_gather_62_s32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_62_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, 62), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, 62)) + +/* +** ldff1uh_gather_64_s32_offset: +** mov (x[0-9]+), #?64 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_64_s32_offset, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_s32 (p0, z0, 64), + z0_res = svldff1uh_gather_offset_s32 (p0, z0, 64)) + +/* +** ldff1uh_gather_x0_s32_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, x0), + z0_res = svldff1uh_gather_index_s32 (p0, z0, x0)) + +/* +** ldff1uh_gather_m1_s32_index: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m1_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, -1), + z0_res = svldff1uh_gather_index_s32 (p0, z0, -1)) + +/* +** ldff1uh_gather_0_s32_index: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, 0), + z0_res = svldff1uh_gather_index_s32 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_s32_index: +** ldff1h z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, 5), + z0_res = svldff1uh_gather_index_s32 (p0, z0, 5)) + +/* +** ldff1uh_gather_31_s32_index: +** ldff1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_31_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, 31), + z0_res = svldff1uh_gather_index_s32 (p0, z0, 31)) + +/* +** ldff1uh_gather_32_s32_index: +** mov (x[0-9]+), #?64 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_32_s32_index, svint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_s32 (p0, z0, 32), + z0_res = svldff1uh_gather_index_s32 (p0, z0, 32)) + +/* +** ldff1uh_gather_x0_s32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s32_s32offset, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_s32 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_s32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s32_u32offset, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_s32 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_s32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_s32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s32_s32index, svint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_s32 (p0, x0, z1), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_s32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_s32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s32_u32index, svint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_s32 (p0, x0, z1), + z0_res = svldff1uh_gather_index_s32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s64.c new file mode 100644 index 00000000000..79aebb3a967 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_s64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_gather_s64_tied1: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_s64 (p0, z0), + z0_res = svldff1uh_gather_s64 (p0, z0)) + +/* +** ldff1uh_gather_s64_untied: +** ldff1h z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_s64 (p0, z1), + z0_res = svldff1uh_gather_s64 (p0, z1)) + +/* +** ldff1uh_gather_x0_s64_offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1uh_gather_m2_s64_offset: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m2_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, -2), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, -2)) + +/* +** ldff1uh_gather_0_s64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1uh_gather_6_s64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, 6)) + +/* +** ldff1uh_gather_62_s64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_62_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, 62), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, 62)) + +/* +** ldff1uh_gather_64_s64_offset: +** mov (x[0-9]+), #?64 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_64_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_s64 (p0, z0, 64), + z0_res = svldff1uh_gather_offset_s64 (p0, z0, 64)) + +/* +** ldff1uh_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svldff1uh_gather_index_s64 (p0, z0, x0)) + +/* +** ldff1uh_gather_m1_s64_index: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svldff1uh_gather_index_s64 (p0, z0, -1)) + +/* +** ldff1uh_gather_0_s64_index: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svldff1uh_gather_index_s64 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_s64_index: +** ldff1h z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svldff1uh_gather_index_s64 (p0, z0, 5)) + +/* +** ldff1uh_gather_31_s64_index: +** ldff1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svldff1uh_gather_index_s64 (p0, z0, 31)) + +/* +** ldff1uh_gather_32_s64_index: +** mov (x[0-9]+), #?64 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svldff1uh_gather_index_s64 (p0, z0, 32)) + +/* +** ldff1uh_gather_x0_s64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_s64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_s64_s64offset, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_s64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_s64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_s64_u64offset, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uh_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_s64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_s64 (p0, x0, z1), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_s64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_s64_s64index, svint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_s64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_s64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_s64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_s64 (p0, x0, z1), + z0_res = svldff1uh_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_s64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_s64_u64index, svint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uh_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u32.c new file mode 100644 index 00000000000..b6aa5b0e2a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u32.c @@ -0,0 +1,252 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_gather_u32_tied1: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_u32_tied1, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_u32 (p0, z0), + z0_res = svldff1uh_gather_u32 (p0, z0)) + +/* +** ldff1uh_gather_u32_untied: +** ldff1h z0\.s, p0/z, \[z1\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_u32_untied, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_u32 (p0, z1), + z0_res = svldff1uh_gather_u32 (p0, z1)) + +/* +** ldff1uh_gather_x0_u32_offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, x0), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, x0)) + +/* +** ldff1uh_gather_m2_u32_offset: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m2_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, -2), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, -2)) + +/* +** ldff1uh_gather_0_u32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, 0), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_u32_offset: +** mov (x[0-9]+), #?5 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, 5), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, 5)) + +/* +** ldff1uh_gather_6_u32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_6_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, 6), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, 6)) + +/* +** ldff1uh_gather_62_u32_offset: +** ldff1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_62_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, 62), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, 62)) + +/* +** ldff1uh_gather_64_u32_offset: +** mov (x[0-9]+), #?64 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_64_u32_offset, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_offset_u32 (p0, z0, 64), + z0_res = svldff1uh_gather_offset_u32 (p0, z0, 64)) + +/* +** ldff1uh_gather_x0_u32_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, x0), + z0_res = svldff1uh_gather_index_u32 (p0, z0, x0)) + +/* +** ldff1uh_gather_m1_u32_index: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m1_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, -1), + z0_res = svldff1uh_gather_index_u32 (p0, z0, -1)) + +/* +** ldff1uh_gather_0_u32_index: +** ldff1h z0\.s, p0/z, \[z0\.s\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, 0), + z0_res = svldff1uh_gather_index_u32 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_u32_index: +** ldff1h z0\.s, p0/z, \[z0\.s, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, 5), + z0_res = svldff1uh_gather_index_u32 (p0, z0, 5)) + +/* +** ldff1uh_gather_31_u32_index: +** ldff1h z0\.s, p0/z, \[z0\.s, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_31_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, 31), + z0_res = svldff1uh_gather_index_u32 (p0, z0, 31)) + +/* +** ldff1uh_gather_32_u32_index: +** mov (x[0-9]+), #?64 +** ldff1h z0\.s, p0/z, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_32_u32_index, svuint32_t, svuint32_t, + z0_res = svldff1uh_gather_u32base_index_u32 (p0, z0, 32), + z0_res = svldff1uh_gather_index_u32 (p0, z0, 32)) + +/* +** ldff1uh_gather_x0_u32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u32_s32offset: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u32_s32offset, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32offset_u32 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_u32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u32_u32offset: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32offset_u32 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_u32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_u32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u32_s32index: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u32_s32index, svuint32_t, uint16_t, svint32_t, + z0_res = svldff1uh_gather_s32index_u32 (p0, x0, z1), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z1)) + +/* +** ldff1uh_gather_x0_u32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_u32 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u32_u32index: +** ldff1h z0\.s, p0/z, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u32_u32index, svuint32_t, uint16_t, svuint32_t, + z0_res = svldff1uh_gather_u32index_u32 (p0, x0, z1), + z0_res = svldff1uh_gather_index_u32 (p0, x0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u64.c new file mode 100644 index 00000000000..1a5ab6fe7d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_gather_u64.c @@ -0,0 +1,288 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_gather_u64_tied1: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_u64 (p0, z0), + z0_res = svldff1uh_gather_u64 (p0, z0)) + +/* +** ldff1uh_gather_u64_untied: +** ldff1h z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_u64 (p0, z1), + z0_res = svldff1uh_gather_u64 (p0, z1)) + +/* +** ldff1uh_gather_x0_u64_offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1uh_gather_m2_u64_offset: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m2_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, -2), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, -2)) + +/* +** ldff1uh_gather_0_u64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1uh_gather_6_u64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d, #6\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, 6)) + +/* +** ldff1uh_gather_62_u64_offset: +** ldff1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_62_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, 62), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, 62)) + +/* +** ldff1uh_gather_64_u64_offset: +** mov (x[0-9]+), #?64 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_64_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_offset_u64 (p0, z0, 64), + z0_res = svldff1uh_gather_offset_u64 (p0, z0, 64)) + +/* +** ldff1uh_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?1 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svldff1uh_gather_index_u64 (p0, z0, x0)) + +/* +** ldff1uh_gather_m1_u64_index: +** mov (x[0-9]+), #?-2 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svldff1uh_gather_index_u64 (p0, z0, -1)) + +/* +** ldff1uh_gather_0_u64_index: +** ldff1h z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svldff1uh_gather_index_u64 (p0, z0, 0)) + +/* +** ldff1uh_gather_5_u64_index: +** ldff1h z0\.d, p0/z, \[z0\.d, #10\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svldff1uh_gather_index_u64 (p0, z0, 5)) + +/* +** ldff1uh_gather_31_u64_index: +** ldff1h z0\.d, p0/z, \[z0\.d, #62\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svldff1uh_gather_index_u64 (p0, z0, 31)) + +/* +** ldff1uh_gather_32_u64_index: +** mov (x[0-9]+), #?64 +** ldff1h z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uh_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uh_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svldff1uh_gather_index_u64 (p0, z0, 32)) + +/* +** ldff1uh_gather_x0_u64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_u64_s64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_u64_s64offset, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_u64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_u64_u64offset: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uh_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_u64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_u64 (p0, x0, z1), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_u64_s64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_u64_s64index, svuint64_t, uint16_t, svint64_t, + z0_res = svldff1uh_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uh_gather_x0_u64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_x0_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_tied1_u64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_tied1_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uh_gather_untied_u64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_untied_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_u64 (p0, x0, z1), + z0_res = svldff1uh_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1uh_gather_ext_u64_u64index: +** ldff1h z0\.d, p0/z, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uh_gather_ext_u64_u64index, svuint64_t, uint16_t, svuint64_t, + z0_res = svldff1uh_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uh_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s32.c new file mode 100644 index 00000000000..734a066c30c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_s32_base: +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s32_base, svint32_t, uint16_t, + z0 = svldff1uh_s32 (p0, x0), + z0 = svldff1uh_s32 (p0, x0)) + +/* +** ldff1uh_s32_index: +** ldff1h z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1uh_s32_index, svint32_t, uint16_t, + z0 = svldff1uh_s32 (p0, x0 + x1), + z0 = svldff1uh_s32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_s32_1: +** inch x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s32_1, svint32_t, uint16_t, + z0 = svldff1uh_s32 (p0, x0 + svcntw ()), + z0 = svldff1uh_s32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_s32_m1: +** dech x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s32_m1, svint32_t, uint16_t, + z0 = svldff1uh_s32 (p0, x0 - svcntw ()), + z0 = svldff1uh_s32 (p0, x0 - svcntw ())) + +/* +** ldff1uh_vnum_s32_0: +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s32_0, svint32_t, uint16_t, + z0 = svldff1uh_vnum_s32 (p0, x0, 0), + z0 = svldff1uh_vnum_s32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_s32_1: +** inch x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s32_1, svint32_t, uint16_t, + z0 = svldff1uh_vnum_s32 (p0, x0, 1), + z0 = svldff1uh_vnum_s32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_s32_m1: +** dech x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s32_m1, svint32_t, uint16_t, + z0 = svldff1uh_vnum_s32 (p0, x0, -1), + z0 = svldff1uh_vnum_s32 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s32_x1, svint32_t, uint16_t, + z0 = svldff1uh_vnum_s32 (p0, x0, x1), + z0 = svldff1uh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s64.c new file mode 100644 index 00000000000..e809408db49 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_s64_base: +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s64_base, svint64_t, uint16_t, + z0 = svldff1uh_s64 (p0, x0), + z0 = svldff1uh_s64 (p0, x0)) + +/* +** ldff1uh_s64_index: +** ldff1h z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1uh_s64_index, svint64_t, uint16_t, + z0 = svldff1uh_s64 (p0, x0 + x1), + z0 = svldff1uh_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_s64_1: +** incw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s64_1, svint64_t, uint16_t, + z0 = svldff1uh_s64 (p0, x0 + svcntd ()), + z0 = svldff1uh_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_s64_m1: +** decw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_s64_m1, svint64_t, uint16_t, + z0 = svldff1uh_s64 (p0, x0 - svcntd ()), + z0 = svldff1uh_s64 (p0, x0 - svcntd ())) + +/* +** ldff1uh_vnum_s64_0: +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s64_0, svint64_t, uint16_t, + z0 = svldff1uh_vnum_s64 (p0, x0, 0), + z0 = svldff1uh_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_s64_1: +** incw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s64_1, svint64_t, uint16_t, + z0 = svldff1uh_vnum_s64 (p0, x0, 1), + z0 = svldff1uh_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_s64_m1: +** decw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s64_m1, svint64_t, uint16_t, + z0 = svldff1uh_vnum_s64 (p0, x0, -1), + z0 = svldff1uh_vnum_s64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_s64_x1, svint64_t, uint16_t, + z0 = svldff1uh_vnum_s64 (p0, x0, x1), + z0 = svldff1uh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u32.c new file mode 100644 index 00000000000..ed248e11b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u32.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_u32_base: +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u32_base, svuint32_t, uint16_t, + z0 = svldff1uh_u32 (p0, x0), + z0 = svldff1uh_u32 (p0, x0)) + +/* +** ldff1uh_u32_index: +** ldff1h z0\.s, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1uh_u32_index, svuint32_t, uint16_t, + z0 = svldff1uh_u32 (p0, x0 + x1), + z0 = svldff1uh_u32 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_u32_1: +** inch x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u32_1, svuint32_t, uint16_t, + z0 = svldff1uh_u32 (p0, x0 + svcntw ()), + z0 = svldff1uh_u32 (p0, x0 + svcntw ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_u32_m1: +** dech x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u32_m1, svuint32_t, uint16_t, + z0 = svldff1uh_u32 (p0, x0 - svcntw ()), + z0 = svldff1uh_u32 (p0, x0 - svcntw ())) + +/* +** ldff1uh_vnum_u32_0: +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u32_0, svuint32_t, uint16_t, + z0 = svldff1uh_vnum_u32 (p0, x0, 0), + z0 = svldff1uh_vnum_u32 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_u32_1: +** inch x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u32_1, svuint32_t, uint16_t, + z0 = svldff1uh_vnum_u32 (p0, x0, 1), + z0 = svldff1uh_vnum_u32 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_u32_m1: +** dech x0 +** ldff1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u32_m1, svuint32_t, uint16_t, + z0 = svldff1uh_vnum_u32 (p0, x0, -1), + z0 = svldff1uh_vnum_u32 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u32_x1, svuint32_t, uint16_t, + z0 = svldff1uh_vnum_u32 (p0, x0, x1), + z0 = svldff1uh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u64.c new file mode 100644 index 00000000000..0413930bee8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uh_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uh_u64_base: +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u64_base, svuint64_t, uint16_t, + z0 = svldff1uh_u64 (p0, x0), + z0 = svldff1uh_u64 (p0, x0)) + +/* +** ldff1uh_u64_index: +** ldff1h z0\.d, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldff1uh_u64_index, svuint64_t, uint16_t, + z0 = svldff1uh_u64 (p0, x0 + x1), + z0 = svldff1uh_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_u64_1: +** incw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u64_1, svuint64_t, uint16_t, + z0 = svldff1uh_u64 (p0, x0 + svcntd ()), + z0 = svldff1uh_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_u64_m1: +** decw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_u64_m1, svuint64_t, uint16_t, + z0 = svldff1uh_u64 (p0, x0 - svcntd ()), + z0 = svldff1uh_u64 (p0, x0 - svcntd ())) + +/* +** ldff1uh_vnum_u64_0: +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u64_0, svuint64_t, uint16_t, + z0 = svldff1uh_vnum_u64 (p0, x0, 0), + z0 = svldff1uh_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_u64_1: +** incw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u64_1, svuint64_t, uint16_t, + z0 = svldff1uh_vnum_u64 (p0, x0, 1), + z0 = svldff1uh_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uh_vnum_u64_m1: +** decw x0 +** ldff1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u64_m1, svuint64_t, uint16_t, + z0 = svldff1uh_vnum_u64 (p0, x0, -1), + z0 = svldff1uh_vnum_u64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uh_vnum_u64_x1, svuint64_t, uint16_t, + z0 = svldff1uh_vnum_u64 (p0, x0, x1), + z0 = svldff1uh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_s64.c new file mode 100644 index 00000000000..25fadcf4045 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_s64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uw_gather_s64_tied1: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_s64_tied1, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_s64 (p0, z0), + z0_res = svldff1uw_gather_s64 (p0, z0)) + +/* +** ldff1uw_gather_s64_untied: +** ldff1w z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_s64_untied, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_s64 (p0, z1), + z0_res = svldff1uw_gather_s64 (p0, z1)) + +/* +** ldff1uw_gather_x0_s64_offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_x0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, x0), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, x0)) + +/* +** ldff1uw_gather_m4_s64_offset: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_m4_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, -4), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, -4)) + +/* +** ldff1uw_gather_0_s64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_0_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 0), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 0)) + +/* +** ldff1uw_gather_5_s64_offset: +** mov (x[0-9]+), #?5 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_5_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 5), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 5)) + +/* +** ldff1uw_gather_6_s64_offset: +** mov (x[0-9]+), #?6 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_6_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 6), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 6)) + +/* +** ldff1uw_gather_7_s64_offset: +** mov (x[0-9]+), #?7 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_7_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 7), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 7)) + +/* +** ldff1uw_gather_8_s64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_8_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 8), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 8)) + +/* +** ldff1uw_gather_124_s64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_124_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 124), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 124)) + +/* +** ldff1uw_gather_128_s64_offset: +** mov (x[0-9]+), #?128 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_128_s64_offset, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_s64 (p0, z0, 128), + z0_res = svldff1uw_gather_offset_s64 (p0, z0, 128)) + +/* +** ldff1uw_gather_x0_s64_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_x0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, x0), + z0_res = svldff1uw_gather_index_s64 (p0, z0, x0)) + +/* +** ldff1uw_gather_m1_s64_index: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_m1_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, -1), + z0_res = svldff1uw_gather_index_s64 (p0, z0, -1)) + +/* +** ldff1uw_gather_0_s64_index: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_0_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, 0), + z0_res = svldff1uw_gather_index_s64 (p0, z0, 0)) + +/* +** ldff1uw_gather_5_s64_index: +** ldff1w z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_5_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, 5), + z0_res = svldff1uw_gather_index_s64 (p0, z0, 5)) + +/* +** ldff1uw_gather_31_s64_index: +** ldff1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_31_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, 31), + z0_res = svldff1uw_gather_index_s64 (p0, z0, 31)) + +/* +** ldff1uw_gather_32_s64_index: +** mov (x[0-9]+), #?128 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_32_s64_index, svint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_s64 (p0, z0, 32), + z0_res = svldff1uw_gather_index_s64 (p0, z0, 32)) + +/* +** ldff1uw_gather_x0_s64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_s64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_s64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_s64 (p0, x0, z1), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_s64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_s64_s64offset, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_s64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_s64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_s64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_s64 (p0, x0, z1), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_s64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_s64_u64offset, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uw_gather_offset_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_s64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_s64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_s64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_s64 (p0, x0, z1), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_s64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_s64_s64index, svint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_s64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_s64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_s64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_s64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_s64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_s64 (p0, x0, z1), + z0_res = svldff1uw_gather_index_s64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_s64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_s64_u64index, svint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_s64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uw_gather_index_s64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_u64.c new file mode 100644 index 00000000000..c7eae375f3b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_gather_u64.c @@ -0,0 +1,308 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uw_gather_u64_tied1: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_u64_tied1, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_u64 (p0, z0), + z0_res = svldff1uw_gather_u64 (p0, z0)) + +/* +** ldff1uw_gather_u64_untied: +** ldff1w z0\.d, p0/z, \[z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_u64_untied, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_u64 (p0, z1), + z0_res = svldff1uw_gather_u64 (p0, z1)) + +/* +** ldff1uw_gather_x0_u64_offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_x0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, x0), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, x0)) + +/* +** ldff1uw_gather_m4_u64_offset: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_m4_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, -4), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, -4)) + +/* +** ldff1uw_gather_0_u64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_0_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 0), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 0)) + +/* +** ldff1uw_gather_5_u64_offset: +** mov (x[0-9]+), #?5 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_5_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 5), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 5)) + +/* +** ldff1uw_gather_6_u64_offset: +** mov (x[0-9]+), #?6 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_6_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 6), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 6)) + +/* +** ldff1uw_gather_7_u64_offset: +** mov (x[0-9]+), #?7 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_7_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 7), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 7)) + +/* +** ldff1uw_gather_8_u64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d, #8\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_8_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 8), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 8)) + +/* +** ldff1uw_gather_124_u64_offset: +** ldff1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_124_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 124), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 124)) + +/* +** ldff1uw_gather_128_u64_offset: +** mov (x[0-9]+), #?128 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_128_u64_offset, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_offset_u64 (p0, z0, 128), + z0_res = svldff1uw_gather_offset_u64 (p0, z0, 128)) + +/* +** ldff1uw_gather_x0_u64_index: +** lsl (x[0-9]+), x0, #?2 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_x0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, x0), + z0_res = svldff1uw_gather_index_u64 (p0, z0, x0)) + +/* +** ldff1uw_gather_m1_u64_index: +** mov (x[0-9]+), #?-4 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_m1_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, -1), + z0_res = svldff1uw_gather_index_u64 (p0, z0, -1)) + +/* +** ldff1uw_gather_0_u64_index: +** ldff1w z0\.d, p0/z, \[z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_0_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, 0), + z0_res = svldff1uw_gather_index_u64 (p0, z0, 0)) + +/* +** ldff1uw_gather_5_u64_index: +** ldff1w z0\.d, p0/z, \[z0\.d, #20\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_5_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, 5), + z0_res = svldff1uw_gather_index_u64 (p0, z0, 5)) + +/* +** ldff1uw_gather_31_u64_index: +** ldff1w z0\.d, p0/z, \[z0\.d, #124\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_31_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, 31), + z0_res = svldff1uw_gather_index_u64 (p0, z0, 31)) + +/* +** ldff1uw_gather_32_u64_index: +** mov (x[0-9]+), #?128 +** ldff1w z0\.d, p0/z, \[\1, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_ZS (ldff1uw_gather_32_u64_index, svuint64_t, svuint64_t, + z0_res = svldff1uw_gather_u64base_index_u64 (p0, z0, 32), + z0_res = svldff1uw_gather_index_u64 (p0, z0, 32)) + +/* +** ldff1uw_gather_x0_u64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_u64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_u64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_u64 (p0, x0, z1), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_u64_s64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_u64_s64offset, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_u64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_u64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z0\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_u64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_u64 (p0, x0, z1), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_u64_u64offset: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uw_gather_offset_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_u64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_u64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_u64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_u64 (p0, x0, z1), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_u64_s64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_u64_s64index, svuint64_t, uint32_t, svint64_t, + z0_res = svldff1uw_gather_s64index_u64 (p0, x0, svextw_s64_x (p0, z1)), + z0_res = svldff1uw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) + +/* +** ldff1uw_gather_x0_u64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_x0_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_tied1_u64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_tied1_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_u64 (p0, x0, z0), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z0)) + +/* +** ldff1uw_gather_untied_u64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_untied_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_u64 (p0, x0, z1), + z0_res = svldff1uw_gather_index_u64 (p0, x0, z1)) + +/* +** ldff1uw_gather_ext_u64_u64index: +** ldff1w z0\.d, p0/z, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_LOAD_GATHER_SZ (ldff1uw_gather_ext_u64_u64index, svuint64_t, uint32_t, svuint64_t, + z0_res = svldff1uw_gather_u64index_u64 (p0, x0, svextw_u64_x (p0, z1)), + z0_res = svldff1uw_gather_index_u64 (p0, x0, svextw_x (p0, z1))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_s64.c new file mode 100644 index 00000000000..7518752cb01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_s64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uw_s64_base: +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_s64_base, svint64_t, uint32_t, + z0 = svldff1uw_s64 (p0, x0), + z0 = svldff1uw_s64 (p0, x0)) + +/* +** ldff1uw_s64_index: +** ldff1w z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1uw_s64_index, svint64_t, uint32_t, + z0 = svldff1uw_s64 (p0, x0 + x1), + z0 = svldff1uw_s64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_s64_1: +** inch x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_s64_1, svint64_t, uint32_t, + z0 = svldff1uw_s64 (p0, x0 + svcntd ()), + z0 = svldff1uw_s64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_s64_m1: +** dech x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_s64_m1, svint64_t, uint32_t, + z0 = svldff1uw_s64 (p0, x0 - svcntd ()), + z0 = svldff1uw_s64 (p0, x0 - svcntd ())) + +/* +** ldff1uw_vnum_s64_0: +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_s64_0, svint64_t, uint32_t, + z0 = svldff1uw_vnum_s64 (p0, x0, 0), + z0 = svldff1uw_vnum_s64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_vnum_s64_1: +** inch x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_s64_1, svint64_t, uint32_t, + z0 = svldff1uw_vnum_s64 (p0, x0, 1), + z0 = svldff1uw_vnum_s64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_vnum_s64_m1: +** dech x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_s64_m1, svint64_t, uint32_t, + z0 = svldff1uw_vnum_s64 (p0, x0, -1), + z0 = svldff1uw_vnum_s64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_s64_x1, svint64_t, uint32_t, + z0 = svldff1uw_vnum_s64 (p0, x0, x1), + z0 = svldff1uw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_u64.c new file mode 100644 index 00000000000..45ebbf9924e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldff1uw_u64.c @@ -0,0 +1,86 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldff1uw_u64_base: +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_u64_base, svuint64_t, uint32_t, + z0 = svldff1uw_u64 (p0, x0), + z0 = svldff1uw_u64 (p0, x0)) + +/* +** ldff1uw_u64_index: +** ldff1w z0\.d, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldff1uw_u64_index, svuint64_t, uint32_t, + z0 = svldff1uw_u64 (p0, x0 + x1), + z0 = svldff1uw_u64 (p0, x0 + x1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_u64_1: +** inch x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_u64_1, svuint64_t, uint32_t, + z0 = svldff1uw_u64 (p0, x0 + svcntd ()), + z0 = svldff1uw_u64 (p0, x0 + svcntd ())) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_u64_m1: +** dech x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_u64_m1, svuint64_t, uint32_t, + z0 = svldff1uw_u64 (p0, x0 - svcntd ()), + z0 = svldff1uw_u64 (p0, x0 - svcntd ())) + +/* +** ldff1uw_vnum_u64_0: +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_u64_0, svuint64_t, uint32_t, + z0 = svldff1uw_vnum_u64 (p0, x0, 0), + z0 = svldff1uw_vnum_u64 (p0, x0, 0)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_vnum_u64_1: +** inch x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_u64_1, svuint64_t, uint32_t, + z0 = svldff1uw_vnum_u64 (p0, x0, 1), + z0 = svldff1uw_vnum_u64 (p0, x0, 1)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldff1uw_vnum_u64_m1: +** dech x0 +** ldff1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_u64_m1, svuint64_t, uint32_t, + z0 = svldff1uw_vnum_u64 (p0, x0, -1), + z0 = svldff1uw_vnum_u64 (p0, x0, -1)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldff1uw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldff1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldff1uw_vnum_u64_x1, svuint64_t, uint32_t, + z0 = svldff1uw_vnum_u64 (p0, x0, x1), + z0 = svldff1uw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f16.c new file mode 100644 index 00000000000..627427c3d44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_f16_base: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f16_base, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_f16_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_f16_index, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_f16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f16_1, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 + svcnth ()), + z0 = svldnf1 (p0, x0 + svcnth ())) + +/* +** ldnf1_f16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f16_7, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 + svcnth () * 7), + z0 = svldnf1 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1_f16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f16_8, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 + svcnth () * 8), + z0 = svldnf1 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1_f16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f16_m1, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 - svcnth ()), + z0 = svldnf1 (p0, x0 - svcnth ())) + +/* +** ldnf1_f16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f16_m8, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 - svcnth () * 8), + z0 = svldnf1 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1_f16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f16_m9, svfloat16_t, float16_t, + z0 = svldnf1_f16 (p0, x0 - svcnth () * 9), + z0 = svldnf1 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1_vnum_f16_0: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_0, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_f16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_1, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_f16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_7, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_f16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_8, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_f16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_m1, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_f16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_m8, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_f16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_m9, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f16_x1, svfloat16_t, float16_t, + z0 = svldnf1_vnum_f16 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f32.c new file mode 100644 index 00000000000..b45d611c890 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_f32_base: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f32_base, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_f32_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1w z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_f32_index, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_f32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f32_1, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 + svcntw ()), + z0 = svldnf1 (p0, x0 + svcntw ())) + +/* +** ldnf1_f32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f32_7, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 + svcntw () * 7), + z0 = svldnf1 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1_f32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f32_8, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 + svcntw () * 8), + z0 = svldnf1 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1_f32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f32_m1, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 - svcntw ()), + z0 = svldnf1 (p0, x0 - svcntw ())) + +/* +** ldnf1_f32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f32_m8, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 - svcntw () * 8), + z0 = svldnf1 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1_f32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f32_m9, svfloat32_t, float32_t, + z0 = svldnf1_f32 (p0, x0 - svcntw () * 9), + z0 = svldnf1 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1_vnum_f32_0: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_0, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_f32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_1, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_f32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_7, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_f32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_8, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_f32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_m1, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_f32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_m8, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_f32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_m9, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f32_x1, svfloat32_t, float32_t, + z0 = svldnf1_vnum_f32 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f64.c new file mode 100644 index 00000000000..81e767ea372 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_f64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_f64_base: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f64_base, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_f64_index: +** add (x[0-9]+), x0, x1, lsl 3 +** ldnf1d z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_f64_index, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_f64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f64_1, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 + svcntd ()), + z0 = svldnf1 (p0, x0 + svcntd ())) + +/* +** ldnf1_f64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f64_7, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 + svcntd () * 7), + z0 = svldnf1 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1_f64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f64_8, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 + svcntd () * 8), + z0 = svldnf1 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1_f64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f64_m1, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 - svcntd ()), + z0 = svldnf1 (p0, x0 - svcntd ())) + +/* +** ldnf1_f64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_f64_m8, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 - svcntd () * 8), + z0 = svldnf1 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1_f64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_f64_m9, svfloat64_t, float64_t, + z0 = svldnf1_f64 (p0, x0 - svcntd () * 9), + z0 = svldnf1 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1_vnum_f64_0: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_0, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_f64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_1, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_f64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_7, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_f64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_8, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_f64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_m1, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_f64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_m8, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_f64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_m9, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_f64_x1, svfloat64_t, float64_t, + z0 = svldnf1_vnum_f64 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s16.c new file mode 100644 index 00000000000..a9c512056ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_s16_base: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s16_base, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_s16_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_s16_index, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_s16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s16_1, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 + svcnth ()), + z0 = svldnf1 (p0, x0 + svcnth ())) + +/* +** ldnf1_s16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s16_7, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 + svcnth () * 7), + z0 = svldnf1 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1_s16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s16_8, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 + svcnth () * 8), + z0 = svldnf1 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1_s16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s16_m1, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 - svcnth ()), + z0 = svldnf1 (p0, x0 - svcnth ())) + +/* +** ldnf1_s16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s16_m8, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 - svcnth () * 8), + z0 = svldnf1 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1_s16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s16_m9, svint16_t, int16_t, + z0 = svldnf1_s16 (p0, x0 - svcnth () * 9), + z0 = svldnf1 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1_vnum_s16_0: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_0, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_s16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_1, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_s16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_7, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_s16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_8, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_s16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_m1, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_s16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_m8, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_s16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_m9, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s16_x1, svint16_t, int16_t, + z0 = svldnf1_vnum_s16 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s32.c new file mode 100644 index 00000000000..22b4148309c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_s32_base: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s32_base, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_s32_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1w z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_s32_index, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_s32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s32_1, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 + svcntw ()), + z0 = svldnf1 (p0, x0 + svcntw ())) + +/* +** ldnf1_s32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s32_7, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 + svcntw () * 7), + z0 = svldnf1 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1_s32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s32_8, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 + svcntw () * 8), + z0 = svldnf1 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1_s32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s32_m1, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 - svcntw ()), + z0 = svldnf1 (p0, x0 - svcntw ())) + +/* +** ldnf1_s32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s32_m8, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 - svcntw () * 8), + z0 = svldnf1 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1_s32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s32_m9, svint32_t, int32_t, + z0 = svldnf1_s32 (p0, x0 - svcntw () * 9), + z0 = svldnf1 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1_vnum_s32_0: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_0, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_s32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_1, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_s32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_7, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_s32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_8, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_s32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_m1, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_s32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_m8, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_s32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_m9, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s32_x1, svint32_t, int32_t, + z0 = svldnf1_vnum_s32 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s64.c new file mode 100644 index 00000000000..3d52a2b34cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_s64_base: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s64_base, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_s64_index: +** add (x[0-9]+), x0, x1, lsl 3 +** ldnf1d z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_s64_index, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_s64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s64_1, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 + svcntd ()), + z0 = svldnf1 (p0, x0 + svcntd ())) + +/* +** ldnf1_s64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s64_7, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1_s64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s64_8, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1_s64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s64_m1, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 - svcntd ()), + z0 = svldnf1 (p0, x0 - svcntd ())) + +/* +** ldnf1_s64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s64_m8, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1_s64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s64_m9, svint64_t, int64_t, + z0 = svldnf1_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1_vnum_s64_0: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_0, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_s64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_1, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_s64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_7, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_s64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_8, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_s64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_m1, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_s64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_m8, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_s64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_m9, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s64_x1, svint64_t, int64_t, + z0 = svldnf1_vnum_s64 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s8.c new file mode 100644 index 00000000000..ace56672465 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_s8.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_s8_base: +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s8_base, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_s8_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_s8_index, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_s8_1: +** ldnf1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s8_1, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 + svcntb ()), + z0 = svldnf1 (p0, x0 + svcntb ())) + +/* +** ldnf1_s8_7: +** ldnf1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s8_7, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 + svcntb () * 7), + z0 = svldnf1 (p0, x0 + svcntb () * 7)) + +/* +** ldnf1_s8_8: +** incb x0, all, mul #8 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s8_8, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 + svcntb () * 8), + z0 = svldnf1 (p0, x0 + svcntb () * 8)) + +/* +** ldnf1_s8_m1: +** ldnf1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s8_m1, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 - svcntb ()), + z0 = svldnf1 (p0, x0 - svcntb ())) + +/* +** ldnf1_s8_m8: +** ldnf1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_s8_m8, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 - svcntb () * 8), + z0 = svldnf1 (p0, x0 - svcntb () * 8)) + +/* +** ldnf1_s8_m9: +** decb x0, all, mul #9 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_s8_m9, svint8_t, int8_t, + z0 = svldnf1_s8 (p0, x0 - svcntb () * 9), + z0 = svldnf1 (p0, x0 - svcntb () * 9)) + +/* +** ldnf1_vnum_s8_0: +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_0, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_s8_1: +** ldnf1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_1, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_s8_7: +** ldnf1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_7, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_s8_8: +** incb x0, all, mul #8 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_8, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_s8_m1: +** ldnf1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_m1, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_s8_m8: +** ldnf1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_m8, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_s8_m9: +** decb x0, all, mul #9 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_m9, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_s8_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.b, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_s8_x1, svint8_t, int8_t, + z0 = svldnf1_vnum_s8 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u16.c new file mode 100644 index 00000000000..9a98f930509 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_u16_base: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u16_base, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_u16_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_u16_index, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_u16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u16_1, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 + svcnth ()), + z0 = svldnf1 (p0, x0 + svcnth ())) + +/* +** ldnf1_u16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u16_7, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 + svcnth () * 7), + z0 = svldnf1 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1_u16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u16_8, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 + svcnth () * 8), + z0 = svldnf1 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1_u16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u16_m1, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 - svcnth ()), + z0 = svldnf1 (p0, x0 - svcnth ())) + +/* +** ldnf1_u16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u16_m8, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 - svcnth () * 8), + z0 = svldnf1 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1_u16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u16_m9, svuint16_t, uint16_t, + z0 = svldnf1_u16 (p0, x0 - svcnth () * 9), + z0 = svldnf1 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1_vnum_u16_0: +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_0, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_u16_1: +** ldnf1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_1, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_u16_7: +** ldnf1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_7, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_u16_8: +** incb x0, all, mul #8 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_8, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_u16_m1: +** ldnf1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_m1, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_u16_m8: +** ldnf1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_m8, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_u16_m9: +** decb x0, all, mul #9 +** ldnf1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_m9, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u16_x1, svuint16_t, uint16_t, + z0 = svldnf1_vnum_u16 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u32.c new file mode 100644 index 00000000000..ebe25098e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_u32_base: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u32_base, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_u32_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1w z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_u32_index, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_u32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u32_1, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 + svcntw ()), + z0 = svldnf1 (p0, x0 + svcntw ())) + +/* +** ldnf1_u32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u32_7, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 + svcntw () * 7), + z0 = svldnf1 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1_u32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u32_8, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 + svcntw () * 8), + z0 = svldnf1 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1_u32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u32_m1, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 - svcntw ()), + z0 = svldnf1 (p0, x0 - svcntw ())) + +/* +** ldnf1_u32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u32_m8, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 - svcntw () * 8), + z0 = svldnf1 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1_u32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u32_m9, svuint32_t, uint32_t, + z0 = svldnf1_u32 (p0, x0 - svcntw () * 9), + z0 = svldnf1 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1_vnum_u32_0: +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_0, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_u32_1: +** ldnf1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_1, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_u32_7: +** ldnf1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_7, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_u32_8: +** incb x0, all, mul #8 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_8, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_u32_m1: +** ldnf1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_m1, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_u32_m8: +** ldnf1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_m8, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_u32_m9: +** decb x0, all, mul #9 +** ldnf1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_m9, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u32_x1, svuint32_t, uint32_t, + z0 = svldnf1_vnum_u32 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u64.c new file mode 100644 index 00000000000..46bd3cea75c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_u64_base: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u64_base, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_u64_index: +** add (x[0-9]+), x0, x1, lsl 3 +** ldnf1d z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_u64_index, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_u64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u64_1, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 + svcntd ()), + z0 = svldnf1 (p0, x0 + svcntd ())) + +/* +** ldnf1_u64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u64_7, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1_u64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u64_8, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1_u64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u64_m1, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 - svcntd ()), + z0 = svldnf1 (p0, x0 - svcntd ())) + +/* +** ldnf1_u64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u64_m8, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1_u64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u64_m9, svuint64_t, uint64_t, + z0 = svldnf1_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1_vnum_u64_0: +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_0, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_u64_1: +** ldnf1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_1, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_u64_7: +** ldnf1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_7, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_u64_8: +** incb x0, all, mul #8 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_8, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_u64_m1: +** ldnf1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_m1, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_u64_m8: +** ldnf1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_m8, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_u64_m9: +** decb x0, all, mul #9 +** ldnf1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_m9, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u64_x1, svuint64_t, uint64_t, + z0 = svldnf1_vnum_u64 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u8.c new file mode 100644 index 00000000000..1fff2b2fc98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1_u8.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1_u8_base: +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u8_base, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0), + z0 = svldnf1 (p0, x0)) + +/* +** ldnf1_u8_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.b, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1_u8_index, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 + x1), + z0 = svldnf1 (p0, x0 + x1)) + +/* +** ldnf1_u8_1: +** ldnf1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u8_1, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 + svcntb ()), + z0 = svldnf1 (p0, x0 + svcntb ())) + +/* +** ldnf1_u8_7: +** ldnf1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u8_7, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 + svcntb () * 7), + z0 = svldnf1 (p0, x0 + svcntb () * 7)) + +/* +** ldnf1_u8_8: +** incb x0, all, mul #8 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u8_8, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 + svcntb () * 8), + z0 = svldnf1 (p0, x0 + svcntb () * 8)) + +/* +** ldnf1_u8_m1: +** ldnf1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u8_m1, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 - svcntb ()), + z0 = svldnf1 (p0, x0 - svcntb ())) + +/* +** ldnf1_u8_m8: +** ldnf1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_u8_m8, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 - svcntb () * 8), + z0 = svldnf1 (p0, x0 - svcntb () * 8)) + +/* +** ldnf1_u8_m9: +** decb x0, all, mul #9 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_u8_m9, svuint8_t, uint8_t, + z0 = svldnf1_u8 (p0, x0 - svcntb () * 9), + z0 = svldnf1 (p0, x0 - svcntb () * 9)) + +/* +** ldnf1_vnum_u8_0: +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_0, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, 0), + z0 = svldnf1_vnum (p0, x0, 0)) + +/* +** ldnf1_vnum_u8_1: +** ldnf1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_1, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, 1), + z0 = svldnf1_vnum (p0, x0, 1)) + +/* +** ldnf1_vnum_u8_7: +** ldnf1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_7, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, 7), + z0 = svldnf1_vnum (p0, x0, 7)) + +/* +** ldnf1_vnum_u8_8: +** incb x0, all, mul #8 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_8, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, 8), + z0 = svldnf1_vnum (p0, x0, 8)) + +/* +** ldnf1_vnum_u8_m1: +** ldnf1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_m1, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, -1), + z0 = svldnf1_vnum (p0, x0, -1)) + +/* +** ldnf1_vnum_u8_m8: +** ldnf1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_m8, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, -8), + z0 = svldnf1_vnum (p0, x0, -8)) + +/* +** ldnf1_vnum_u8_m9: +** decb x0, all, mul #9 +** ldnf1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_m9, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, -9), + z0 = svldnf1_vnum (p0, x0, -9)) + +/* +** ldnf1_vnum_u8_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.b, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1_vnum_u8_x1, svuint8_t, uint8_t, + z0 = svldnf1_vnum_u8 (p0, x0, x1), + z0 = svldnf1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s16.c new file mode 100644 index 00000000000..9602c3414a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_s16_base: +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_base, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0), + z0 = svldnf1sb_s16 (p0, x0)) + +/* +** ldnf1sb_s16_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_index, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 + x1), + z0 = svldnf1sb_s16 (p0, x0 + x1)) + +/* +** ldnf1sb_s16_1: +** ldnf1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_1, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 + svcnth ()), + z0 = svldnf1sb_s16 (p0, x0 + svcnth ())) + +/* +** ldnf1sb_s16_7: +** ldnf1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_7, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 + svcnth () * 7), + z0 = svldnf1sb_s16 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1sb_s16_8: +** incb x0, all, mul #4 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_8, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 + svcnth () * 8), + z0 = svldnf1sb_s16 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1sb_s16_m1: +** ldnf1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_m1, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 - svcnth ()), + z0 = svldnf1sb_s16 (p0, x0 - svcnth ())) + +/* +** ldnf1sb_s16_m8: +** ldnf1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_m8, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 - svcnth () * 8), + z0 = svldnf1sb_s16 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1sb_s16_m9: +** dech x0, all, mul #9 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s16_m9, svint16_t, int8_t, + z0 = svldnf1sb_s16 (p0, x0 - svcnth () * 9), + z0 = svldnf1sb_s16 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1sb_vnum_s16_0: +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_0, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, 0), + z0 = svldnf1sb_vnum_s16 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_s16_1: +** ldnf1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_1, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, 1), + z0 = svldnf1sb_vnum_s16 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_s16_7: +** ldnf1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_7, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, 7), + z0 = svldnf1sb_vnum_s16 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_s16_8: +** incb x0, all, mul #4 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_8, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, 8), + z0 = svldnf1sb_vnum_s16 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_s16_m1: +** ldnf1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_m1, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, -1), + z0 = svldnf1sb_vnum_s16 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_s16_m8: +** ldnf1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_m8, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, -8), + z0 = svldnf1sb_vnum_s16 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_s16_m9: +** dech x0, all, mul #9 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_m9, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, -9), + z0 = svldnf1sb_vnum_s16 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_s16_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s16_x1, svint16_t, int8_t, + z0 = svldnf1sb_vnum_s16 (p0, x0, x1), + z0 = svldnf1sb_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s32.c new file mode 100644 index 00000000000..83d4536e888 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_s32_base: +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_base, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0), + z0 = svldnf1sb_s32 (p0, x0)) + +/* +** ldnf1sb_s32_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_index, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 + x1), + z0 = svldnf1sb_s32 (p0, x0 + x1)) + +/* +** ldnf1sb_s32_1: +** ldnf1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_1, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 + svcntw ()), + z0 = svldnf1sb_s32 (p0, x0 + svcntw ())) + +/* +** ldnf1sb_s32_7: +** ldnf1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_7, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 + svcntw () * 7), + z0 = svldnf1sb_s32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1sb_s32_8: +** incb x0, all, mul #2 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_8, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 + svcntw () * 8), + z0 = svldnf1sb_s32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1sb_s32_m1: +** ldnf1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_m1, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 - svcntw ()), + z0 = svldnf1sb_s32 (p0, x0 - svcntw ())) + +/* +** ldnf1sb_s32_m8: +** ldnf1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_m8, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 - svcntw () * 8), + z0 = svldnf1sb_s32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1sb_s32_m9: +** decw x0, all, mul #9 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s32_m9, svint32_t, int8_t, + z0 = svldnf1sb_s32 (p0, x0 - svcntw () * 9), + z0 = svldnf1sb_s32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1sb_vnum_s32_0: +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_0, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, 0), + z0 = svldnf1sb_vnum_s32 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_s32_1: +** ldnf1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_1, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, 1), + z0 = svldnf1sb_vnum_s32 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_s32_7: +** ldnf1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_7, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, 7), + z0 = svldnf1sb_vnum_s32 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_s32_8: +** incb x0, all, mul #2 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_8, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, 8), + z0 = svldnf1sb_vnum_s32 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_s32_m1: +** ldnf1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_m1, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, -1), + z0 = svldnf1sb_vnum_s32 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_s32_m8: +** ldnf1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_m8, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, -8), + z0 = svldnf1sb_vnum_s32 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_s32_m9: +** decw x0, all, mul #9 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_m9, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, -9), + z0 = svldnf1sb_vnum_s32 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_s32_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s32_x1, svint32_t, int8_t, + z0 = svldnf1sb_vnum_s32 (p0, x0, x1), + z0 = svldnf1sb_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s64.c new file mode 100644 index 00000000000..ec306705f3e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_s64_base: +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_base, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0), + z0 = svldnf1sb_s64 (p0, x0)) + +/* +** ldnf1sb_s64_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_index, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 + x1), + z0 = svldnf1sb_s64 (p0, x0 + x1)) + +/* +** ldnf1sb_s64_1: +** ldnf1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_1, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 + svcntd ()), + z0 = svldnf1sb_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1sb_s64_7: +** ldnf1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_7, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sb_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sb_s64_8: +** incb x0 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_8, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sb_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sb_s64_m1: +** ldnf1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_m1, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 - svcntd ()), + z0 = svldnf1sb_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1sb_s64_m8: +** ldnf1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_m8, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sb_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sb_s64_m9: +** decd x0, all, mul #9 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_s64_m9, svint64_t, int8_t, + z0 = svldnf1sb_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sb_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sb_vnum_s64_0: +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_0, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, 0), + z0 = svldnf1sb_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_s64_1: +** ldnf1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_1, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, 1), + z0 = svldnf1sb_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_s64_7: +** ldnf1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_7, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, 7), + z0 = svldnf1sb_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_s64_8: +** incb x0 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_8, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, 8), + z0 = svldnf1sb_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_s64_m1: +** ldnf1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_m1, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, -1), + z0 = svldnf1sb_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_s64_m8: +** ldnf1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_m8, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, -8), + z0 = svldnf1sb_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_s64_m9: +** decd x0, all, mul #9 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_m9, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, -9), + z0 = svldnf1sb_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_s64_x1: +** cntd (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_s64_x1, svint64_t, int8_t, + z0 = svldnf1sb_vnum_s64 (p0, x0, x1), + z0 = svldnf1sb_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u16.c new file mode 100644 index 00000000000..24816fdcc8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_u16_base: +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_base, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0), + z0 = svldnf1sb_u16 (p0, x0)) + +/* +** ldnf1sb_u16_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_index, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 + x1), + z0 = svldnf1sb_u16 (p0, x0 + x1)) + +/* +** ldnf1sb_u16_1: +** ldnf1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_1, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 + svcnth ()), + z0 = svldnf1sb_u16 (p0, x0 + svcnth ())) + +/* +** ldnf1sb_u16_7: +** ldnf1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_7, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 + svcnth () * 7), + z0 = svldnf1sb_u16 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1sb_u16_8: +** incb x0, all, mul #4 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_8, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 + svcnth () * 8), + z0 = svldnf1sb_u16 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1sb_u16_m1: +** ldnf1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_m1, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 - svcnth ()), + z0 = svldnf1sb_u16 (p0, x0 - svcnth ())) + +/* +** ldnf1sb_u16_m8: +** ldnf1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_m8, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 - svcnth () * 8), + z0 = svldnf1sb_u16 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1sb_u16_m9: +** dech x0, all, mul #9 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u16_m9, svuint16_t, int8_t, + z0 = svldnf1sb_u16 (p0, x0 - svcnth () * 9), + z0 = svldnf1sb_u16 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1sb_vnum_u16_0: +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_0, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, 0), + z0 = svldnf1sb_vnum_u16 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_u16_1: +** ldnf1sb z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_1, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, 1), + z0 = svldnf1sb_vnum_u16 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_u16_7: +** ldnf1sb z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_7, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, 7), + z0 = svldnf1sb_vnum_u16 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_u16_8: +** incb x0, all, mul #4 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_8, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, 8), + z0 = svldnf1sb_vnum_u16 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_u16_m1: +** ldnf1sb z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_m1, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, -1), + z0 = svldnf1sb_vnum_u16 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_u16_m8: +** ldnf1sb z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_m8, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, -8), + z0 = svldnf1sb_vnum_u16 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_u16_m9: +** dech x0, all, mul #9 +** ldnf1sb z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_m9, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, -9), + z0 = svldnf1sb_vnum_u16 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_u16_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u16_x1, svuint16_t, int8_t, + z0 = svldnf1sb_vnum_u16 (p0, x0, x1), + z0 = svldnf1sb_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u32.c new file mode 100644 index 00000000000..0f6ae3f9bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_u32_base: +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_base, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0), + z0 = svldnf1sb_u32 (p0, x0)) + +/* +** ldnf1sb_u32_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_index, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 + x1), + z0 = svldnf1sb_u32 (p0, x0 + x1)) + +/* +** ldnf1sb_u32_1: +** ldnf1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_1, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 + svcntw ()), + z0 = svldnf1sb_u32 (p0, x0 + svcntw ())) + +/* +** ldnf1sb_u32_7: +** ldnf1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_7, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 + svcntw () * 7), + z0 = svldnf1sb_u32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1sb_u32_8: +** incb x0, all, mul #2 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_8, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 + svcntw () * 8), + z0 = svldnf1sb_u32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1sb_u32_m1: +** ldnf1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_m1, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 - svcntw ()), + z0 = svldnf1sb_u32 (p0, x0 - svcntw ())) + +/* +** ldnf1sb_u32_m8: +** ldnf1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_m8, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 - svcntw () * 8), + z0 = svldnf1sb_u32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1sb_u32_m9: +** decw x0, all, mul #9 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u32_m9, svuint32_t, int8_t, + z0 = svldnf1sb_u32 (p0, x0 - svcntw () * 9), + z0 = svldnf1sb_u32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1sb_vnum_u32_0: +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_0, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, 0), + z0 = svldnf1sb_vnum_u32 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_u32_1: +** ldnf1sb z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_1, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, 1), + z0 = svldnf1sb_vnum_u32 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_u32_7: +** ldnf1sb z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_7, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, 7), + z0 = svldnf1sb_vnum_u32 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_u32_8: +** incb x0, all, mul #2 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_8, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, 8), + z0 = svldnf1sb_vnum_u32 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_u32_m1: +** ldnf1sb z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_m1, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, -1), + z0 = svldnf1sb_vnum_u32 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_u32_m8: +** ldnf1sb z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_m8, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, -8), + z0 = svldnf1sb_vnum_u32 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_u32_m9: +** decw x0, all, mul #9 +** ldnf1sb z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_m9, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, -9), + z0 = svldnf1sb_vnum_u32 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_u32_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u32_x1, svuint32_t, int8_t, + z0 = svldnf1sb_vnum_u32 (p0, x0, x1), + z0 = svldnf1sb_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u64.c new file mode 100644 index 00000000000..bc4e3418ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sb_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sb_u64_base: +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_base, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0), + z0 = svldnf1sb_u64 (p0, x0)) + +/* +** ldnf1sb_u64_index: +** add (x[0-9]+), x0, x1 +** ldnf1sb z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_index, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 + x1), + z0 = svldnf1sb_u64 (p0, x0 + x1)) + +/* +** ldnf1sb_u64_1: +** ldnf1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_1, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 + svcntd ()), + z0 = svldnf1sb_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1sb_u64_7: +** ldnf1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_7, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sb_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sb_u64_8: +** incb x0 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_8, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sb_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sb_u64_m1: +** ldnf1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_m1, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 - svcntd ()), + z0 = svldnf1sb_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1sb_u64_m8: +** ldnf1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_m8, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sb_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sb_u64_m9: +** decd x0, all, mul #9 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_u64_m9, svuint64_t, int8_t, + z0 = svldnf1sb_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sb_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sb_vnum_u64_0: +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_0, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, 0), + z0 = svldnf1sb_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1sb_vnum_u64_1: +** ldnf1sb z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_1, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, 1), + z0 = svldnf1sb_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1sb_vnum_u64_7: +** ldnf1sb z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_7, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, 7), + z0 = svldnf1sb_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1sb_vnum_u64_8: +** incb x0 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_8, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, 8), + z0 = svldnf1sb_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1sb_vnum_u64_m1: +** ldnf1sb z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_m1, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, -1), + z0 = svldnf1sb_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1sb_vnum_u64_m8: +** ldnf1sb z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_m8, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, -8), + z0 = svldnf1sb_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1sb_vnum_u64_m9: +** decd x0, all, mul #9 +** ldnf1sb z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_m9, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, -9), + z0 = svldnf1sb_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1sb_vnum_u64_x1: +** cntd (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sb z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sb_vnum_u64_x1, svuint64_t, int8_t, + z0 = svldnf1sb_vnum_u64 (p0, x0, x1), + z0 = svldnf1sb_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s32.c new file mode 100644 index 00000000000..05abc04adfc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sh_s32_base: +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_base, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0), + z0 = svldnf1sh_s32 (p0, x0)) + +/* +** ldnf1sh_s32_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1sh z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_index, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 + x1), + z0 = svldnf1sh_s32 (p0, x0 + x1)) + +/* +** ldnf1sh_s32_1: +** ldnf1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_1, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 + svcntw ()), + z0 = svldnf1sh_s32 (p0, x0 + svcntw ())) + +/* +** ldnf1sh_s32_7: +** ldnf1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_7, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 + svcntw () * 7), + z0 = svldnf1sh_s32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1sh_s32_8: +** incb x0, all, mul #4 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_8, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 + svcntw () * 8), + z0 = svldnf1sh_s32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1sh_s32_m1: +** ldnf1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_m1, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 - svcntw ()), + z0 = svldnf1sh_s32 (p0, x0 - svcntw ())) + +/* +** ldnf1sh_s32_m8: +** ldnf1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_m8, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 - svcntw () * 8), + z0 = svldnf1sh_s32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1sh_s32_m9: +** dech x0, all, mul #9 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s32_m9, svint32_t, int16_t, + z0 = svldnf1sh_s32 (p0, x0 - svcntw () * 9), + z0 = svldnf1sh_s32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1sh_vnum_s32_0: +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_0, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, 0), + z0 = svldnf1sh_vnum_s32 (p0, x0, 0)) + +/* +** ldnf1sh_vnum_s32_1: +** ldnf1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_1, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, 1), + z0 = svldnf1sh_vnum_s32 (p0, x0, 1)) + +/* +** ldnf1sh_vnum_s32_7: +** ldnf1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_7, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, 7), + z0 = svldnf1sh_vnum_s32 (p0, x0, 7)) + +/* +** ldnf1sh_vnum_s32_8: +** incb x0, all, mul #4 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_8, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, 8), + z0 = svldnf1sh_vnum_s32 (p0, x0, 8)) + +/* +** ldnf1sh_vnum_s32_m1: +** ldnf1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_m1, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, -1), + z0 = svldnf1sh_vnum_s32 (p0, x0, -1)) + +/* +** ldnf1sh_vnum_s32_m8: +** ldnf1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_m8, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, -8), + z0 = svldnf1sh_vnum_s32 (p0, x0, -8)) + +/* +** ldnf1sh_vnum_s32_m9: +** dech x0, all, mul #9 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_m9, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, -9), + z0 = svldnf1sh_vnum_s32 (p0, x0, -9)) + +/* +** ldnf1sh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s32_x1, svint32_t, int16_t, + z0 = svldnf1sh_vnum_s32 (p0, x0, x1), + z0 = svldnf1sh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s64.c new file mode 100644 index 00000000000..a7ca2aef7d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sh_s64_base: +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_base, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0), + z0 = svldnf1sh_s64 (p0, x0)) + +/* +** ldnf1sh_s64_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1sh z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_index, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 + x1), + z0 = svldnf1sh_s64 (p0, x0 + x1)) + +/* +** ldnf1sh_s64_1: +** ldnf1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_1, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 + svcntd ()), + z0 = svldnf1sh_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1sh_s64_7: +** ldnf1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_7, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sh_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sh_s64_8: +** incb x0, all, mul #2 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_8, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sh_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sh_s64_m1: +** ldnf1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_m1, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 - svcntd ()), + z0 = svldnf1sh_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1sh_s64_m8: +** ldnf1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_m8, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sh_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sh_s64_m9: +** decw x0, all, mul #9 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_s64_m9, svint64_t, int16_t, + z0 = svldnf1sh_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sh_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sh_vnum_s64_0: +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_0, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, 0), + z0 = svldnf1sh_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1sh_vnum_s64_1: +** ldnf1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_1, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, 1), + z0 = svldnf1sh_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1sh_vnum_s64_7: +** ldnf1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_7, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, 7), + z0 = svldnf1sh_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1sh_vnum_s64_8: +** incb x0, all, mul #2 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_8, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, 8), + z0 = svldnf1sh_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1sh_vnum_s64_m1: +** ldnf1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_m1, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, -1), + z0 = svldnf1sh_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1sh_vnum_s64_m8: +** ldnf1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_m8, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, -8), + z0 = svldnf1sh_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1sh_vnum_s64_m9: +** decw x0, all, mul #9 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_m9, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, -9), + z0 = svldnf1sh_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1sh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_s64_x1, svint64_t, int16_t, + z0 = svldnf1sh_vnum_s64 (p0, x0, x1), + z0 = svldnf1sh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u32.c new file mode 100644 index 00000000000..7a81aae036f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sh_u32_base: +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_base, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0), + z0 = svldnf1sh_u32 (p0, x0)) + +/* +** ldnf1sh_u32_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1sh z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_index, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 + x1), + z0 = svldnf1sh_u32 (p0, x0 + x1)) + +/* +** ldnf1sh_u32_1: +** ldnf1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_1, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 + svcntw ()), + z0 = svldnf1sh_u32 (p0, x0 + svcntw ())) + +/* +** ldnf1sh_u32_7: +** ldnf1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_7, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 + svcntw () * 7), + z0 = svldnf1sh_u32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1sh_u32_8: +** incb x0, all, mul #4 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_8, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 + svcntw () * 8), + z0 = svldnf1sh_u32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1sh_u32_m1: +** ldnf1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_m1, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 - svcntw ()), + z0 = svldnf1sh_u32 (p0, x0 - svcntw ())) + +/* +** ldnf1sh_u32_m8: +** ldnf1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_m8, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 - svcntw () * 8), + z0 = svldnf1sh_u32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1sh_u32_m9: +** dech x0, all, mul #9 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u32_m9, svuint32_t, int16_t, + z0 = svldnf1sh_u32 (p0, x0 - svcntw () * 9), + z0 = svldnf1sh_u32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1sh_vnum_u32_0: +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_0, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, 0), + z0 = svldnf1sh_vnum_u32 (p0, x0, 0)) + +/* +** ldnf1sh_vnum_u32_1: +** ldnf1sh z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_1, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, 1), + z0 = svldnf1sh_vnum_u32 (p0, x0, 1)) + +/* +** ldnf1sh_vnum_u32_7: +** ldnf1sh z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_7, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, 7), + z0 = svldnf1sh_vnum_u32 (p0, x0, 7)) + +/* +** ldnf1sh_vnum_u32_8: +** incb x0, all, mul #4 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_8, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, 8), + z0 = svldnf1sh_vnum_u32 (p0, x0, 8)) + +/* +** ldnf1sh_vnum_u32_m1: +** ldnf1sh z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_m1, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, -1), + z0 = svldnf1sh_vnum_u32 (p0, x0, -1)) + +/* +** ldnf1sh_vnum_u32_m8: +** ldnf1sh z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_m8, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, -8), + z0 = svldnf1sh_vnum_u32 (p0, x0, -8)) + +/* +** ldnf1sh_vnum_u32_m9: +** dech x0, all, mul #9 +** ldnf1sh z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_m9, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, -9), + z0 = svldnf1sh_vnum_u32 (p0, x0, -9)) + +/* +** ldnf1sh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sh z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u32_x1, svuint32_t, int16_t, + z0 = svldnf1sh_vnum_u32 (p0, x0, x1), + z0 = svldnf1sh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u64.c new file mode 100644 index 00000000000..2a18790bc29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sh_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sh_u64_base: +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_base, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0), + z0 = svldnf1sh_u64 (p0, x0)) + +/* +** ldnf1sh_u64_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1sh z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_index, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 + x1), + z0 = svldnf1sh_u64 (p0, x0 + x1)) + +/* +** ldnf1sh_u64_1: +** ldnf1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_1, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 + svcntd ()), + z0 = svldnf1sh_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1sh_u64_7: +** ldnf1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_7, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sh_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sh_u64_8: +** incb x0, all, mul #2 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_8, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sh_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sh_u64_m1: +** ldnf1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_m1, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 - svcntd ()), + z0 = svldnf1sh_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1sh_u64_m8: +** ldnf1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_m8, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sh_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sh_u64_m9: +** decw x0, all, mul #9 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_u64_m9, svuint64_t, int16_t, + z0 = svldnf1sh_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sh_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sh_vnum_u64_0: +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_0, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, 0), + z0 = svldnf1sh_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1sh_vnum_u64_1: +** ldnf1sh z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_1, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, 1), + z0 = svldnf1sh_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1sh_vnum_u64_7: +** ldnf1sh z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_7, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, 7), + z0 = svldnf1sh_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1sh_vnum_u64_8: +** incb x0, all, mul #2 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_8, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, 8), + z0 = svldnf1sh_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1sh_vnum_u64_m1: +** ldnf1sh z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_m1, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, -1), + z0 = svldnf1sh_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1sh_vnum_u64_m8: +** ldnf1sh z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_m8, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, -8), + z0 = svldnf1sh_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1sh_vnum_u64_m9: +** decw x0, all, mul #9 +** ldnf1sh z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_m9, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, -9), + z0 = svldnf1sh_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1sh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sh z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sh_vnum_u64_x1, svuint64_t, int16_t, + z0 = svldnf1sh_vnum_u64 (p0, x0, x1), + z0 = svldnf1sh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_s64.c new file mode 100644 index 00000000000..91b6e73cdf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sw_s64_base: +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_base, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0), + z0 = svldnf1sw_s64 (p0, x0)) + +/* +** ldnf1sw_s64_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1sw z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_index, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 + x1), + z0 = svldnf1sw_s64 (p0, x0 + x1)) + +/* +** ldnf1sw_s64_1: +** ldnf1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_1, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 + svcntd ()), + z0 = svldnf1sw_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1sw_s64_7: +** ldnf1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_7, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sw_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sw_s64_8: +** incb x0, all, mul #4 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_8, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sw_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sw_s64_m1: +** ldnf1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_m1, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 - svcntd ()), + z0 = svldnf1sw_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1sw_s64_m8: +** ldnf1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_m8, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sw_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sw_s64_m9: +** dech x0, all, mul #9 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_s64_m9, svint64_t, int32_t, + z0 = svldnf1sw_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sw_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sw_vnum_s64_0: +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_0, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, 0), + z0 = svldnf1sw_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1sw_vnum_s64_1: +** ldnf1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_1, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, 1), + z0 = svldnf1sw_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1sw_vnum_s64_7: +** ldnf1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_7, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, 7), + z0 = svldnf1sw_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1sw_vnum_s64_8: +** incb x0, all, mul #4 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_8, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, 8), + z0 = svldnf1sw_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1sw_vnum_s64_m1: +** ldnf1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_m1, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, -1), + z0 = svldnf1sw_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1sw_vnum_s64_m8: +** ldnf1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_m8, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, -8), + z0 = svldnf1sw_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1sw_vnum_s64_m9: +** dech x0, all, mul #9 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_m9, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, -9), + z0 = svldnf1sw_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1sw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_s64_x1, svint64_t, int32_t, + z0 = svldnf1sw_vnum_s64 (p0, x0, x1), + z0 = svldnf1sw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_u64.c new file mode 100644 index 00000000000..89cc0ea26b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1sw_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1sw_u64_base: +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_base, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0), + z0 = svldnf1sw_u64 (p0, x0)) + +/* +** ldnf1sw_u64_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1sw z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_index, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 + x1), + z0 = svldnf1sw_u64 (p0, x0 + x1)) + +/* +** ldnf1sw_u64_1: +** ldnf1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_1, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 + svcntd ()), + z0 = svldnf1sw_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1sw_u64_7: +** ldnf1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_7, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1sw_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1sw_u64_8: +** incb x0, all, mul #4 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_8, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1sw_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1sw_u64_m1: +** ldnf1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_m1, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 - svcntd ()), + z0 = svldnf1sw_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1sw_u64_m8: +** ldnf1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_m8, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1sw_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1sw_u64_m9: +** dech x0, all, mul #9 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_u64_m9, svuint64_t, int32_t, + z0 = svldnf1sw_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1sw_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1sw_vnum_u64_0: +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_0, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, 0), + z0 = svldnf1sw_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1sw_vnum_u64_1: +** ldnf1sw z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_1, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, 1), + z0 = svldnf1sw_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1sw_vnum_u64_7: +** ldnf1sw z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_7, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, 7), + z0 = svldnf1sw_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1sw_vnum_u64_8: +** incb x0, all, mul #4 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_8, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, 8), + z0 = svldnf1sw_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1sw_vnum_u64_m1: +** ldnf1sw z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_m1, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, -1), + z0 = svldnf1sw_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1sw_vnum_u64_m8: +** ldnf1sw z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_m8, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, -8), + z0 = svldnf1sw_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1sw_vnum_u64_m9: +** dech x0, all, mul #9 +** ldnf1sw z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_m9, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, -9), + z0 = svldnf1sw_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1sw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1sw z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1sw_vnum_u64_x1, svuint64_t, int32_t, + z0 = svldnf1sw_vnum_u64 (p0, x0, x1), + z0 = svldnf1sw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s16.c new file mode 100644 index 00000000000..2b496a861bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_s16_base: +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_base, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0), + z0 = svldnf1ub_s16 (p0, x0)) + +/* +** ldnf1ub_s16_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_index, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 + x1), + z0 = svldnf1ub_s16 (p0, x0 + x1)) + +/* +** ldnf1ub_s16_1: +** ldnf1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_1, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 + svcnth ()), + z0 = svldnf1ub_s16 (p0, x0 + svcnth ())) + +/* +** ldnf1ub_s16_7: +** ldnf1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_7, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 + svcnth () * 7), + z0 = svldnf1ub_s16 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1ub_s16_8: +** incb x0, all, mul #4 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_8, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 + svcnth () * 8), + z0 = svldnf1ub_s16 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1ub_s16_m1: +** ldnf1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_m1, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 - svcnth ()), + z0 = svldnf1ub_s16 (p0, x0 - svcnth ())) + +/* +** ldnf1ub_s16_m8: +** ldnf1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_m8, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 - svcnth () * 8), + z0 = svldnf1ub_s16 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1ub_s16_m9: +** dech x0, all, mul #9 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s16_m9, svint16_t, uint8_t, + z0 = svldnf1ub_s16 (p0, x0 - svcnth () * 9), + z0 = svldnf1ub_s16 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1ub_vnum_s16_0: +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_0, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, 0), + z0 = svldnf1ub_vnum_s16 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_s16_1: +** ldnf1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_1, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, 1), + z0 = svldnf1ub_vnum_s16 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_s16_7: +** ldnf1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_7, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, 7), + z0 = svldnf1ub_vnum_s16 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_s16_8: +** incb x0, all, mul #4 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_8, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, 8), + z0 = svldnf1ub_vnum_s16 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_s16_m1: +** ldnf1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_m1, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, -1), + z0 = svldnf1ub_vnum_s16 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_s16_m8: +** ldnf1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_m8, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, -8), + z0 = svldnf1ub_vnum_s16 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_s16_m9: +** dech x0, all, mul #9 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_m9, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, -9), + z0 = svldnf1ub_vnum_s16 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_s16_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s16_x1, svint16_t, uint8_t, + z0 = svldnf1ub_vnum_s16 (p0, x0, x1), + z0 = svldnf1ub_vnum_s16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s32.c new file mode 100644 index 00000000000..7d72524b166 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_s32_base: +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_base, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0), + z0 = svldnf1ub_s32 (p0, x0)) + +/* +** ldnf1ub_s32_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_index, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 + x1), + z0 = svldnf1ub_s32 (p0, x0 + x1)) + +/* +** ldnf1ub_s32_1: +** ldnf1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_1, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 + svcntw ()), + z0 = svldnf1ub_s32 (p0, x0 + svcntw ())) + +/* +** ldnf1ub_s32_7: +** ldnf1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_7, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 + svcntw () * 7), + z0 = svldnf1ub_s32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1ub_s32_8: +** incb x0, all, mul #2 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_8, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 + svcntw () * 8), + z0 = svldnf1ub_s32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1ub_s32_m1: +** ldnf1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_m1, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 - svcntw ()), + z0 = svldnf1ub_s32 (p0, x0 - svcntw ())) + +/* +** ldnf1ub_s32_m8: +** ldnf1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_m8, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 - svcntw () * 8), + z0 = svldnf1ub_s32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1ub_s32_m9: +** decw x0, all, mul #9 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s32_m9, svint32_t, uint8_t, + z0 = svldnf1ub_s32 (p0, x0 - svcntw () * 9), + z0 = svldnf1ub_s32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1ub_vnum_s32_0: +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_0, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, 0), + z0 = svldnf1ub_vnum_s32 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_s32_1: +** ldnf1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_1, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, 1), + z0 = svldnf1ub_vnum_s32 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_s32_7: +** ldnf1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_7, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, 7), + z0 = svldnf1ub_vnum_s32 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_s32_8: +** incb x0, all, mul #2 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_8, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, 8), + z0 = svldnf1ub_vnum_s32 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_s32_m1: +** ldnf1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_m1, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, -1), + z0 = svldnf1ub_vnum_s32 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_s32_m8: +** ldnf1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_m8, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, -8), + z0 = svldnf1ub_vnum_s32 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_s32_m9: +** decw x0, all, mul #9 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_m9, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, -9), + z0 = svldnf1ub_vnum_s32 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_s32_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s32_x1, svint32_t, uint8_t, + z0 = svldnf1ub_vnum_s32 (p0, x0, x1), + z0 = svldnf1ub_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s64.c new file mode 100644 index 00000000000..36f14a97856 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_s64_base: +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_base, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0), + z0 = svldnf1ub_s64 (p0, x0)) + +/* +** ldnf1ub_s64_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_index, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 + x1), + z0 = svldnf1ub_s64 (p0, x0 + x1)) + +/* +** ldnf1ub_s64_1: +** ldnf1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_1, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 + svcntd ()), + z0 = svldnf1ub_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1ub_s64_7: +** ldnf1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_7, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1ub_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1ub_s64_8: +** incb x0 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_8, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1ub_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1ub_s64_m1: +** ldnf1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_m1, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 - svcntd ()), + z0 = svldnf1ub_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1ub_s64_m8: +** ldnf1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_m8, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1ub_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1ub_s64_m9: +** decd x0, all, mul #9 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_s64_m9, svint64_t, uint8_t, + z0 = svldnf1ub_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1ub_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1ub_vnum_s64_0: +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_0, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, 0), + z0 = svldnf1ub_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_s64_1: +** ldnf1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_1, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, 1), + z0 = svldnf1ub_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_s64_7: +** ldnf1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_7, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, 7), + z0 = svldnf1ub_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_s64_8: +** incb x0 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_8, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, 8), + z0 = svldnf1ub_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_s64_m1: +** ldnf1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_m1, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, -1), + z0 = svldnf1ub_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_s64_m8: +** ldnf1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_m8, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, -8), + z0 = svldnf1ub_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_s64_m9: +** decd x0, all, mul #9 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_m9, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, -9), + z0 = svldnf1ub_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_s64_x1: +** cntd (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_s64_x1, svint64_t, uint8_t, + z0 = svldnf1ub_vnum_s64 (p0, x0, x1), + z0 = svldnf1ub_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u16.c new file mode 100644 index 00000000000..e0fd3f65285 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u16.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_u16_base: +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_base, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0), + z0 = svldnf1ub_u16 (p0, x0)) + +/* +** ldnf1ub_u16_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.h, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_index, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 + x1), + z0 = svldnf1ub_u16 (p0, x0 + x1)) + +/* +** ldnf1ub_u16_1: +** ldnf1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_1, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 + svcnth ()), + z0 = svldnf1ub_u16 (p0, x0 + svcnth ())) + +/* +** ldnf1ub_u16_7: +** ldnf1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_7, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 + svcnth () * 7), + z0 = svldnf1ub_u16 (p0, x0 + svcnth () * 7)) + +/* +** ldnf1ub_u16_8: +** incb x0, all, mul #4 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_8, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 + svcnth () * 8), + z0 = svldnf1ub_u16 (p0, x0 + svcnth () * 8)) + +/* +** ldnf1ub_u16_m1: +** ldnf1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_m1, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 - svcnth ()), + z0 = svldnf1ub_u16 (p0, x0 - svcnth ())) + +/* +** ldnf1ub_u16_m8: +** ldnf1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_m8, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 - svcnth () * 8), + z0 = svldnf1ub_u16 (p0, x0 - svcnth () * 8)) + +/* +** ldnf1ub_u16_m9: +** dech x0, all, mul #9 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u16_m9, svuint16_t, uint8_t, + z0 = svldnf1ub_u16 (p0, x0 - svcnth () * 9), + z0 = svldnf1ub_u16 (p0, x0 - svcnth () * 9)) + +/* +** ldnf1ub_vnum_u16_0: +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_0, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, 0), + z0 = svldnf1ub_vnum_u16 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_u16_1: +** ldnf1b z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_1, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, 1), + z0 = svldnf1ub_vnum_u16 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_u16_7: +** ldnf1b z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_7, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, 7), + z0 = svldnf1ub_vnum_u16 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_u16_8: +** incb x0, all, mul #4 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_8, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, 8), + z0 = svldnf1ub_vnum_u16 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_u16_m1: +** ldnf1b z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_m1, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, -1), + z0 = svldnf1ub_vnum_u16 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_u16_m8: +** ldnf1b z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_m8, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, -8), + z0 = svldnf1ub_vnum_u16 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_u16_m9: +** dech x0, all, mul #9 +** ldnf1b z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_m9, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, -9), + z0 = svldnf1ub_vnum_u16 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_u16_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u16_x1, svuint16_t, uint8_t, + z0 = svldnf1ub_vnum_u16 (p0, x0, x1), + z0 = svldnf1ub_vnum_u16 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u32.c new file mode 100644 index 00000000000..26ec879a453 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_u32_base: +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_base, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0), + z0 = svldnf1ub_u32 (p0, x0)) + +/* +** ldnf1ub_u32_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_index, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 + x1), + z0 = svldnf1ub_u32 (p0, x0 + x1)) + +/* +** ldnf1ub_u32_1: +** ldnf1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_1, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 + svcntw ()), + z0 = svldnf1ub_u32 (p0, x0 + svcntw ())) + +/* +** ldnf1ub_u32_7: +** ldnf1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_7, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 + svcntw () * 7), + z0 = svldnf1ub_u32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1ub_u32_8: +** incb x0, all, mul #2 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_8, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 + svcntw () * 8), + z0 = svldnf1ub_u32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1ub_u32_m1: +** ldnf1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_m1, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 - svcntw ()), + z0 = svldnf1ub_u32 (p0, x0 - svcntw ())) + +/* +** ldnf1ub_u32_m8: +** ldnf1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_m8, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 - svcntw () * 8), + z0 = svldnf1ub_u32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1ub_u32_m9: +** decw x0, all, mul #9 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u32_m9, svuint32_t, uint8_t, + z0 = svldnf1ub_u32 (p0, x0 - svcntw () * 9), + z0 = svldnf1ub_u32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1ub_vnum_u32_0: +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_0, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, 0), + z0 = svldnf1ub_vnum_u32 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_u32_1: +** ldnf1b z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_1, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, 1), + z0 = svldnf1ub_vnum_u32 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_u32_7: +** ldnf1b z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_7, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, 7), + z0 = svldnf1ub_vnum_u32 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_u32_8: +** incb x0, all, mul #2 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_8, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, 8), + z0 = svldnf1ub_vnum_u32 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_u32_m1: +** ldnf1b z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_m1, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, -1), + z0 = svldnf1ub_vnum_u32 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_u32_m8: +** ldnf1b z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_m8, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, -8), + z0 = svldnf1ub_vnum_u32 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_u32_m9: +** decw x0, all, mul #9 +** ldnf1b z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_m9, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, -9), + z0 = svldnf1ub_vnum_u32 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_u32_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u32_x1, svuint32_t, uint8_t, + z0 = svldnf1ub_vnum_u32 (p0, x0, x1), + z0 = svldnf1ub_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u64.c new file mode 100644 index 00000000000..ae357ce46a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1ub_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1ub_u64_base: +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_base, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0), + z0 = svldnf1ub_u64 (p0, x0)) + +/* +** ldnf1ub_u64_index: +** add (x[0-9]+), x0, x1 +** ldnf1b z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_index, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 + x1), + z0 = svldnf1ub_u64 (p0, x0 + x1)) + +/* +** ldnf1ub_u64_1: +** ldnf1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_1, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 + svcntd ()), + z0 = svldnf1ub_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1ub_u64_7: +** ldnf1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_7, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1ub_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1ub_u64_8: +** incb x0 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_8, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1ub_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1ub_u64_m1: +** ldnf1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_m1, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 - svcntd ()), + z0 = svldnf1ub_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1ub_u64_m8: +** ldnf1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_m8, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1ub_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1ub_u64_m9: +** decd x0, all, mul #9 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_u64_m9, svuint64_t, uint8_t, + z0 = svldnf1ub_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1ub_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1ub_vnum_u64_0: +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_0, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, 0), + z0 = svldnf1ub_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1ub_vnum_u64_1: +** ldnf1b z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_1, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, 1), + z0 = svldnf1ub_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1ub_vnum_u64_7: +** ldnf1b z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_7, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, 7), + z0 = svldnf1ub_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1ub_vnum_u64_8: +** incb x0 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_8, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, 8), + z0 = svldnf1ub_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1ub_vnum_u64_m1: +** ldnf1b z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_m1, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, -1), + z0 = svldnf1ub_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1ub_vnum_u64_m8: +** ldnf1b z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_m8, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, -8), + z0 = svldnf1ub_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1ub_vnum_u64_m9: +** decd x0, all, mul #9 +** ldnf1b z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_m9, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, -9), + z0 = svldnf1ub_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1ub_vnum_u64_x1: +** cntd (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1b z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1ub_vnum_u64_x1, svuint64_t, uint8_t, + z0 = svldnf1ub_vnum_u64 (p0, x0, x1), + z0 = svldnf1ub_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s32.c new file mode 100644 index 00000000000..bb01eab7701 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uh_s32_base: +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_base, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0), + z0 = svldnf1uh_s32 (p0, x0)) + +/* +** ldnf1uh_s32_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_index, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 + x1), + z0 = svldnf1uh_s32 (p0, x0 + x1)) + +/* +** ldnf1uh_s32_1: +** ldnf1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_1, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 + svcntw ()), + z0 = svldnf1uh_s32 (p0, x0 + svcntw ())) + +/* +** ldnf1uh_s32_7: +** ldnf1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_7, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 + svcntw () * 7), + z0 = svldnf1uh_s32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1uh_s32_8: +** incb x0, all, mul #4 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_8, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 + svcntw () * 8), + z0 = svldnf1uh_s32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1uh_s32_m1: +** ldnf1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_m1, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 - svcntw ()), + z0 = svldnf1uh_s32 (p0, x0 - svcntw ())) + +/* +** ldnf1uh_s32_m8: +** ldnf1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_m8, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 - svcntw () * 8), + z0 = svldnf1uh_s32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1uh_s32_m9: +** dech x0, all, mul #9 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s32_m9, svint32_t, uint16_t, + z0 = svldnf1uh_s32 (p0, x0 - svcntw () * 9), + z0 = svldnf1uh_s32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1uh_vnum_s32_0: +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_0, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, 0), + z0 = svldnf1uh_vnum_s32 (p0, x0, 0)) + +/* +** ldnf1uh_vnum_s32_1: +** ldnf1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_1, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, 1), + z0 = svldnf1uh_vnum_s32 (p0, x0, 1)) + +/* +** ldnf1uh_vnum_s32_7: +** ldnf1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_7, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, 7), + z0 = svldnf1uh_vnum_s32 (p0, x0, 7)) + +/* +** ldnf1uh_vnum_s32_8: +** incb x0, all, mul #4 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_8, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, 8), + z0 = svldnf1uh_vnum_s32 (p0, x0, 8)) + +/* +** ldnf1uh_vnum_s32_m1: +** ldnf1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_m1, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, -1), + z0 = svldnf1uh_vnum_s32 (p0, x0, -1)) + +/* +** ldnf1uh_vnum_s32_m8: +** ldnf1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_m8, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, -8), + z0 = svldnf1uh_vnum_s32 (p0, x0, -8)) + +/* +** ldnf1uh_vnum_s32_m9: +** dech x0, all, mul #9 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_m9, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, -9), + z0 = svldnf1uh_vnum_s32 (p0, x0, -9)) + +/* +** ldnf1uh_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s32_x1, svint32_t, uint16_t, + z0 = svldnf1uh_vnum_s32 (p0, x0, x1), + z0 = svldnf1uh_vnum_s32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s64.c new file mode 100644 index 00000000000..285caf66b93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uh_s64_base: +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_base, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0), + z0 = svldnf1uh_s64 (p0, x0)) + +/* +** ldnf1uh_s64_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_index, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 + x1), + z0 = svldnf1uh_s64 (p0, x0 + x1)) + +/* +** ldnf1uh_s64_1: +** ldnf1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_1, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 + svcntd ()), + z0 = svldnf1uh_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1uh_s64_7: +** ldnf1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_7, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1uh_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1uh_s64_8: +** incb x0, all, mul #2 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_8, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1uh_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1uh_s64_m1: +** ldnf1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_m1, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 - svcntd ()), + z0 = svldnf1uh_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1uh_s64_m8: +** ldnf1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_m8, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1uh_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1uh_s64_m9: +** decw x0, all, mul #9 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_s64_m9, svint64_t, uint16_t, + z0 = svldnf1uh_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1uh_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1uh_vnum_s64_0: +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_0, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, 0), + z0 = svldnf1uh_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1uh_vnum_s64_1: +** ldnf1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_1, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, 1), + z0 = svldnf1uh_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1uh_vnum_s64_7: +** ldnf1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_7, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, 7), + z0 = svldnf1uh_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1uh_vnum_s64_8: +** incb x0, all, mul #2 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_8, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, 8), + z0 = svldnf1uh_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1uh_vnum_s64_m1: +** ldnf1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_m1, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, -1), + z0 = svldnf1uh_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1uh_vnum_s64_m8: +** ldnf1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_m8, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, -8), + z0 = svldnf1uh_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1uh_vnum_s64_m9: +** decw x0, all, mul #9 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_m9, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, -9), + z0 = svldnf1uh_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1uh_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_s64_x1, svint64_t, uint16_t, + z0 = svldnf1uh_vnum_s64 (p0, x0, x1), + z0 = svldnf1uh_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u32.c new file mode 100644 index 00000000000..3255d94386e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u32.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uh_u32_base: +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_base, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0), + z0 = svldnf1uh_u32 (p0, x0)) + +/* +** ldnf1uh_u32_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.s, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_index, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 + x1), + z0 = svldnf1uh_u32 (p0, x0 + x1)) + +/* +** ldnf1uh_u32_1: +** ldnf1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_1, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 + svcntw ()), + z0 = svldnf1uh_u32 (p0, x0 + svcntw ())) + +/* +** ldnf1uh_u32_7: +** ldnf1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_7, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 + svcntw () * 7), + z0 = svldnf1uh_u32 (p0, x0 + svcntw () * 7)) + +/* +** ldnf1uh_u32_8: +** incb x0, all, mul #4 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_8, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 + svcntw () * 8), + z0 = svldnf1uh_u32 (p0, x0 + svcntw () * 8)) + +/* +** ldnf1uh_u32_m1: +** ldnf1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_m1, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 - svcntw ()), + z0 = svldnf1uh_u32 (p0, x0 - svcntw ())) + +/* +** ldnf1uh_u32_m8: +** ldnf1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_m8, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 - svcntw () * 8), + z0 = svldnf1uh_u32 (p0, x0 - svcntw () * 8)) + +/* +** ldnf1uh_u32_m9: +** dech x0, all, mul #9 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u32_m9, svuint32_t, uint16_t, + z0 = svldnf1uh_u32 (p0, x0 - svcntw () * 9), + z0 = svldnf1uh_u32 (p0, x0 - svcntw () * 9)) + +/* +** ldnf1uh_vnum_u32_0: +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_0, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, 0), + z0 = svldnf1uh_vnum_u32 (p0, x0, 0)) + +/* +** ldnf1uh_vnum_u32_1: +** ldnf1h z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_1, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, 1), + z0 = svldnf1uh_vnum_u32 (p0, x0, 1)) + +/* +** ldnf1uh_vnum_u32_7: +** ldnf1h z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_7, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, 7), + z0 = svldnf1uh_vnum_u32 (p0, x0, 7)) + +/* +** ldnf1uh_vnum_u32_8: +** incb x0, all, mul #4 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_8, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, 8), + z0 = svldnf1uh_vnum_u32 (p0, x0, 8)) + +/* +** ldnf1uh_vnum_u32_m1: +** ldnf1h z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_m1, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, -1), + z0 = svldnf1uh_vnum_u32 (p0, x0, -1)) + +/* +** ldnf1uh_vnum_u32_m8: +** ldnf1h z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_m8, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, -8), + z0 = svldnf1uh_vnum_u32 (p0, x0, -8)) + +/* +** ldnf1uh_vnum_u32_m9: +** dech x0, all, mul #9 +** ldnf1h z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_m9, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, -9), + z0 = svldnf1uh_vnum_u32 (p0, x0, -9)) + +/* +** ldnf1uh_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u32_x1, svuint32_t, uint16_t, + z0 = svldnf1uh_vnum_u32 (p0, x0, x1), + z0 = svldnf1uh_vnum_u32 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u64.c new file mode 100644 index 00000000000..69fe0cb56df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uh_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uh_u64_base: +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_base, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0), + z0 = svldnf1uh_u64 (p0, x0)) + +/* +** ldnf1uh_u64_index: +** add (x[0-9]+), x0, x1, lsl 1 +** ldnf1h z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_index, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 + x1), + z0 = svldnf1uh_u64 (p0, x0 + x1)) + +/* +** ldnf1uh_u64_1: +** ldnf1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_1, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 + svcntd ()), + z0 = svldnf1uh_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1uh_u64_7: +** ldnf1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_7, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1uh_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1uh_u64_8: +** incb x0, all, mul #2 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_8, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1uh_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1uh_u64_m1: +** ldnf1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_m1, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 - svcntd ()), + z0 = svldnf1uh_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1uh_u64_m8: +** ldnf1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_m8, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1uh_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1uh_u64_m9: +** decw x0, all, mul #9 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_u64_m9, svuint64_t, uint16_t, + z0 = svldnf1uh_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1uh_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1uh_vnum_u64_0: +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_0, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, 0), + z0 = svldnf1uh_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1uh_vnum_u64_1: +** ldnf1h z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_1, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, 1), + z0 = svldnf1uh_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1uh_vnum_u64_7: +** ldnf1h z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_7, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, 7), + z0 = svldnf1uh_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1uh_vnum_u64_8: +** incb x0, all, mul #2 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_8, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, 8), + z0 = svldnf1uh_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1uh_vnum_u64_m1: +** ldnf1h z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_m1, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, -1), + z0 = svldnf1uh_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1uh_vnum_u64_m8: +** ldnf1h z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_m8, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, -8), + z0 = svldnf1uh_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1uh_vnum_u64_m9: +** decw x0, all, mul #9 +** ldnf1h z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_m9, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, -9), + z0 = svldnf1uh_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1uh_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1h z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uh_vnum_u64_x1, svuint64_t, uint16_t, + z0 = svldnf1uh_vnum_u64 (p0, x0, x1), + z0 = svldnf1uh_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_s64.c new file mode 100644 index 00000000000..e20f2c3ced4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_s64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uw_s64_base: +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_base, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0), + z0 = svldnf1uw_s64 (p0, x0)) + +/* +** ldnf1uw_s64_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1w z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_index, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 + x1), + z0 = svldnf1uw_s64 (p0, x0 + x1)) + +/* +** ldnf1uw_s64_1: +** ldnf1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_1, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 + svcntd ()), + z0 = svldnf1uw_s64 (p0, x0 + svcntd ())) + +/* +** ldnf1uw_s64_7: +** ldnf1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_7, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 + svcntd () * 7), + z0 = svldnf1uw_s64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1uw_s64_8: +** incb x0, all, mul #4 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_8, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 + svcntd () * 8), + z0 = svldnf1uw_s64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1uw_s64_m1: +** ldnf1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_m1, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 - svcntd ()), + z0 = svldnf1uw_s64 (p0, x0 - svcntd ())) + +/* +** ldnf1uw_s64_m8: +** ldnf1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_m8, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 - svcntd () * 8), + z0 = svldnf1uw_s64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1uw_s64_m9: +** dech x0, all, mul #9 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_s64_m9, svint64_t, uint32_t, + z0 = svldnf1uw_s64 (p0, x0 - svcntd () * 9), + z0 = svldnf1uw_s64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1uw_vnum_s64_0: +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_0, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, 0), + z0 = svldnf1uw_vnum_s64 (p0, x0, 0)) + +/* +** ldnf1uw_vnum_s64_1: +** ldnf1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_1, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, 1), + z0 = svldnf1uw_vnum_s64 (p0, x0, 1)) + +/* +** ldnf1uw_vnum_s64_7: +** ldnf1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_7, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, 7), + z0 = svldnf1uw_vnum_s64 (p0, x0, 7)) + +/* +** ldnf1uw_vnum_s64_8: +** incb x0, all, mul #4 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_8, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, 8), + z0 = svldnf1uw_vnum_s64 (p0, x0, 8)) + +/* +** ldnf1uw_vnum_s64_m1: +** ldnf1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_m1, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, -1), + z0 = svldnf1uw_vnum_s64 (p0, x0, -1)) + +/* +** ldnf1uw_vnum_s64_m8: +** ldnf1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_m8, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, -8), + z0 = svldnf1uw_vnum_s64 (p0, x0, -8)) + +/* +** ldnf1uw_vnum_s64_m9: +** dech x0, all, mul #9 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_m9, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, -9), + z0 = svldnf1uw_vnum_s64 (p0, x0, -9)) + +/* +** ldnf1uw_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_s64_x1, svint64_t, uint32_t, + z0 = svldnf1uw_vnum_s64 (p0, x0, x1), + z0 = svldnf1uw_vnum_s64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_u64.c new file mode 100644 index 00000000000..f9fdd65ca60 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnf1uw_u64.c @@ -0,0 +1,154 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnf1uw_u64_base: +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_base, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0), + z0 = svldnf1uw_u64 (p0, x0)) + +/* +** ldnf1uw_u64_index: +** add (x[0-9]+), x0, x1, lsl 2 +** ldnf1w z0\.d, p0/z, \[\1\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_index, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 + x1), + z0 = svldnf1uw_u64 (p0, x0 + x1)) + +/* +** ldnf1uw_u64_1: +** ldnf1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_1, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 + svcntd ()), + z0 = svldnf1uw_u64 (p0, x0 + svcntd ())) + +/* +** ldnf1uw_u64_7: +** ldnf1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_7, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 + svcntd () * 7), + z0 = svldnf1uw_u64 (p0, x0 + svcntd () * 7)) + +/* +** ldnf1uw_u64_8: +** incb x0, all, mul #4 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_8, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 + svcntd () * 8), + z0 = svldnf1uw_u64 (p0, x0 + svcntd () * 8)) + +/* +** ldnf1uw_u64_m1: +** ldnf1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_m1, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 - svcntd ()), + z0 = svldnf1uw_u64 (p0, x0 - svcntd ())) + +/* +** ldnf1uw_u64_m8: +** ldnf1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_m8, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 - svcntd () * 8), + z0 = svldnf1uw_u64 (p0, x0 - svcntd () * 8)) + +/* +** ldnf1uw_u64_m9: +** dech x0, all, mul #9 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_u64_m9, svuint64_t, uint32_t, + z0 = svldnf1uw_u64 (p0, x0 - svcntd () * 9), + z0 = svldnf1uw_u64 (p0, x0 - svcntd () * 9)) + +/* +** ldnf1uw_vnum_u64_0: +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_0, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, 0), + z0 = svldnf1uw_vnum_u64 (p0, x0, 0)) + +/* +** ldnf1uw_vnum_u64_1: +** ldnf1w z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_1, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, 1), + z0 = svldnf1uw_vnum_u64 (p0, x0, 1)) + +/* +** ldnf1uw_vnum_u64_7: +** ldnf1w z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_7, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, 7), + z0 = svldnf1uw_vnum_u64 (p0, x0, 7)) + +/* +** ldnf1uw_vnum_u64_8: +** incb x0, all, mul #4 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_8, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, 8), + z0 = svldnf1uw_vnum_u64 (p0, x0, 8)) + +/* +** ldnf1uw_vnum_u64_m1: +** ldnf1w z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_m1, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, -1), + z0 = svldnf1uw_vnum_u64 (p0, x0, -1)) + +/* +** ldnf1uw_vnum_u64_m8: +** ldnf1w z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_m8, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, -8), + z0 = svldnf1uw_vnum_u64 (p0, x0, -8)) + +/* +** ldnf1uw_vnum_u64_m9: +** dech x0, all, mul #9 +** ldnf1w z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_m9, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, -9), + z0 = svldnf1uw_vnum_u64 (p0, x0, -9)) + +/* +** ldnf1uw_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnf1w z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnf1uw_vnum_u64_x1, svuint64_t, uint32_t, + z0 = svldnf1uw_vnum_u64 (p0, x0, x1), + z0 = svldnf1uw_vnum_u64 (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f16.c new file mode 100644 index 00000000000..925391d991c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_f16_base: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f16_base, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_f16_index: +** ldnt1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldnt1_f16_index, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_f16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f16_1, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 + svcnth ()), + z0 = svldnt1 (p0, x0 + svcnth ())) + +/* +** ldnt1_f16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f16_7, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 + svcnth () * 7), + z0 = svldnt1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f16_8, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 + svcnth () * 8), + z0 = svldnt1 (p0, x0 + svcnth () * 8)) + +/* +** ldnt1_f16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f16_m1, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 - svcnth ()), + z0 = svldnt1 (p0, x0 - svcnth ())) + +/* +** ldnt1_f16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f16_m8, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 - svcnth () * 8), + z0 = svldnt1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f16_m9, svfloat16_t, float16_t, + z0 = svldnt1_f16 (p0, x0 - svcnth () * 9), + z0 = svldnt1 (p0, x0 - svcnth () * 9)) + +/* +** ldnt1_vnum_f16_0: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_0, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_f16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_1, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_f16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_7, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_8, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_f16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_m1, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_f16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_m8, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_m9, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f16_x1, svfloat16_t, float16_t, + z0 = svldnt1_vnum_f16 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f32.c new file mode 100644 index 00000000000..b8924c108e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_f32_base: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f32_base, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_f32_index: +** ldnt1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldnt1_f32_index, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_f32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f32_1, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 + svcntw ()), + z0 = svldnt1 (p0, x0 + svcntw ())) + +/* +** ldnt1_f32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f32_7, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 + svcntw () * 7), + z0 = svldnt1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f32_8, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 + svcntw () * 8), + z0 = svldnt1 (p0, x0 + svcntw () * 8)) + +/* +** ldnt1_f32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f32_m1, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 - svcntw ()), + z0 = svldnt1 (p0, x0 - svcntw ())) + +/* +** ldnt1_f32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f32_m8, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 - svcntw () * 8), + z0 = svldnt1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f32_m9, svfloat32_t, float32_t, + z0 = svldnt1_f32 (p0, x0 - svcntw () * 9), + z0 = svldnt1 (p0, x0 - svcntw () * 9)) + +/* +** ldnt1_vnum_f32_0: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_0, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_f32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_1, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_f32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_7, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_8, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_f32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_m1, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_f32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_m8, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_m9, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f32_x1, svfloat32_t, float32_t, + z0 = svldnt1_vnum_f32 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f64.c new file mode 100644 index 00000000000..890dcd1f00e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_f64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_f64_base: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f64_base, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_f64_index: +** ldnt1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldnt1_f64_index, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_f64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f64_1, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 + svcntd ()), + z0 = svldnt1 (p0, x0 + svcntd ())) + +/* +** ldnt1_f64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f64_7, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 + svcntd () * 7), + z0 = svldnt1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f64_8, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 + svcntd () * 8), + z0 = svldnt1 (p0, x0 + svcntd () * 8)) + +/* +** ldnt1_f64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f64_m1, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 - svcntd ()), + z0 = svldnt1 (p0, x0 - svcntd ())) + +/* +** ldnt1_f64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_f64_m8, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 - svcntd () * 8), + z0 = svldnt1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_f64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_f64_m9, svfloat64_t, float64_t, + z0 = svldnt1_f64 (p0, x0 - svcntd () * 9), + z0 = svldnt1 (p0, x0 - svcntd () * 9)) + +/* +** ldnt1_vnum_f64_0: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_0, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_f64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_1, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_f64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_7, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_8, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_f64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_m1, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_f64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_m8, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_f64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_m9, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_f64_x1, svfloat64_t, float64_t, + z0 = svldnt1_vnum_f64 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s16.c new file mode 100644 index 00000000000..5abcee71826 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_s16_base: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s16_base, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_s16_index: +** ldnt1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldnt1_s16_index, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_s16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s16_1, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 + svcnth ()), + z0 = svldnt1 (p0, x0 + svcnth ())) + +/* +** ldnt1_s16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s16_7, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 + svcnth () * 7), + z0 = svldnt1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s16_8, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 + svcnth () * 8), + z0 = svldnt1 (p0, x0 + svcnth () * 8)) + +/* +** ldnt1_s16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s16_m1, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 - svcnth ()), + z0 = svldnt1 (p0, x0 - svcnth ())) + +/* +** ldnt1_s16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s16_m8, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 - svcnth () * 8), + z0 = svldnt1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s16_m9, svint16_t, int16_t, + z0 = svldnt1_s16 (p0, x0 - svcnth () * 9), + z0 = svldnt1 (p0, x0 - svcnth () * 9)) + +/* +** ldnt1_vnum_s16_0: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_0, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_s16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_1, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_s16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_7, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_8, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_s16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_m1, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_s16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_m8, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_m9, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s16_x1, svint16_t, int16_t, + z0 = svldnt1_vnum_s16 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s32.c new file mode 100644 index 00000000000..3e3c8aa6fc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_s32_base: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s32_base, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_s32_index: +** ldnt1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldnt1_s32_index, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_s32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s32_1, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 + svcntw ()), + z0 = svldnt1 (p0, x0 + svcntw ())) + +/* +** ldnt1_s32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s32_7, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 + svcntw () * 7), + z0 = svldnt1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s32_8, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 + svcntw () * 8), + z0 = svldnt1 (p0, x0 + svcntw () * 8)) + +/* +** ldnt1_s32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s32_m1, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 - svcntw ()), + z0 = svldnt1 (p0, x0 - svcntw ())) + +/* +** ldnt1_s32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s32_m8, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 - svcntw () * 8), + z0 = svldnt1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s32_m9, svint32_t, int32_t, + z0 = svldnt1_s32 (p0, x0 - svcntw () * 9), + z0 = svldnt1 (p0, x0 - svcntw () * 9)) + +/* +** ldnt1_vnum_s32_0: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_0, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_s32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_1, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_s32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_7, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_8, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_s32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_m1, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_s32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_m8, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_m9, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s32_x1, svint32_t, int32_t, + z0 = svldnt1_vnum_s32 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s64.c new file mode 100644 index 00000000000..a06bf6195de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_s64_base: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s64_base, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_s64_index: +** ldnt1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldnt1_s64_index, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_s64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s64_1, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 + svcntd ()), + z0 = svldnt1 (p0, x0 + svcntd ())) + +/* +** ldnt1_s64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s64_7, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 + svcntd () * 7), + z0 = svldnt1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s64_8, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 + svcntd () * 8), + z0 = svldnt1 (p0, x0 + svcntd () * 8)) + +/* +** ldnt1_s64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s64_m1, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 - svcntd ()), + z0 = svldnt1 (p0, x0 - svcntd ())) + +/* +** ldnt1_s64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s64_m8, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 - svcntd () * 8), + z0 = svldnt1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s64_m9, svint64_t, int64_t, + z0 = svldnt1_s64 (p0, x0 - svcntd () * 9), + z0 = svldnt1 (p0, x0 - svcntd () * 9)) + +/* +** ldnt1_vnum_s64_0: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_0, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_s64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_1, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_s64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_7, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_8, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_s64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_m1, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_s64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_m8, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_m9, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s64_x1, svint64_t, int64_t, + z0 = svldnt1_vnum_s64 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s8.c new file mode 100644 index 00000000000..58591d935ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_s8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_s8_base: +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s8_base, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_s8_index: +** ldnt1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldnt1_s8_index, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_s8_1: +** ldnt1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s8_1, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 + svcntb ()), + z0 = svldnt1 (p0, x0 + svcntb ())) + +/* +** ldnt1_s8_7: +** ldnt1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s8_7, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 + svcntb () * 7), + z0 = svldnt1 (p0, x0 + svcntb () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s8_8: +** incb x0, all, mul #8 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s8_8, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 + svcntb () * 8), + z0 = svldnt1 (p0, x0 + svcntb () * 8)) + +/* +** ldnt1_s8_m1: +** ldnt1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s8_m1, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 - svcntb ()), + z0 = svldnt1 (p0, x0 - svcntb ())) + +/* +** ldnt1_s8_m8: +** ldnt1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_s8_m8, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 - svcntb () * 8), + z0 = svldnt1 (p0, x0 - svcntb () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_s8_m9: +** decb x0, all, mul #9 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_s8_m9, svint8_t, int8_t, + z0 = svldnt1_s8 (p0, x0 - svcntb () * 9), + z0 = svldnt1 (p0, x0 - svcntb () * 9)) + +/* +** ldnt1_vnum_s8_0: +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_0, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_s8_1: +** ldnt1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_1, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_s8_7: +** ldnt1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_7, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s8_8: +** incb x0, all, mul #8 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_8, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_s8_m1: +** ldnt1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_m1, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_s8_m8: +** ldnt1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_m8, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_s8_m9: +** decb x0, all, mul #9 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_m9, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* +** ldnt1_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnt1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldnt1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldnt1_vnum_s8_x1, svint8_t, int8_t, + z0 = svldnt1_vnum_s8 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u16.c new file mode 100644 index 00000000000..ec6c1f8cb93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_u16_base: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u16_base, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_u16_index: +** ldnt1h z0\.h, p0/z, \[x0, x1, lsl 1\] +** ret +*/ +TEST_LOAD (ldnt1_u16_index, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_u16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u16_1, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 + svcnth ()), + z0 = svldnt1 (p0, x0 + svcnth ())) + +/* +** ldnt1_u16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u16_7, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 + svcnth () * 7), + z0 = svldnt1 (p0, x0 + svcnth () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u16_8, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 + svcnth () * 8), + z0 = svldnt1 (p0, x0 + svcnth () * 8)) + +/* +** ldnt1_u16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u16_m1, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 - svcnth ()), + z0 = svldnt1 (p0, x0 - svcnth ())) + +/* +** ldnt1_u16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u16_m8, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 - svcnth () * 8), + z0 = svldnt1 (p0, x0 - svcnth () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u16_m9, svuint16_t, uint16_t, + z0 = svldnt1_u16 (p0, x0 - svcnth () * 9), + z0 = svldnt1 (p0, x0 - svcnth () * 9)) + +/* +** ldnt1_vnum_u16_0: +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_0, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_u16_1: +** ldnt1h z0\.h, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_1, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_u16_7: +** ldnt1h z0\.h, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_7, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u16_8: +** incb x0, all, mul #8 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_8, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_u16_m1: +** ldnt1h z0\.h, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_m1, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_u16_m8: +** ldnt1h z0\.h, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_m8, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u16_m9: +** decb x0, all, mul #9 +** ldnt1h z0\.h, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_m9, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1h z0\.h, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u16_x1, svuint16_t, uint16_t, + z0 = svldnt1_vnum_u16 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u32.c new file mode 100644 index 00000000000..eab8e8a227d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_u32_base: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u32_base, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_u32_index: +** ldnt1w z0\.s, p0/z, \[x0, x1, lsl 2\] +** ret +*/ +TEST_LOAD (ldnt1_u32_index, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_u32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u32_1, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 + svcntw ()), + z0 = svldnt1 (p0, x0 + svcntw ())) + +/* +** ldnt1_u32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u32_7, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 + svcntw () * 7), + z0 = svldnt1 (p0, x0 + svcntw () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u32_8, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 + svcntw () * 8), + z0 = svldnt1 (p0, x0 + svcntw () * 8)) + +/* +** ldnt1_u32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u32_m1, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 - svcntw ()), + z0 = svldnt1 (p0, x0 - svcntw ())) + +/* +** ldnt1_u32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u32_m8, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 - svcntw () * 8), + z0 = svldnt1 (p0, x0 - svcntw () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u32_m9, svuint32_t, uint32_t, + z0 = svldnt1_u32 (p0, x0 - svcntw () * 9), + z0 = svldnt1 (p0, x0 - svcntw () * 9)) + +/* +** ldnt1_vnum_u32_0: +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_0, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_u32_1: +** ldnt1w z0\.s, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_1, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_u32_7: +** ldnt1w z0\.s, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_7, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u32_8: +** incb x0, all, mul #8 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_8, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_u32_m1: +** ldnt1w z0\.s, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_m1, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_u32_m8: +** ldnt1w z0\.s, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_m8, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u32_m9: +** decb x0, all, mul #9 +** ldnt1w z0\.s, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_m9, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1w z0\.s, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u32_x1, svuint32_t, uint32_t, + z0 = svldnt1_vnum_u32 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u64.c new file mode 100644 index 00000000000..16fce1c896a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_u64_base: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u64_base, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_u64_index: +** ldnt1d z0\.d, p0/z, \[x0, x1, lsl 3\] +** ret +*/ +TEST_LOAD (ldnt1_u64_index, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_u64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u64_1, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 + svcntd ()), + z0 = svldnt1 (p0, x0 + svcntd ())) + +/* +** ldnt1_u64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u64_7, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 + svcntd () * 7), + z0 = svldnt1 (p0, x0 + svcntd () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u64_8, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 + svcntd () * 8), + z0 = svldnt1 (p0, x0 + svcntd () * 8)) + +/* +** ldnt1_u64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u64_m1, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 - svcntd ()), + z0 = svldnt1 (p0, x0 - svcntd ())) + +/* +** ldnt1_u64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u64_m8, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 - svcntd () * 8), + z0 = svldnt1 (p0, x0 - svcntd () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u64_m9, svuint64_t, uint64_t, + z0 = svldnt1_u64 (p0, x0 - svcntd () * 9), + z0 = svldnt1 (p0, x0 - svcntd () * 9)) + +/* +** ldnt1_vnum_u64_0: +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_0, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_u64_1: +** ldnt1d z0\.d, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_1, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_u64_7: +** ldnt1d z0\.d, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_7, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u64_8: +** incb x0, all, mul #8 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_8, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_u64_m1: +** ldnt1d z0\.d, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_m1, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_u64_m8: +** ldnt1d z0\.d, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_m8, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u64_m9: +** decb x0, all, mul #9 +** ldnt1d z0\.d, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_m9, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** ldnt1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** ldnt1d z0\.d, p0/z, \[\2\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u64_x1, svuint64_t, uint64_t, + z0 = svldnt1_vnum_u64 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u8.c new file mode 100644 index 00000000000..6dcbcec6284 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ldnt1_u8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ldnt1_u8_base: +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u8_base, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0), + z0 = svldnt1 (p0, x0)) + +/* +** ldnt1_u8_index: +** ldnt1b z0\.b, p0/z, \[x0, x1\] +** ret +*/ +TEST_LOAD (ldnt1_u8_index, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 + x1), + z0 = svldnt1 (p0, x0 + x1)) + +/* +** ldnt1_u8_1: +** ldnt1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u8_1, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 + svcntb ()), + z0 = svldnt1 (p0, x0 + svcntb ())) + +/* +** ldnt1_u8_7: +** ldnt1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u8_7, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 + svcntb () * 7), + z0 = svldnt1 (p0, x0 + svcntb () * 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u8_8: +** incb x0, all, mul #8 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u8_8, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 + svcntb () * 8), + z0 = svldnt1 (p0, x0 + svcntb () * 8)) + +/* +** ldnt1_u8_m1: +** ldnt1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u8_m1, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 - svcntb ()), + z0 = svldnt1 (p0, x0 - svcntb ())) + +/* +** ldnt1_u8_m8: +** ldnt1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_u8_m8, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 - svcntb () * 8), + z0 = svldnt1 (p0, x0 - svcntb () * 8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_u8_m9: +** decb x0, all, mul #9 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_u8_m9, svuint8_t, uint8_t, + z0 = svldnt1_u8 (p0, x0 - svcntb () * 9), + z0 = svldnt1 (p0, x0 - svcntb () * 9)) + +/* +** ldnt1_vnum_u8_0: +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_0, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, 0), + z0 = svldnt1_vnum (p0, x0, 0)) + +/* +** ldnt1_vnum_u8_1: +** ldnt1b z0\.b, p0/z, \[x0, #1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_1, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, 1), + z0 = svldnt1_vnum (p0, x0, 1)) + +/* +** ldnt1_vnum_u8_7: +** ldnt1b z0\.b, p0/z, \[x0, #7, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_7, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, 7), + z0 = svldnt1_vnum (p0, x0, 7)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u8_8: +** incb x0, all, mul #8 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_8, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, 8), + z0 = svldnt1_vnum (p0, x0, 8)) + +/* +** ldnt1_vnum_u8_m1: +** ldnt1b z0\.b, p0/z, \[x0, #-1, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_m1, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, -1), + z0 = svldnt1_vnum (p0, x0, -1)) + +/* +** ldnt1_vnum_u8_m8: +** ldnt1b z0\.b, p0/z, \[x0, #-8, mul vl\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_m8, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, -8), + z0 = svldnt1_vnum (p0, x0, -8)) + +/* Moving the constant into a register would also be OK. */ +/* +** ldnt1_vnum_u8_m9: +** decb x0, all, mul #9 +** ldnt1b z0\.b, p0/z, \[x0\] +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_m9, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, -9), + z0 = svldnt1_vnum (p0, x0, -9)) + +/* +** ldnt1_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** ldnt1b z0\.b, p0/z, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** ldnt1b z0\.b, p0/z, \[x0, \3\] +** ) +** ret +*/ +TEST_LOAD (ldnt1_vnum_u8_x1, svuint8_t, uint8_t, + z0 = svldnt1_vnum_u8 (p0, x0, x1), + z0 = svldnt1_vnum (p0, x0, x1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f16.c new file mode 100644 index 00000000000..aa6d94bbc68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_f16: +** cnth x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_f16, uint64_t, svfloat16_t, + x0 = svlen_f16 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f32.c new file mode 100644 index 00000000000..1dd50cee09b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_f32: +** cntw x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_f32, uint64_t, svfloat32_t, + x0 = svlen_f32 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f64.c new file mode 100644 index 00000000000..1f210653ee2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_f64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_f64: +** cntd x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_f64, uint64_t, svfloat64_t, + x0 = svlen_f64 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s16.c new file mode 100644 index 00000000000..f567961827f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_s16: +** cnth x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_s16, uint64_t, svint16_t, + x0 = svlen_s16 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s32.c new file mode 100644 index 00000000000..662fac177d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_s32: +** cntw x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_s32, uint64_t, svint32_t, + x0 = svlen_s32 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s64.c new file mode 100644 index 00000000000..f95770302a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_s64: +** cntd x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_s64, uint64_t, svint64_t, + x0 = svlen_s64 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s8.c new file mode 100644 index 00000000000..6ed8a7177a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_s8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_s8: +** cntb x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_s8, uint64_t, svint8_t, + x0 = svlen_s8 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u16.c new file mode 100644 index 00000000000..13692c927d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u16.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_u16: +** cnth x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_u16, uint64_t, svuint16_t, + x0 = svlen_u16 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u32.c new file mode 100644 index 00000000000..b03146089b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u32.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_u32: +** cntw x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_u32, uint64_t, svuint32_t, + x0 = svlen_u32 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u64.c new file mode 100644 index 00000000000..11f2e4b817d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u64.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_u64: +** cntd x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_u64, uint64_t, svuint64_t, + x0 = svlen_u64 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u8.c new file mode 100644 index 00000000000..fbd39a43225 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/len_u8.c @@ -0,0 +1,12 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** len_x0_u8: +** cntb x0 +** ret +*/ +TEST_REDUCTION_X (len_x0_u8, uint64_t, svuint8_t, + x0 = svlen_u8 (z0), + x0 = svlen (z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c new file mode 100644 index 00000000000..edaaca5f155 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (lsl_s16_m_tied1, svint16_t, svuint16_t, + z0 = svlsl_s16_m (p0, z0, z4), + z0 = svlsl_m (p0, z0, z4)) + +/* +** lsl_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** lsl z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (lsl_s16_m_tied2, svint16_t, svuint16_t, + z0_res = svlsl_s16_m (p0, z4, z0), + z0_res = svlsl_m (p0, z4, z0)) + +/* +** lsl_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (lsl_s16_m_untied, svint16_t, svuint16_t, + z0 = svlsl_s16_m (p0, z1, z4), + z0 = svlsl_m (p0, z1, z4)) + +/* +** lsl_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_m_tied1, svint16_t, uint16_t, + z0 = svlsl_n_s16_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_m_untied, svint16_t, uint16_t, + z0 = svlsl_n_s16_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_m_tied1, svint16_t, + z0 = svlsl_n_s16_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_m_untied, svint16_t, + z0 = svlsl_n_s16_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_15_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_m_tied1, svint16_t, + z0 = svlsl_n_s16_m (p0, z0, 15), + z0 = svlsl_m (p0, z0, 15)) + +/* +** lsl_15_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_m_untied, svint16_t, + z0 = svlsl_n_s16_m (p0, z1, 15), + z0 = svlsl_m (p0, z1, 15)) + +/* +** lsl_16_s16_m_tied1: +** mov (z[0-9]+\.h), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_m_tied1, svint16_t, + z0 = svlsl_n_s16_m (p0, z0, 16), + z0 = svlsl_m (p0, z0, 16)) + +/* +** lsl_16_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #16 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_m_untied, svint16_t, + z0 = svlsl_n_s16_m (p0, z1, 16), + z0 = svlsl_m (p0, z1, 16)) + +/* +** lsl_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (lsl_s16_z_tied1, svint16_t, svuint16_t, + z0 = svlsl_s16_z (p0, z0, z4), + z0 = svlsl_z (p0, z0, z4)) + +/* +** lsl_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** lslr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z_REV (lsl_s16_z_tied2, svint16_t, svuint16_t, + z0_res = svlsl_s16_z (p0, z4, z0), + z0_res = svlsl_z (p0, z4, z0)) + +/* +** lsl_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, z4\.h +** | +** movprfx z0\.h, p0/z, z4\.h +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s16_z_untied, svint16_t, svuint16_t, + z0 = svlsl_s16_z (p0, z1, z4), + z0 = svlsl_z (p0, z1, z4)) + +/* +** lsl_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_z_tied1, svint16_t, uint16_t, + z0 = svlsl_n_s16_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_z_untied, svint16_t, uint16_t, + z0 = svlsl_n_s16_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_z_tied1, svint16_t, + z0 = svlsl_n_s16_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_z_untied, svint16_t, + z0 = svlsl_n_s16_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_15_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_z_tied1, svint16_t, + z0 = svlsl_n_s16_z (p0, z0, 15), + z0 = svlsl_z (p0, z0, 15)) + +/* +** lsl_15_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_z_untied, svint16_t, + z0 = svlsl_n_s16_z (p0, z1, 15), + z0 = svlsl_z (p0, z1, 15)) + +/* +** lsl_16_s16_z_tied1: +** mov (z[0-9]+\.h), #16 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_z_tied1, svint16_t, + z0 = svlsl_n_s16_z (p0, z0, 16), + z0 = svlsl_z (p0, z0, 16)) + +/* +** lsl_16_s16_z_untied: +** mov (z[0-9]+\.h), #16 +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_z_untied, svint16_t, + z0 = svlsl_n_s16_z (p0, z1, 16), + z0 = svlsl_z (p0, z1, 16)) + +/* +** lsl_s16_x_tied1: +** lsl z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (lsl_s16_x_tied1, svint16_t, svuint16_t, + z0 = svlsl_s16_x (p0, z0, z4), + z0 = svlsl_x (p0, z0, z4)) + +/* +** lsl_s16_x_tied2: +** lslr z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z_REV (lsl_s16_x_tied2, svint16_t, svuint16_t, + z0_res = svlsl_s16_x (p0, z4, z0), + z0_res = svlsl_x (p0, z4, z0)) + +/* +** lsl_s16_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z4\.h +** | +** movprfx z0, z4 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s16_x_untied, svint16_t, svuint16_t, + z0 = svlsl_s16_x (p0, z1, z4), + z0 = svlsl_x (p0, z1, z4)) + +/* +** lsl_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_x_tied1, svint16_t, uint16_t, + z0 = svlsl_n_s16_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_s16_x_untied: +** mov z0\.h, w0 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s16_x_untied, svint16_t, uint16_t, + z0 = svlsl_n_s16_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_s16_x_tied1: +** lsl z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_x_tied1, svint16_t, + z0 = svlsl_n_s16_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_s16_x_untied: +** lsl z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s16_x_untied, svint16_t, + z0 = svlsl_n_s16_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_15_s16_x_tied1: +** lsl z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_x_tied1, svint16_t, + z0 = svlsl_n_s16_x (p0, z0, 15), + z0 = svlsl_x (p0, z0, 15)) + +/* +** lsl_15_s16_x_untied: +** lsl z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_s16_x_untied, svint16_t, + z0 = svlsl_n_s16_x (p0, z1, 15), + z0 = svlsl_x (p0, z1, 15)) + +/* +** lsl_16_s16_x_tied1: +** mov (z[0-9]+\.h), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_x_tied1, svint16_t, + z0 = svlsl_n_s16_x (p0, z0, 16), + z0 = svlsl_x (p0, z0, 16)) + +/* +** lsl_16_s16_x_untied: +** mov z0\.h, #16 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_16_s16_x_untied, svint16_t, + z0 = svlsl_n_s16_x (p0, z1, 16), + z0 = svlsl_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c new file mode 100644 index 00000000000..f98f1f94b44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (lsl_s32_m_tied1, svint32_t, svuint32_t, + z0 = svlsl_s32_m (p0, z0, z4), + z0 = svlsl_m (p0, z0, z4)) + +/* +** lsl_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** lsl z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (lsl_s32_m_tied2, svint32_t, svuint32_t, + z0_res = svlsl_s32_m (p0, z4, z0), + z0_res = svlsl_m (p0, z4, z0)) + +/* +** lsl_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (lsl_s32_m_untied, svint32_t, svuint32_t, + z0 = svlsl_s32_m (p0, z1, z4), + z0 = svlsl_m (p0, z1, z4)) + +/* +** lsl_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_m_tied1, svint32_t, uint32_t, + z0 = svlsl_n_s32_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_m_untied, svint32_t, uint32_t, + z0 = svlsl_n_s32_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_m_tied1, svint32_t, + z0 = svlsl_n_s32_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_m_untied, svint32_t, + z0 = svlsl_n_s32_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_31_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_m_tied1, svint32_t, + z0 = svlsl_n_s32_m (p0, z0, 31), + z0 = svlsl_m (p0, z0, 31)) + +/* +** lsl_31_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_m_untied, svint32_t, + z0 = svlsl_n_s32_m (p0, z1, 31), + z0 = svlsl_m (p0, z1, 31)) + +/* +** lsl_32_s32_m_tied1: +** mov (z[0-9]+\.s), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_m_tied1, svint32_t, + z0 = svlsl_n_s32_m (p0, z0, 32), + z0 = svlsl_m (p0, z0, 32)) + +/* +** lsl_32_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #32 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_m_untied, svint32_t, + z0 = svlsl_n_s32_m (p0, z1, 32), + z0 = svlsl_m (p0, z1, 32)) + +/* +** lsl_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (lsl_s32_z_tied1, svint32_t, svuint32_t, + z0 = svlsl_s32_z (p0, z0, z4), + z0 = svlsl_z (p0, z0, z4)) + +/* +** lsl_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** lslr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z_REV (lsl_s32_z_tied2, svint32_t, svuint32_t, + z0_res = svlsl_s32_z (p0, z4, z0), + z0_res = svlsl_z (p0, z4, z0)) + +/* +** lsl_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, z4\.s +** | +** movprfx z0\.s, p0/z, z4\.s +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s32_z_untied, svint32_t, svuint32_t, + z0 = svlsl_s32_z (p0, z1, z4), + z0 = svlsl_z (p0, z1, z4)) + +/* +** lsl_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_z_tied1, svint32_t, uint32_t, + z0 = svlsl_n_s32_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_z_untied, svint32_t, uint32_t, + z0 = svlsl_n_s32_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_z_tied1, svint32_t, + z0 = svlsl_n_s32_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_z_untied, svint32_t, + z0 = svlsl_n_s32_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_31_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_z_tied1, svint32_t, + z0 = svlsl_n_s32_z (p0, z0, 31), + z0 = svlsl_z (p0, z0, 31)) + +/* +** lsl_31_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_z_untied, svint32_t, + z0 = svlsl_n_s32_z (p0, z1, 31), + z0 = svlsl_z (p0, z1, 31)) + +/* +** lsl_32_s32_z_tied1: +** mov (z[0-9]+\.s), #32 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_z_tied1, svint32_t, + z0 = svlsl_n_s32_z (p0, z0, 32), + z0 = svlsl_z (p0, z0, 32)) + +/* +** lsl_32_s32_z_untied: +** mov (z[0-9]+\.s), #32 +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_z_untied, svint32_t, + z0 = svlsl_n_s32_z (p0, z1, 32), + z0 = svlsl_z (p0, z1, 32)) + +/* +** lsl_s32_x_tied1: +** lsl z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (lsl_s32_x_tied1, svint32_t, svuint32_t, + z0 = svlsl_s32_x (p0, z0, z4), + z0 = svlsl_x (p0, z0, z4)) + +/* +** lsl_s32_x_tied2: +** lslr z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z_REV (lsl_s32_x_tied2, svint32_t, svuint32_t, + z0_res = svlsl_s32_x (p0, z4, z0), + z0_res = svlsl_x (p0, z4, z0)) + +/* +** lsl_s32_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z4\.s +** | +** movprfx z0, z4 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s32_x_untied, svint32_t, svuint32_t, + z0 = svlsl_s32_x (p0, z1, z4), + z0 = svlsl_x (p0, z1, z4)) + +/* +** lsl_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_x_tied1, svint32_t, uint32_t, + z0 = svlsl_n_s32_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_s32_x_untied: +** mov z0\.s, w0 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s32_x_untied, svint32_t, uint32_t, + z0 = svlsl_n_s32_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_s32_x_tied1: +** lsl z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_x_tied1, svint32_t, + z0 = svlsl_n_s32_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_s32_x_untied: +** lsl z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s32_x_untied, svint32_t, + z0 = svlsl_n_s32_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_31_s32_x_tied1: +** lsl z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_x_tied1, svint32_t, + z0 = svlsl_n_s32_x (p0, z0, 31), + z0 = svlsl_x (p0, z0, 31)) + +/* +** lsl_31_s32_x_untied: +** lsl z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_s32_x_untied, svint32_t, + z0 = svlsl_n_s32_x (p0, z1, 31), + z0 = svlsl_x (p0, z1, 31)) + +/* +** lsl_32_s32_x_tied1: +** mov (z[0-9]+\.s), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_x_tied1, svint32_t, + z0 = svlsl_n_s32_x (p0, z0, 32), + z0 = svlsl_x (p0, z0, 32)) + +/* +** lsl_32_s32_x_untied: +** mov z0\.s, #32 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_32_s32_x_untied, svint32_t, + z0 = svlsl_n_s32_x (p0, z1, 32), + z0 = svlsl_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c new file mode 100644 index 00000000000..39753986b1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_s64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_s64_m_tied1, svint64_t, svuint64_t, + z0 = svlsl_s64_m (p0, z0, z4), + z0 = svlsl_m (p0, z0, z4)) + +/* +** lsl_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_s64_m_tied2, svint64_t, svuint64_t, + z0_res = svlsl_s64_m (p0, z4, z0), + z0_res = svlsl_m (p0, z4, z0)) + +/* +** lsl_s64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_s64_m_untied, svint64_t, svuint64_t, + z0 = svlsl_s64_m (p0, z1, z4), + z0 = svlsl_m (p0, z1, z4)) + +/* +** lsl_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_m_tied1, svint64_t, uint64_t, + z0 = svlsl_n_s64_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_m_untied, svint64_t, uint64_t, + z0 = svlsl_n_s64_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_s64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_m_tied1, svint64_t, + z0 = svlsl_n_s64_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_s64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_m_untied, svint64_t, + z0 = svlsl_n_s64_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_63_s64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_m_tied1, svint64_t, + z0 = svlsl_n_s64_m (p0, z0, 63), + z0 = svlsl_m (p0, z0, 63)) + +/* +** lsl_63_s64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_m_untied, svint64_t, + z0 = svlsl_n_s64_m (p0, z1, 63), + z0 = svlsl_m (p0, z1, 63)) + +/* +** lsl_64_s64_m_tied1: +** mov (z[0-9]+\.d), #64 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_m_tied1, svint64_t, + z0 = svlsl_n_s64_m (p0, z0, 64), + z0 = svlsl_m (p0, z0, 64)) + +/* +** lsl_64_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #64 +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_m_untied, svint64_t, + z0 = svlsl_n_s64_m (p0, z1, 64), + z0 = svlsl_m (p0, z1, 64)) + +/* +** lsl_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_s64_z_tied1, svint64_t, svuint64_t, + z0 = svlsl_s64_z (p0, z0, z4), + z0 = svlsl_z (p0, z0, z4)) + +/* +** lsl_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** lslr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_s64_z_tied2, svint64_t, svuint64_t, + z0_res = svlsl_s64_z (p0, z4, z0), + z0_res = svlsl_z (p0, z4, z0)) + +/* +** lsl_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, z4\.d +** | +** movprfx z0\.d, p0/z, z4\.d +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s64_z_untied, svint64_t, svuint64_t, + z0 = svlsl_s64_z (p0, z1, z4), + z0 = svlsl_z (p0, z1, z4)) + +/* +** lsl_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_z_tied1, svint64_t, uint64_t, + z0 = svlsl_n_s64_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_z_untied, svint64_t, uint64_t, + z0 = svlsl_n_s64_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_z_tied1, svint64_t, + z0 = svlsl_n_s64_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_z_untied, svint64_t, + z0 = svlsl_n_s64_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_63_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_z_tied1, svint64_t, + z0 = svlsl_n_s64_z (p0, z0, 63), + z0 = svlsl_z (p0, z0, 63)) + +/* +** lsl_63_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_z_untied, svint64_t, + z0 = svlsl_n_s64_z (p0, z1, 63), + z0 = svlsl_z (p0, z1, 63)) + +/* +** lsl_64_s64_z_tied1: +** mov (z[0-9]+\.d), #64 +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_z_tied1, svint64_t, + z0 = svlsl_n_s64_z (p0, z0, 64), + z0 = svlsl_z (p0, z0, 64)) + +/* +** lsl_64_s64_z_untied: +** mov (z[0-9]+\.d), #64 +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_z_untied, svint64_t, + z0 = svlsl_n_s64_z (p0, z1, 64), + z0 = svlsl_z (p0, z1, 64)) + +/* +** lsl_s64_x_tied1: +** lsl z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_s64_x_tied1, svint64_t, svuint64_t, + z0 = svlsl_s64_x (p0, z0, z4), + z0 = svlsl_x (p0, z0, z4)) + +/* +** lsl_s64_x_tied2: +** lslr z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_s64_x_tied2, svint64_t, svuint64_t, + z0_res = svlsl_s64_x (p0, z4, z0), + z0_res = svlsl_x (p0, z4, z0)) + +/* +** lsl_s64_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, z4\.d +** | +** movprfx z0, z4 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s64_x_untied, svint64_t, svuint64_t, + z0 = svlsl_s64_x (p0, z1, z4), + z0 = svlsl_x (p0, z1, z4)) + +/* +** lsl_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_x_tied1, svint64_t, uint64_t, + z0 = svlsl_n_s64_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_x0_s64_x_untied: +** mov z0\.d, x0 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_s64_x_untied, svint64_t, uint64_t, + z0 = svlsl_n_s64_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_s64_x_tied1: +** lsl z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_x_tied1, svint64_t, + z0 = svlsl_n_s64_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_s64_x_untied: +** lsl z0\.d, z1\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s64_x_untied, svint64_t, + z0 = svlsl_n_s64_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_63_s64_x_tied1: +** lsl z0\.d, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_x_tied1, svint64_t, + z0 = svlsl_n_s64_x (p0, z0, 63), + z0 = svlsl_x (p0, z0, 63)) + +/* +** lsl_63_s64_x_untied: +** lsl z0\.d, z1\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_s64_x_untied, svint64_t, + z0 = svlsl_n_s64_x (p0, z1, 63), + z0 = svlsl_x (p0, z1, 63)) + +/* +** lsl_64_s64_x_tied1: +** mov (z[0-9]+\.d), #64 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_x_tied1, svint64_t, + z0 = svlsl_n_s64_x (p0, z0, 64), + z0 = svlsl_x (p0, z0, 64)) + +/* +** lsl_64_s64_x_untied: +** mov z0\.d, #64 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_64_s64_x_untied, svint64_t, + z0 = svlsl_n_s64_x (p0, z1, 64), + z0 = svlsl_x (p0, z1, 64)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c new file mode 100644 index 00000000000..9a9cc959c33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (lsl_s8_m_tied1, svint8_t, svuint8_t, + z0 = svlsl_s8_m (p0, z0, z4), + z0 = svlsl_m (p0, z0, z4)) + +/* +** lsl_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** lsl z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_DUAL_Z_REV (lsl_s8_m_tied2, svint8_t, svuint8_t, + z0_res = svlsl_s8_m (p0, z4, z0), + z0_res = svlsl_m (p0, z4, z0)) + +/* +** lsl_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (lsl_s8_m_untied, svint8_t, svuint8_t, + z0 = svlsl_s8_m (p0, z1, z4), + z0 = svlsl_m (p0, z1, z4)) + +/* +** lsl_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_m_tied1, svint8_t, uint8_t, + z0 = svlsl_n_s8_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_m_untied, svint8_t, uint8_t, + z0 = svlsl_n_s8_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_m_tied1, svint8_t, + z0 = svlsl_n_s8_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_m_untied, svint8_t, + z0 = svlsl_n_s8_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_7_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_m_tied1, svint8_t, + z0 = svlsl_n_s8_m (p0, z0, 7), + z0 = svlsl_m (p0, z0, 7)) + +/* +** lsl_7_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_m_untied, svint8_t, + z0 = svlsl_n_s8_m (p0, z1, 7), + z0 = svlsl_m (p0, z1, 7)) + +/* +** lsl_8_s8_m_tied1: +** mov (z[0-9]+\.b), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_m_tied1, svint8_t, + z0 = svlsl_n_s8_m (p0, z0, 8), + z0 = svlsl_m (p0, z0, 8)) + +/* +** lsl_8_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #8 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_m_untied, svint8_t, + z0 = svlsl_n_s8_m (p0, z1, 8), + z0 = svlsl_m (p0, z1, 8)) + +/* +** lsl_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (lsl_s8_z_tied1, svint8_t, svuint8_t, + z0 = svlsl_s8_z (p0, z0, z4), + z0 = svlsl_z (p0, z0, z4)) + +/* +** lsl_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** lslr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z_REV (lsl_s8_z_tied2, svint8_t, svuint8_t, + z0_res = svlsl_s8_z (p0, z4, z0), + z0_res = svlsl_z (p0, z4, z0)) + +/* +** lsl_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, z4\.b +** | +** movprfx z0\.b, p0/z, z4\.b +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s8_z_untied, svint8_t, svuint8_t, + z0 = svlsl_s8_z (p0, z1, z4), + z0 = svlsl_z (p0, z1, z4)) + +/* +** lsl_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_z_tied1, svint8_t, uint8_t, + z0 = svlsl_n_s8_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_z_untied, svint8_t, uint8_t, + z0 = svlsl_n_s8_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_z_tied1, svint8_t, + z0 = svlsl_n_s8_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_z_untied, svint8_t, + z0 = svlsl_n_s8_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_7_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_z_tied1, svint8_t, + z0 = svlsl_n_s8_z (p0, z0, 7), + z0 = svlsl_z (p0, z0, 7)) + +/* +** lsl_7_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_z_untied, svint8_t, + z0 = svlsl_n_s8_z (p0, z1, 7), + z0 = svlsl_z (p0, z1, 7)) + +/* +** lsl_8_s8_z_tied1: +** mov (z[0-9]+\.b), #8 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_z_tied1, svint8_t, + z0 = svlsl_n_s8_z (p0, z0, 8), + z0 = svlsl_z (p0, z0, 8)) + +/* +** lsl_8_s8_z_untied: +** mov (z[0-9]+\.b), #8 +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_z_untied, svint8_t, + z0 = svlsl_n_s8_z (p0, z1, 8), + z0 = svlsl_z (p0, z1, 8)) + +/* +** lsl_s8_x_tied1: +** lsl z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (lsl_s8_x_tied1, svint8_t, svuint8_t, + z0 = svlsl_s8_x (p0, z0, z4), + z0 = svlsl_x (p0, z0, z4)) + +/* +** lsl_s8_x_tied2: +** lslr z0\.b, p0/m, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z_REV (lsl_s8_x_tied2, svint8_t, svuint8_t, + z0_res = svlsl_s8_x (p0, z4, z0), + z0_res = svlsl_x (p0, z4, z0)) + +/* +** lsl_s8_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z4\.b +** | +** movprfx z0, z4 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_DUAL_Z (lsl_s8_x_untied, svint8_t, svuint8_t, + z0 = svlsl_s8_x (p0, z1, z4), + z0 = svlsl_x (p0, z1, z4)) + +/* +** lsl_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_x_tied1, svint8_t, uint8_t, + z0 = svlsl_n_s8_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_s8_x_untied: +** mov z0\.b, w0 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_s8_x_untied, svint8_t, uint8_t, + z0 = svlsl_n_s8_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_s8_x_tied1: +** lsl z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_x_tied1, svint8_t, + z0 = svlsl_n_s8_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_s8_x_untied: +** lsl z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_s8_x_untied, svint8_t, + z0 = svlsl_n_s8_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_7_s8_x_tied1: +** lsl z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_x_tied1, svint8_t, + z0 = svlsl_n_s8_x (p0, z0, 7), + z0 = svlsl_x (p0, z0, 7)) + +/* +** lsl_7_s8_x_untied: +** lsl z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_s8_x_untied, svint8_t, + z0 = svlsl_n_s8_x (p0, z1, 7), + z0 = svlsl_x (p0, z1, 7)) + +/* +** lsl_8_s8_x_tied1: +** mov (z[0-9]+\.b), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_x_tied1, svint8_t, + z0 = svlsl_n_s8_x (p0, z0, 8), + z0 = svlsl_x (p0, z0, 8)) + +/* +** lsl_8_s8_x_untied: +** mov z0\.b, #8 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_8_s8_x_untied, svint8_t, + z0 = svlsl_n_s8_x (p0, z1, 8), + z0 = svlsl_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c new file mode 100644 index 00000000000..57db0fda66a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_m_tied1, svuint16_t, + z0 = svlsl_u16_m (p0, z0, z1), + z0 = svlsl_m (p0, z0, z1)) + +/* +** lsl_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_m_tied2, svuint16_t, + z0 = svlsl_u16_m (p0, z1, z0), + z0 = svlsl_m (p0, z1, z0)) + +/* +** lsl_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_m_untied, svuint16_t, + z0 = svlsl_u16_m (p0, z1, z2), + z0 = svlsl_m (p0, z1, z2)) + +/* +** lsl_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svlsl_n_u16_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svlsl_n_u16_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_m_tied1, svuint16_t, + z0 = svlsl_n_u16_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_m_untied, svuint16_t, + z0 = svlsl_n_u16_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_15_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_m_tied1, svuint16_t, + z0 = svlsl_n_u16_m (p0, z0, 15), + z0 = svlsl_m (p0, z0, 15)) + +/* +** lsl_15_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_m_untied, svuint16_t, + z0 = svlsl_n_u16_m (p0, z1, 15), + z0 = svlsl_m (p0, z1, 15)) + +/* +** lsl_16_u16_m_tied1: +** mov (z[0-9]+\.h), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_m_tied1, svuint16_t, + z0 = svlsl_n_u16_m (p0, z0, 16), + z0 = svlsl_m (p0, z0, 16)) + +/* +** lsl_16_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #16 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_m_untied, svuint16_t, + z0 = svlsl_n_u16_m (p0, z1, 16), + z0 = svlsl_m (p0, z1, 16)) + +/* +** lsl_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_z_tied1, svuint16_t, + z0 = svlsl_u16_z (p0, z0, z1), + z0 = svlsl_z (p0, z0, z1)) + +/* +** lsl_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_z_tied2, svuint16_t, + z0 = svlsl_u16_z (p0, z1, z0), + z0 = svlsl_z (p0, z1, z0)) + +/* +** lsl_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_z_untied, svuint16_t, + z0 = svlsl_u16_z (p0, z1, z2), + z0 = svlsl_z (p0, z1, z2)) + +/* +** lsl_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svlsl_n_u16_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svlsl_n_u16_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_z_tied1, svuint16_t, + z0 = svlsl_n_u16_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_z_untied, svuint16_t, + z0 = svlsl_n_u16_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_15_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_z_tied1, svuint16_t, + z0 = svlsl_n_u16_z (p0, z0, 15), + z0 = svlsl_z (p0, z0, 15)) + +/* +** lsl_15_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_z_untied, svuint16_t, + z0 = svlsl_n_u16_z (p0, z1, 15), + z0 = svlsl_z (p0, z1, 15)) + +/* +** lsl_16_u16_z_tied1: +** mov (z[0-9]+\.h), #16 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_z_tied1, svuint16_t, + z0 = svlsl_n_u16_z (p0, z0, 16), + z0 = svlsl_z (p0, z0, 16)) + +/* +** lsl_16_u16_z_untied: +** mov (z[0-9]+\.h), #16 +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_z_untied, svuint16_t, + z0 = svlsl_n_u16_z (p0, z1, 16), + z0 = svlsl_z (p0, z1, 16)) + +/* +** lsl_u16_x_tied1: +** lsl z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_x_tied1, svuint16_t, + z0 = svlsl_u16_x (p0, z0, z1), + z0 = svlsl_x (p0, z0, z1)) + +/* +** lsl_u16_x_tied2: +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_x_tied2, svuint16_t, + z0 = svlsl_u16_x (p0, z1, z0), + z0 = svlsl_x (p0, z1, z0)) + +/* +** lsl_u16_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u16_x_untied, svuint16_t, + z0 = svlsl_u16_x (p0, z1, z2), + z0 = svlsl_x (p0, z1, z2)) + +/* +** lsl_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svlsl_n_u16_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_u16_x_untied: +** mov z0\.h, w0 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svlsl_n_u16_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_u16_x_tied1: +** lsl z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_x_tied1, svuint16_t, + z0 = svlsl_n_u16_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_u16_x_untied: +** lsl z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u16_x_untied, svuint16_t, + z0 = svlsl_n_u16_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_15_u16_x_tied1: +** lsl z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_x_tied1, svuint16_t, + z0 = svlsl_n_u16_x (p0, z0, 15), + z0 = svlsl_x (p0, z0, 15)) + +/* +** lsl_15_u16_x_untied: +** lsl z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_15_u16_x_untied, svuint16_t, + z0 = svlsl_n_u16_x (p0, z1, 15), + z0 = svlsl_x (p0, z1, 15)) + +/* +** lsl_16_u16_x_tied1: +** mov (z[0-9]+\.h), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_x_tied1, svuint16_t, + z0 = svlsl_n_u16_x (p0, z0, 16), + z0 = svlsl_x (p0, z0, 16)) + +/* +** lsl_16_u16_x_untied: +** mov z0\.h, #16 +** lslr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsl_16_u16_x_untied, svuint16_t, + z0 = svlsl_n_u16_x (p0, z1, 16), + z0 = svlsl_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c new file mode 100644 index 00000000000..8773f15db44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_m_tied1, svuint32_t, + z0 = svlsl_u32_m (p0, z0, z1), + z0 = svlsl_m (p0, z0, z1)) + +/* +** lsl_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_m_tied2, svuint32_t, + z0 = svlsl_u32_m (p0, z1, z0), + z0 = svlsl_m (p0, z1, z0)) + +/* +** lsl_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_m_untied, svuint32_t, + z0 = svlsl_u32_m (p0, z1, z2), + z0 = svlsl_m (p0, z1, z2)) + +/* +** lsl_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svlsl_n_u32_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svlsl_n_u32_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_m_tied1, svuint32_t, + z0 = svlsl_n_u32_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_m_untied, svuint32_t, + z0 = svlsl_n_u32_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_31_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_m_tied1, svuint32_t, + z0 = svlsl_n_u32_m (p0, z0, 31), + z0 = svlsl_m (p0, z0, 31)) + +/* +** lsl_31_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_m_untied, svuint32_t, + z0 = svlsl_n_u32_m (p0, z1, 31), + z0 = svlsl_m (p0, z1, 31)) + +/* +** lsl_32_u32_m_tied1: +** mov (z[0-9]+\.s), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_m_tied1, svuint32_t, + z0 = svlsl_n_u32_m (p0, z0, 32), + z0 = svlsl_m (p0, z0, 32)) + +/* +** lsl_32_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #32 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_m_untied, svuint32_t, + z0 = svlsl_n_u32_m (p0, z1, 32), + z0 = svlsl_m (p0, z1, 32)) + +/* +** lsl_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_z_tied1, svuint32_t, + z0 = svlsl_u32_z (p0, z0, z1), + z0 = svlsl_z (p0, z0, z1)) + +/* +** lsl_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_z_tied2, svuint32_t, + z0 = svlsl_u32_z (p0, z1, z0), + z0 = svlsl_z (p0, z1, z0)) + +/* +** lsl_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_z_untied, svuint32_t, + z0 = svlsl_u32_z (p0, z1, z2), + z0 = svlsl_z (p0, z1, z2)) + +/* +** lsl_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svlsl_n_u32_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svlsl_n_u32_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_z_tied1, svuint32_t, + z0 = svlsl_n_u32_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_z_untied, svuint32_t, + z0 = svlsl_n_u32_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_31_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_z_tied1, svuint32_t, + z0 = svlsl_n_u32_z (p0, z0, 31), + z0 = svlsl_z (p0, z0, 31)) + +/* +** lsl_31_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_z_untied, svuint32_t, + z0 = svlsl_n_u32_z (p0, z1, 31), + z0 = svlsl_z (p0, z1, 31)) + +/* +** lsl_32_u32_z_tied1: +** mov (z[0-9]+\.s), #32 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_z_tied1, svuint32_t, + z0 = svlsl_n_u32_z (p0, z0, 32), + z0 = svlsl_z (p0, z0, 32)) + +/* +** lsl_32_u32_z_untied: +** mov (z[0-9]+\.s), #32 +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_z_untied, svuint32_t, + z0 = svlsl_n_u32_z (p0, z1, 32), + z0 = svlsl_z (p0, z1, 32)) + +/* +** lsl_u32_x_tied1: +** lsl z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_x_tied1, svuint32_t, + z0 = svlsl_u32_x (p0, z0, z1), + z0 = svlsl_x (p0, z0, z1)) + +/* +** lsl_u32_x_tied2: +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_x_tied2, svuint32_t, + z0 = svlsl_u32_x (p0, z1, z0), + z0 = svlsl_x (p0, z1, z0)) + +/* +** lsl_u32_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u32_x_untied, svuint32_t, + z0 = svlsl_u32_x (p0, z1, z2), + z0 = svlsl_x (p0, z1, z2)) + +/* +** lsl_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svlsl_n_u32_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_u32_x_untied: +** mov z0\.s, w0 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svlsl_n_u32_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_u32_x_tied1: +** lsl z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_x_tied1, svuint32_t, + z0 = svlsl_n_u32_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_u32_x_untied: +** lsl z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u32_x_untied, svuint32_t, + z0 = svlsl_n_u32_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_31_u32_x_tied1: +** lsl z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_x_tied1, svuint32_t, + z0 = svlsl_n_u32_x (p0, z0, 31), + z0 = svlsl_x (p0, z0, 31)) + +/* +** lsl_31_u32_x_untied: +** lsl z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_31_u32_x_untied, svuint32_t, + z0 = svlsl_n_u32_x (p0, z1, 31), + z0 = svlsl_x (p0, z1, 31)) + +/* +** lsl_32_u32_x_tied1: +** mov (z[0-9]+\.s), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_x_tied1, svuint32_t, + z0 = svlsl_n_u32_x (p0, z0, 32), + z0 = svlsl_x (p0, z0, 32)) + +/* +** lsl_32_u32_x_untied: +** mov z0\.s, #32 +** lslr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsl_32_u32_x_untied, svuint32_t, + z0 = svlsl_n_u32_x (p0, z1, 32), + z0 = svlsl_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c new file mode 100644 index 00000000000..7b12bd43e1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_u64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_m_tied1, svuint64_t, + z0 = svlsl_u64_m (p0, z0, z1), + z0 = svlsl_m (p0, z0, z1)) + +/* +** lsl_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_m_tied2, svuint64_t, + z0 = svlsl_u64_m (p0, z1, z0), + z0 = svlsl_m (p0, z1, z0)) + +/* +** lsl_u64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_m_untied, svuint64_t, + z0 = svlsl_u64_m (p0, z1, z2), + z0 = svlsl_m (p0, z1, z2)) + +/* +** lsl_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svlsl_n_u64_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svlsl_n_u64_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_u64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_m_tied1, svuint64_t, + z0 = svlsl_n_u64_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_u64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_m_untied, svuint64_t, + z0 = svlsl_n_u64_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_63_u64_m_tied1: +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_m_tied1, svuint64_t, + z0 = svlsl_n_u64_m (p0, z0, 63), + z0 = svlsl_m (p0, z0, 63)) + +/* +** lsl_63_u64_m_untied: +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_m_untied, svuint64_t, + z0 = svlsl_n_u64_m (p0, z1, 63), + z0 = svlsl_m (p0, z1, 63)) + +/* +** lsl_64_u64_m_tied1: +** mov (z[0-9]+\.d), #64 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_m_tied1, svuint64_t, + z0 = svlsl_n_u64_m (p0, z0, 64), + z0 = svlsl_m (p0, z0, 64)) + +/* +** lsl_64_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #64 +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_m_untied, svuint64_t, + z0 = svlsl_n_u64_m (p0, z1, 64), + z0 = svlsl_m (p0, z1, 64)) + +/* +** lsl_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_z_tied1, svuint64_t, + z0 = svlsl_u64_z (p0, z0, z1), + z0 = svlsl_z (p0, z0, z1)) + +/* +** lsl_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_z_tied2, svuint64_t, + z0 = svlsl_u64_z (p0, z1, z0), + z0 = svlsl_z (p0, z1, z0)) + +/* +** lsl_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_z_untied, svuint64_t, + z0 = svlsl_u64_z (p0, z1, z2), + z0 = svlsl_z (p0, z1, z2)) + +/* +** lsl_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svlsl_n_u64_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svlsl_n_u64_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_z_tied1, svuint64_t, + z0 = svlsl_n_u64_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_z_untied, svuint64_t, + z0 = svlsl_n_u64_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_63_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_z_tied1, svuint64_t, + z0 = svlsl_n_u64_z (p0, z0, 63), + z0 = svlsl_z (p0, z0, 63)) + +/* +** lsl_63_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_z_untied, svuint64_t, + z0 = svlsl_n_u64_z (p0, z1, 63), + z0 = svlsl_z (p0, z1, 63)) + +/* +** lsl_64_u64_z_tied1: +** mov (z[0-9]+\.d), #64 +** movprfx z0\.d, p0/z, z0\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_z_tied1, svuint64_t, + z0 = svlsl_n_u64_z (p0, z0, 64), + z0 = svlsl_z (p0, z0, 64)) + +/* +** lsl_64_u64_z_untied: +** mov (z[0-9]+\.d), #64 +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsl z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_z_untied, svuint64_t, + z0 = svlsl_n_u64_z (p0, z1, 64), + z0 = svlsl_z (p0, z1, 64)) + +/* +** lsl_u64_x_tied1: +** lsl z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_x_tied1, svuint64_t, + z0 = svlsl_u64_x (p0, z0, z1), + z0 = svlsl_x (p0, z0, z1)) + +/* +** lsl_u64_x_tied2: +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_x_tied2, svuint64_t, + z0 = svlsl_u64_x (p0, z1, z0), + z0 = svlsl_x (p0, z1, z0)) + +/* +** lsl_u64_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u64_x_untied, svuint64_t, + z0 = svlsl_u64_x (p0, z1, z2), + z0 = svlsl_x (p0, z1, z2)) + +/* +** lsl_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svlsl_n_u64_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_x0_u64_x_untied: +** mov z0\.d, x0 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (lsl_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svlsl_n_u64_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_u64_x_tied1: +** lsl z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_x_tied1, svuint64_t, + z0 = svlsl_n_u64_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_u64_x_untied: +** lsl z0\.d, z1\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u64_x_untied, svuint64_t, + z0 = svlsl_n_u64_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_63_u64_x_tied1: +** lsl z0\.d, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_x_tied1, svuint64_t, + z0 = svlsl_n_u64_x (p0, z0, 63), + z0 = svlsl_x (p0, z0, 63)) + +/* +** lsl_63_u64_x_untied: +** lsl z0\.d, z1\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsl_63_u64_x_untied, svuint64_t, + z0 = svlsl_n_u64_x (p0, z1, 63), + z0 = svlsl_x (p0, z1, 63)) + +/* +** lsl_64_u64_x_tied1: +** mov (z[0-9]+\.d), #64 +** lsl z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_x_tied1, svuint64_t, + z0 = svlsl_n_u64_x (p0, z0, 64), + z0 = svlsl_x (p0, z0, 64)) + +/* +** lsl_64_u64_x_untied: +** mov z0\.d, #64 +** lslr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsl_64_u64_x_untied, svuint64_t, + z0 = svlsl_n_u64_x (p0, z1, 64), + z0 = svlsl_x (p0, z1, 64)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c new file mode 100644 index 00000000000..894b5513857 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c @@ -0,0 +1,351 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_m_tied1, svuint8_t, + z0 = svlsl_u8_m (p0, z0, z1), + z0 = svlsl_m (p0, z0, z1)) + +/* +** lsl_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_m_tied2, svuint8_t, + z0 = svlsl_u8_m (p0, z1, z0), + z0 = svlsl_m (p0, z1, z0)) + +/* +** lsl_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_m_untied, svuint8_t, + z0 = svlsl_u8_m (p0, z1, z2), + z0 = svlsl_m (p0, z1, z2)) + +/* +** lsl_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svlsl_n_u8_m (p0, z0, x0), + z0 = svlsl_m (p0, z0, x0)) + +/* +** lsl_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svlsl_n_u8_m (p0, z1, x0), + z0 = svlsl_m (p0, z1, x0)) + +/* +** lsl_1_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_m_tied1, svuint8_t, + z0 = svlsl_n_u8_m (p0, z0, 1), + z0 = svlsl_m (p0, z0, 1)) + +/* +** lsl_1_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_m_untied, svuint8_t, + z0 = svlsl_n_u8_m (p0, z1, 1), + z0 = svlsl_m (p0, z1, 1)) + +/* +** lsl_7_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_m_tied1, svuint8_t, + z0 = svlsl_n_u8_m (p0, z0, 7), + z0 = svlsl_m (p0, z0, 7)) + +/* +** lsl_7_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_m_untied, svuint8_t, + z0 = svlsl_n_u8_m (p0, z1, 7), + z0 = svlsl_m (p0, z1, 7)) + +/* +** lsl_8_u8_m_tied1: +** mov (z[0-9]+\.b), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_m_tied1, svuint8_t, + z0 = svlsl_n_u8_m (p0, z0, 8), + z0 = svlsl_m (p0, z0, 8)) + +/* +** lsl_8_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #8 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_m_untied, svuint8_t, + z0 = svlsl_n_u8_m (p0, z1, 8), + z0 = svlsl_m (p0, z1, 8)) + +/* +** lsl_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_z_tied1, svuint8_t, + z0 = svlsl_u8_z (p0, z0, z1), + z0 = svlsl_z (p0, z0, z1)) + +/* +** lsl_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_z_tied2, svuint8_t, + z0 = svlsl_u8_z (p0, z1, z0), + z0 = svlsl_z (p0, z1, z0)) + +/* +** lsl_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_z_untied, svuint8_t, + z0 = svlsl_u8_z (p0, z1, z2), + z0 = svlsl_z (p0, z1, z2)) + +/* +** lsl_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svlsl_n_u8_z (p0, z0, x0), + z0 = svlsl_z (p0, z0, x0)) + +/* +** lsl_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svlsl_n_u8_z (p0, z1, x0), + z0 = svlsl_z (p0, z1, x0)) + +/* +** lsl_1_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_z_tied1, svuint8_t, + z0 = svlsl_n_u8_z (p0, z0, 1), + z0 = svlsl_z (p0, z0, 1)) + +/* +** lsl_1_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_z_untied, svuint8_t, + z0 = svlsl_n_u8_z (p0, z1, 1), + z0 = svlsl_z (p0, z1, 1)) + +/* +** lsl_7_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_z_tied1, svuint8_t, + z0 = svlsl_n_u8_z (p0, z0, 7), + z0 = svlsl_z (p0, z0, 7)) + +/* +** lsl_7_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_z_untied, svuint8_t, + z0 = svlsl_n_u8_z (p0, z1, 7), + z0 = svlsl_z (p0, z1, 7)) + +/* +** lsl_8_u8_z_tied1: +** mov (z[0-9]+\.b), #8 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_z_tied1, svuint8_t, + z0 = svlsl_n_u8_z (p0, z0, 8), + z0 = svlsl_z (p0, z0, 8)) + +/* +** lsl_8_u8_z_untied: +** mov (z[0-9]+\.b), #8 +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_z_untied, svuint8_t, + z0 = svlsl_n_u8_z (p0, z1, 8), + z0 = svlsl_z (p0, z1, 8)) + +/* +** lsl_u8_x_tied1: +** lsl z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_x_tied1, svuint8_t, + z0 = svlsl_u8_x (p0, z0, z1), + z0 = svlsl_x (p0, z0, z1)) + +/* +** lsl_u8_x_tied2: +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_x_tied2, svuint8_t, + z0 = svlsl_u8_x (p0, z1, z0), + z0 = svlsl_x (p0, z1, z0)) + +/* +** lsl_u8_x_untied: +** ( +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsl_u8_x_untied, svuint8_t, + z0 = svlsl_u8_x (p0, z1, z2), + z0 = svlsl_x (p0, z1, z2)) + +/* +** lsl_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svlsl_n_u8_x (p0, z0, x0), + z0 = svlsl_x (p0, z0, x0)) + +/* +** lsl_w0_u8_x_untied: +** mov z0\.b, w0 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (lsl_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svlsl_n_u8_x (p0, z1, x0), + z0 = svlsl_x (p0, z1, x0)) + +/* +** lsl_1_u8_x_tied1: +** lsl z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_x_tied1, svuint8_t, + z0 = svlsl_n_u8_x (p0, z0, 1), + z0 = svlsl_x (p0, z0, 1)) + +/* +** lsl_1_u8_x_untied: +** lsl z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_1_u8_x_untied, svuint8_t, + z0 = svlsl_n_u8_x (p0, z1, 1), + z0 = svlsl_x (p0, z1, 1)) + +/* +** lsl_7_u8_x_tied1: +** lsl z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_x_tied1, svuint8_t, + z0 = svlsl_n_u8_x (p0, z0, 7), + z0 = svlsl_x (p0, z0, 7)) + +/* +** lsl_7_u8_x_untied: +** lsl z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_7_u8_x_untied, svuint8_t, + z0 = svlsl_n_u8_x (p0, z1, 7), + z0 = svlsl_x (p0, z1, 7)) + +/* +** lsl_8_u8_x_tied1: +** mov (z[0-9]+\.b), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_x_tied1, svuint8_t, + z0 = svlsl_n_u8_x (p0, z0, 8), + z0 = svlsl_x (p0, z0, 8)) + +/* +** lsl_8_u8_x_untied: +** mov z0\.b, #8 +** lslr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsl_8_u8_x_untied, svuint8_t, + z0 = svlsl_n_u8_x (p0, z1, 8), + z0 = svlsl_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c new file mode 100644 index 00000000000..8d63d390984 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_m_tied1, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_s16_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s16_m_tied2, svint16_t, svuint64_t, + z0_res = svlsl_wide_s16_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_m_untied, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_s16_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_m_tied1, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_s16_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_m_untied, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_m_tied1, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_m_untied, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_15_s16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_m_tied1, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z0, 15), + z0 = svlsl_wide_m (p0, z0, 15)) + +/* +** lsl_wide_15_s16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_m_untied, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z1, 15), + z0 = svlsl_wide_m (p0, z1, 15)) + +/* +** lsl_wide_16_s16_m_tied1: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_m_tied1, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z0, 16), + z0 = svlsl_wide_m (p0, z0, 16)) + +/* +** lsl_wide_16_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #16 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_m_untied, svint16_t, + z0 = svlsl_wide_n_s16_m (p0, z1, 16), + z0 = svlsl_wide_m (p0, z1, 16)) + +/* +** lsl_wide_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_z_tied1, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_s16_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.h, p0/z, z4\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s16_z_tied2, svint16_t, svuint64_t, + z0_res = svlsl_wide_s16_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_z_untied, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_s16_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_z_tied1, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_s16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_z_untied, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_z_tied1, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_z_untied, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_15_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_z_tied1, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z0, 15), + z0 = svlsl_wide_z (p0, z0, 15)) + +/* +** lsl_wide_15_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_z_untied, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z1, 15), + z0 = svlsl_wide_z (p0, z1, 15)) + +/* +** lsl_wide_16_s16_z_tied1: +** mov (z[0-9]+\.d), #16 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_z_tied1, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z0, 16), + z0 = svlsl_wide_z (p0, z0, 16)) + +/* +** lsl_wide_16_s16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #16 +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_z_untied, svint16_t, + z0 = svlsl_wide_n_s16_z (p0, z1, 16), + z0 = svlsl_wide_z (p0, z1, 16)) + +/* +** lsl_wide_s16_x_tied1: +** lsl z0\.h, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_x_tied1, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_s16_x_tied2: +** lsl z0\.h, z4\.h, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s16_x_tied2, svint16_t, svuint64_t, + z0_res = svlsl_wide_s16_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_s16_x_untied: +** lsl z0\.h, z1\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s16_x_untied, svint16_t, svuint64_t, + z0 = svlsl_wide_s16_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_s16_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_x_tied1, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_s16_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s16_x_untied, svint16_t, uint64_t, + z0 = svlsl_wide_n_s16_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_s16_x_tied1: +** lsl z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_x_tied1, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_s16_x_untied: +** lsl z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s16_x_untied, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_15_s16_x_tied1: +** lsl z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_x_tied1, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z0, 15), + z0 = svlsl_wide_x (p0, z0, 15)) + +/* +** lsl_wide_15_s16_x_untied: +** lsl z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_s16_x_untied, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z1, 15), + z0 = svlsl_wide_x (p0, z1, 15)) + +/* +** lsl_wide_16_s16_x_tied1: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_x_tied1, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z0, 16), + z0 = svlsl_wide_x (p0, z0, 16)) + +/* +** lsl_wide_16_s16_x_untied: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_s16_x_untied, svint16_t, + z0 = svlsl_wide_n_s16_x (p0, z1, 16), + z0 = svlsl_wide_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c new file mode 100644 index 00000000000..acd813df34f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_m_tied1, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_s32_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s32_m_tied2, svint32_t, svuint64_t, + z0_res = svlsl_wide_s32_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_m_untied, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_s32_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_m_tied1, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_s32_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_m_untied, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_m_tied1, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_m_untied, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_31_s32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_m_tied1, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z0, 31), + z0 = svlsl_wide_m (p0, z0, 31)) + +/* +** lsl_wide_31_s32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_m_untied, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z1, 31), + z0 = svlsl_wide_m (p0, z1, 31)) + +/* +** lsl_wide_32_s32_m_tied1: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_m_tied1, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z0, 32), + z0 = svlsl_wide_m (p0, z0, 32)) + +/* +** lsl_wide_32_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #32 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_m_untied, svint32_t, + z0 = svlsl_wide_n_s32_m (p0, z1, 32), + z0 = svlsl_wide_m (p0, z1, 32)) + +/* +** lsl_wide_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_z_tied1, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_s32_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.s, p0/z, z4\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s32_z_tied2, svint32_t, svuint64_t, + z0_res = svlsl_wide_s32_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_z_untied, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_s32_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_z_tied1, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_s32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_z_untied, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_z_tied1, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_z_untied, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_31_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_z_tied1, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z0, 31), + z0 = svlsl_wide_z (p0, z0, 31)) + +/* +** lsl_wide_31_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_z_untied, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z1, 31), + z0 = svlsl_wide_z (p0, z1, 31)) + +/* +** lsl_wide_32_s32_z_tied1: +** mov (z[0-9]+\.d), #32 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_z_tied1, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z0, 32), + z0 = svlsl_wide_z (p0, z0, 32)) + +/* +** lsl_wide_32_s32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #32 +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_z_untied, svint32_t, + z0 = svlsl_wide_n_s32_z (p0, z1, 32), + z0 = svlsl_wide_z (p0, z1, 32)) + +/* +** lsl_wide_s32_x_tied1: +** lsl z0\.s, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_x_tied1, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_s32_x_tied2: +** lsl z0\.s, z4\.s, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s32_x_tied2, svint32_t, svuint64_t, + z0_res = svlsl_wide_s32_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_s32_x_untied: +** lsl z0\.s, z1\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s32_x_untied, svint32_t, svuint64_t, + z0 = svlsl_wide_s32_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_s32_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_x_tied1, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_s32_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s32_x_untied, svint32_t, uint64_t, + z0 = svlsl_wide_n_s32_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_s32_x_tied1: +** lsl z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_x_tied1, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_s32_x_untied: +** lsl z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s32_x_untied, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_31_s32_x_tied1: +** lsl z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_x_tied1, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z0, 31), + z0 = svlsl_wide_x (p0, z0, 31)) + +/* +** lsl_wide_31_s32_x_untied: +** lsl z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_s32_x_untied, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z1, 31), + z0 = svlsl_wide_x (p0, z1, 31)) + +/* +** lsl_wide_32_s32_x_tied1: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_x_tied1, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z0, 32), + z0 = svlsl_wide_x (p0, z0, 32)) + +/* +** lsl_wide_32_s32_x_untied: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_s32_x_untied, svint32_t, + z0 = svlsl_wide_n_s32_x (p0, z1, 32), + z0 = svlsl_wide_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c new file mode 100644 index 00000000000..17e8e8685e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_m_tied1, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_s8_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s8_m_tied2, svint8_t, svuint64_t, + z0_res = svlsl_wide_s8_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_m_untied, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_s8_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_m_tied1, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_s8_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_m_untied, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_m_tied1, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_m_untied, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_7_s8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_m_tied1, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z0, 7), + z0 = svlsl_wide_m (p0, z0, 7)) + +/* +** lsl_wide_7_s8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_m_untied, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z1, 7), + z0 = svlsl_wide_m (p0, z1, 7)) + +/* +** lsl_wide_8_s8_m_tied1: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_m_tied1, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z0, 8), + z0 = svlsl_wide_m (p0, z0, 8)) + +/* +** lsl_wide_8_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #8 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_m_untied, svint8_t, + z0 = svlsl_wide_n_s8_m (p0, z1, 8), + z0 = svlsl_wide_m (p0, z1, 8)) + +/* +** lsl_wide_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_z_tied1, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_s8_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.b, p0/z, z4\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s8_z_tied2, svint8_t, svuint64_t, + z0_res = svlsl_wide_s8_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_z_untied, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_s8_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_z_tied1, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_s8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_z_untied, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_z_tied1, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_z_untied, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_7_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_z_tied1, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z0, 7), + z0 = svlsl_wide_z (p0, z0, 7)) + +/* +** lsl_wide_7_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_z_untied, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z1, 7), + z0 = svlsl_wide_z (p0, z1, 7)) + +/* +** lsl_wide_8_s8_z_tied1: +** mov (z[0-9]+\.d), #8 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_z_tied1, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z0, 8), + z0 = svlsl_wide_z (p0, z0, 8)) + +/* +** lsl_wide_8_s8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #8 +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_z_untied, svint8_t, + z0 = svlsl_wide_n_s8_z (p0, z1, 8), + z0 = svlsl_wide_z (p0, z1, 8)) + +/* +** lsl_wide_s8_x_tied1: +** lsl z0\.b, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_x_tied1, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_s8_x_tied2: +** lsl z0\.b, z4\.b, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_s8_x_tied2, svint8_t, svuint64_t, + z0_res = svlsl_wide_s8_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_s8_x_untied: +** lsl z0\.b, z1\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_s8_x_untied, svint8_t, svuint64_t, + z0 = svlsl_wide_s8_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_s8_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_x_tied1, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_s8_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_s8_x_untied, svint8_t, uint64_t, + z0 = svlsl_wide_n_s8_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_s8_x_tied1: +** lsl z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_x_tied1, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_s8_x_untied: +** lsl z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_s8_x_untied, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_7_s8_x_tied1: +** lsl z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_x_tied1, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z0, 7), + z0 = svlsl_wide_x (p0, z0, 7)) + +/* +** lsl_wide_7_s8_x_untied: +** lsl z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_s8_x_untied, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z1, 7), + z0 = svlsl_wide_x (p0, z1, 7)) + +/* +** lsl_wide_8_s8_x_tied1: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_x_tied1, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z0, 8), + z0 = svlsl_wide_x (p0, z0, 8)) + +/* +** lsl_wide_8_s8_x_untied: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_s8_x_untied, svint8_t, + z0 = svlsl_wide_n_s8_x (p0, z1, 8), + z0 = svlsl_wide_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c new file mode 100644 index 00000000000..cff24a85090 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_m_tied1, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_u16_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u16_m_tied2, svuint16_t, svuint64_t, + z0_res = svlsl_wide_u16_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_m_untied, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_u16_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_m_tied1, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_u16_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_m_untied, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_m_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_m_untied, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_15_u16_m_tied1: +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_m_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z0, 15), + z0 = svlsl_wide_m (p0, z0, 15)) + +/* +** lsl_wide_15_u16_m_untied: +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_m_untied, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z1, 15), + z0 = svlsl_wide_m (p0, z1, 15)) + +/* +** lsl_wide_16_u16_m_tied1: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_m_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z0, 16), + z0 = svlsl_wide_m (p0, z0, 16)) + +/* +** lsl_wide_16_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #16 +** movprfx z0, z1 +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_m_untied, svuint16_t, + z0 = svlsl_wide_n_u16_m (p0, z1, 16), + z0 = svlsl_wide_m (p0, z1, 16)) + +/* +** lsl_wide_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_z_tied1, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_u16_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.h, p0/z, z4\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u16_z_tied2, svuint16_t, svuint64_t, + z0_res = svlsl_wide_u16_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_z_untied, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_u16_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_z_tied1, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_u16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_z_untied, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_z_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_z_untied, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_15_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_z_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z0, 15), + z0 = svlsl_wide_z (p0, z0, 15)) + +/* +** lsl_wide_15_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_z_untied, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z1, 15), + z0 = svlsl_wide_z (p0, z1, 15)) + +/* +** lsl_wide_16_u16_z_tied1: +** mov (z[0-9]+\.d), #16 +** movprfx z0\.h, p0/z, z0\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_z_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z0, 16), + z0 = svlsl_wide_z (p0, z0, 16)) + +/* +** lsl_wide_16_u16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #16 +** movprfx z0\.h, p0/z, z1\.h +** lsl z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_z_untied, svuint16_t, + z0 = svlsl_wide_n_u16_z (p0, z1, 16), + z0 = svlsl_wide_z (p0, z1, 16)) + +/* +** lsl_wide_u16_x_tied1: +** lsl z0\.h, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_x_tied1, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_u16_x_tied2: +** lsl z0\.h, z4\.h, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u16_x_tied2, svuint16_t, svuint64_t, + z0_res = svlsl_wide_u16_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_u16_x_untied: +** lsl z0\.h, z1\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u16_x_untied, svuint16_t, svuint64_t, + z0 = svlsl_wide_u16_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_u16_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_x_tied1, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_u16_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u16_x_untied, svuint16_t, uint64_t, + z0 = svlsl_wide_n_u16_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_u16_x_tied1: +** lsl z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_x_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_u16_x_untied: +** lsl z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u16_x_untied, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_15_u16_x_tied1: +** lsl z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_x_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z0, 15), + z0 = svlsl_wide_x (p0, z0, 15)) + +/* +** lsl_wide_15_u16_x_untied: +** lsl z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_15_u16_x_untied, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z1, 15), + z0 = svlsl_wide_x (p0, z1, 15)) + +/* +** lsl_wide_16_u16_x_tied1: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_x_tied1, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z0, 16), + z0 = svlsl_wide_x (p0, z0, 16)) + +/* +** lsl_wide_16_u16_x_untied: +** mov (z[0-9]+\.d), #16 +** lsl z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_16_u16_x_untied, svuint16_t, + z0 = svlsl_wide_n_u16_x (p0, z1, 16), + z0 = svlsl_wide_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c new file mode 100644 index 00000000000..7b1afab4918 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_m_tied1, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_u32_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u32_m_tied2, svuint32_t, svuint64_t, + z0_res = svlsl_wide_u32_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_m_untied, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_u32_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_m_tied1, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_u32_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_m_untied, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_m_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_m_untied, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_31_u32_m_tied1: +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_m_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z0, 31), + z0 = svlsl_wide_m (p0, z0, 31)) + +/* +** lsl_wide_31_u32_m_untied: +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_m_untied, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z1, 31), + z0 = svlsl_wide_m (p0, z1, 31)) + +/* +** lsl_wide_32_u32_m_tied1: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_m_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z0, 32), + z0 = svlsl_wide_m (p0, z0, 32)) + +/* +** lsl_wide_32_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #32 +** movprfx z0, z1 +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_m_untied, svuint32_t, + z0 = svlsl_wide_n_u32_m (p0, z1, 32), + z0 = svlsl_wide_m (p0, z1, 32)) + +/* +** lsl_wide_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_z_tied1, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_u32_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.s, p0/z, z4\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u32_z_tied2, svuint32_t, svuint64_t, + z0_res = svlsl_wide_u32_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_z_untied, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_u32_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_z_tied1, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_u32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_z_untied, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_z_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_z_untied, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_31_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_z_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z0, 31), + z0 = svlsl_wide_z (p0, z0, 31)) + +/* +** lsl_wide_31_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_z_untied, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z1, 31), + z0 = svlsl_wide_z (p0, z1, 31)) + +/* +** lsl_wide_32_u32_z_tied1: +** mov (z[0-9]+\.d), #32 +** movprfx z0\.s, p0/z, z0\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_z_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z0, 32), + z0 = svlsl_wide_z (p0, z0, 32)) + +/* +** lsl_wide_32_u32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #32 +** movprfx z0\.s, p0/z, z1\.s +** lsl z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_z_untied, svuint32_t, + z0 = svlsl_wide_n_u32_z (p0, z1, 32), + z0 = svlsl_wide_z (p0, z1, 32)) + +/* +** lsl_wide_u32_x_tied1: +** lsl z0\.s, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_x_tied1, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_u32_x_tied2: +** lsl z0\.s, z4\.s, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u32_x_tied2, svuint32_t, svuint64_t, + z0_res = svlsl_wide_u32_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_u32_x_untied: +** lsl z0\.s, z1\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u32_x_untied, svuint32_t, svuint64_t, + z0 = svlsl_wide_u32_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_u32_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_x_tied1, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_u32_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u32_x_untied, svuint32_t, uint64_t, + z0 = svlsl_wide_n_u32_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_u32_x_tied1: +** lsl z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_x_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_u32_x_untied: +** lsl z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u32_x_untied, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_31_u32_x_tied1: +** lsl z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_x_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z0, 31), + z0 = svlsl_wide_x (p0, z0, 31)) + +/* +** lsl_wide_31_u32_x_untied: +** lsl z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_31_u32_x_untied, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z1, 31), + z0 = svlsl_wide_x (p0, z1, 31)) + +/* +** lsl_wide_32_u32_x_tied1: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_x_tied1, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z0, 32), + z0 = svlsl_wide_x (p0, z0, 32)) + +/* +** lsl_wide_32_u32_x_untied: +** mov (z[0-9]+\.d), #32 +** lsl z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_32_u32_x_untied, svuint32_t, + z0 = svlsl_wide_n_u32_x (p0, z1, 32), + z0 = svlsl_wide_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c new file mode 100644 index 00000000000..df8b1ec86b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c @@ -0,0 +1,331 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsl_wide_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_m_tied1, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_m (p0, z0, z4), + z0 = svlsl_wide_m (p0, z0, z4)) + +/* +** lsl_wide_u8_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u8_m_tied2, svuint8_t, svuint64_t, + z0_res = svlsl_wide_u8_m (p0, z4, z0), + z0_res = svlsl_wide_m (p0, z4, z0)) + +/* +** lsl_wide_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_m_untied, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_m (p0, z1, z4), + z0 = svlsl_wide_m (p0, z1, z4)) + +/* +** lsl_wide_x0_u8_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_m_tied1, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_m (p0, z0, x0), + z0 = svlsl_wide_m (p0, z0, x0)) + +/* +** lsl_wide_x0_u8_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_m_untied, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_m (p0, z1, x0), + z0 = svlsl_wide_m (p0, z1, x0)) + +/* +** lsl_wide_1_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_m_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z0, 1), + z0 = svlsl_wide_m (p0, z0, 1)) + +/* +** lsl_wide_1_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_m_untied, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z1, 1), + z0 = svlsl_wide_m (p0, z1, 1)) + +/* +** lsl_wide_7_u8_m_tied1: +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_m_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z0, 7), + z0 = svlsl_wide_m (p0, z0, 7)) + +/* +** lsl_wide_7_u8_m_untied: +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_m_untied, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z1, 7), + z0 = svlsl_wide_m (p0, z1, 7)) + +/* +** lsl_wide_8_u8_m_tied1: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_m_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z0, 8), + z0 = svlsl_wide_m (p0, z0, 8)) + +/* +** lsl_wide_8_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #8 +** movprfx z0, z1 +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_m_untied, svuint8_t, + z0 = svlsl_wide_n_u8_m (p0, z1, 8), + z0 = svlsl_wide_m (p0, z1, 8)) + +/* +** lsl_wide_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_z_tied1, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_z (p0, z0, z4), + z0 = svlsl_wide_z (p0, z0, z4)) + +/* +** lsl_wide_u8_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.b, p0/z, z4\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u8_z_tied2, svuint8_t, svuint64_t, + z0_res = svlsl_wide_u8_z (p0, z4, z0), + z0_res = svlsl_wide_z (p0, z4, z0)) + +/* +** lsl_wide_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_z_untied, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_z (p0, z1, z4), + z0 = svlsl_wide_z (p0, z1, z4)) + +/* +** lsl_wide_x0_u8_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_z_tied1, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_z (p0, z0, x0), + z0 = svlsl_wide_z (p0, z0, x0)) + +/* +** lsl_wide_x0_u8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_z_untied, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_z (p0, z1, x0), + z0 = svlsl_wide_z (p0, z1, x0)) + +/* +** lsl_wide_1_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_z_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z0, 1), + z0 = svlsl_wide_z (p0, z0, 1)) + +/* +** lsl_wide_1_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_z_untied, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z1, 1), + z0 = svlsl_wide_z (p0, z1, 1)) + +/* +** lsl_wide_7_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_z_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z0, 7), + z0 = svlsl_wide_z (p0, z0, 7)) + +/* +** lsl_wide_7_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_z_untied, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z1, 7), + z0 = svlsl_wide_z (p0, z1, 7)) + +/* +** lsl_wide_8_u8_z_tied1: +** mov (z[0-9]+\.d), #8 +** movprfx z0\.b, p0/z, z0\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_z_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z0, 8), + z0 = svlsl_wide_z (p0, z0, 8)) + +/* +** lsl_wide_8_u8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #8 +** movprfx z0\.b, p0/z, z1\.b +** lsl z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_z_untied, svuint8_t, + z0 = svlsl_wide_n_u8_z (p0, z1, 8), + z0 = svlsl_wide_z (p0, z1, 8)) + +/* +** lsl_wide_u8_x_tied1: +** lsl z0\.b, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_x_tied1, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_x (p0, z0, z4), + z0 = svlsl_wide_x (p0, z0, z4)) + +/* +** lsl_wide_u8_x_tied2: +** lsl z0\.b, z4\.b, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsl_wide_u8_x_tied2, svuint8_t, svuint64_t, + z0_res = svlsl_wide_u8_x (p0, z4, z0), + z0_res = svlsl_wide_x (p0, z4, z0)) + +/* +** lsl_wide_u8_x_untied: +** lsl z0\.b, z1\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsl_wide_u8_x_untied, svuint8_t, svuint64_t, + z0 = svlsl_wide_u8_x (p0, z1, z4), + z0 = svlsl_wide_x (p0, z1, z4)) + +/* +** lsl_wide_x0_u8_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_x_tied1, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_x (p0, z0, x0), + z0 = svlsl_wide_x (p0, z0, x0)) + +/* +** lsl_wide_x0_u8_x_untied: +** mov (z[0-9]+\.d), x0 +** lsl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsl_wide_x0_u8_x_untied, svuint8_t, uint64_t, + z0 = svlsl_wide_n_u8_x (p0, z1, x0), + z0 = svlsl_wide_x (p0, z1, x0)) + +/* +** lsl_wide_1_u8_x_tied1: +** lsl z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_x_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z0, 1), + z0 = svlsl_wide_x (p0, z0, 1)) + +/* +** lsl_wide_1_u8_x_untied: +** lsl z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_1_u8_x_untied, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z1, 1), + z0 = svlsl_wide_x (p0, z1, 1)) + +/* +** lsl_wide_7_u8_x_tied1: +** lsl z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_x_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z0, 7), + z0 = svlsl_wide_x (p0, z0, 7)) + +/* +** lsl_wide_7_u8_x_untied: +** lsl z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_7_u8_x_untied, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z1, 7), + z0 = svlsl_wide_x (p0, z1, 7)) + +/* +** lsl_wide_8_u8_x_tied1: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_x_tied1, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z0, 8), + z0 = svlsl_wide_x (p0, z0, 8)) + +/* +** lsl_wide_8_u8_x_untied: +** mov (z[0-9]+\.d), #8 +** lsl z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (lsl_wide_8_u8_x_untied, svuint8_t, + z0 = svlsl_wide_n_u8_x (p0, z1, 8), + z0 = svlsl_wide_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c new file mode 100644 index 00000000000..61575645fad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_m_tied1, svuint16_t, + z0 = svlsr_u16_m (p0, z0, z1), + z0 = svlsr_m (p0, z0, z1)) + +/* +** lsr_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_m_tied2, svuint16_t, + z0 = svlsr_u16_m (p0, z1, z0), + z0 = svlsr_m (p0, z1, z0)) + +/* +** lsr_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_m_untied, svuint16_t, + z0 = svlsr_u16_m (p0, z1, z2), + z0 = svlsr_m (p0, z1, z2)) + +/* +** lsr_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svlsr_n_u16_m (p0, z0, x0), + z0 = svlsr_m (p0, z0, x0)) + +/* +** lsr_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svlsr_n_u16_m (p0, z1, x0), + z0 = svlsr_m (p0, z1, x0)) + +/* +** lsr_1_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_m_tied1, svuint16_t, + z0 = svlsr_n_u16_m (p0, z0, 1), + z0 = svlsr_m (p0, z0, 1)) + +/* +** lsr_1_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_m_untied, svuint16_t, + z0 = svlsr_n_u16_m (p0, z1, 1), + z0 = svlsr_m (p0, z1, 1)) + +/* +** lsr_15_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_m_tied1, svuint16_t, + z0 = svlsr_n_u16_m (p0, z0, 15), + z0 = svlsr_m (p0, z0, 15)) + +/* +** lsr_15_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_m_untied, svuint16_t, + z0 = svlsr_n_u16_m (p0, z1, 15), + z0 = svlsr_m (p0, z1, 15)) + +/* +** lsr_16_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_m_tied1, svuint16_t, + z0 = svlsr_n_u16_m (p0, z0, 16), + z0 = svlsr_m (p0, z0, 16)) + +/* +** lsr_16_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_m_untied, svuint16_t, + z0 = svlsr_n_u16_m (p0, z1, 16), + z0 = svlsr_m (p0, z1, 16)) + +/* +** lsr_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_z_tied1, svuint16_t, + z0 = svlsr_u16_z (p0, z0, z1), + z0 = svlsr_z (p0, z0, z1)) + +/* +** lsr_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_z_tied2, svuint16_t, + z0 = svlsr_u16_z (p0, z1, z0), + z0 = svlsr_z (p0, z1, z0)) + +/* +** lsr_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_z_untied, svuint16_t, + z0 = svlsr_u16_z (p0, z1, z2), + z0 = svlsr_z (p0, z1, z2)) + +/* +** lsr_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svlsr_n_u16_z (p0, z0, x0), + z0 = svlsr_z (p0, z0, x0)) + +/* +** lsr_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svlsr_n_u16_z (p0, z1, x0), + z0 = svlsr_z (p0, z1, x0)) + +/* +** lsr_1_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_z_tied1, svuint16_t, + z0 = svlsr_n_u16_z (p0, z0, 1), + z0 = svlsr_z (p0, z0, 1)) + +/* +** lsr_1_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_z_untied, svuint16_t, + z0 = svlsr_n_u16_z (p0, z1, 1), + z0 = svlsr_z (p0, z1, 1)) + +/* +** lsr_15_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_z_tied1, svuint16_t, + z0 = svlsr_n_u16_z (p0, z0, 15), + z0 = svlsr_z (p0, z0, 15)) + +/* +** lsr_15_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_z_untied, svuint16_t, + z0 = svlsr_n_u16_z (p0, z1, 15), + z0 = svlsr_z (p0, z1, 15)) + +/* +** lsr_16_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_z_tied1, svuint16_t, + z0 = svlsr_n_u16_z (p0, z0, 16), + z0 = svlsr_z (p0, z0, 16)) + +/* +** lsr_16_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_z_untied, svuint16_t, + z0 = svlsr_n_u16_z (p0, z1, 16), + z0 = svlsr_z (p0, z1, 16)) + +/* +** lsr_u16_x_tied1: +** lsr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_x_tied1, svuint16_t, + z0 = svlsr_u16_x (p0, z0, z1), + z0 = svlsr_x (p0, z0, z1)) + +/* +** lsr_u16_x_tied2: +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_x_tied2, svuint16_t, + z0 = svlsr_u16_x (p0, z1, z0), + z0 = svlsr_x (p0, z1, z0)) + +/* +** lsr_u16_x_untied: +** ( +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u16_x_untied, svuint16_t, + z0 = svlsr_u16_x (p0, z1, z2), + z0 = svlsr_x (p0, z1, z2)) + +/* +** lsr_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svlsr_n_u16_x (p0, z0, x0), + z0 = svlsr_x (p0, z0, x0)) + +/* +** lsr_w0_u16_x_untied: +** mov z0\.h, w0 +** lsrr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svlsr_n_u16_x (p0, z1, x0), + z0 = svlsr_x (p0, z1, x0)) + +/* +** lsr_1_u16_x_tied1: +** lsr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_x_tied1, svuint16_t, + z0 = svlsr_n_u16_x (p0, z0, 1), + z0 = svlsr_x (p0, z0, 1)) + +/* +** lsr_1_u16_x_untied: +** lsr z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u16_x_untied, svuint16_t, + z0 = svlsr_n_u16_x (p0, z1, 1), + z0 = svlsr_x (p0, z1, 1)) + +/* +** lsr_15_u16_x_tied1: +** lsr z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_x_tied1, svuint16_t, + z0 = svlsr_n_u16_x (p0, z0, 15), + z0 = svlsr_x (p0, z0, 15)) + +/* +** lsr_15_u16_x_untied: +** lsr z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_15_u16_x_untied, svuint16_t, + z0 = svlsr_n_u16_x (p0, z1, 15), + z0 = svlsr_x (p0, z1, 15)) + +/* +** lsr_16_u16_x_tied1: +** lsr z0\.h, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_x_tied1, svuint16_t, + z0 = svlsr_n_u16_x (p0, z0, 16), + z0 = svlsr_x (p0, z0, 16)) + +/* +** lsr_16_u16_x_untied: +** lsr z0\.h, z1\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_16_u16_x_untied, svuint16_t, + z0 = svlsr_n_u16_x (p0, z1, 16), + z0 = svlsr_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u32.c new file mode 100644 index 00000000000..796867ef8f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u32.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_m_tied1, svuint32_t, + z0 = svlsr_u32_m (p0, z0, z1), + z0 = svlsr_m (p0, z0, z1)) + +/* +** lsr_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_m_tied2, svuint32_t, + z0 = svlsr_u32_m (p0, z1, z0), + z0 = svlsr_m (p0, z1, z0)) + +/* +** lsr_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_m_untied, svuint32_t, + z0 = svlsr_u32_m (p0, z1, z2), + z0 = svlsr_m (p0, z1, z2)) + +/* +** lsr_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svlsr_n_u32_m (p0, z0, x0), + z0 = svlsr_m (p0, z0, x0)) + +/* +** lsr_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svlsr_n_u32_m (p0, z1, x0), + z0 = svlsr_m (p0, z1, x0)) + +/* +** lsr_1_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_m_tied1, svuint32_t, + z0 = svlsr_n_u32_m (p0, z0, 1), + z0 = svlsr_m (p0, z0, 1)) + +/* +** lsr_1_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_m_untied, svuint32_t, + z0 = svlsr_n_u32_m (p0, z1, 1), + z0 = svlsr_m (p0, z1, 1)) + +/* +** lsr_31_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_m_tied1, svuint32_t, + z0 = svlsr_n_u32_m (p0, z0, 31), + z0 = svlsr_m (p0, z0, 31)) + +/* +** lsr_31_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_m_untied, svuint32_t, + z0 = svlsr_n_u32_m (p0, z1, 31), + z0 = svlsr_m (p0, z1, 31)) + +/* +** lsr_32_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_m_tied1, svuint32_t, + z0 = svlsr_n_u32_m (p0, z0, 32), + z0 = svlsr_m (p0, z0, 32)) + +/* +** lsr_32_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_m_untied, svuint32_t, + z0 = svlsr_n_u32_m (p0, z1, 32), + z0 = svlsr_m (p0, z1, 32)) + +/* +** lsr_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_z_tied1, svuint32_t, + z0 = svlsr_u32_z (p0, z0, z1), + z0 = svlsr_z (p0, z0, z1)) + +/* +** lsr_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_z_tied2, svuint32_t, + z0 = svlsr_u32_z (p0, z1, z0), + z0 = svlsr_z (p0, z1, z0)) + +/* +** lsr_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_z_untied, svuint32_t, + z0 = svlsr_u32_z (p0, z1, z2), + z0 = svlsr_z (p0, z1, z2)) + +/* +** lsr_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svlsr_n_u32_z (p0, z0, x0), + z0 = svlsr_z (p0, z0, x0)) + +/* +** lsr_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svlsr_n_u32_z (p0, z1, x0), + z0 = svlsr_z (p0, z1, x0)) + +/* +** lsr_1_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_z_tied1, svuint32_t, + z0 = svlsr_n_u32_z (p0, z0, 1), + z0 = svlsr_z (p0, z0, 1)) + +/* +** lsr_1_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_z_untied, svuint32_t, + z0 = svlsr_n_u32_z (p0, z1, 1), + z0 = svlsr_z (p0, z1, 1)) + +/* +** lsr_31_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_z_tied1, svuint32_t, + z0 = svlsr_n_u32_z (p0, z0, 31), + z0 = svlsr_z (p0, z0, 31)) + +/* +** lsr_31_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_z_untied, svuint32_t, + z0 = svlsr_n_u32_z (p0, z1, 31), + z0 = svlsr_z (p0, z1, 31)) + +/* +** lsr_32_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_z_tied1, svuint32_t, + z0 = svlsr_n_u32_z (p0, z0, 32), + z0 = svlsr_z (p0, z0, 32)) + +/* +** lsr_32_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_z_untied, svuint32_t, + z0 = svlsr_n_u32_z (p0, z1, 32), + z0 = svlsr_z (p0, z1, 32)) + +/* +** lsr_u32_x_tied1: +** lsr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_x_tied1, svuint32_t, + z0 = svlsr_u32_x (p0, z0, z1), + z0 = svlsr_x (p0, z0, z1)) + +/* +** lsr_u32_x_tied2: +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_x_tied2, svuint32_t, + z0 = svlsr_u32_x (p0, z1, z0), + z0 = svlsr_x (p0, z1, z0)) + +/* +** lsr_u32_x_untied: +** ( +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u32_x_untied, svuint32_t, + z0 = svlsr_u32_x (p0, z1, z2), + z0 = svlsr_x (p0, z1, z2)) + +/* +** lsr_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svlsr_n_u32_x (p0, z0, x0), + z0 = svlsr_x (p0, z0, x0)) + +/* +** lsr_w0_u32_x_untied: +** mov z0\.s, w0 +** lsrr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svlsr_n_u32_x (p0, z1, x0), + z0 = svlsr_x (p0, z1, x0)) + +/* +** lsr_1_u32_x_tied1: +** lsr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_x_tied1, svuint32_t, + z0 = svlsr_n_u32_x (p0, z0, 1), + z0 = svlsr_x (p0, z0, 1)) + +/* +** lsr_1_u32_x_untied: +** lsr z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u32_x_untied, svuint32_t, + z0 = svlsr_n_u32_x (p0, z1, 1), + z0 = svlsr_x (p0, z1, 1)) + +/* +** lsr_31_u32_x_tied1: +** lsr z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_x_tied1, svuint32_t, + z0 = svlsr_n_u32_x (p0, z0, 31), + z0 = svlsr_x (p0, z0, 31)) + +/* +** lsr_31_u32_x_untied: +** lsr z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_31_u32_x_untied, svuint32_t, + z0 = svlsr_n_u32_x (p0, z1, 31), + z0 = svlsr_x (p0, z1, 31)) + +/* +** lsr_32_u32_x_tied1: +** lsr z0\.s, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_x_tied1, svuint32_t, + z0 = svlsr_n_u32_x (p0, z0, 32), + z0 = svlsr_x (p0, z0, 32)) + +/* +** lsr_32_u32_x_untied: +** lsr z0\.s, z1\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_32_u32_x_untied, svuint32_t, + z0 = svlsr_n_u32_x (p0, z1, 32), + z0 = svlsr_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u64.c new file mode 100644 index 00000000000..b50777f500d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u64.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_u64_m_tied1: +** lsr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_m_tied1, svuint64_t, + z0 = svlsr_u64_m (p0, z0, z1), + z0 = svlsr_m (p0, z0, z1)) + +/* +** lsr_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_m_tied2, svuint64_t, + z0 = svlsr_u64_m (p0, z1, z0), + z0 = svlsr_m (p0, z1, z0)) + +/* +** lsr_u64_m_untied: +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_m_untied, svuint64_t, + z0 = svlsr_u64_m (p0, z1, z2), + z0 = svlsr_m (p0, z1, z2)) + +/* +** lsr_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svlsr_n_u64_m (p0, z0, x0), + z0 = svlsr_m (p0, z0, x0)) + +/* +** lsr_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svlsr_n_u64_m (p0, z1, x0), + z0 = svlsr_m (p0, z1, x0)) + +/* +** lsr_1_u64_m_tied1: +** lsr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_m_tied1, svuint64_t, + z0 = svlsr_n_u64_m (p0, z0, 1), + z0 = svlsr_m (p0, z0, 1)) + +/* +** lsr_1_u64_m_untied: +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_m_untied, svuint64_t, + z0 = svlsr_n_u64_m (p0, z1, 1), + z0 = svlsr_m (p0, z1, 1)) + +/* +** lsr_63_u64_m_tied1: +** lsr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_m_tied1, svuint64_t, + z0 = svlsr_n_u64_m (p0, z0, 63), + z0 = svlsr_m (p0, z0, 63)) + +/* +** lsr_63_u64_m_untied: +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_m_untied, svuint64_t, + z0 = svlsr_n_u64_m (p0, z1, 63), + z0 = svlsr_m (p0, z1, 63)) + +/* +** lsr_64_u64_m_tied1: +** lsr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_m_tied1, svuint64_t, + z0 = svlsr_n_u64_m (p0, z0, 64), + z0 = svlsr_m (p0, z0, 64)) + +/* +** lsr_64_u64_m_untied: +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_m_untied, svuint64_t, + z0 = svlsr_n_u64_m (p0, z1, 64), + z0 = svlsr_m (p0, z1, 64)) + +/* +** lsr_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_z_tied1, svuint64_t, + z0 = svlsr_u64_z (p0, z0, z1), + z0 = svlsr_z (p0, z0, z1)) + +/* +** lsr_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_z_tied2, svuint64_t, + z0 = svlsr_u64_z (p0, z1, z0), + z0 = svlsr_z (p0, z1, z0)) + +/* +** lsr_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_z_untied, svuint64_t, + z0 = svlsr_u64_z (p0, z1, z2), + z0 = svlsr_z (p0, z1, z2)) + +/* +** lsr_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** lsr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svlsr_n_u64_z (p0, z0, x0), + z0 = svlsr_z (p0, z0, x0)) + +/* +** lsr_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** lsr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svlsr_n_u64_z (p0, z1, x0), + z0 = svlsr_z (p0, z1, x0)) + +/* +** lsr_1_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_z_tied1, svuint64_t, + z0 = svlsr_n_u64_z (p0, z0, 1), + z0 = svlsr_z (p0, z0, 1)) + +/* +** lsr_1_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsr z0\.d, p0/m, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_z_untied, svuint64_t, + z0 = svlsr_n_u64_z (p0, z1, 1), + z0 = svlsr_z (p0, z1, 1)) + +/* +** lsr_63_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_z_tied1, svuint64_t, + z0 = svlsr_n_u64_z (p0, z0, 63), + z0 = svlsr_z (p0, z0, 63)) + +/* +** lsr_63_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsr z0\.d, p0/m, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_z_untied, svuint64_t, + z0 = svlsr_n_u64_z (p0, z1, 63), + z0 = svlsr_z (p0, z1, 63)) + +/* +** lsr_64_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** lsr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_z_tied1, svuint64_t, + z0 = svlsr_n_u64_z (p0, z0, 64), + z0 = svlsr_z (p0, z0, 64)) + +/* +** lsr_64_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** lsr z0\.d, p0/m, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_z_untied, svuint64_t, + z0 = svlsr_n_u64_z (p0, z1, 64), + z0 = svlsr_z (p0, z1, 64)) + +/* +** lsr_u64_x_tied1: +** lsr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_x_tied1, svuint64_t, + z0 = svlsr_u64_x (p0, z0, z1), + z0 = svlsr_x (p0, z0, z1)) + +/* +** lsr_u64_x_tied2: +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_x_tied2, svuint64_t, + z0 = svlsr_u64_x (p0, z1, z0), + z0 = svlsr_x (p0, z1, z0)) + +/* +** lsr_u64_x_untied: +** ( +** movprfx z0, z1 +** lsr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u64_x_untied, svuint64_t, + z0 = svlsr_u64_x (p0, z1, z2), + z0 = svlsr_x (p0, z1, z2)) + +/* +** lsr_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svlsr_n_u64_x (p0, z0, x0), + z0 = svlsr_x (p0, z0, x0)) + +/* +** lsr_x0_u64_x_untied: +** mov z0\.d, x0 +** lsrr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (lsr_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svlsr_n_u64_x (p0, z1, x0), + z0 = svlsr_x (p0, z1, x0)) + +/* +** lsr_1_u64_x_tied1: +** lsr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_x_tied1, svuint64_t, + z0 = svlsr_n_u64_x (p0, z0, 1), + z0 = svlsr_x (p0, z0, 1)) + +/* +** lsr_1_u64_x_untied: +** lsr z0\.d, z1\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u64_x_untied, svuint64_t, + z0 = svlsr_n_u64_x (p0, z1, 1), + z0 = svlsr_x (p0, z1, 1)) + +/* +** lsr_63_u64_x_tied1: +** lsr z0\.d, z0\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_x_tied1, svuint64_t, + z0 = svlsr_n_u64_x (p0, z0, 63), + z0 = svlsr_x (p0, z0, 63)) + +/* +** lsr_63_u64_x_untied: +** lsr z0\.d, z1\.d, #63 +** ret +*/ +TEST_UNIFORM_Z (lsr_63_u64_x_untied, svuint64_t, + z0 = svlsr_n_u64_x (p0, z1, 63), + z0 = svlsr_x (p0, z1, 63)) + +/* +** lsr_64_u64_x_tied1: +** lsr z0\.d, z0\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_x_tied1, svuint64_t, + z0 = svlsr_n_u64_x (p0, z0, 64), + z0 = svlsr_x (p0, z0, 64)) + +/* +** lsr_64_u64_x_untied: +** lsr z0\.d, z1\.d, #64 +** ret +*/ +TEST_UNIFORM_Z (lsr_64_u64_x_untied, svuint64_t, + z0 = svlsr_n_u64_x (p0, z1, 64), + z0 = svlsr_x (p0, z1, 64)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c new file mode 100644 index 00000000000..a049ca90556 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c @@ -0,0 +1,340 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_m_tied1, svuint8_t, + z0 = svlsr_u8_m (p0, z0, z1), + z0 = svlsr_m (p0, z0, z1)) + +/* +** lsr_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_m_tied2, svuint8_t, + z0 = svlsr_u8_m (p0, z1, z0), + z0 = svlsr_m (p0, z1, z0)) + +/* +** lsr_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_m_untied, svuint8_t, + z0 = svlsr_u8_m (p0, z1, z2), + z0 = svlsr_m (p0, z1, z2)) + +/* +** lsr_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svlsr_n_u8_m (p0, z0, x0), + z0 = svlsr_m (p0, z0, x0)) + +/* +** lsr_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svlsr_n_u8_m (p0, z1, x0), + z0 = svlsr_m (p0, z1, x0)) + +/* +** lsr_1_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_m_tied1, svuint8_t, + z0 = svlsr_n_u8_m (p0, z0, 1), + z0 = svlsr_m (p0, z0, 1)) + +/* +** lsr_1_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_m_untied, svuint8_t, + z0 = svlsr_n_u8_m (p0, z1, 1), + z0 = svlsr_m (p0, z1, 1)) + +/* +** lsr_7_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_m_tied1, svuint8_t, + z0 = svlsr_n_u8_m (p0, z0, 7), + z0 = svlsr_m (p0, z0, 7)) + +/* +** lsr_7_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_m_untied, svuint8_t, + z0 = svlsr_n_u8_m (p0, z1, 7), + z0 = svlsr_m (p0, z1, 7)) + +/* +** lsr_8_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_m_tied1, svuint8_t, + z0 = svlsr_n_u8_m (p0, z0, 8), + z0 = svlsr_m (p0, z0, 8)) + +/* +** lsr_8_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_m_untied, svuint8_t, + z0 = svlsr_n_u8_m (p0, z1, 8), + z0 = svlsr_m (p0, z1, 8)) + +/* +** lsr_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_z_tied1, svuint8_t, + z0 = svlsr_u8_z (p0, z0, z1), + z0 = svlsr_z (p0, z0, z1)) + +/* +** lsr_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_z_tied2, svuint8_t, + z0 = svlsr_u8_z (p0, z1, z0), + z0 = svlsr_z (p0, z1, z0)) + +/* +** lsr_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_z_untied, svuint8_t, + z0 = svlsr_u8_z (p0, z1, z2), + z0 = svlsr_z (p0, z1, z2)) + +/* +** lsr_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svlsr_n_u8_z (p0, z0, x0), + z0 = svlsr_z (p0, z0, x0)) + +/* +** lsr_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svlsr_n_u8_z (p0, z1, x0), + z0 = svlsr_z (p0, z1, x0)) + +/* +** lsr_1_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_z_tied1, svuint8_t, + z0 = svlsr_n_u8_z (p0, z0, 1), + z0 = svlsr_z (p0, z0, 1)) + +/* +** lsr_1_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_z_untied, svuint8_t, + z0 = svlsr_n_u8_z (p0, z1, 1), + z0 = svlsr_z (p0, z1, 1)) + +/* +** lsr_7_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_z_tied1, svuint8_t, + z0 = svlsr_n_u8_z (p0, z0, 7), + z0 = svlsr_z (p0, z0, 7)) + +/* +** lsr_7_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_z_untied, svuint8_t, + z0 = svlsr_n_u8_z (p0, z1, 7), + z0 = svlsr_z (p0, z1, 7)) + +/* +** lsr_8_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_z_tied1, svuint8_t, + z0 = svlsr_n_u8_z (p0, z0, 8), + z0 = svlsr_z (p0, z0, 8)) + +/* +** lsr_8_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_z_untied, svuint8_t, + z0 = svlsr_n_u8_z (p0, z1, 8), + z0 = svlsr_z (p0, z1, 8)) + +/* +** lsr_u8_x_tied1: +** lsr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_x_tied1, svuint8_t, + z0 = svlsr_u8_x (p0, z0, z1), + z0 = svlsr_x (p0, z0, z1)) + +/* +** lsr_u8_x_tied2: +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_x_tied2, svuint8_t, + z0 = svlsr_u8_x (p0, z1, z0), + z0 = svlsr_x (p0, z1, z0)) + +/* +** lsr_u8_x_untied: +** ( +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (lsr_u8_x_untied, svuint8_t, + z0 = svlsr_u8_x (p0, z1, z2), + z0 = svlsr_x (p0, z1, z2)) + +/* +** lsr_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svlsr_n_u8_x (p0, z0, x0), + z0 = svlsr_x (p0, z0, x0)) + +/* +** lsr_w0_u8_x_untied: +** mov z0\.b, w0 +** lsrr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (lsr_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svlsr_n_u8_x (p0, z1, x0), + z0 = svlsr_x (p0, z1, x0)) + +/* +** lsr_1_u8_x_tied1: +** lsr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_x_tied1, svuint8_t, + z0 = svlsr_n_u8_x (p0, z0, 1), + z0 = svlsr_x (p0, z0, 1)) + +/* +** lsr_1_u8_x_untied: +** lsr z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_1_u8_x_untied, svuint8_t, + z0 = svlsr_n_u8_x (p0, z1, 1), + z0 = svlsr_x (p0, z1, 1)) + +/* +** lsr_7_u8_x_tied1: +** lsr z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_x_tied1, svuint8_t, + z0 = svlsr_n_u8_x (p0, z0, 7), + z0 = svlsr_x (p0, z0, 7)) + +/* +** lsr_7_u8_x_untied: +** lsr z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_7_u8_x_untied, svuint8_t, + z0 = svlsr_n_u8_x (p0, z1, 7), + z0 = svlsr_x (p0, z1, 7)) + +/* +** lsr_8_u8_x_tied1: +** lsr z0\.b, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_x_tied1, svuint8_t, + z0 = svlsr_n_u8_x (p0, z0, 8), + z0 = svlsr_x (p0, z0, 8)) + +/* +** lsr_8_u8_x_untied: +** lsr z0\.b, z1\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_8_u8_x_untied, svuint8_t, + z0 = svlsr_n_u8_x (p0, z1, 8), + z0 = svlsr_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u16.c new file mode 100644 index 00000000000..863b51a2fc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u16.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_wide_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_m_tied1, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_m (p0, z0, z4), + z0 = svlsr_wide_m (p0, z0, z4)) + +/* +** lsr_wide_u16_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u16_m_tied2, svuint16_t, svuint64_t, + z0_res = svlsr_wide_u16_m (p0, z4, z0), + z0_res = svlsr_wide_m (p0, z4, z0)) + +/* +** lsr_wide_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_m_untied, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_m (p0, z1, z4), + z0 = svlsr_wide_m (p0, z1, z4)) + +/* +** lsr_wide_x0_u16_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_m_tied1, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_m (p0, z0, x0), + z0 = svlsr_wide_m (p0, z0, x0)) + +/* +** lsr_wide_x0_u16_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_m_untied, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_m (p0, z1, x0), + z0 = svlsr_wide_m (p0, z1, x0)) + +/* +** lsr_wide_1_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_m_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z0, 1), + z0 = svlsr_wide_m (p0, z0, 1)) + +/* +** lsr_wide_1_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_m_untied, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z1, 1), + z0 = svlsr_wide_m (p0, z1, 1)) + +/* +** lsr_wide_15_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_m_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z0, 15), + z0 = svlsr_wide_m (p0, z0, 15)) + +/* +** lsr_wide_15_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_m_untied, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z1, 15), + z0 = svlsr_wide_m (p0, z1, 15)) + +/* +** lsr_wide_16_u16_m_tied1: +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_m_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z0, 16), + z0 = svlsr_wide_m (p0, z0, 16)) + +/* +** lsr_wide_16_u16_m_untied: +** movprfx z0, z1 +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_m_untied, svuint16_t, + z0 = svlsr_wide_n_u16_m (p0, z1, 16), + z0 = svlsr_wide_m (p0, z1, 16)) + +/* +** lsr_wide_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_z_tied1, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_z (p0, z0, z4), + z0 = svlsr_wide_z (p0, z0, z4)) + +/* +** lsr_wide_u16_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.h, p0/z, z4\.h +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u16_z_tied2, svuint16_t, svuint64_t, + z0_res = svlsr_wide_u16_z (p0, z4, z0), + z0_res = svlsr_wide_z (p0, z4, z0)) + +/* +** lsr_wide_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_z_untied, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_z (p0, z1, z4), + z0 = svlsr_wide_z (p0, z1, z4)) + +/* +** lsr_wide_x0_u16_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_z_tied1, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_z (p0, z0, x0), + z0 = svlsr_wide_z (p0, z0, x0)) + +/* +** lsr_wide_x0_u16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_z_untied, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_z (p0, z1, x0), + z0 = svlsr_wide_z (p0, z1, x0)) + +/* +** lsr_wide_1_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_z_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z0, 1), + z0 = svlsr_wide_z (p0, z0, 1)) + +/* +** lsr_wide_1_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_z_untied, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z1, 1), + z0 = svlsr_wide_z (p0, z1, 1)) + +/* +** lsr_wide_15_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_z_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z0, 15), + z0 = svlsr_wide_z (p0, z0, 15)) + +/* +** lsr_wide_15_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_z_untied, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z1, 15), + z0 = svlsr_wide_z (p0, z1, 15)) + +/* +** lsr_wide_16_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_z_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z0, 16), + z0 = svlsr_wide_z (p0, z0, 16)) + +/* +** lsr_wide_16_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** lsr z0\.h, p0/m, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_z_untied, svuint16_t, + z0 = svlsr_wide_n_u16_z (p0, z1, 16), + z0 = svlsr_wide_z (p0, z1, 16)) + +/* +** lsr_wide_u16_x_tied1: +** lsr z0\.h, z0\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_x_tied1, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_x (p0, z0, z4), + z0 = svlsr_wide_x (p0, z0, z4)) + +/* +** lsr_wide_u16_x_tied2: +** lsr z0\.h, z4\.h, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u16_x_tied2, svuint16_t, svuint64_t, + z0_res = svlsr_wide_u16_x (p0, z4, z0), + z0_res = svlsr_wide_x (p0, z4, z0)) + +/* +** lsr_wide_u16_x_untied: +** lsr z0\.h, z1\.h, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u16_x_untied, svuint16_t, svuint64_t, + z0 = svlsr_wide_u16_x (p0, z1, z4), + z0 = svlsr_wide_x (p0, z1, z4)) + +/* +** lsr_wide_x0_u16_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_x_tied1, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_x (p0, z0, x0), + z0 = svlsr_wide_x (p0, z0, x0)) + +/* +** lsr_wide_x0_u16_x_untied: +** mov (z[0-9]+\.d), x0 +** lsr z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u16_x_untied, svuint16_t, uint64_t, + z0 = svlsr_wide_n_u16_x (p0, z1, x0), + z0 = svlsr_wide_x (p0, z1, x0)) + +/* +** lsr_wide_1_u16_x_tied1: +** lsr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_x_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z0, 1), + z0 = svlsr_wide_x (p0, z0, 1)) + +/* +** lsr_wide_1_u16_x_untied: +** lsr z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u16_x_untied, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z1, 1), + z0 = svlsr_wide_x (p0, z1, 1)) + +/* +** lsr_wide_15_u16_x_tied1: +** lsr z0\.h, z0\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_x_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z0, 15), + z0 = svlsr_wide_x (p0, z0, 15)) + +/* +** lsr_wide_15_u16_x_untied: +** lsr z0\.h, z1\.h, #15 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_15_u16_x_untied, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z1, 15), + z0 = svlsr_wide_x (p0, z1, 15)) + +/* +** lsr_wide_16_u16_x_tied1: +** lsr z0\.h, z0\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_x_tied1, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z0, 16), + z0 = svlsr_wide_x (p0, z0, 16)) + +/* +** lsr_wide_16_u16_x_untied: +** lsr z0\.h, z1\.h, #16 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_16_u16_x_untied, svuint16_t, + z0 = svlsr_wide_n_u16_x (p0, z1, 16), + z0 = svlsr_wide_x (p0, z1, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u32.c new file mode 100644 index 00000000000..73c2cf86e33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u32.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_wide_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_m_tied1, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_m (p0, z0, z4), + z0 = svlsr_wide_m (p0, z0, z4)) + +/* +** lsr_wide_u32_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u32_m_tied2, svuint32_t, svuint64_t, + z0_res = svlsr_wide_u32_m (p0, z4, z0), + z0_res = svlsr_wide_m (p0, z4, z0)) + +/* +** lsr_wide_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_m_untied, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_m (p0, z1, z4), + z0 = svlsr_wide_m (p0, z1, z4)) + +/* +** lsr_wide_x0_u32_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_m_tied1, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_m (p0, z0, x0), + z0 = svlsr_wide_m (p0, z0, x0)) + +/* +** lsr_wide_x0_u32_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_m_untied, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_m (p0, z1, x0), + z0 = svlsr_wide_m (p0, z1, x0)) + +/* +** lsr_wide_1_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_m_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z0, 1), + z0 = svlsr_wide_m (p0, z0, 1)) + +/* +** lsr_wide_1_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_m_untied, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z1, 1), + z0 = svlsr_wide_m (p0, z1, 1)) + +/* +** lsr_wide_31_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_m_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z0, 31), + z0 = svlsr_wide_m (p0, z0, 31)) + +/* +** lsr_wide_31_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_m_untied, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z1, 31), + z0 = svlsr_wide_m (p0, z1, 31)) + +/* +** lsr_wide_32_u32_m_tied1: +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_m_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z0, 32), + z0 = svlsr_wide_m (p0, z0, 32)) + +/* +** lsr_wide_32_u32_m_untied: +** movprfx z0, z1 +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_m_untied, svuint32_t, + z0 = svlsr_wide_n_u32_m (p0, z1, 32), + z0 = svlsr_wide_m (p0, z1, 32)) + +/* +** lsr_wide_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_z_tied1, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_z (p0, z0, z4), + z0 = svlsr_wide_z (p0, z0, z4)) + +/* +** lsr_wide_u32_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.s, p0/z, z4\.s +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u32_z_tied2, svuint32_t, svuint64_t, + z0_res = svlsr_wide_u32_z (p0, z4, z0), + z0_res = svlsr_wide_z (p0, z4, z0)) + +/* +** lsr_wide_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_z_untied, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_z (p0, z1, z4), + z0 = svlsr_wide_z (p0, z1, z4)) + +/* +** lsr_wide_x0_u32_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_z_tied1, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_z (p0, z0, x0), + z0 = svlsr_wide_z (p0, z0, x0)) + +/* +** lsr_wide_x0_u32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_z_untied, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_z (p0, z1, x0), + z0 = svlsr_wide_z (p0, z1, x0)) + +/* +** lsr_wide_1_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_z_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z0, 1), + z0 = svlsr_wide_z (p0, z0, 1)) + +/* +** lsr_wide_1_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_z_untied, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z1, 1), + z0 = svlsr_wide_z (p0, z1, 1)) + +/* +** lsr_wide_31_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_z_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z0, 31), + z0 = svlsr_wide_z (p0, z0, 31)) + +/* +** lsr_wide_31_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_z_untied, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z1, 31), + z0 = svlsr_wide_z (p0, z1, 31)) + +/* +** lsr_wide_32_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_z_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z0, 32), + z0 = svlsr_wide_z (p0, z0, 32)) + +/* +** lsr_wide_32_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** lsr z0\.s, p0/m, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_z_untied, svuint32_t, + z0 = svlsr_wide_n_u32_z (p0, z1, 32), + z0 = svlsr_wide_z (p0, z1, 32)) + +/* +** lsr_wide_u32_x_tied1: +** lsr z0\.s, z0\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_x_tied1, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_x (p0, z0, z4), + z0 = svlsr_wide_x (p0, z0, z4)) + +/* +** lsr_wide_u32_x_tied2: +** lsr z0\.s, z4\.s, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u32_x_tied2, svuint32_t, svuint64_t, + z0_res = svlsr_wide_u32_x (p0, z4, z0), + z0_res = svlsr_wide_x (p0, z4, z0)) + +/* +** lsr_wide_u32_x_untied: +** lsr z0\.s, z1\.s, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u32_x_untied, svuint32_t, svuint64_t, + z0 = svlsr_wide_u32_x (p0, z1, z4), + z0 = svlsr_wide_x (p0, z1, z4)) + +/* +** lsr_wide_x0_u32_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_x_tied1, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_x (p0, z0, x0), + z0 = svlsr_wide_x (p0, z0, x0)) + +/* +** lsr_wide_x0_u32_x_untied: +** mov (z[0-9]+\.d), x0 +** lsr z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u32_x_untied, svuint32_t, uint64_t, + z0 = svlsr_wide_n_u32_x (p0, z1, x0), + z0 = svlsr_wide_x (p0, z1, x0)) + +/* +** lsr_wide_1_u32_x_tied1: +** lsr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_x_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z0, 1), + z0 = svlsr_wide_x (p0, z0, 1)) + +/* +** lsr_wide_1_u32_x_untied: +** lsr z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u32_x_untied, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z1, 1), + z0 = svlsr_wide_x (p0, z1, 1)) + +/* +** lsr_wide_31_u32_x_tied1: +** lsr z0\.s, z0\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_x_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z0, 31), + z0 = svlsr_wide_x (p0, z0, 31)) + +/* +** lsr_wide_31_u32_x_untied: +** lsr z0\.s, z1\.s, #31 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_31_u32_x_untied, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z1, 31), + z0 = svlsr_wide_x (p0, z1, 31)) + +/* +** lsr_wide_32_u32_x_tied1: +** lsr z0\.s, z0\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_x_tied1, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z0, 32), + z0 = svlsr_wide_x (p0, z0, 32)) + +/* +** lsr_wide_32_u32_x_untied: +** lsr z0\.s, z1\.s, #32 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_32_u32_x_untied, svuint32_t, + z0 = svlsr_wide_n_u32_x (p0, z1, 32), + z0 = svlsr_wide_x (p0, z1, 32)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u8.c new file mode 100644 index 00000000000..fe44eabda11 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_wide_u8.c @@ -0,0 +1,325 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** lsr_wide_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_m_tied1, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_m (p0, z0, z4), + z0 = svlsr_wide_m (p0, z0, z4)) + +/* +** lsr_wide_u8_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u8_m_tied2, svuint8_t, svuint64_t, + z0_res = svlsr_wide_u8_m (p0, z4, z0), + z0_res = svlsr_wide_m (p0, z4, z0)) + +/* +** lsr_wide_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_m_untied, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_m (p0, z1, z4), + z0 = svlsr_wide_m (p0, z1, z4)) + +/* +** lsr_wide_x0_u8_m_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_m_tied1, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_m (p0, z0, x0), + z0 = svlsr_wide_m (p0, z0, x0)) + +/* +** lsr_wide_x0_u8_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_m_untied, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_m (p0, z1, x0), + z0 = svlsr_wide_m (p0, z1, x0)) + +/* +** lsr_wide_1_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_m_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z0, 1), + z0 = svlsr_wide_m (p0, z0, 1)) + +/* +** lsr_wide_1_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_m_untied, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z1, 1), + z0 = svlsr_wide_m (p0, z1, 1)) + +/* +** lsr_wide_7_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_m_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z0, 7), + z0 = svlsr_wide_m (p0, z0, 7)) + +/* +** lsr_wide_7_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_m_untied, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z1, 7), + z0 = svlsr_wide_m (p0, z1, 7)) + +/* +** lsr_wide_8_u8_m_tied1: +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_m_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z0, 8), + z0 = svlsr_wide_m (p0, z0, 8)) + +/* +** lsr_wide_8_u8_m_untied: +** movprfx z0, z1 +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_m_untied, svuint8_t, + z0 = svlsr_wide_n_u8_m (p0, z1, 8), + z0 = svlsr_wide_m (p0, z1, 8)) + +/* +** lsr_wide_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_z_tied1, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_z (p0, z0, z4), + z0 = svlsr_wide_z (p0, z0, z4)) + +/* +** lsr_wide_u8_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.b, p0/z, z4\.b +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u8_z_tied2, svuint8_t, svuint64_t, + z0_res = svlsr_wide_u8_z (p0, z4, z0), + z0_res = svlsr_wide_z (p0, z4, z0)) + +/* +** lsr_wide_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_z_untied, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_z (p0, z1, z4), + z0 = svlsr_wide_z (p0, z1, z4)) + +/* +** lsr_wide_x0_u8_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_z_tied1, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_z (p0, z0, x0), + z0 = svlsr_wide_z (p0, z0, x0)) + +/* +** lsr_wide_x0_u8_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_z_untied, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_z (p0, z1, x0), + z0 = svlsr_wide_z (p0, z1, x0)) + +/* +** lsr_wide_1_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_z_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z0, 1), + z0 = svlsr_wide_z (p0, z0, 1)) + +/* +** lsr_wide_1_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_z_untied, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z1, 1), + z0 = svlsr_wide_z (p0, z1, 1)) + +/* +** lsr_wide_7_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_z_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z0, 7), + z0 = svlsr_wide_z (p0, z0, 7)) + +/* +** lsr_wide_7_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_z_untied, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z1, 7), + z0 = svlsr_wide_z (p0, z1, 7)) + +/* +** lsr_wide_8_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_z_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z0, 8), + z0 = svlsr_wide_z (p0, z0, 8)) + +/* +** lsr_wide_8_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** lsr z0\.b, p0/m, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_z_untied, svuint8_t, + z0 = svlsr_wide_n_u8_z (p0, z1, 8), + z0 = svlsr_wide_z (p0, z1, 8)) + +/* +** lsr_wide_u8_x_tied1: +** lsr z0\.b, z0\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_x_tied1, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_x (p0, z0, z4), + z0 = svlsr_wide_x (p0, z0, z4)) + +/* +** lsr_wide_u8_x_tied2: +** lsr z0\.b, z4\.b, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (lsr_wide_u8_x_tied2, svuint8_t, svuint64_t, + z0_res = svlsr_wide_u8_x (p0, z4, z0), + z0_res = svlsr_wide_x (p0, z4, z0)) + +/* +** lsr_wide_u8_x_untied: +** lsr z0\.b, z1\.b, z4\.d +** ret +*/ +TEST_DUAL_Z (lsr_wide_u8_x_untied, svuint8_t, svuint64_t, + z0 = svlsr_wide_u8_x (p0, z1, z4), + z0 = svlsr_wide_x (p0, z1, z4)) + +/* +** lsr_wide_x0_u8_x_tied1: +** mov (z[0-9]+\.d), x0 +** lsr z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_x_tied1, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_x (p0, z0, x0), + z0 = svlsr_wide_x (p0, z0, x0)) + +/* +** lsr_wide_x0_u8_x_untied: +** mov (z[0-9]+\.d), x0 +** lsr z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (lsr_wide_x0_u8_x_untied, svuint8_t, uint64_t, + z0 = svlsr_wide_n_u8_x (p0, z1, x0), + z0 = svlsr_wide_x (p0, z1, x0)) + +/* +** lsr_wide_1_u8_x_tied1: +** lsr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_x_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z0, 1), + z0 = svlsr_wide_x (p0, z0, 1)) + +/* +** lsr_wide_1_u8_x_untied: +** lsr z0\.b, z1\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_1_u8_x_untied, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z1, 1), + z0 = svlsr_wide_x (p0, z1, 1)) + +/* +** lsr_wide_7_u8_x_tied1: +** lsr z0\.b, z0\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_x_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z0, 7), + z0 = svlsr_wide_x (p0, z0, 7)) + +/* +** lsr_wide_7_u8_x_untied: +** lsr z0\.b, z1\.b, #7 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_7_u8_x_untied, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z1, 7), + z0 = svlsr_wide_x (p0, z1, 7)) + +/* +** lsr_wide_8_u8_x_tied1: +** lsr z0\.b, z0\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_x_tied1, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z0, 8), + z0 = svlsr_wide_x (p0, z0, 8)) + +/* +** lsr_wide_8_u8_x_untied: +** lsr z0\.b, z1\.b, #8 +** ret +*/ +TEST_UNIFORM_Z (lsr_wide_8_u8_x_untied, svuint8_t, + z0 = svlsr_wide_n_u8_x (p0, z1, 8), + z0 = svlsr_wide_x (p0, z1, 8)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f16.c new file mode 100644 index 00000000000..7656f9e5410 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_f16_m_tied1: +** fmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_m_tied1, svfloat16_t, + z0 = svmad_f16_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmad z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_m_tied2, svfloat16_t, + z0 = svmad_f16_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmad z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_m_tied3, svfloat16_t, + z0 = svmad_f16_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_f16_m_untied: +** movprfx z0, z1 +** fmad z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_m_untied, svfloat16_t, + z0 = svmad_f16_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmad_n_f16_m (p0, z0, z1, d4), + z0 = svmad_m (p0, z0, z1, d4)) + +/* +** mad_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmad_n_f16_m (p0, z1, z2, d4), + z0 = svmad_m (p0, z1, z2, d4)) + +/* +** mad_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_m_tied1, svfloat16_t, + z0 = svmad_n_f16_m (p0, z0, z1, 2), + z0 = svmad_m (p0, z0, z1, 2)) + +/* +** mad_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_m_untied, svfloat16_t, + z0 = svmad_n_f16_m (p0, z1, z2, 2), + z0 = svmad_m (p0, z1, z2, 2)) + +/* +** mad_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_z_tied1, svfloat16_t, + z0 = svmad_f16_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_z_tied2, svfloat16_t, + z0 = svmad_f16_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_z_tied3, svfloat16_t, + z0 = svmad_f16_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f16_z_untied, svfloat16_t, + z0 = svmad_f16_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmad_n_f16_z (p0, z0, z1, d4), + z0 = svmad_z (p0, z0, z1, d4)) + +/* +** mad_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svmad_n_f16_z (p0, z1, z0, d4), + z0 = svmad_z (p0, z1, z0, d4)) + +/* +** mad_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmad_n_f16_z (p0, z1, z2, d4), + z0 = svmad_z (p0, z1, z2, d4)) + +/* +** mad_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_z_tied1, svfloat16_t, + z0 = svmad_n_f16_z (p0, z0, z1, 2), + z0 = svmad_z (p0, z0, z1, 2)) + +/* +** mad_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_z_tied2, svfloat16_t, + z0 = svmad_n_f16_z (p0, z1, z0, 2), + z0 = svmad_z (p0, z1, z0, 2)) + +/* +** mad_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_z_untied, svfloat16_t, + z0 = svmad_n_f16_z (p0, z1, z2, 2), + z0 = svmad_z (p0, z1, z2, 2)) + +/* +** mad_f16_x_tied1: +** fmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_x_tied1, svfloat16_t, + z0 = svmad_f16_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_f16_x_tied2: +** fmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_x_tied2, svfloat16_t, + z0 = svmad_f16_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_f16_x_tied3: +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_f16_x_tied3, svfloat16_t, + z0 = svmad_f16_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_f16_x_untied: +** ( +** movprfx z0, z1 +** fmad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fmad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f16_x_untied, svfloat16_t, + z0 = svmad_f16_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmad_n_f16_x (p0, z0, z1, d4), + z0 = svmad_x (p0, z0, z1, d4)) + +/* +** mad_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svmad_n_f16_x (p0, z1, z0, d4), + z0 = svmad_x (p0, z1, z0, d4)) + +/* +** mad_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZD (mad_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmad_n_f16_x (p0, z1, z2, d4), + z0 = svmad_x (p0, z1, z2, d4)) + +/* +** mad_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_x_tied1, svfloat16_t, + z0 = svmad_n_f16_x (p0, z0, z1, 2), + z0 = svmad_x (p0, z0, z1, 2)) + +/* +** mad_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_x_tied2, svfloat16_t, + z0 = svmad_n_f16_x (p0, z1, z0, 2), + z0 = svmad_x (p0, z1, z0, 2)) + +/* +** mad_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_2_f16_x_untied, svfloat16_t, + z0 = svmad_n_f16_x (p0, z1, z2, 2), + z0 = svmad_x (p0, z1, z2, 2)) + +/* +** ptrue_mad_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f16_x_tied1, svfloat16_t, + z0 = svmad_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svmad_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_mad_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f16_x_tied2, svfloat16_t, + z0 = svmad_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svmad_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_mad_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f16_x_tied3, svfloat16_t, + z0 = svmad_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svmad_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_mad_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f16_x_untied, svfloat16_t, + z0 = svmad_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svmad_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_mad_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f16_x_tied1, svfloat16_t, + z0 = svmad_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svmad_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_mad_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f16_x_tied2, svfloat16_t, + z0 = svmad_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svmad_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_mad_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f16_x_untied, svfloat16_t, + z0 = svmad_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svmad_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f32.c new file mode 100644 index 00000000000..dbdd2b9d10b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_f32_m_tied1: +** fmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_m_tied1, svfloat32_t, + z0 = svmad_f32_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmad z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_m_tied2, svfloat32_t, + z0 = svmad_f32_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmad z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_m_tied3, svfloat32_t, + z0 = svmad_f32_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_f32_m_untied: +** movprfx z0, z1 +** fmad z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_m_untied, svfloat32_t, + z0 = svmad_f32_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmad_n_f32_m (p0, z0, z1, d4), + z0 = svmad_m (p0, z0, z1, d4)) + +/* +** mad_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_m_untied, svfloat32_t, float, + z0 = svmad_n_f32_m (p0, z1, z2, d4), + z0 = svmad_m (p0, z1, z2, d4)) + +/* +** mad_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_m_tied1, svfloat32_t, + z0 = svmad_n_f32_m (p0, z0, z1, 2), + z0 = svmad_m (p0, z0, z1, 2)) + +/* +** mad_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_m_untied, svfloat32_t, + z0 = svmad_n_f32_m (p0, z1, z2, 2), + z0 = svmad_m (p0, z1, z2, 2)) + +/* +** mad_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_z_tied1, svfloat32_t, + z0 = svmad_f32_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_z_tied2, svfloat32_t, + z0 = svmad_f32_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_z_tied3, svfloat32_t, + z0 = svmad_f32_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f32_z_untied, svfloat32_t, + z0 = svmad_f32_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmad_n_f32_z (p0, z0, z1, d4), + z0 = svmad_z (p0, z0, z1, d4)) + +/* +** mad_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_z_tied2, svfloat32_t, float, + z0 = svmad_n_f32_z (p0, z1, z0, d4), + z0 = svmad_z (p0, z1, z0, d4)) + +/* +** mad_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_z_untied, svfloat32_t, float, + z0 = svmad_n_f32_z (p0, z1, z2, d4), + z0 = svmad_z (p0, z1, z2, d4)) + +/* +** mad_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_z_tied1, svfloat32_t, + z0 = svmad_n_f32_z (p0, z0, z1, 2), + z0 = svmad_z (p0, z0, z1, 2)) + +/* +** mad_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_z_tied2, svfloat32_t, + z0 = svmad_n_f32_z (p0, z1, z0, 2), + z0 = svmad_z (p0, z1, z0, 2)) + +/* +** mad_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_z_untied, svfloat32_t, + z0 = svmad_n_f32_z (p0, z1, z2, 2), + z0 = svmad_z (p0, z1, z2, 2)) + +/* +** mad_f32_x_tied1: +** fmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_x_tied1, svfloat32_t, + z0 = svmad_f32_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_f32_x_tied2: +** fmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_x_tied2, svfloat32_t, + z0 = svmad_f32_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_f32_x_tied3: +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_f32_x_tied3, svfloat32_t, + z0 = svmad_f32_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_f32_x_untied: +** ( +** movprfx z0, z1 +** fmad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fmad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f32_x_untied, svfloat32_t, + z0 = svmad_f32_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmad_n_f32_x (p0, z0, z1, d4), + z0 = svmad_x (p0, z0, z1, d4)) + +/* +** mad_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_x_tied2, svfloat32_t, float, + z0 = svmad_n_f32_x (p0, z1, z0, d4), + z0 = svmad_x (p0, z1, z0, d4)) + +/* +** mad_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZD (mad_s4_f32_x_untied, svfloat32_t, float, + z0 = svmad_n_f32_x (p0, z1, z2, d4), + z0 = svmad_x (p0, z1, z2, d4)) + +/* +** mad_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_x_tied1, svfloat32_t, + z0 = svmad_n_f32_x (p0, z0, z1, 2), + z0 = svmad_x (p0, z0, z1, 2)) + +/* +** mad_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_x_tied2, svfloat32_t, + z0 = svmad_n_f32_x (p0, z1, z0, 2), + z0 = svmad_x (p0, z1, z0, 2)) + +/* +** mad_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_2_f32_x_untied, svfloat32_t, + z0 = svmad_n_f32_x (p0, z1, z2, 2), + z0 = svmad_x (p0, z1, z2, 2)) + +/* +** ptrue_mad_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f32_x_tied1, svfloat32_t, + z0 = svmad_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svmad_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_mad_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f32_x_tied2, svfloat32_t, + z0 = svmad_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svmad_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_mad_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f32_x_tied3, svfloat32_t, + z0 = svmad_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svmad_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_mad_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f32_x_untied, svfloat32_t, + z0 = svmad_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svmad_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_mad_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f32_x_tied1, svfloat32_t, + z0 = svmad_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svmad_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_mad_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f32_x_tied2, svfloat32_t, + z0 = svmad_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svmad_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_mad_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f32_x_untied, svfloat32_t, + z0 = svmad_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svmad_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f64.c new file mode 100644 index 00000000000..978281295e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_f64_m_tied1: +** fmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_m_tied1, svfloat64_t, + z0 = svmad_f64_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmad z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_m_tied2, svfloat64_t, + z0 = svmad_f64_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_f64_m_tied3, svfloat64_t, + z0 = svmad_f64_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_f64_m_untied: +** movprfx z0, z1 +** fmad z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_m_untied, svfloat64_t, + z0 = svmad_f64_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmad_n_f64_m (p0, z0, z1, d4), + z0 = svmad_m (p0, z0, z1, d4)) + +/* +** mad_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_m_untied, svfloat64_t, double, + z0 = svmad_n_f64_m (p0, z1, z2, d4), + z0 = svmad_m (p0, z1, z2, d4)) + +/* +** mad_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_m_tied1, svfloat64_t, + z0 = svmad_n_f64_m (p0, z0, z1, 2), + z0 = svmad_m (p0, z0, z1, 2)) + +/* +** mad_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_m_untied, svfloat64_t, + z0 = svmad_n_f64_m (p0, z1, z2, 2), + z0 = svmad_m (p0, z1, z2, 2)) + +/* +** mad_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_z_tied1, svfloat64_t, + z0 = svmad_f64_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_z_tied2, svfloat64_t, + z0 = svmad_f64_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_z_tied3, svfloat64_t, + z0 = svmad_f64_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f64_z_untied, svfloat64_t, + z0 = svmad_f64_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmad_n_f64_z (p0, z0, z1, d4), + z0 = svmad_z (p0, z0, z1, d4)) + +/* +** mad_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_z_tied2, svfloat64_t, double, + z0 = svmad_n_f64_z (p0, z1, z0, d4), + z0 = svmad_z (p0, z1, z0, d4)) + +/* +** mad_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_z_untied, svfloat64_t, double, + z0 = svmad_n_f64_z (p0, z1, z2, d4), + z0 = svmad_z (p0, z1, z2, d4)) + +/* +** mad_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_z_tied1, svfloat64_t, + z0 = svmad_n_f64_z (p0, z0, z1, 2), + z0 = svmad_z (p0, z0, z1, 2)) + +/* +** mad_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_z_tied2, svfloat64_t, + z0 = svmad_n_f64_z (p0, z1, z0, 2), + z0 = svmad_z (p0, z1, z0, 2)) + +/* +** mad_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_z_untied, svfloat64_t, + z0 = svmad_n_f64_z (p0, z1, z2, 2), + z0 = svmad_z (p0, z1, z2, 2)) + +/* +** mad_f64_x_tied1: +** fmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_x_tied1, svfloat64_t, + z0 = svmad_f64_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_f64_x_tied2: +** fmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_x_tied2, svfloat64_t, + z0 = svmad_f64_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_f64_x_tied3: +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_f64_x_tied3, svfloat64_t, + z0 = svmad_f64_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_f64_x_untied: +** ( +** movprfx z0, z1 +** fmad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fmad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_f64_x_untied, svfloat64_t, + z0 = svmad_f64_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmad_n_f64_x (p0, z0, z1, d4), + z0 = svmad_x (p0, z0, z1, d4)) + +/* +** mad_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_x_tied2, svfloat64_t, double, + z0 = svmad_n_f64_x (p0, z1, z0, d4), + z0 = svmad_x (p0, z1, z0, d4)) + +/* +** mad_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZD (mad_d4_f64_x_untied, svfloat64_t, double, + z0 = svmad_n_f64_x (p0, z1, z2, d4), + z0 = svmad_x (p0, z1, z2, d4)) + +/* +** mad_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_x_tied1, svfloat64_t, + z0 = svmad_n_f64_x (p0, z0, z1, 2), + z0 = svmad_x (p0, z0, z1, 2)) + +/* +** mad_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_x_tied2, svfloat64_t, + z0 = svmad_n_f64_x (p0, z1, z0, 2), + z0 = svmad_x (p0, z1, z0, 2)) + +/* +** mad_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_2_f64_x_untied, svfloat64_t, + z0 = svmad_n_f64_x (p0, z1, z2, 2), + z0 = svmad_x (p0, z1, z2, 2)) + +/* +** ptrue_mad_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f64_x_tied1, svfloat64_t, + z0 = svmad_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svmad_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_mad_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f64_x_tied2, svfloat64_t, + z0 = svmad_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svmad_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_mad_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f64_x_tied3, svfloat64_t, + z0 = svmad_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svmad_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_mad_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_f64_x_untied, svfloat64_t, + z0 = svmad_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svmad_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_mad_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f64_x_tied1, svfloat64_t, + z0 = svmad_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svmad_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_mad_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f64_x_tied2, svfloat64_t, + z0 = svmad_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svmad_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_mad_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mad_2_f64_x_untied, svfloat64_t, + z0 = svmad_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svmad_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c new file mode 100644 index 00000000000..02a6d4588b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_s16_m_tied1: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_m_tied1, svint16_t, + z0 = svmad_s16_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_m_tied2, svint16_t, + z0 = svmad_s16_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_s16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_m_tied3, svint16_t, + z0 = svmad_s16_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_s16_m_untied: +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_m_untied, svint16_t, + z0 = svmad_s16_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmad_n_s16_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmad_n_s16_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_s16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_m_tied1, svint16_t, + z0 = svmad_n_s16_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_m_untied, svint16_t, + z0 = svmad_n_s16_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_z_tied1, svint16_t, + z0 = svmad_s16_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_z_tied2, svint16_t, + z0 = svmad_s16_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_s16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_z_tied3, svint16_t, + z0 = svmad_s16_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s16_z_untied, svint16_t, + z0 = svmad_s16_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmad_n_s16_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_s16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_z_tied2, svint16_t, int16_t, + z0 = svmad_n_s16_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmad_n_s16_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_s16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_z_tied1, svint16_t, + z0 = svmad_n_s16_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_s16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_z_tied2, svint16_t, + z0 = svmad_n_s16_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_s16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_z_untied, svint16_t, + z0 = svmad_n_s16_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_s16_x_tied1: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_x_tied1, svint16_t, + z0 = svmad_s16_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_s16_x_tied2: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_x_tied2, svint16_t, + z0 = svmad_s16_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_s16_x_tied3: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_s16_x_tied3, svint16_t, + z0 = svmad_s16_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_s16_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** mad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s16_x_untied, svint16_t, + z0 = svmad_s16_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmad_n_s16_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_s16_x_tied2: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_x_tied2, svint16_t, int16_t, + z0 = svmad_n_s16_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_s16_x_untied: +** mov z0\.h, w0 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmad_n_s16_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_x_tied1, svint16_t, + z0 = svmad_n_s16_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_s16_x_tied2: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_x_tied2, svint16_t, + z0 = svmad_n_s16_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_s16_x_untied: +** mov z0\.h, #11 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_11_s16_x_untied, svint16_t, + z0 = svmad_n_s16_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s32.c new file mode 100644 index 00000000000..d676a0c1142 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_s32_m_tied1: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_m_tied1, svint32_t, + z0 = svmad_s32_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_m_tied2, svint32_t, + z0 = svmad_s32_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_s32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_m_tied3, svint32_t, + z0 = svmad_s32_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_s32_m_untied: +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_m_untied, svint32_t, + z0 = svmad_s32_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmad_n_s32_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmad_n_s32_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_s32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_m_tied1, svint32_t, + z0 = svmad_n_s32_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_m_untied, svint32_t, + z0 = svmad_n_s32_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_z_tied1, svint32_t, + z0 = svmad_s32_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_z_tied2, svint32_t, + z0 = svmad_s32_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_s32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_z_tied3, svint32_t, + z0 = svmad_s32_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s32_z_untied, svint32_t, + z0 = svmad_s32_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmad_n_s32_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_s32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_z_tied2, svint32_t, int32_t, + z0 = svmad_n_s32_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmad_n_s32_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_s32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_z_tied1, svint32_t, + z0 = svmad_n_s32_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_s32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_z_tied2, svint32_t, + z0 = svmad_n_s32_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_s32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_z_untied, svint32_t, + z0 = svmad_n_s32_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_s32_x_tied1: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_x_tied1, svint32_t, + z0 = svmad_s32_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_s32_x_tied2: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_x_tied2, svint32_t, + z0 = svmad_s32_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_s32_x_tied3: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_s32_x_tied3, svint32_t, + z0 = svmad_s32_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_s32_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** mad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s32_x_untied, svint32_t, + z0 = svmad_s32_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmad_n_s32_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_s32_x_tied2: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_x_tied2, svint32_t, int32_t, + z0 = svmad_n_s32_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_s32_x_untied: +** mov z0\.s, w0 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmad_n_s32_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_x_tied1, svint32_t, + z0 = svmad_n_s32_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_s32_x_tied2: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_x_tied2, svint32_t, + z0 = svmad_n_s32_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_s32_x_untied: +** mov z0\.s, #11 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_11_s32_x_untied, svint32_t, + z0 = svmad_n_s32_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s64.c new file mode 100644 index 00000000000..7aa017536af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_s64_m_tied1: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_m_tied1, svint64_t, + z0 = svmad_s64_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mad z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_m_tied2, svint64_t, + z0 = svmad_s64_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_s64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_s64_m_tied3, svint64_t, + z0 = svmad_s64_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_s64_m_untied: +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_m_untied, svint64_t, + z0 = svmad_s64_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmad_n_s64_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmad_n_s64_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_s64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_m_tied1, svint64_t, + z0 = svmad_n_s64_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_m_untied, svint64_t, + z0 = svmad_n_s64_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_z_tied1, svint64_t, + z0 = svmad_s64_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_z_tied2, svint64_t, + z0 = svmad_s64_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_s64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_z_tied3, svint64_t, + z0 = svmad_s64_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s64_z_untied, svint64_t, + z0 = svmad_s64_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmad_n_s64_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_x0_s64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_z_tied2, svint64_t, int64_t, + z0 = svmad_n_s64_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmad_n_s64_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_s64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_z_tied1, svint64_t, + z0 = svmad_n_s64_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_s64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_z_tied2, svint64_t, + z0 = svmad_n_s64_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_s64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_z_untied, svint64_t, + z0 = svmad_n_s64_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_s64_x_tied1: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_x_tied1, svint64_t, + z0 = svmad_s64_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_s64_x_tied2: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_x_tied2, svint64_t, + z0 = svmad_s64_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_s64_x_tied3: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_s64_x_tied3, svint64_t, + z0 = svmad_s64_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_s64_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** mad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s64_x_untied, svint64_t, + z0 = svmad_s64_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmad_n_s64_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_x0_s64_x_tied2: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_x_tied2, svint64_t, int64_t, + z0 = svmad_n_s64_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_x0_s64_x_untied: +** mov z0\.d, x0 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmad_n_s64_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_x_tied1, svint64_t, + z0 = svmad_n_s64_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_s64_x_tied2: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_x_tied2, svint64_t, + z0 = svmad_n_s64_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_s64_x_untied: +** mov z0\.d, #11 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_11_s64_x_untied, svint64_t, + z0 = svmad_n_s64_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c new file mode 100644 index 00000000000..90d712686ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_s8_m_tied1: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_m_tied1, svint8_t, + z0 = svmad_s8_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_m_tied2, svint8_t, + z0 = svmad_s8_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_s8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_m_tied3, svint8_t, + z0 = svmad_s8_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_s8_m_untied: +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_m_untied, svint8_t, + z0 = svmad_s8_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmad_n_s8_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmad_n_s8_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_s8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_m_tied1, svint8_t, + z0 = svmad_n_s8_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_m_untied, svint8_t, + z0 = svmad_n_s8_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_z_tied1, svint8_t, + z0 = svmad_s8_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_z_tied2, svint8_t, + z0 = svmad_s8_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_s8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_z_tied3, svint8_t, + z0 = svmad_s8_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s8_z_untied, svint8_t, + z0 = svmad_s8_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmad_n_s8_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_s8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_z_tied2, svint8_t, int8_t, + z0 = svmad_n_s8_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmad_n_s8_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_s8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_z_tied1, svint8_t, + z0 = svmad_n_s8_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_s8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_z_tied2, svint8_t, + z0 = svmad_n_s8_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_s8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_z_untied, svint8_t, + z0 = svmad_n_s8_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_s8_x_tied1: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_x_tied1, svint8_t, + z0 = svmad_s8_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_s8_x_tied2: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_x_tied2, svint8_t, + z0 = svmad_s8_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_s8_x_tied3: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_s8_x_tied3, svint8_t, + z0 = svmad_s8_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_s8_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** mad z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0, z3 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_s8_x_untied, svint8_t, + z0 = svmad_s8_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmad_n_s8_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_s8_x_tied2: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_x_tied2, svint8_t, int8_t, + z0 = svmad_n_s8_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_s8_x_untied: +** mov z0\.b, w0 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmad_n_s8_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_x_tied1, svint8_t, + z0 = svmad_n_s8_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_s8_x_tied2: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_x_tied2, svint8_t, + z0 = svmad_n_s8_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_s8_x_untied: +** mov z0\.b, #11 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_11_s8_x_untied, svint8_t, + z0 = svmad_n_s8_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c new file mode 100644 index 00000000000..1d2ad9c5fc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_u16_m_tied1: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_m_tied1, svuint16_t, + z0 = svmad_u16_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_m_tied2, svuint16_t, + z0 = svmad_u16_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_u16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_m_tied3, svuint16_t, + z0 = svmad_u16_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_u16_m_untied: +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_m_untied, svuint16_t, + z0 = svmad_u16_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmad_n_u16_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmad_n_u16_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_u16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_m_tied1, svuint16_t, + z0 = svmad_n_u16_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_m_untied, svuint16_t, + z0 = svmad_n_u16_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_z_tied1, svuint16_t, + z0 = svmad_u16_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_z_tied2, svuint16_t, + z0 = svmad_u16_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_u16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_z_tied3, svuint16_t, + z0 = svmad_u16_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u16_z_untied, svuint16_t, + z0 = svmad_u16_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmad_n_u16_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_u16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_z_tied2, svuint16_t, uint16_t, + z0 = svmad_n_u16_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmad_n_u16_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_u16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_z_tied1, svuint16_t, + z0 = svmad_n_u16_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_u16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_z_tied2, svuint16_t, + z0 = svmad_n_u16_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_u16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_z_untied, svuint16_t, + z0 = svmad_n_u16_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_u16_x_tied1: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_x_tied1, svuint16_t, + z0 = svmad_u16_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_u16_x_tied2: +** mad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_x_tied2, svuint16_t, + z0 = svmad_u16_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_u16_x_tied3: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_u16_x_tied3, svuint16_t, + z0 = svmad_u16_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_u16_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** mad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u16_x_untied, svuint16_t, + z0 = svmad_u16_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmad_n_u16_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_u16_x_tied2: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_x_tied2, svuint16_t, uint16_t, + z0 = svmad_n_u16_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_u16_x_untied: +** mov z0\.h, w0 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmad_n_u16_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_x_tied1, svuint16_t, + z0 = svmad_n_u16_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_u16_x_tied2: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_x_tied2, svuint16_t, + z0 = svmad_n_u16_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_u16_x_untied: +** mov z0\.h, #11 +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mad_11_u16_x_untied, svuint16_t, + z0 = svmad_n_u16_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u32.c new file mode 100644 index 00000000000..4b51958b176 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_u32_m_tied1: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_m_tied1, svuint32_t, + z0 = svmad_u32_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_m_tied2, svuint32_t, + z0 = svmad_u32_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_u32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_m_tied3, svuint32_t, + z0 = svmad_u32_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_u32_m_untied: +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_m_untied, svuint32_t, + z0 = svmad_u32_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmad_n_u32_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmad_n_u32_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_u32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_m_tied1, svuint32_t, + z0 = svmad_n_u32_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_m_untied, svuint32_t, + z0 = svmad_n_u32_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_z_tied1, svuint32_t, + z0 = svmad_u32_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_z_tied2, svuint32_t, + z0 = svmad_u32_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_u32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_z_tied3, svuint32_t, + z0 = svmad_u32_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u32_z_untied, svuint32_t, + z0 = svmad_u32_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmad_n_u32_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_u32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_z_tied2, svuint32_t, uint32_t, + z0 = svmad_n_u32_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmad_n_u32_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_u32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_z_tied1, svuint32_t, + z0 = svmad_n_u32_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_u32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_z_tied2, svuint32_t, + z0 = svmad_n_u32_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_u32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_z_untied, svuint32_t, + z0 = svmad_n_u32_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_u32_x_tied1: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_x_tied1, svuint32_t, + z0 = svmad_u32_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_u32_x_tied2: +** mad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_x_tied2, svuint32_t, + z0 = svmad_u32_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_u32_x_tied3: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_u32_x_tied3, svuint32_t, + z0 = svmad_u32_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_u32_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** mad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u32_x_untied, svuint32_t, + z0 = svmad_u32_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmad_n_u32_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_u32_x_tied2: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_x_tied2, svuint32_t, uint32_t, + z0 = svmad_n_u32_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_u32_x_untied: +** mov z0\.s, w0 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmad_n_u32_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_x_tied1, svuint32_t, + z0 = svmad_n_u32_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_u32_x_tied2: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_x_tied2, svuint32_t, + z0 = svmad_n_u32_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_u32_x_untied: +** mov z0\.s, #11 +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mad_11_u32_x_untied, svuint32_t, + z0 = svmad_n_u32_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u64.c new file mode 100644 index 00000000000..c4939093eff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_u64_m_tied1: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_m_tied1, svuint64_t, + z0 = svmad_u64_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mad z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_m_tied2, svuint64_t, + z0 = svmad_u64_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_u64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_u64_m_tied3, svuint64_t, + z0 = svmad_u64_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_u64_m_untied: +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_m_untied, svuint64_t, + z0 = svmad_u64_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmad_n_u64_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmad_n_u64_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_u64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_m_tied1, svuint64_t, + z0 = svmad_n_u64_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_m_untied, svuint64_t, + z0 = svmad_n_u64_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_z_tied1, svuint64_t, + z0 = svmad_u64_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_z_tied2, svuint64_t, + z0 = svmad_u64_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_u64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_z_tied3, svuint64_t, + z0 = svmad_u64_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u64_z_untied, svuint64_t, + z0 = svmad_u64_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmad_n_u64_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_x0_u64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_z_tied2, svuint64_t, uint64_t, + z0 = svmad_n_u64_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmad_n_u64_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_u64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_z_tied1, svuint64_t, + z0 = svmad_n_u64_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_u64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_z_tied2, svuint64_t, + z0 = svmad_n_u64_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_u64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_z_untied, svuint64_t, + z0 = svmad_n_u64_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_u64_x_tied1: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_x_tied1, svuint64_t, + z0 = svmad_u64_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_u64_x_tied2: +** mad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_x_tied2, svuint64_t, + z0 = svmad_u64_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_u64_x_tied3: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_u64_x_tied3, svuint64_t, + z0 = svmad_u64_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_u64_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** mad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u64_x_untied, svuint64_t, + z0 = svmad_u64_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmad_n_u64_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_x0_u64_x_tied2: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_x_tied2, svuint64_t, uint64_t, + z0 = svmad_n_u64_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_x0_u64_x_untied: +** mov z0\.d, x0 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZX (mad_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmad_n_u64_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_x_tied1, svuint64_t, + z0 = svmad_n_u64_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_u64_x_tied2: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_x_tied2, svuint64_t, + z0 = svmad_n_u64_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_u64_x_untied: +** mov z0\.d, #11 +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mad_11_u64_x_untied, svuint64_t, + z0 = svmad_n_u64_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c new file mode 100644 index 00000000000..0b4b1b8cfe6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mad_u8_m_tied1: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_m_tied1, svuint8_t, + z0 = svmad_u8_m (p0, z0, z1, z2), + z0 = svmad_m (p0, z0, z1, z2)) + +/* +** mad_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_m_tied2, svuint8_t, + z0 = svmad_u8_m (p0, z1, z0, z2), + z0 = svmad_m (p0, z1, z0, z2)) + +/* +** mad_u8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_m_tied3, svuint8_t, + z0 = svmad_u8_m (p0, z1, z2, z0), + z0 = svmad_m (p0, z1, z2, z0)) + +/* +** mad_u8_m_untied: +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_m_untied, svuint8_t, + z0 = svmad_u8_m (p0, z1, z2, z3), + z0 = svmad_m (p0, z1, z2, z3)) + +/* +** mad_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmad_n_u8_m (p0, z0, z1, x0), + z0 = svmad_m (p0, z0, z1, x0)) + +/* +** mad_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmad_n_u8_m (p0, z1, z2, x0), + z0 = svmad_m (p0, z1, z2, x0)) + +/* +** mad_11_u8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_m_tied1, svuint8_t, + z0 = svmad_n_u8_m (p0, z0, z1, 11), + z0 = svmad_m (p0, z0, z1, 11)) + +/* +** mad_11_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_m_untied, svuint8_t, + z0 = svmad_n_u8_m (p0, z1, z2, 11), + z0 = svmad_m (p0, z1, z2, 11)) + +/* +** mad_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_z_tied1, svuint8_t, + z0 = svmad_u8_z (p0, z0, z1, z2), + z0 = svmad_z (p0, z0, z1, z2)) + +/* +** mad_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_z_tied2, svuint8_t, + z0 = svmad_u8_z (p0, z1, z0, z2), + z0 = svmad_z (p0, z1, z0, z2)) + +/* +** mad_u8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_z_tied3, svuint8_t, + z0 = svmad_u8_z (p0, z1, z2, z0), + z0 = svmad_z (p0, z1, z2, z0)) + +/* +** mad_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u8_z_untied, svuint8_t, + z0 = svmad_u8_z (p0, z1, z2, z3), + z0 = svmad_z (p0, z1, z2, z3)) + +/* +** mad_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmad_n_u8_z (p0, z0, z1, x0), + z0 = svmad_z (p0, z0, z1, x0)) + +/* +** mad_w0_u8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_z_tied2, svuint8_t, uint8_t, + z0 = svmad_n_u8_z (p0, z1, z0, x0), + z0 = svmad_z (p0, z1, z0, x0)) + +/* +** mad_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmad_n_u8_z (p0, z1, z2, x0), + z0 = svmad_z (p0, z1, z2, x0)) + +/* +** mad_11_u8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_z_tied1, svuint8_t, + z0 = svmad_n_u8_z (p0, z0, z1, 11), + z0 = svmad_z (p0, z0, z1, 11)) + +/* +** mad_11_u8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_z_tied2, svuint8_t, + z0 = svmad_n_u8_z (p0, z1, z0, 11), + z0 = svmad_z (p0, z1, z0, 11)) + +/* +** mad_11_u8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mad z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_z_untied, svuint8_t, + z0 = svmad_n_u8_z (p0, z1, z2, 11), + z0 = svmad_z (p0, z1, z2, 11)) + +/* +** mad_u8_x_tied1: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_x_tied1, svuint8_t, + z0 = svmad_u8_x (p0, z0, z1, z2), + z0 = svmad_x (p0, z0, z1, z2)) + +/* +** mad_u8_x_tied2: +** mad z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_x_tied2, svuint8_t, + z0 = svmad_u8_x (p0, z1, z0, z2), + z0 = svmad_x (p0, z1, z0, z2)) + +/* +** mad_u8_x_tied3: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_u8_x_tied3, svuint8_t, + z0 = svmad_u8_x (p0, z1, z2, z0), + z0 = svmad_x (p0, z1, z2, z0)) + +/* +** mad_u8_x_untied: +** ( +** movprfx z0, z1 +** mad z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** mad z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0, z3 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mad_u8_x_untied, svuint8_t, + z0 = svmad_u8_x (p0, z1, z2, z3), + z0 = svmad_x (p0, z1, z2, z3)) + +/* +** mad_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmad_n_u8_x (p0, z0, z1, x0), + z0 = svmad_x (p0, z0, z1, x0)) + +/* +** mad_w0_u8_x_tied2: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_x_tied2, svuint8_t, uint8_t, + z0 = svmad_n_u8_x (p0, z1, z0, x0), + z0 = svmad_x (p0, z1, z0, x0)) + +/* +** mad_w0_u8_x_untied: +** mov z0\.b, w0 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_ZX (mad_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmad_n_u8_x (p0, z1, z2, x0), + z0 = svmad_x (p0, z1, z2, x0)) + +/* +** mad_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_x_tied1, svuint8_t, + z0 = svmad_n_u8_x (p0, z0, z1, 11), + z0 = svmad_x (p0, z0, z1, 11)) + +/* +** mad_11_u8_x_tied2: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_x_tied2, svuint8_t, + z0 = svmad_n_u8_x (p0, z1, z0, 11), + z0 = svmad_x (p0, z1, z0, 11)) + +/* +** mad_11_u8_x_untied: +** mov z0\.b, #11 +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mad_11_u8_x_untied, svuint8_t, + z0 = svmad_n_u8_x (p0, z1, z2, 11), + z0 = svmad_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f16.c new file mode 100644 index 00000000000..f21099a2439 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f16.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_f16_m_tied1: +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_m_tied1, svfloat16_t, + z0 = svmax_f16_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_m_tied2, svfloat16_t, + z0 = svmax_f16_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_f16_m_untied: +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_m_untied, svfloat16_t, + z0 = svmax_f16_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmax_n_f16_m (p0, z0, d4), + z0 = svmax_m (p0, z0, d4)) + +/* +** max_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmax_n_f16_m (p0, z1, d4), + z0 = svmax_m (p0, z1, d4)) + +/* +** max_0_f16_m_tied1: +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_m_tied1, svfloat16_t, + z0 = svmax_n_f16_m (p0, z0, 0), + z0 = svmax_m (p0, z0, 0)) + +/* +** max_0_f16_m_untied: +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_m_untied, svfloat16_t, + z0 = svmax_n_f16_m (p0, z1, 0), + z0 = svmax_m (p0, z1, 0)) + +/* +** max_1_f16_m_tied1: +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_m_tied1, svfloat16_t, + z0 = svmax_n_f16_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_f16_m_untied: +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_m_untied, svfloat16_t, + z0 = svmax_n_f16_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f16_m, svfloat16_t, + z0 = svmax_n_f16_m (p0, z0, 2), + z0 = svmax_m (p0, z0, 2)) + +/* +** max_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_z_tied1, svfloat16_t, + z0 = svmax_f16_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_z_tied2, svfloat16_t, + z0 = svmax_f16_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f16_z_untied, svfloat16_t, + z0 = svmax_f16_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmax_n_f16_z (p0, z0, d4), + z0 = svmax_z (p0, z0, d4)) + +/* +** max_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmax z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmax_n_f16_z (p0, z1, d4), + z0 = svmax_z (p0, z1, d4)) + +/* +** max_0_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_z_tied1, svfloat16_t, + z0 = svmax_n_f16_z (p0, z0, 0), + z0 = svmax_z (p0, z0, 0)) + +/* +** max_0_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_z_untied, svfloat16_t, + z0 = svmax_n_f16_z (p0, z1, 0), + z0 = svmax_z (p0, z1, 0)) + +/* +** max_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_z_tied1, svfloat16_t, + z0 = svmax_n_f16_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_z_untied, svfloat16_t, + z0 = svmax_n_f16_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f16_z, svfloat16_t, + z0 = svmax_n_f16_z (p0, z0, 2), + z0 = svmax_z (p0, z0, 2)) + +/* +** max_f16_x_tied1: +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_x_tied1, svfloat16_t, + z0 = svmax_f16_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_f16_x_tied2: +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_f16_x_tied2, svfloat16_t, + z0 = svmax_f16_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_f16_x_untied: +** ( +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f16_x_untied, svfloat16_t, + z0 = svmax_f16_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmax_n_f16_x (p0, z0, d4), + z0 = svmax_x (p0, z0, d4)) + +/* +** max_h4_f16_x_untied: +** mov z0\.h, h4 +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (max_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmax_n_f16_x (p0, z1, d4), + z0 = svmax_x (p0, z1, d4)) + +/* +** max_0_f16_x_tied1: +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (p0, z0, 0), + z0 = svmax_x (p0, z0, 0)) + +/* +** max_0_f16_x_untied: +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (p0, z1, 0), + z0 = svmax_x (p0, z1, 0)) + +/* +** max_1_f16_x_tied1: +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_f16_x_untied: +** movprfx z0, z1 +** fmax z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (p0, z0, 2), + z0 = svmax_x (p0, z0, 2)) + +/* +** max_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_2_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (p0, z1, 2), + z0 = svmax_x (p0, z1, 2)) + +/* +** ptrue_max_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f16_x_tied1, svfloat16_t, + z0 = svmax_f16_x (svptrue_b16 (), z0, z1), + z0 = svmax_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_max_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f16_x_tied2, svfloat16_t, + z0 = svmax_f16_x (svptrue_b16 (), z1, z0), + z0 = svmax_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_max_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f16_x_untied, svfloat16_t, + z0 = svmax_f16_x (svptrue_b16 (), z1, z2), + z0 = svmax_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_max_0_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z0, 0), + z0 = svmax_x (svptrue_b16 (), z0, 0)) + +/* +** ptrue_max_0_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z1, 0), + z0 = svmax_x (svptrue_b16 (), z1, 0)) + +/* +** ptrue_max_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmax_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_max_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmax_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_max_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f16_x_tied1, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmax_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_max_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f16_x_untied, svfloat16_t, + z0 = svmax_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmax_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f32.c new file mode 100644 index 00000000000..6f5c92c9fec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f32.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_f32_m_tied1: +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_m_tied1, svfloat32_t, + z0 = svmax_f32_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_m_tied2, svfloat32_t, + z0 = svmax_f32_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_f32_m_untied: +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_m_untied, svfloat32_t, + z0 = svmax_f32_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmax_n_f32_m (p0, z0, d4), + z0 = svmax_m (p0, z0, d4)) + +/* +** max_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_m_untied, svfloat32_t, float, + z0 = svmax_n_f32_m (p0, z1, d4), + z0 = svmax_m (p0, z1, d4)) + +/* +** max_0_f32_m_tied1: +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_m_tied1, svfloat32_t, + z0 = svmax_n_f32_m (p0, z0, 0), + z0 = svmax_m (p0, z0, 0)) + +/* +** max_0_f32_m_untied: +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_m_untied, svfloat32_t, + z0 = svmax_n_f32_m (p0, z1, 0), + z0 = svmax_m (p0, z1, 0)) + +/* +** max_1_f32_m_tied1: +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_m_tied1, svfloat32_t, + z0 = svmax_n_f32_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_f32_m_untied: +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_m_untied, svfloat32_t, + z0 = svmax_n_f32_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f32_m, svfloat32_t, + z0 = svmax_n_f32_m (p0, z0, 2), + z0 = svmax_m (p0, z0, 2)) + +/* +** max_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_z_tied1, svfloat32_t, + z0 = svmax_f32_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_z_tied2, svfloat32_t, + z0 = svmax_f32_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f32_z_untied, svfloat32_t, + z0 = svmax_f32_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmax_n_f32_z (p0, z0, d4), + z0 = svmax_z (p0, z0, d4)) + +/* +** max_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmax z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_z_untied, svfloat32_t, float, + z0 = svmax_n_f32_z (p0, z1, d4), + z0 = svmax_z (p0, z1, d4)) + +/* +** max_0_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_z_tied1, svfloat32_t, + z0 = svmax_n_f32_z (p0, z0, 0), + z0 = svmax_z (p0, z0, 0)) + +/* +** max_0_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_z_untied, svfloat32_t, + z0 = svmax_n_f32_z (p0, z1, 0), + z0 = svmax_z (p0, z1, 0)) + +/* +** max_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_z_tied1, svfloat32_t, + z0 = svmax_n_f32_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_z_untied, svfloat32_t, + z0 = svmax_n_f32_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f32_z, svfloat32_t, + z0 = svmax_n_f32_z (p0, z0, 2), + z0 = svmax_z (p0, z0, 2)) + +/* +** max_f32_x_tied1: +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_x_tied1, svfloat32_t, + z0 = svmax_f32_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_f32_x_tied2: +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_f32_x_tied2, svfloat32_t, + z0 = svmax_f32_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_f32_x_untied: +** ( +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f32_x_untied, svfloat32_t, + z0 = svmax_f32_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmax_n_f32_x (p0, z0, d4), + z0 = svmax_x (p0, z0, d4)) + +/* +** max_s4_f32_x_untied: +** mov z0\.s, s4 +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (max_s4_f32_x_untied, svfloat32_t, float, + z0 = svmax_n_f32_x (p0, z1, d4), + z0 = svmax_x (p0, z1, d4)) + +/* +** max_0_f32_x_tied1: +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (p0, z0, 0), + z0 = svmax_x (p0, z0, 0)) + +/* +** max_0_f32_x_untied: +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (p0, z1, 0), + z0 = svmax_x (p0, z1, 0)) + +/* +** max_1_f32_x_tied1: +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_f32_x_untied: +** movprfx z0, z1 +** fmax z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (p0, z0, 2), + z0 = svmax_x (p0, z0, 2)) + +/* +** max_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_2_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (p0, z1, 2), + z0 = svmax_x (p0, z1, 2)) + +/* +** ptrue_max_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f32_x_tied1, svfloat32_t, + z0 = svmax_f32_x (svptrue_b32 (), z0, z1), + z0 = svmax_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_max_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f32_x_tied2, svfloat32_t, + z0 = svmax_f32_x (svptrue_b32 (), z1, z0), + z0 = svmax_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_max_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f32_x_untied, svfloat32_t, + z0 = svmax_f32_x (svptrue_b32 (), z1, z2), + z0 = svmax_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_max_0_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z0, 0), + z0 = svmax_x (svptrue_b32 (), z0, 0)) + +/* +** ptrue_max_0_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z1, 0), + z0 = svmax_x (svptrue_b32 (), z1, 0)) + +/* +** ptrue_max_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmax_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_max_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmax_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_max_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f32_x_tied1, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmax_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_max_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f32_x_untied, svfloat32_t, + z0 = svmax_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmax_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f64.c new file mode 100644 index 00000000000..8ac6cca75d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_f64.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_f64_m_tied1: +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_m_tied1, svfloat64_t, + z0 = svmax_f64_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_f64_m_tied2, svfloat64_t, + z0 = svmax_f64_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_f64_m_untied: +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_m_untied, svfloat64_t, + z0 = svmax_f64_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmax_n_f64_m (p0, z0, d4), + z0 = svmax_m (p0, z0, d4)) + +/* +** max_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_m_untied, svfloat64_t, double, + z0 = svmax_n_f64_m (p0, z1, d4), + z0 = svmax_m (p0, z1, d4)) + +/* +** max_0_f64_m_tied1: +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_m_tied1, svfloat64_t, + z0 = svmax_n_f64_m (p0, z0, 0), + z0 = svmax_m (p0, z0, 0)) + +/* +** max_0_f64_m_untied: +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_m_untied, svfloat64_t, + z0 = svmax_n_f64_m (p0, z1, 0), + z0 = svmax_m (p0, z1, 0)) + +/* +** max_1_f64_m_tied1: +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_m_tied1, svfloat64_t, + z0 = svmax_n_f64_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_f64_m_untied: +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_m_untied, svfloat64_t, + z0 = svmax_n_f64_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f64_m, svfloat64_t, + z0 = svmax_n_f64_m (p0, z0, 2), + z0 = svmax_m (p0, z0, 2)) + +/* +** max_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_z_tied1, svfloat64_t, + z0 = svmax_f64_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_z_tied2, svfloat64_t, + z0 = svmax_f64_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f64_z_untied, svfloat64_t, + z0 = svmax_f64_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmax_n_f64_z (p0, z0, d4), + z0 = svmax_z (p0, z0, d4)) + +/* +** max_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmax z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_z_untied, svfloat64_t, double, + z0 = svmax_n_f64_z (p0, z1, d4), + z0 = svmax_z (p0, z1, d4)) + +/* +** max_0_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_z_tied1, svfloat64_t, + z0 = svmax_n_f64_z (p0, z0, 0), + z0 = svmax_z (p0, z0, 0)) + +/* +** max_0_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_z_untied, svfloat64_t, + z0 = svmax_n_f64_z (p0, z1, 0), + z0 = svmax_z (p0, z1, 0)) + +/* +** max_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_z_tied1, svfloat64_t, + z0 = svmax_n_f64_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_z_untied, svfloat64_t, + z0 = svmax_n_f64_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f64_z, svfloat64_t, + z0 = svmax_n_f64_z (p0, z0, 2), + z0 = svmax_z (p0, z0, 2)) + +/* +** max_f64_x_tied1: +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_x_tied1, svfloat64_t, + z0 = svmax_f64_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_f64_x_tied2: +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_f64_x_tied2, svfloat64_t, + z0 = svmax_f64_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_f64_x_untied: +** ( +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_f64_x_untied, svfloat64_t, + z0 = svmax_f64_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmax_n_f64_x (p0, z0, d4), + z0 = svmax_x (p0, z0, d4)) + +/* +** max_d4_f64_x_untied: +** mov z0\.d, d4 +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (max_d4_f64_x_untied, svfloat64_t, double, + z0 = svmax_n_f64_x (p0, z1, d4), + z0 = svmax_x (p0, z1, d4)) + +/* +** max_0_f64_x_tied1: +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (p0, z0, 0), + z0 = svmax_x (p0, z0, 0)) + +/* +** max_0_f64_x_untied: +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (max_0_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (p0, z1, 0), + z0 = svmax_x (p0, z1, 0)) + +/* +** max_1_f64_x_tied1: +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_f64_x_untied: +** movprfx z0, z1 +** fmax z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (max_1_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_2_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (p0, z0, 2), + z0 = svmax_x (p0, z0, 2)) + +/* +** max_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_2_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (p0, z1, 2), + z0 = svmax_x (p0, z1, 2)) + +/* +** ptrue_max_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f64_x_tied1, svfloat64_t, + z0 = svmax_f64_x (svptrue_b64 (), z0, z1), + z0 = svmax_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_max_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f64_x_tied2, svfloat64_t, + z0 = svmax_f64_x (svptrue_b64 (), z1, z0), + z0 = svmax_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_max_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_f64_x_untied, svfloat64_t, + z0 = svmax_f64_x (svptrue_b64 (), z1, z2), + z0 = svmax_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_max_0_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z0, 0), + z0 = svmax_x (svptrue_b64 (), z0, 0)) + +/* +** ptrue_max_0_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_0_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z1, 0), + z0 = svmax_x (svptrue_b64 (), z1, 0)) + +/* +** ptrue_max_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmax_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_max_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_1_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmax_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_max_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f64_x_tied1, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmax_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_max_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_max_2_f64_x_untied, svfloat64_t, + z0 = svmax_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmax_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c new file mode 100644 index 00000000000..6a216752282 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_s16_m_tied1: +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_m_tied1, svint16_t, + z0 = svmax_s16_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smax z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_m_tied2, svint16_t, + z0 = svmax_s16_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_s16_m_untied: +** movprfx z0, z1 +** smax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_m_untied, svint16_t, + z0 = svmax_s16_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmax_n_s16_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmax_n_s16_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_m_tied1, svint16_t, + z0 = svmax_n_s16_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_m_untied, svint16_t, + z0 = svmax_n_s16_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_s16_m: +** mov (z[0-9]+)\.b, #-1 +** smax z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (max_m1_s16_m, svint16_t, + z0 = svmax_n_s16_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_z_tied1, svint16_t, + z0 = svmax_s16_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_z_tied2, svint16_t, + z0 = svmax_s16_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** smax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** smax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s16_z_untied, svint16_t, + z0 = svmax_s16_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmax_n_s16_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smax z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmax_n_s16_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_z_tied1, svint16_t, + z0 = svmax_n_s16_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smax z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_z_untied, svint16_t, + z0 = svmax_n_s16_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_s16_x_tied1: +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_x_tied1, svint16_t, + z0 = svmax_s16_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_s16_x_tied2: +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_s16_x_tied2, svint16_t, + z0 = svmax_s16_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_s16_x_untied: +** ( +** movprfx z0, z1 +** smax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** smax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s16_x_untied, svint16_t, + z0 = svmax_s16_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmax_n_s16_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_s16_x_untied: +** mov z0\.h, w0 +** smax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmax_n_s16_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_s16_x_tied1: +** smax z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_x_tied1, svint16_t, + z0 = svmax_n_s16_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_s16_x_untied: +** movprfx z0, z1 +** smax z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s16_x_untied, svint16_t, + z0 = svmax_n_s16_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_s16_x: +** smax z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_s16_x, svint16_t, + z0 = svmax_n_s16_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_s16_x: +** mov (z[0-9]+\.h), #128 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_128_s16_x, svint16_t, + z0 = svmax_n_s16_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_m1_s16_x: +** smax z0\.h, z0\.h, #-1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_s16_x, svint16_t, + z0 = svmax_n_s16_x (p0, z0, -1), + z0 = svmax_x (p0, z0, -1)) + +/* +** max_m128_s16_x: +** smax z0\.h, z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (max_m128_s16_x, svint16_t, + z0 = svmax_n_s16_x (p0, z0, -128), + z0 = svmax_x (p0, z0, -128)) + +/* +** max_m129_s16_x: +** mov (z[0-9]+\.h), #-129 +** smax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m129_s16_x, svint16_t, + z0 = svmax_n_s16_x (p0, z0, -129), + z0 = svmax_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s32.c new file mode 100644 index 00000000000..07402c7a901 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s32.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_s32_m_tied1: +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_m_tied1, svint32_t, + z0 = svmax_s32_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smax z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_m_tied2, svint32_t, + z0 = svmax_s32_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_s32_m_untied: +** movprfx z0, z1 +** smax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_m_untied, svint32_t, + z0 = svmax_s32_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmax_n_s32_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmax_n_s32_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_m_tied1, svint32_t, + z0 = svmax_n_s32_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_m_untied, svint32_t, + z0 = svmax_n_s32_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_s32_m: +** mov (z[0-9]+)\.b, #-1 +** smax z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (max_m1_s32_m, svint32_t, + z0 = svmax_n_s32_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_z_tied1, svint32_t, + z0 = svmax_s32_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_z_tied2, svint32_t, + z0 = svmax_s32_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** smax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** smax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s32_z_untied, svint32_t, + z0 = svmax_s32_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmax_n_s32_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smax z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmax_n_s32_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_z_tied1, svint32_t, + z0 = svmax_n_s32_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smax z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_z_untied, svint32_t, + z0 = svmax_n_s32_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_s32_x_tied1: +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_x_tied1, svint32_t, + z0 = svmax_s32_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_s32_x_tied2: +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_s32_x_tied2, svint32_t, + z0 = svmax_s32_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_s32_x_untied: +** ( +** movprfx z0, z1 +** smax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** smax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s32_x_untied, svint32_t, + z0 = svmax_s32_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmax_n_s32_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_s32_x_untied: +** mov z0\.s, w0 +** smax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmax_n_s32_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_s32_x_tied1: +** smax z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_x_tied1, svint32_t, + z0 = svmax_n_s32_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_s32_x_untied: +** movprfx z0, z1 +** smax z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s32_x_untied, svint32_t, + z0 = svmax_n_s32_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_s32_x: +** smax z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_s32_x, svint32_t, + z0 = svmax_n_s32_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_s32_x: +** mov (z[0-9]+\.s), #128 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_128_s32_x, svint32_t, + z0 = svmax_n_s32_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_m1_s32_x: +** smax z0\.s, z0\.s, #-1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_s32_x, svint32_t, + z0 = svmax_n_s32_x (p0, z0, -1), + z0 = svmax_x (p0, z0, -1)) + +/* +** max_m128_s32_x: +** smax z0\.s, z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (max_m128_s32_x, svint32_t, + z0 = svmax_n_s32_x (p0, z0, -128), + z0 = svmax_x (p0, z0, -128)) + +/* +** max_m129_s32_x: +** mov (z[0-9]+\.s), #-129 +** smax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m129_s32_x, svint32_t, + z0 = svmax_n_s32_x (p0, z0, -129), + z0 = svmax_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s64.c new file mode 100644 index 00000000000..66f00fdf170 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s64.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_s64_m_tied1: +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_m_tied1, svint64_t, + z0 = svmax_s64_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_s64_m_tied2, svint64_t, + z0 = svmax_s64_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_s64_m_untied: +** movprfx z0, z1 +** smax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_m_untied, svint64_t, + z0 = svmax_s64_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmax_n_s64_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmax_n_s64_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_m_tied1, svint64_t, + z0 = svmax_n_s64_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_m_untied, svint64_t, + z0 = svmax_n_s64_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_s64_m: +** mov (z[0-9]+)\.b, #-1 +** smax z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (max_m1_s64_m, svint64_t, + z0 = svmax_n_s64_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_z_tied1, svint64_t, + z0 = svmax_s64_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_z_tied2, svint64_t, + z0 = svmax_s64_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** smax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** smax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s64_z_untied, svint64_t, + z0 = svmax_s64_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmax_n_s64_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smax z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmax_n_s64_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_z_tied1, svint64_t, + z0 = svmax_n_s64_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smax z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_z_untied, svint64_t, + z0 = svmax_n_s64_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_s64_x_tied1: +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_x_tied1, svint64_t, + z0 = svmax_s64_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_s64_x_tied2: +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_s64_x_tied2, svint64_t, + z0 = svmax_s64_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_s64_x_untied: +** ( +** movprfx z0, z1 +** smax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** smax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s64_x_untied, svint64_t, + z0 = svmax_s64_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmax_n_s64_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_x0_s64_x_untied: +** mov z0\.d, x0 +** smax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (max_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmax_n_s64_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_s64_x_tied1: +** smax z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_x_tied1, svint64_t, + z0 = svmax_n_s64_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_s64_x_untied: +** movprfx z0, z1 +** smax z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s64_x_untied, svint64_t, + z0 = svmax_n_s64_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_s64_x: +** smax z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_s64_x, svint64_t, + z0 = svmax_n_s64_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_s64_x: +** mov (z[0-9]+\.d), #128 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_128_s64_x, svint64_t, + z0 = svmax_n_s64_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_m1_s64_x: +** smax z0\.d, z0\.d, #-1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_s64_x, svint64_t, + z0 = svmax_n_s64_x (p0, z0, -1), + z0 = svmax_x (p0, z0, -1)) + +/* +** max_m128_s64_x: +** smax z0\.d, z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (max_m128_s64_x, svint64_t, + z0 = svmax_n_s64_x (p0, z0, -128), + z0 = svmax_x (p0, z0, -128)) + +/* +** max_m129_s64_x: +** mov (z[0-9]+\.d), #-129 +** smax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m129_s64_x, svint64_t, + z0 = svmax_n_s64_x (p0, z0, -129), + z0 = svmax_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c new file mode 100644 index 00000000000..c651a26f0d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c @@ -0,0 +1,273 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_s8_m_tied1: +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_m_tied1, svint8_t, + z0 = svmax_s8_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smax z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_m_tied2, svint8_t, + z0 = svmax_s8_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_s8_m_untied: +** movprfx z0, z1 +** smax z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_m_untied, svint8_t, + z0 = svmax_s8_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmax_n_s8_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmax_n_s8_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_m_tied1, svint8_t, + z0 = svmax_n_s8_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_m_untied, svint8_t, + z0 = svmax_n_s8_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_s8_m: +** mov (z[0-9]+\.b), #-1 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_s8_m, svint8_t, + z0 = svmax_n_s8_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_z_tied1, svint8_t, + z0 = svmax_s8_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_z_tied2, svint8_t, + z0 = svmax_s8_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** smax z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** smax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s8_z_untied, svint8_t, + z0 = svmax_s8_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmax_n_s8_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smax z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmax_n_s8_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_z_tied1, svint8_t, + z0 = svmax_n_s8_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smax z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_z_untied, svint8_t, + z0 = svmax_n_s8_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_s8_x_tied1: +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_x_tied1, svint8_t, + z0 = svmax_s8_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_s8_x_tied2: +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_s8_x_tied2, svint8_t, + z0 = svmax_s8_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_s8_x_untied: +** ( +** movprfx z0, z1 +** smax z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** smax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_s8_x_untied, svint8_t, + z0 = svmax_s8_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** smax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmax_n_s8_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_s8_x_untied: +** mov z0\.b, w0 +** smax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (max_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmax_n_s8_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_s8_x_tied1: +** smax z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_x_tied1, svint8_t, + z0 = svmax_n_s8_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_s8_x_untied: +** movprfx z0, z1 +** smax z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_s8_x_untied, svint8_t, + z0 = svmax_n_s8_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_s8_x: +** smax z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_s8_x, svint8_t, + z0 = svmax_n_s8_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_m1_s8_x: +** smax z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_s8_x, svint8_t, + z0 = svmax_n_s8_x (p0, z0, -1), + z0 = svmax_x (p0, z0, -1)) + +/* +** max_m127_s8_x: +** smax z0\.b, z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (max_m127_s8_x, svint8_t, + z0 = svmax_n_s8_x (p0, z0, -127), + z0 = svmax_x (p0, z0, -127)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c new file mode 100644 index 00000000000..9a0b9543169 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_u16_m_tied1: +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_m_tied1, svuint16_t, + z0 = svmax_u16_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umax z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_m_tied2, svuint16_t, + z0 = svmax_u16_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_u16_m_untied: +** movprfx z0, z1 +** umax z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_m_untied, svuint16_t, + z0 = svmax_u16_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmax_n_u16_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmax_n_u16_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_m_tied1, svuint16_t, + z0 = svmax_n_u16_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_m_untied, svuint16_t, + z0 = svmax_n_u16_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_u16_m: +** mov (z[0-9]+)\.b, #-1 +** umax z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (max_m1_u16_m, svuint16_t, + z0 = svmax_n_u16_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_z_tied1, svuint16_t, + z0 = svmax_u16_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_z_tied2, svuint16_t, + z0 = svmax_u16_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** umax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** umax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u16_z_untied, svuint16_t, + z0 = svmax_u16_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmax_n_u16_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umax z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmax_n_u16_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_z_tied1, svuint16_t, + z0 = svmax_n_u16_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umax z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_z_untied, svuint16_t, + z0 = svmax_n_u16_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_u16_x_tied1: +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_x_tied1, svuint16_t, + z0 = svmax_u16_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_u16_x_tied2: +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (max_u16_x_tied2, svuint16_t, + z0 = svmax_u16_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_u16_x_untied: +** ( +** movprfx z0, z1 +** umax z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** umax z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u16_x_untied, svuint16_t, + z0 = svmax_u16_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmax_n_u16_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_u16_x_untied: +** mov z0\.h, w0 +** umax z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmax_n_u16_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_u16_x_tied1: +** umax z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_x_tied1, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_u16_x_untied: +** movprfx z0, z1 +** umax z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u16_x_untied, svuint16_t, + z0 = svmax_n_u16_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_u16_x: +** umax z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_u16_x, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_u16_x: +** umax z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (max_128_u16_x, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_255_u16_x: +** umax z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (max_255_u16_x, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, 255), + z0 = svmax_x (p0, z0, 255)) + +/* +** max_256_u16_x: +** mov (z[0-9]+\.h), #256 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_256_u16_x, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, 256), + z0 = svmax_x (p0, z0, 256)) + +/* +** max_m2_u16_x: +** mov (z[0-9]+\.h), #-2 +** umax z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m2_u16_x, svuint16_t, + z0 = svmax_n_u16_x (p0, z0, -2), + z0 = svmax_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u32.c new file mode 100644 index 00000000000..91eba25c131 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u32.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_u32_m_tied1: +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_m_tied1, svuint32_t, + z0 = svmax_u32_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umax z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_m_tied2, svuint32_t, + z0 = svmax_u32_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_u32_m_untied: +** movprfx z0, z1 +** umax z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_m_untied, svuint32_t, + z0 = svmax_u32_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmax_n_u32_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmax_n_u32_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_m_tied1, svuint32_t, + z0 = svmax_n_u32_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_m_untied, svuint32_t, + z0 = svmax_n_u32_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_u32_m: +** mov (z[0-9]+)\.b, #-1 +** umax z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (max_m1_u32_m, svuint32_t, + z0 = svmax_n_u32_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_z_tied1, svuint32_t, + z0 = svmax_u32_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_z_tied2, svuint32_t, + z0 = svmax_u32_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** umax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** umax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u32_z_untied, svuint32_t, + z0 = svmax_u32_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmax_n_u32_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umax z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmax_n_u32_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_z_tied1, svuint32_t, + z0 = svmax_n_u32_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umax z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_z_untied, svuint32_t, + z0 = svmax_n_u32_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_u32_x_tied1: +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_x_tied1, svuint32_t, + z0 = svmax_u32_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_u32_x_tied2: +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (max_u32_x_tied2, svuint32_t, + z0 = svmax_u32_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_u32_x_untied: +** ( +** movprfx z0, z1 +** umax z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** umax z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u32_x_untied, svuint32_t, + z0 = svmax_u32_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmax_n_u32_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_u32_x_untied: +** mov z0\.s, w0 +** umax z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmax_n_u32_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_u32_x_tied1: +** umax z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_x_tied1, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_u32_x_untied: +** movprfx z0, z1 +** umax z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u32_x_untied, svuint32_t, + z0 = svmax_n_u32_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_u32_x: +** umax z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_u32_x, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_u32_x: +** umax z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (max_128_u32_x, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_255_u32_x: +** umax z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (max_255_u32_x, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, 255), + z0 = svmax_x (p0, z0, 255)) + +/* +** max_256_u32_x: +** mov (z[0-9]+\.s), #256 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_256_u32_x, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, 256), + z0 = svmax_x (p0, z0, 256)) + +/* +** max_m2_u32_x: +** mov (z[0-9]+\.s), #-2 +** umax z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m2_u32_x, svuint32_t, + z0 = svmax_n_u32_x (p0, z0, -2), + z0 = svmax_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u64.c new file mode 100644 index 00000000000..5be4c9fb77f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u64.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_u64_m_tied1: +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_m_tied1, svuint64_t, + z0 = svmax_u64_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_u64_m_tied2, svuint64_t, + z0 = svmax_u64_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_u64_m_untied: +** movprfx z0, z1 +** umax z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_m_untied, svuint64_t, + z0 = svmax_u64_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmax_n_u64_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmax_n_u64_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_m_tied1, svuint64_t, + z0 = svmax_n_u64_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_m_untied, svuint64_t, + z0 = svmax_n_u64_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_u64_m: +** mov (z[0-9]+)\.b, #-1 +** umax z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (max_m1_u64_m, svuint64_t, + z0 = svmax_n_u64_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_z_tied1, svuint64_t, + z0 = svmax_u64_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_z_tied2, svuint64_t, + z0 = svmax_u64_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** umax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** umax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u64_z_untied, svuint64_t, + z0 = svmax_u64_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmax_n_u64_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umax z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmax_n_u64_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_z_tied1, svuint64_t, + z0 = svmax_n_u64_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umax z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_z_untied, svuint64_t, + z0 = svmax_n_u64_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_u64_x_tied1: +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_x_tied1, svuint64_t, + z0 = svmax_u64_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_u64_x_tied2: +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (max_u64_x_tied2, svuint64_t, + z0 = svmax_u64_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_u64_x_untied: +** ( +** movprfx z0, z1 +** umax z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** umax z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u64_x_untied, svuint64_t, + z0 = svmax_u64_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmax_n_u64_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_x0_u64_x_untied: +** mov z0\.d, x0 +** umax z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (max_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmax_n_u64_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_u64_x_tied1: +** umax z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_x_tied1, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_u64_x_untied: +** movprfx z0, z1 +** umax z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u64_x_untied, svuint64_t, + z0 = svmax_n_u64_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_u64_x: +** umax z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_u64_x, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_u64_x: +** umax z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (max_128_u64_x, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_255_u64_x: +** umax z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (max_255_u64_x, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, 255), + z0 = svmax_x (p0, z0, 255)) + +/* +** max_256_u64_x: +** mov (z[0-9]+\.d), #256 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_256_u64_x, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, 256), + z0 = svmax_x (p0, z0, 256)) + +/* +** max_m2_u64_x: +** mov (z[0-9]+\.d), #-2 +** umax z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m2_u64_x, svuint64_t, + z0 = svmax_n_u64_x (p0, z0, -2), + z0 = svmax_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c new file mode 100644 index 00000000000..04c9ddb36a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c @@ -0,0 +1,273 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** max_u8_m_tied1: +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_m_tied1, svuint8_t, + z0 = svmax_u8_m (p0, z0, z1), + z0 = svmax_m (p0, z0, z1)) + +/* +** max_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umax z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_m_tied2, svuint8_t, + z0 = svmax_u8_m (p0, z1, z0), + z0 = svmax_m (p0, z1, z0)) + +/* +** max_u8_m_untied: +** movprfx z0, z1 +** umax z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_m_untied, svuint8_t, + z0 = svmax_u8_m (p0, z1, z2), + z0 = svmax_m (p0, z1, z2)) + +/* +** max_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmax_n_u8_m (p0, z0, x0), + z0 = svmax_m (p0, z0, x0)) + +/* +** max_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmax_n_u8_m (p0, z1, x0), + z0 = svmax_m (p0, z1, x0)) + +/* +** max_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_m_tied1, svuint8_t, + z0 = svmax_n_u8_m (p0, z0, 1), + z0 = svmax_m (p0, z0, 1)) + +/* +** max_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_m_untied, svuint8_t, + z0 = svmax_n_u8_m (p0, z1, 1), + z0 = svmax_m (p0, z1, 1)) + +/* +** max_m1_u8_m: +** mov (z[0-9]+\.b), #-1 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_m1_u8_m, svuint8_t, + z0 = svmax_n_u8_m (p0, z0, -1), + z0 = svmax_m (p0, z0, -1)) + +/* +** max_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_z_tied1, svuint8_t, + z0 = svmax_u8_z (p0, z0, z1), + z0 = svmax_z (p0, z0, z1)) + +/* +** max_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_z_tied2, svuint8_t, + z0 = svmax_u8_z (p0, z1, z0), + z0 = svmax_z (p0, z1, z0)) + +/* +** max_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** umax z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** umax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u8_z_untied, svuint8_t, + z0 = svmax_u8_z (p0, z1, z2), + z0 = svmax_z (p0, z1, z2)) + +/* +** max_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmax_n_u8_z (p0, z0, x0), + z0 = svmax_z (p0, z0, x0)) + +/* +** max_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umax z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmax_n_u8_z (p0, z1, x0), + z0 = svmax_z (p0, z1, x0)) + +/* +** max_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_z_tied1, svuint8_t, + z0 = svmax_n_u8_z (p0, z0, 1), + z0 = svmax_z (p0, z0, 1)) + +/* +** max_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umax z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_z_untied, svuint8_t, + z0 = svmax_n_u8_z (p0, z1, 1), + z0 = svmax_z (p0, z1, 1)) + +/* +** max_u8_x_tied1: +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_x_tied1, svuint8_t, + z0 = svmax_u8_x (p0, z0, z1), + z0 = svmax_x (p0, z0, z1)) + +/* +** max_u8_x_tied2: +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (max_u8_x_tied2, svuint8_t, + z0 = svmax_u8_x (p0, z1, z0), + z0 = svmax_x (p0, z1, z0)) + +/* +** max_u8_x_untied: +** ( +** movprfx z0, z1 +** umax z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** umax z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (max_u8_x_untied, svuint8_t, + z0 = svmax_u8_x (p0, z1, z2), + z0 = svmax_x (p0, z1, z2)) + +/* +** max_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** umax z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmax_n_u8_x (p0, z0, x0), + z0 = svmax_x (p0, z0, x0)) + +/* +** max_w0_u8_x_untied: +** mov z0\.b, w0 +** umax z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (max_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmax_n_u8_x (p0, z1, x0), + z0 = svmax_x (p0, z1, x0)) + +/* +** max_1_u8_x_tied1: +** umax z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_x_tied1, svuint8_t, + z0 = svmax_n_u8_x (p0, z0, 1), + z0 = svmax_x (p0, z0, 1)) + +/* +** max_1_u8_x_untied: +** movprfx z0, z1 +** umax z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (max_1_u8_x_untied, svuint8_t, + z0 = svmax_n_u8_x (p0, z1, 1), + z0 = svmax_x (p0, z1, 1)) + +/* +** max_127_u8_x: +** umax z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (max_127_u8_x, svuint8_t, + z0 = svmax_n_u8_x (p0, z0, 127), + z0 = svmax_x (p0, z0, 127)) + +/* +** max_128_u8_x: +** umax z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (max_128_u8_x, svuint8_t, + z0 = svmax_n_u8_x (p0, z0, 128), + z0 = svmax_x (p0, z0, 128)) + +/* +** max_254_u8_x: +** umax z0\.b, z0\.b, #254 +** ret +*/ +TEST_UNIFORM_Z (max_254_u8_x, svuint8_t, + z0 = svmax_n_u8_x (p0, z0, 254), + z0 = svmax_x (p0, z0, 254)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f16.c new file mode 100644 index 00000000000..a9da710d059 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f16.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnm_f16_m_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_m_tied1, svfloat16_t, + z0 = svmaxnm_f16_m (p0, z0, z1), + z0 = svmaxnm_m (p0, z0, z1)) + +/* +** maxnm_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_m_tied2, svfloat16_t, + z0 = svmaxnm_f16_m (p0, z1, z0), + z0 = svmaxnm_m (p0, z1, z0)) + +/* +** maxnm_f16_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_m_untied, svfloat16_t, + z0 = svmaxnm_f16_m (p0, z1, z2), + z0 = svmaxnm_m (p0, z1, z2)) + +/* +** maxnm_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_m (p0, z0, d4), + z0 = svmaxnm_m (p0, z0, d4)) + +/* +** maxnm_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_m (p0, z1, d4), + z0 = svmaxnm_m (p0, z1, d4)) + +/* +** maxnm_0_f16_m_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_m_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_m (p0, z0, 0), + z0 = svmaxnm_m (p0, z0, 0)) + +/* +** maxnm_0_f16_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_m_untied, svfloat16_t, + z0 = svmaxnm_n_f16_m (p0, z1, 0), + z0 = svmaxnm_m (p0, z1, 0)) + +/* +** maxnm_1_f16_m_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_m_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_m (p0, z0, 1), + z0 = svmaxnm_m (p0, z0, 1)) + +/* +** maxnm_1_f16_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_m_untied, svfloat16_t, + z0 = svmaxnm_n_f16_m (p0, z1, 1), + z0 = svmaxnm_m (p0, z1, 1)) + +/* +** maxnm_2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f16_m, svfloat16_t, + z0 = svmaxnm_n_f16_m (p0, z0, 2), + z0 = svmaxnm_m (p0, z0, 2)) + +/* +** maxnm_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_z_tied1, svfloat16_t, + z0 = svmaxnm_f16_z (p0, z0, z1), + z0 = svmaxnm_z (p0, z0, z1)) + +/* +** maxnm_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_z_tied2, svfloat16_t, + z0 = svmaxnm_f16_z (p0, z1, z0), + z0 = svmaxnm_z (p0, z1, z0)) + +/* +** maxnm_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmaxnm z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_z_untied, svfloat16_t, + z0 = svmaxnm_f16_z (p0, z1, z2), + z0 = svmaxnm_z (p0, z1, z2)) + +/* +** maxnm_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_z (p0, z0, d4), + z0 = svmaxnm_z (p0, z0, d4)) + +/* +** maxnm_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_z (p0, z1, d4), + z0 = svmaxnm_z (p0, z1, d4)) + +/* +** maxnm_0_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_z_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_z (p0, z0, 0), + z0 = svmaxnm_z (p0, z0, 0)) + +/* +** maxnm_0_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_z_untied, svfloat16_t, + z0 = svmaxnm_n_f16_z (p0, z1, 0), + z0 = svmaxnm_z (p0, z1, 0)) + +/* +** maxnm_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_z_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_z (p0, z0, 1), + z0 = svmaxnm_z (p0, z0, 1)) + +/* +** maxnm_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_z_untied, svfloat16_t, + z0 = svmaxnm_n_f16_z (p0, z1, 1), + z0 = svmaxnm_z (p0, z1, 1)) + +/* +** maxnm_2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f16_z, svfloat16_t, + z0 = svmaxnm_n_f16_z (p0, z0, 2), + z0 = svmaxnm_z (p0, z0, 2)) + +/* +** maxnm_f16_x_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_f16_x (p0, z0, z1), + z0 = svmaxnm_x (p0, z0, z1)) + +/* +** maxnm_f16_x_tied2: +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_x_tied2, svfloat16_t, + z0 = svmaxnm_f16_x (p0, z1, z0), + z0 = svmaxnm_x (p0, z1, z0)) + +/* +** maxnm_f16_x_untied: +** ( +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f16_x_untied, svfloat16_t, + z0 = svmaxnm_f16_x (p0, z1, z2), + z0 = svmaxnm_x (p0, z1, z2)) + +/* +** maxnm_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_x (p0, z0, d4), + z0 = svmaxnm_x (p0, z0, d4)) + +/* +** maxnm_h4_f16_x_untied: +** mov z0\.h, h4 +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (maxnm_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmaxnm_n_f16_x (p0, z1, d4), + z0 = svmaxnm_x (p0, z1, d4)) + +/* +** maxnm_0_f16_x_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z0, 0), + z0 = svmaxnm_x (p0, z0, 0)) + +/* +** maxnm_0_f16_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z1, 0), + z0 = svmaxnm_x (p0, z1, 0)) + +/* +** maxnm_1_f16_x_tied1: +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z0, 1), + z0 = svmaxnm_x (p0, z0, 1)) + +/* +** maxnm_1_f16_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z1, 1), + z0 = svmaxnm_x (p0, z1, 1)) + +/* +** maxnm_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmaxnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z0, 2), + z0 = svmaxnm_x (p0, z0, 2)) + +/* +** maxnm_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmaxnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (p0, z1, 2), + z0 = svmaxnm_x (p0, z1, 2)) + +/* +** ptrue_maxnm_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_f16_x (svptrue_b16 (), z0, z1), + z0 = svmaxnm_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_maxnm_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f16_x_tied2, svfloat16_t, + z0 = svmaxnm_f16_x (svptrue_b16 (), z1, z0), + z0 = svmaxnm_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_maxnm_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f16_x_untied, svfloat16_t, + z0 = svmaxnm_f16_x (svptrue_b16 (), z1, z2), + z0 = svmaxnm_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_maxnm_0_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z0, 0), + z0 = svmaxnm_x (svptrue_b16 (), z0, 0)) + +/* +** ptrue_maxnm_0_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z1, 0), + z0 = svmaxnm_x (svptrue_b16 (), z1, 0)) + +/* +** ptrue_maxnm_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmaxnm_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_maxnm_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmaxnm_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_maxnm_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f16_x_tied1, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmaxnm_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_maxnm_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f16_x_untied, svfloat16_t, + z0 = svmaxnm_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmaxnm_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f32.c new file mode 100644 index 00000000000..4657d57c007 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f32.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnm_f32_m_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_m_tied1, svfloat32_t, + z0 = svmaxnm_f32_m (p0, z0, z1), + z0 = svmaxnm_m (p0, z0, z1)) + +/* +** maxnm_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_m_tied2, svfloat32_t, + z0 = svmaxnm_f32_m (p0, z1, z0), + z0 = svmaxnm_m (p0, z1, z0)) + +/* +** maxnm_f32_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_m_untied, svfloat32_t, + z0 = svmaxnm_f32_m (p0, z1, z2), + z0 = svmaxnm_m (p0, z1, z2)) + +/* +** maxnm_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmaxnm_n_f32_m (p0, z0, d4), + z0 = svmaxnm_m (p0, z0, d4)) + +/* +** maxnm_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_m_untied, svfloat32_t, float, + z0 = svmaxnm_n_f32_m (p0, z1, d4), + z0 = svmaxnm_m (p0, z1, d4)) + +/* +** maxnm_0_f32_m_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_m_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_m (p0, z0, 0), + z0 = svmaxnm_m (p0, z0, 0)) + +/* +** maxnm_0_f32_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_m_untied, svfloat32_t, + z0 = svmaxnm_n_f32_m (p0, z1, 0), + z0 = svmaxnm_m (p0, z1, 0)) + +/* +** maxnm_1_f32_m_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_m_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_m (p0, z0, 1), + z0 = svmaxnm_m (p0, z0, 1)) + +/* +** maxnm_1_f32_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_m_untied, svfloat32_t, + z0 = svmaxnm_n_f32_m (p0, z1, 1), + z0 = svmaxnm_m (p0, z1, 1)) + +/* +** maxnm_2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f32_m, svfloat32_t, + z0 = svmaxnm_n_f32_m (p0, z0, 2), + z0 = svmaxnm_m (p0, z0, 2)) + +/* +** maxnm_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_z_tied1, svfloat32_t, + z0 = svmaxnm_f32_z (p0, z0, z1), + z0 = svmaxnm_z (p0, z0, z1)) + +/* +** maxnm_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_z_tied2, svfloat32_t, + z0 = svmaxnm_f32_z (p0, z1, z0), + z0 = svmaxnm_z (p0, z1, z0)) + +/* +** maxnm_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmaxnm z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_z_untied, svfloat32_t, + z0 = svmaxnm_f32_z (p0, z1, z2), + z0 = svmaxnm_z (p0, z1, z2)) + +/* +** maxnm_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmaxnm_n_f32_z (p0, z0, d4), + z0 = svmaxnm_z (p0, z0, d4)) + +/* +** maxnm_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_z_untied, svfloat32_t, float, + z0 = svmaxnm_n_f32_z (p0, z1, d4), + z0 = svmaxnm_z (p0, z1, d4)) + +/* +** maxnm_0_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_z_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_z (p0, z0, 0), + z0 = svmaxnm_z (p0, z0, 0)) + +/* +** maxnm_0_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_z_untied, svfloat32_t, + z0 = svmaxnm_n_f32_z (p0, z1, 0), + z0 = svmaxnm_z (p0, z1, 0)) + +/* +** maxnm_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_z_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_z (p0, z0, 1), + z0 = svmaxnm_z (p0, z0, 1)) + +/* +** maxnm_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_z_untied, svfloat32_t, + z0 = svmaxnm_n_f32_z (p0, z1, 1), + z0 = svmaxnm_z (p0, z1, 1)) + +/* +** maxnm_2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f32_z, svfloat32_t, + z0 = svmaxnm_n_f32_z (p0, z0, 2), + z0 = svmaxnm_z (p0, z0, 2)) + +/* +** maxnm_f32_x_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_f32_x (p0, z0, z1), + z0 = svmaxnm_x (p0, z0, z1)) + +/* +** maxnm_f32_x_tied2: +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_x_tied2, svfloat32_t, + z0 = svmaxnm_f32_x (p0, z1, z0), + z0 = svmaxnm_x (p0, z1, z0)) + +/* +** maxnm_f32_x_untied: +** ( +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f32_x_untied, svfloat32_t, + z0 = svmaxnm_f32_x (p0, z1, z2), + z0 = svmaxnm_x (p0, z1, z2)) + +/* +** maxnm_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmaxnm_n_f32_x (p0, z0, d4), + z0 = svmaxnm_x (p0, z0, d4)) + +/* +** maxnm_s4_f32_x_untied: +** mov z0\.s, s4 +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (maxnm_s4_f32_x_untied, svfloat32_t, float, + z0 = svmaxnm_n_f32_x (p0, z1, d4), + z0 = svmaxnm_x (p0, z1, d4)) + +/* +** maxnm_0_f32_x_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z0, 0), + z0 = svmaxnm_x (p0, z0, 0)) + +/* +** maxnm_0_f32_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z1, 0), + z0 = svmaxnm_x (p0, z1, 0)) + +/* +** maxnm_1_f32_x_tied1: +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z0, 1), + z0 = svmaxnm_x (p0, z0, 1)) + +/* +** maxnm_1_f32_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z1, 1), + z0 = svmaxnm_x (p0, z1, 1)) + +/* +** maxnm_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmaxnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z0, 2), + z0 = svmaxnm_x (p0, z0, 2)) + +/* +** maxnm_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmaxnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (p0, z1, 2), + z0 = svmaxnm_x (p0, z1, 2)) + +/* +** ptrue_maxnm_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_f32_x (svptrue_b32 (), z0, z1), + z0 = svmaxnm_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_maxnm_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f32_x_tied2, svfloat32_t, + z0 = svmaxnm_f32_x (svptrue_b32 (), z1, z0), + z0 = svmaxnm_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_maxnm_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f32_x_untied, svfloat32_t, + z0 = svmaxnm_f32_x (svptrue_b32 (), z1, z2), + z0 = svmaxnm_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_maxnm_0_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z0, 0), + z0 = svmaxnm_x (svptrue_b32 (), z0, 0)) + +/* +** ptrue_maxnm_0_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z1, 0), + z0 = svmaxnm_x (svptrue_b32 (), z1, 0)) + +/* +** ptrue_maxnm_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmaxnm_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_maxnm_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmaxnm_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_maxnm_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f32_x_tied1, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmaxnm_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_maxnm_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f32_x_untied, svfloat32_t, + z0 = svmaxnm_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmaxnm_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f64.c new file mode 100644 index 00000000000..07d88e6c134 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnm_f64.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnm_f64_m_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_m_tied1, svfloat64_t, + z0 = svmaxnm_f64_m (p0, z0, z1), + z0 = svmaxnm_m (p0, z0, z1)) + +/* +** maxnm_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_m_tied2, svfloat64_t, + z0 = svmaxnm_f64_m (p0, z1, z0), + z0 = svmaxnm_m (p0, z1, z0)) + +/* +** maxnm_f64_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_m_untied, svfloat64_t, + z0 = svmaxnm_f64_m (p0, z1, z2), + z0 = svmaxnm_m (p0, z1, z2)) + +/* +** maxnm_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmaxnm_n_f64_m (p0, z0, d4), + z0 = svmaxnm_m (p0, z0, d4)) + +/* +** maxnm_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_m_untied, svfloat64_t, double, + z0 = svmaxnm_n_f64_m (p0, z1, d4), + z0 = svmaxnm_m (p0, z1, d4)) + +/* +** maxnm_0_f64_m_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_m_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_m (p0, z0, 0), + z0 = svmaxnm_m (p0, z0, 0)) + +/* +** maxnm_0_f64_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_m_untied, svfloat64_t, + z0 = svmaxnm_n_f64_m (p0, z1, 0), + z0 = svmaxnm_m (p0, z1, 0)) + +/* +** maxnm_1_f64_m_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_m_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_m (p0, z0, 1), + z0 = svmaxnm_m (p0, z0, 1)) + +/* +** maxnm_1_f64_m_untied: +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_m_untied, svfloat64_t, + z0 = svmaxnm_n_f64_m (p0, z1, 1), + z0 = svmaxnm_m (p0, z1, 1)) + +/* +** maxnm_2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f64_m, svfloat64_t, + z0 = svmaxnm_n_f64_m (p0, z0, 2), + z0 = svmaxnm_m (p0, z0, 2)) + +/* +** maxnm_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_z_tied1, svfloat64_t, + z0 = svmaxnm_f64_z (p0, z0, z1), + z0 = svmaxnm_z (p0, z0, z1)) + +/* +** maxnm_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_z_tied2, svfloat64_t, + z0 = svmaxnm_f64_z (p0, z1, z0), + z0 = svmaxnm_z (p0, z1, z0)) + +/* +** maxnm_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmaxnm z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_z_untied, svfloat64_t, + z0 = svmaxnm_f64_z (p0, z1, z2), + z0 = svmaxnm_z (p0, z1, z2)) + +/* +** maxnm_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmaxnm_n_f64_z (p0, z0, d4), + z0 = svmaxnm_z (p0, z0, d4)) + +/* +** maxnm_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_z_untied, svfloat64_t, double, + z0 = svmaxnm_n_f64_z (p0, z1, d4), + z0 = svmaxnm_z (p0, z1, d4)) + +/* +** maxnm_0_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_z_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_z (p0, z0, 0), + z0 = svmaxnm_z (p0, z0, 0)) + +/* +** maxnm_0_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_z_untied, svfloat64_t, + z0 = svmaxnm_n_f64_z (p0, z1, 0), + z0 = svmaxnm_z (p0, z1, 0)) + +/* +** maxnm_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_z_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_z (p0, z0, 1), + z0 = svmaxnm_z (p0, z0, 1)) + +/* +** maxnm_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_z_untied, svfloat64_t, + z0 = svmaxnm_n_f64_z (p0, z1, 1), + z0 = svmaxnm_z (p0, z1, 1)) + +/* +** maxnm_2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f64_z, svfloat64_t, + z0 = svmaxnm_n_f64_z (p0, z0, 2), + z0 = svmaxnm_z (p0, z0, 2)) + +/* +** maxnm_f64_x_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_f64_x (p0, z0, z1), + z0 = svmaxnm_x (p0, z0, z1)) + +/* +** maxnm_f64_x_tied2: +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_x_tied2, svfloat64_t, + z0 = svmaxnm_f64_x (p0, z1, z0), + z0 = svmaxnm_x (p0, z1, z0)) + +/* +** maxnm_f64_x_untied: +** ( +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (maxnm_f64_x_untied, svfloat64_t, + z0 = svmaxnm_f64_x (p0, z1, z2), + z0 = svmaxnm_x (p0, z1, z2)) + +/* +** maxnm_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmaxnm_n_f64_x (p0, z0, d4), + z0 = svmaxnm_x (p0, z0, d4)) + +/* +** maxnm_d4_f64_x_untied: +** mov z0\.d, d4 +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (maxnm_d4_f64_x_untied, svfloat64_t, double, + z0 = svmaxnm_n_f64_x (p0, z1, d4), + z0 = svmaxnm_x (p0, z1, d4)) + +/* +** maxnm_0_f64_x_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z0, 0), + z0 = svmaxnm_x (p0, z0, 0)) + +/* +** maxnm_0_f64_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_0_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z1, 0), + z0 = svmaxnm_x (p0, z1, 0)) + +/* +** maxnm_1_f64_x_tied1: +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z0, 1), + z0 = svmaxnm_x (p0, z0, 1)) + +/* +** maxnm_1_f64_x_untied: +** movprfx z0, z1 +** fmaxnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (maxnm_1_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z1, 1), + z0 = svmaxnm_x (p0, z1, 1)) + +/* +** maxnm_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmaxnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z0, 2), + z0 = svmaxnm_x (p0, z0, 2)) + +/* +** maxnm_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmaxnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (maxnm_2_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (p0, z1, 2), + z0 = svmaxnm_x (p0, z1, 2)) + +/* +** ptrue_maxnm_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_f64_x (svptrue_b64 (), z0, z1), + z0 = svmaxnm_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_maxnm_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f64_x_tied2, svfloat64_t, + z0 = svmaxnm_f64_x (svptrue_b64 (), z1, z0), + z0 = svmaxnm_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_maxnm_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_f64_x_untied, svfloat64_t, + z0 = svmaxnm_f64_x (svptrue_b64 (), z1, z2), + z0 = svmaxnm_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_maxnm_0_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z0, 0), + z0 = svmaxnm_x (svptrue_b64 (), z0, 0)) + +/* +** ptrue_maxnm_0_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_0_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z1, 0), + z0 = svmaxnm_x (svptrue_b64 (), z1, 0)) + +/* +** ptrue_maxnm_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmaxnm_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_maxnm_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_1_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmaxnm_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_maxnm_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f64_x_tied1, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmaxnm_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_maxnm_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_maxnm_2_f64_x_untied, svfloat64_t, + z0 = svmaxnm_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmaxnm_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f16.c new file mode 100644 index 00000000000..086bcf97475 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnmv_d0_f16_tied: +** fmaxnmv h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f16_tied, float16_t, svfloat16_t, + d0 = svmaxnmv_f16 (p0, z0), + d0 = svmaxnmv (p0, z0)) + +/* +** maxnmv_d0_f16_untied: +** fmaxnmv h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f16_untied, float16_t, svfloat16_t, + d0 = svmaxnmv_f16 (p0, z1), + d0 = svmaxnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f32.c new file mode 100644 index 00000000000..7fca8bc9ea5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnmv_d0_f32_tied: +** fmaxnmv s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f32_tied, float32_t, svfloat32_t, + d0 = svmaxnmv_f32 (p0, z0), + d0 = svmaxnmv (p0, z0)) + +/* +** maxnmv_d0_f32_untied: +** fmaxnmv s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f32_untied, float32_t, svfloat32_t, + d0 = svmaxnmv_f32 (p0, z1), + d0 = svmaxnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f64.c new file mode 100644 index 00000000000..8b088447938 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxnmv_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxnmv_d0_f64_tied: +** fmaxnmv d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f64_tied, float64_t, svfloat64_t, + d0 = svmaxnmv_f64 (p0, z0), + d0 = svmaxnmv (p0, z0)) + +/* +** maxnmv_d0_f64_untied: +** fmaxnmv d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (maxnmv_d0_f64_untied, float64_t, svfloat64_t, + d0 = svmaxnmv_f64 (p0, z1), + d0 = svmaxnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f16.c new file mode 100644 index 00000000000..a1682398702 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_d0_f16_tied: +** fmaxv h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f16_tied, float16_t, svfloat16_t, + d0 = svmaxv_f16 (p0, z0), + d0 = svmaxv (p0, z0)) + +/* +** maxv_d0_f16_untied: +** fmaxv h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f16_untied, float16_t, svfloat16_t, + d0 = svmaxv_f16 (p0, z1), + d0 = svmaxv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f32.c new file mode 100644 index 00000000000..64e5edfef9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_d0_f32_tied: +** fmaxv s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f32_tied, float32_t, svfloat32_t, + d0 = svmaxv_f32 (p0, z0), + d0 = svmaxv (p0, z0)) + +/* +** maxv_d0_f32_untied: +** fmaxv s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f32_untied, float32_t, svfloat32_t, + d0 = svmaxv_f32 (p0, z1), + d0 = svmaxv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f64.c new file mode 100644 index 00000000000..837d6dfdc9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_d0_f64_tied: +** fmaxv d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f64_tied, float64_t, svfloat64_t, + d0 = svmaxv_f64 (p0, z0), + d0 = svmaxv (p0, z0)) + +/* +** maxv_d0_f64_untied: +** fmaxv d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (maxv_d0_f64_untied, float64_t, svfloat64_t, + d0 = svmaxv_f64 (p0, z1), + d0 = svmaxv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s16.c new file mode 100644 index 00000000000..bbf36a11011 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_s16: +** smaxv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (maxv_x0_s16, int16_t, svint16_t, + x0 = svmaxv_s16 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s32.c new file mode 100644 index 00000000000..645169ee861 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_s32: +** smaxv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (maxv_x0_s32, int32_t, svint32_t, + x0 = svmaxv_s32 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s64.c new file mode 100644 index 00000000000..009c1e9e2cb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_s64: +** smaxv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (maxv_x0_s64, int64_t, svint64_t, + x0 = svmaxv_s64 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s8.c new file mode 100644 index 00000000000..2c1f1b9b3b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_s8: +** smaxv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (maxv_x0_s8, int8_t, svint8_t, + x0 = svmaxv_s8 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u16.c new file mode 100644 index 00000000000..978b8251a92 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_u16: +** umaxv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (maxv_x0_u16, uint16_t, svuint16_t, + x0 = svmaxv_u16 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u32.c new file mode 100644 index 00000000000..85853b4b0aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_u32: +** umaxv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (maxv_x0_u32, uint32_t, svuint32_t, + x0 = svmaxv_u32 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u64.c new file mode 100644 index 00000000000..95980ed3491 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_u64: +** umaxv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (maxv_x0_u64, uint64_t, svuint64_t, + x0 = svmaxv_u64 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u8.c new file mode 100644 index 00000000000..a0b23d2425b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/maxv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** maxv_x0_u8: +** umaxv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (maxv_x0_u8, uint8_t, svuint8_t, + x0 = svmaxv_u8 (p0, z0), + x0 = svmaxv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f16.c new file mode 100644 index 00000000000..721ee7389a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f16.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_f16_m_tied1: +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_m_tied1, svfloat16_t, + z0 = svmin_f16_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_m_tied2, svfloat16_t, + z0 = svmin_f16_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_f16_m_untied: +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_m_untied, svfloat16_t, + z0 = svmin_f16_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmin_n_f16_m (p0, z0, d4), + z0 = svmin_m (p0, z0, d4)) + +/* +** min_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmin_n_f16_m (p0, z1, d4), + z0 = svmin_m (p0, z1, d4)) + +/* +** min_0_f16_m_tied1: +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_m_tied1, svfloat16_t, + z0 = svmin_n_f16_m (p0, z0, 0), + z0 = svmin_m (p0, z0, 0)) + +/* +** min_0_f16_m_untied: +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_m_untied, svfloat16_t, + z0 = svmin_n_f16_m (p0, z1, 0), + z0 = svmin_m (p0, z1, 0)) + +/* +** min_1_f16_m_tied1: +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_m_tied1, svfloat16_t, + z0 = svmin_n_f16_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_f16_m_untied: +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_m_untied, svfloat16_t, + z0 = svmin_n_f16_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f16_m, svfloat16_t, + z0 = svmin_n_f16_m (p0, z0, 2), + z0 = svmin_m (p0, z0, 2)) + +/* +** min_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_z_tied1, svfloat16_t, + z0 = svmin_f16_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_z_tied2, svfloat16_t, + z0 = svmin_f16_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f16_z_untied, svfloat16_t, + z0 = svmin_f16_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmin_n_f16_z (p0, z0, d4), + z0 = svmin_z (p0, z0, d4)) + +/* +** min_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmin z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmin_n_f16_z (p0, z1, d4), + z0 = svmin_z (p0, z1, d4)) + +/* +** min_0_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_z_tied1, svfloat16_t, + z0 = svmin_n_f16_z (p0, z0, 0), + z0 = svmin_z (p0, z0, 0)) + +/* +** min_0_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_z_untied, svfloat16_t, + z0 = svmin_n_f16_z (p0, z1, 0), + z0 = svmin_z (p0, z1, 0)) + +/* +** min_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_z_tied1, svfloat16_t, + z0 = svmin_n_f16_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_z_untied, svfloat16_t, + z0 = svmin_n_f16_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f16_z, svfloat16_t, + z0 = svmin_n_f16_z (p0, z0, 2), + z0 = svmin_z (p0, z0, 2)) + +/* +** min_f16_x_tied1: +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_x_tied1, svfloat16_t, + z0 = svmin_f16_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_f16_x_tied2: +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_f16_x_tied2, svfloat16_t, + z0 = svmin_f16_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_f16_x_untied: +** ( +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f16_x_untied, svfloat16_t, + z0 = svmin_f16_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmin_n_f16_x (p0, z0, d4), + z0 = svmin_x (p0, z0, d4)) + +/* +** min_h4_f16_x_untied: +** mov z0\.h, h4 +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (min_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmin_n_f16_x (p0, z1, d4), + z0 = svmin_x (p0, z1, d4)) + +/* +** min_0_f16_x_tied1: +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (p0, z0, 0), + z0 = svmin_x (p0, z0, 0)) + +/* +** min_0_f16_x_untied: +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (p0, z1, 0), + z0 = svmin_x (p0, z1, 0)) + +/* +** min_1_f16_x_tied1: +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_f16_x_untied: +** movprfx z0, z1 +** fmin z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (p0, z0, 2), + z0 = svmin_x (p0, z0, 2)) + +/* +** min_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_2_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (p0, z1, 2), + z0 = svmin_x (p0, z1, 2)) + +/* +** ptrue_min_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f16_x_tied1, svfloat16_t, + z0 = svmin_f16_x (svptrue_b16 (), z0, z1), + z0 = svmin_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_min_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f16_x_tied2, svfloat16_t, + z0 = svmin_f16_x (svptrue_b16 (), z1, z0), + z0 = svmin_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_min_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f16_x_untied, svfloat16_t, + z0 = svmin_f16_x (svptrue_b16 (), z1, z2), + z0 = svmin_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_min_0_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z0, 0), + z0 = svmin_x (svptrue_b16 (), z0, 0)) + +/* +** ptrue_min_0_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z1, 0), + z0 = svmin_x (svptrue_b16 (), z1, 0)) + +/* +** ptrue_min_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmin_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_min_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmin_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_min_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f16_x_tied1, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmin_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_min_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f16_x_untied, svfloat16_t, + z0 = svmin_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmin_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f32.c new file mode 100644 index 00000000000..a3b1cf5c582 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f32.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_f32_m_tied1: +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_m_tied1, svfloat32_t, + z0 = svmin_f32_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_m_tied2, svfloat32_t, + z0 = svmin_f32_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_f32_m_untied: +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_m_untied, svfloat32_t, + z0 = svmin_f32_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmin_n_f32_m (p0, z0, d4), + z0 = svmin_m (p0, z0, d4)) + +/* +** min_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_m_untied, svfloat32_t, float, + z0 = svmin_n_f32_m (p0, z1, d4), + z0 = svmin_m (p0, z1, d4)) + +/* +** min_0_f32_m_tied1: +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_m_tied1, svfloat32_t, + z0 = svmin_n_f32_m (p0, z0, 0), + z0 = svmin_m (p0, z0, 0)) + +/* +** min_0_f32_m_untied: +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_m_untied, svfloat32_t, + z0 = svmin_n_f32_m (p0, z1, 0), + z0 = svmin_m (p0, z1, 0)) + +/* +** min_1_f32_m_tied1: +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_m_tied1, svfloat32_t, + z0 = svmin_n_f32_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_f32_m_untied: +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_m_untied, svfloat32_t, + z0 = svmin_n_f32_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f32_m, svfloat32_t, + z0 = svmin_n_f32_m (p0, z0, 2), + z0 = svmin_m (p0, z0, 2)) + +/* +** min_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_z_tied1, svfloat32_t, + z0 = svmin_f32_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_z_tied2, svfloat32_t, + z0 = svmin_f32_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f32_z_untied, svfloat32_t, + z0 = svmin_f32_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmin_n_f32_z (p0, z0, d4), + z0 = svmin_z (p0, z0, d4)) + +/* +** min_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmin z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_z_untied, svfloat32_t, float, + z0 = svmin_n_f32_z (p0, z1, d4), + z0 = svmin_z (p0, z1, d4)) + +/* +** min_0_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_z_tied1, svfloat32_t, + z0 = svmin_n_f32_z (p0, z0, 0), + z0 = svmin_z (p0, z0, 0)) + +/* +** min_0_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_z_untied, svfloat32_t, + z0 = svmin_n_f32_z (p0, z1, 0), + z0 = svmin_z (p0, z1, 0)) + +/* +** min_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_z_tied1, svfloat32_t, + z0 = svmin_n_f32_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_z_untied, svfloat32_t, + z0 = svmin_n_f32_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f32_z, svfloat32_t, + z0 = svmin_n_f32_z (p0, z0, 2), + z0 = svmin_z (p0, z0, 2)) + +/* +** min_f32_x_tied1: +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_x_tied1, svfloat32_t, + z0 = svmin_f32_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_f32_x_tied2: +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_f32_x_tied2, svfloat32_t, + z0 = svmin_f32_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_f32_x_untied: +** ( +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f32_x_untied, svfloat32_t, + z0 = svmin_f32_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmin_n_f32_x (p0, z0, d4), + z0 = svmin_x (p0, z0, d4)) + +/* +** min_s4_f32_x_untied: +** mov z0\.s, s4 +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (min_s4_f32_x_untied, svfloat32_t, float, + z0 = svmin_n_f32_x (p0, z1, d4), + z0 = svmin_x (p0, z1, d4)) + +/* +** min_0_f32_x_tied1: +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (p0, z0, 0), + z0 = svmin_x (p0, z0, 0)) + +/* +** min_0_f32_x_untied: +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (p0, z1, 0), + z0 = svmin_x (p0, z1, 0)) + +/* +** min_1_f32_x_tied1: +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_f32_x_untied: +** movprfx z0, z1 +** fmin z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (p0, z0, 2), + z0 = svmin_x (p0, z0, 2)) + +/* +** min_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_2_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (p0, z1, 2), + z0 = svmin_x (p0, z1, 2)) + +/* +** ptrue_min_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f32_x_tied1, svfloat32_t, + z0 = svmin_f32_x (svptrue_b32 (), z0, z1), + z0 = svmin_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_min_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f32_x_tied2, svfloat32_t, + z0 = svmin_f32_x (svptrue_b32 (), z1, z0), + z0 = svmin_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_min_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f32_x_untied, svfloat32_t, + z0 = svmin_f32_x (svptrue_b32 (), z1, z2), + z0 = svmin_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_min_0_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z0, 0), + z0 = svmin_x (svptrue_b32 (), z0, 0)) + +/* +** ptrue_min_0_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z1, 0), + z0 = svmin_x (svptrue_b32 (), z1, 0)) + +/* +** ptrue_min_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmin_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_min_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmin_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_min_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f32_x_tied1, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmin_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_min_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f32_x_untied, svfloat32_t, + z0 = svmin_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmin_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f64.c new file mode 100644 index 00000000000..bb31102e218 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_f64.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_f64_m_tied1: +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_m_tied1, svfloat64_t, + z0 = svmin_f64_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_f64_m_tied2, svfloat64_t, + z0 = svmin_f64_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_f64_m_untied: +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_m_untied, svfloat64_t, + z0 = svmin_f64_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmin_n_f64_m (p0, z0, d4), + z0 = svmin_m (p0, z0, d4)) + +/* +** min_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_m_untied, svfloat64_t, double, + z0 = svmin_n_f64_m (p0, z1, d4), + z0 = svmin_m (p0, z1, d4)) + +/* +** min_0_f64_m_tied1: +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_m_tied1, svfloat64_t, + z0 = svmin_n_f64_m (p0, z0, 0), + z0 = svmin_m (p0, z0, 0)) + +/* +** min_0_f64_m_untied: +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_m_untied, svfloat64_t, + z0 = svmin_n_f64_m (p0, z1, 0), + z0 = svmin_m (p0, z1, 0)) + +/* +** min_1_f64_m_tied1: +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_m_tied1, svfloat64_t, + z0 = svmin_n_f64_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_f64_m_untied: +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_m_untied, svfloat64_t, + z0 = svmin_n_f64_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f64_m, svfloat64_t, + z0 = svmin_n_f64_m (p0, z0, 2), + z0 = svmin_m (p0, z0, 2)) + +/* +** min_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_z_tied1, svfloat64_t, + z0 = svmin_f64_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_z_tied2, svfloat64_t, + z0 = svmin_f64_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f64_z_untied, svfloat64_t, + z0 = svmin_f64_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmin_n_f64_z (p0, z0, d4), + z0 = svmin_z (p0, z0, d4)) + +/* +** min_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmin z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_z_untied, svfloat64_t, double, + z0 = svmin_n_f64_z (p0, z1, d4), + z0 = svmin_z (p0, z1, d4)) + +/* +** min_0_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_z_tied1, svfloat64_t, + z0 = svmin_n_f64_z (p0, z0, 0), + z0 = svmin_z (p0, z0, 0)) + +/* +** min_0_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_z_untied, svfloat64_t, + z0 = svmin_n_f64_z (p0, z1, 0), + z0 = svmin_z (p0, z1, 0)) + +/* +** min_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_z_tied1, svfloat64_t, + z0 = svmin_n_f64_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_z_untied, svfloat64_t, + z0 = svmin_n_f64_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f64_z, svfloat64_t, + z0 = svmin_n_f64_z (p0, z0, 2), + z0 = svmin_z (p0, z0, 2)) + +/* +** min_f64_x_tied1: +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_x_tied1, svfloat64_t, + z0 = svmin_f64_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_f64_x_tied2: +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_f64_x_tied2, svfloat64_t, + z0 = svmin_f64_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_f64_x_untied: +** ( +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_f64_x_untied, svfloat64_t, + z0 = svmin_f64_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmin_n_f64_x (p0, z0, d4), + z0 = svmin_x (p0, z0, d4)) + +/* +** min_d4_f64_x_untied: +** mov z0\.d, d4 +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (min_d4_f64_x_untied, svfloat64_t, double, + z0 = svmin_n_f64_x (p0, z1, d4), + z0 = svmin_x (p0, z1, d4)) + +/* +** min_0_f64_x_tied1: +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (p0, z0, 0), + z0 = svmin_x (p0, z0, 0)) + +/* +** min_0_f64_x_untied: +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (min_0_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (p0, z1, 0), + z0 = svmin_x (p0, z1, 0)) + +/* +** min_1_f64_x_tied1: +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_f64_x_untied: +** movprfx z0, z1 +** fmin z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (min_1_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_2_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (p0, z0, 2), + z0 = svmin_x (p0, z0, 2)) + +/* +** min_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_2_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (p0, z1, 2), + z0 = svmin_x (p0, z1, 2)) + +/* +** ptrue_min_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f64_x_tied1, svfloat64_t, + z0 = svmin_f64_x (svptrue_b64 (), z0, z1), + z0 = svmin_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_min_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f64_x_tied2, svfloat64_t, + z0 = svmin_f64_x (svptrue_b64 (), z1, z0), + z0 = svmin_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_min_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_f64_x_untied, svfloat64_t, + z0 = svmin_f64_x (svptrue_b64 (), z1, z2), + z0 = svmin_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_min_0_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z0, 0), + z0 = svmin_x (svptrue_b64 (), z0, 0)) + +/* +** ptrue_min_0_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_0_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z1, 0), + z0 = svmin_x (svptrue_b64 (), z1, 0)) + +/* +** ptrue_min_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmin_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_min_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_1_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmin_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_min_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f64_x_tied1, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmin_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_min_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_min_2_f64_x_untied, svfloat64_t, + z0 = svmin_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmin_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c new file mode 100644 index 00000000000..14dfcc4c333 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_s16_m_tied1: +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_m_tied1, svint16_t, + z0 = svmin_s16_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smin z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_m_tied2, svint16_t, + z0 = svmin_s16_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_s16_m_untied: +** movprfx z0, z1 +** smin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_m_untied, svint16_t, + z0 = svmin_s16_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmin_n_s16_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmin_n_s16_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_m_tied1, svint16_t, + z0 = svmin_n_s16_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_m_untied, svint16_t, + z0 = svmin_n_s16_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_s16_m: +** mov (z[0-9]+)\.b, #-1 +** smin z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (min_m1_s16_m, svint16_t, + z0 = svmin_n_s16_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_z_tied1, svint16_t, + z0 = svmin_s16_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_z_tied2, svint16_t, + z0 = svmin_s16_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** smin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** smin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s16_z_untied, svint16_t, + z0 = svmin_s16_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmin_n_s16_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smin z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmin_n_s16_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_z_tied1, svint16_t, + z0 = svmin_n_s16_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smin z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_z_untied, svint16_t, + z0 = svmin_n_s16_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_s16_x_tied1: +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_x_tied1, svint16_t, + z0 = svmin_s16_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_s16_x_tied2: +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_s16_x_tied2, svint16_t, + z0 = svmin_s16_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_s16_x_untied: +** ( +** movprfx z0, z1 +** smin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** smin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s16_x_untied, svint16_t, + z0 = svmin_s16_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmin_n_s16_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_s16_x_untied: +** mov z0\.h, w0 +** smin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmin_n_s16_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_s16_x_tied1: +** smin z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_x_tied1, svint16_t, + z0 = svmin_n_s16_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_s16_x_untied: +** movprfx z0, z1 +** smin z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s16_x_untied, svint16_t, + z0 = svmin_n_s16_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_s16_x: +** smin z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_s16_x, svint16_t, + z0 = svmin_n_s16_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_s16_x: +** mov (z[0-9]+\.h), #128 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_128_s16_x, svint16_t, + z0 = svmin_n_s16_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_m1_s16_x: +** smin z0\.h, z0\.h, #-1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_s16_x, svint16_t, + z0 = svmin_n_s16_x (p0, z0, -1), + z0 = svmin_x (p0, z0, -1)) + +/* +** min_m128_s16_x: +** smin z0\.h, z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (min_m128_s16_x, svint16_t, + z0 = svmin_n_s16_x (p0, z0, -128), + z0 = svmin_x (p0, z0, -128)) + +/* +** min_m129_s16_x: +** mov (z[0-9]+\.h), #-129 +** smin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m129_s16_x, svint16_t, + z0 = svmin_n_s16_x (p0, z0, -129), + z0 = svmin_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s32.c new file mode 100644 index 00000000000..cee2b649d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s32.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_s32_m_tied1: +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_m_tied1, svint32_t, + z0 = svmin_s32_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smin z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_m_tied2, svint32_t, + z0 = svmin_s32_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_s32_m_untied: +** movprfx z0, z1 +** smin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_m_untied, svint32_t, + z0 = svmin_s32_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmin_n_s32_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmin_n_s32_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_m_tied1, svint32_t, + z0 = svmin_n_s32_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_m_untied, svint32_t, + z0 = svmin_n_s32_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_s32_m: +** mov (z[0-9]+)\.b, #-1 +** smin z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (min_m1_s32_m, svint32_t, + z0 = svmin_n_s32_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_z_tied1, svint32_t, + z0 = svmin_s32_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_z_tied2, svint32_t, + z0 = svmin_s32_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** smin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** smin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s32_z_untied, svint32_t, + z0 = svmin_s32_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmin_n_s32_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smin z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmin_n_s32_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_z_tied1, svint32_t, + z0 = svmin_n_s32_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smin z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_z_untied, svint32_t, + z0 = svmin_n_s32_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_s32_x_tied1: +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_x_tied1, svint32_t, + z0 = svmin_s32_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_s32_x_tied2: +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_s32_x_tied2, svint32_t, + z0 = svmin_s32_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_s32_x_untied: +** ( +** movprfx z0, z1 +** smin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** smin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s32_x_untied, svint32_t, + z0 = svmin_s32_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmin_n_s32_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_s32_x_untied: +** mov z0\.s, w0 +** smin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmin_n_s32_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_s32_x_tied1: +** smin z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_x_tied1, svint32_t, + z0 = svmin_n_s32_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_s32_x_untied: +** movprfx z0, z1 +** smin z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s32_x_untied, svint32_t, + z0 = svmin_n_s32_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_s32_x: +** smin z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_s32_x, svint32_t, + z0 = svmin_n_s32_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_s32_x: +** mov (z[0-9]+\.s), #128 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_128_s32_x, svint32_t, + z0 = svmin_n_s32_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_m1_s32_x: +** smin z0\.s, z0\.s, #-1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_s32_x, svint32_t, + z0 = svmin_n_s32_x (p0, z0, -1), + z0 = svmin_x (p0, z0, -1)) + +/* +** min_m128_s32_x: +** smin z0\.s, z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (min_m128_s32_x, svint32_t, + z0 = svmin_n_s32_x (p0, z0, -128), + z0 = svmin_x (p0, z0, -128)) + +/* +** min_m129_s32_x: +** mov (z[0-9]+\.s), #-129 +** smin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m129_s32_x, svint32_t, + z0 = svmin_n_s32_x (p0, z0, -129), + z0 = svmin_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s64.c new file mode 100644 index 00000000000..0d20bd0b28d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s64.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_s64_m_tied1: +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_m_tied1, svint64_t, + z0 = svmin_s64_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_s64_m_tied2, svint64_t, + z0 = svmin_s64_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_s64_m_untied: +** movprfx z0, z1 +** smin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_m_untied, svint64_t, + z0 = svmin_s64_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmin_n_s64_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmin_n_s64_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_m_tied1, svint64_t, + z0 = svmin_n_s64_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_m_untied, svint64_t, + z0 = svmin_n_s64_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_s64_m: +** mov (z[0-9]+)\.b, #-1 +** smin z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (min_m1_s64_m, svint64_t, + z0 = svmin_n_s64_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_z_tied1, svint64_t, + z0 = svmin_s64_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_z_tied2, svint64_t, + z0 = svmin_s64_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** smin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** smin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s64_z_untied, svint64_t, + z0 = svmin_s64_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmin_n_s64_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smin z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmin_n_s64_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_z_tied1, svint64_t, + z0 = svmin_n_s64_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smin z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_z_untied, svint64_t, + z0 = svmin_n_s64_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_s64_x_tied1: +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_x_tied1, svint64_t, + z0 = svmin_s64_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_s64_x_tied2: +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_s64_x_tied2, svint64_t, + z0 = svmin_s64_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_s64_x_untied: +** ( +** movprfx z0, z1 +** smin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** smin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s64_x_untied, svint64_t, + z0 = svmin_s64_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmin_n_s64_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_x0_s64_x_untied: +** mov z0\.d, x0 +** smin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (min_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmin_n_s64_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_s64_x_tied1: +** smin z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_x_tied1, svint64_t, + z0 = svmin_n_s64_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_s64_x_untied: +** movprfx z0, z1 +** smin z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s64_x_untied, svint64_t, + z0 = svmin_n_s64_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_s64_x: +** smin z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_s64_x, svint64_t, + z0 = svmin_n_s64_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_s64_x: +** mov (z[0-9]+\.d), #128 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_128_s64_x, svint64_t, + z0 = svmin_n_s64_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_m1_s64_x: +** smin z0\.d, z0\.d, #-1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_s64_x, svint64_t, + z0 = svmin_n_s64_x (p0, z0, -1), + z0 = svmin_x (p0, z0, -1)) + +/* +** min_m128_s64_x: +** smin z0\.d, z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (min_m128_s64_x, svint64_t, + z0 = svmin_n_s64_x (p0, z0, -128), + z0 = svmin_x (p0, z0, -128)) + +/* +** min_m129_s64_x: +** mov (z[0-9]+\.d), #-129 +** smin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m129_s64_x, svint64_t, + z0 = svmin_n_s64_x (p0, z0, -129), + z0 = svmin_x (p0, z0, -129)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c new file mode 100644 index 00000000000..714b1576d5c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c @@ -0,0 +1,273 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_s8_m_tied1: +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_m_tied1, svint8_t, + z0 = svmin_s8_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smin z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_m_tied2, svint8_t, + z0 = svmin_s8_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_s8_m_untied: +** movprfx z0, z1 +** smin z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_m_untied, svint8_t, + z0 = svmin_s8_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmin_n_s8_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmin_n_s8_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_m_tied1, svint8_t, + z0 = svmin_n_s8_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_m_untied, svint8_t, + z0 = svmin_n_s8_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_s8_m: +** mov (z[0-9]+\.b), #-1 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_s8_m, svint8_t, + z0 = svmin_n_s8_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_z_tied1, svint8_t, + z0 = svmin_s8_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_z_tied2, svint8_t, + z0 = svmin_s8_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** smin z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** smin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s8_z_untied, svint8_t, + z0 = svmin_s8_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmin_n_s8_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smin z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmin_n_s8_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_z_tied1, svint8_t, + z0 = svmin_n_s8_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smin z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_z_untied, svint8_t, + z0 = svmin_n_s8_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_s8_x_tied1: +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_x_tied1, svint8_t, + z0 = svmin_s8_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_s8_x_tied2: +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_s8_x_tied2, svint8_t, + z0 = svmin_s8_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_s8_x_untied: +** ( +** movprfx z0, z1 +** smin z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** smin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_s8_x_untied, svint8_t, + z0 = svmin_s8_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** smin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmin_n_s8_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_s8_x_untied: +** mov z0\.b, w0 +** smin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (min_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmin_n_s8_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_s8_x_tied1: +** smin z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_x_tied1, svint8_t, + z0 = svmin_n_s8_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_s8_x_untied: +** movprfx z0, z1 +** smin z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_s8_x_untied, svint8_t, + z0 = svmin_n_s8_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_s8_x: +** smin z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_s8_x, svint8_t, + z0 = svmin_n_s8_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_m1_s8_x: +** smin z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_s8_x, svint8_t, + z0 = svmin_n_s8_x (p0, z0, -1), + z0 = svmin_x (p0, z0, -1)) + +/* +** min_m127_s8_x: +** smin z0\.b, z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (min_m127_s8_x, svint8_t, + z0 = svmin_n_s8_x (p0, z0, -127), + z0 = svmin_x (p0, z0, -127)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c new file mode 100644 index 00000000000..df35cf1135e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_u16_m_tied1: +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_m_tied1, svuint16_t, + z0 = svmin_u16_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umin z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_m_tied2, svuint16_t, + z0 = svmin_u16_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_u16_m_untied: +** movprfx z0, z1 +** umin z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_m_untied, svuint16_t, + z0 = svmin_u16_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmin_n_u16_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmin_n_u16_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_m_tied1, svuint16_t, + z0 = svmin_n_u16_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_m_untied, svuint16_t, + z0 = svmin_n_u16_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_u16_m: +** mov (z[0-9]+)\.b, #-1 +** umin z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (min_m1_u16_m, svuint16_t, + z0 = svmin_n_u16_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_z_tied1, svuint16_t, + z0 = svmin_u16_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_z_tied2, svuint16_t, + z0 = svmin_u16_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** umin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** umin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u16_z_untied, svuint16_t, + z0 = svmin_u16_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmin_n_u16_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umin z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmin_n_u16_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_z_tied1, svuint16_t, + z0 = svmin_n_u16_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umin z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_z_untied, svuint16_t, + z0 = svmin_n_u16_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_u16_x_tied1: +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_x_tied1, svuint16_t, + z0 = svmin_u16_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_u16_x_tied2: +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (min_u16_x_tied2, svuint16_t, + z0 = svmin_u16_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_u16_x_untied: +** ( +** movprfx z0, z1 +** umin z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** umin z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u16_x_untied, svuint16_t, + z0 = svmin_u16_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmin_n_u16_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_u16_x_untied: +** mov z0\.h, w0 +** umin z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmin_n_u16_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_u16_x_tied1: +** umin z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_x_tied1, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_u16_x_untied: +** movprfx z0, z1 +** umin z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u16_x_untied, svuint16_t, + z0 = svmin_n_u16_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_u16_x: +** umin z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_u16_x, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_u16_x: +** umin z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (min_128_u16_x, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_255_u16_x: +** umin z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (min_255_u16_x, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, 255), + z0 = svmin_x (p0, z0, 255)) + +/* +** min_256_u16_x: +** mov (z[0-9]+\.h), #256 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_256_u16_x, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, 256), + z0 = svmin_x (p0, z0, 256)) + +/* +** min_m2_u16_x: +** mov (z[0-9]+\.h), #-2 +** umin z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m2_u16_x, svuint16_t, + z0 = svmin_n_u16_x (p0, z0, -2), + z0 = svmin_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u32.c new file mode 100644 index 00000000000..7f84d099d61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u32.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_u32_m_tied1: +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_m_tied1, svuint32_t, + z0 = svmin_u32_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umin z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_m_tied2, svuint32_t, + z0 = svmin_u32_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_u32_m_untied: +** movprfx z0, z1 +** umin z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_m_untied, svuint32_t, + z0 = svmin_u32_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmin_n_u32_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmin_n_u32_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_m_tied1, svuint32_t, + z0 = svmin_n_u32_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_m_untied, svuint32_t, + z0 = svmin_n_u32_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_u32_m: +** mov (z[0-9]+)\.b, #-1 +** umin z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (min_m1_u32_m, svuint32_t, + z0 = svmin_n_u32_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_z_tied1, svuint32_t, + z0 = svmin_u32_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_z_tied2, svuint32_t, + z0 = svmin_u32_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** umin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** umin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u32_z_untied, svuint32_t, + z0 = svmin_u32_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmin_n_u32_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umin z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmin_n_u32_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_z_tied1, svuint32_t, + z0 = svmin_n_u32_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umin z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_z_untied, svuint32_t, + z0 = svmin_n_u32_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_u32_x_tied1: +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_x_tied1, svuint32_t, + z0 = svmin_u32_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_u32_x_tied2: +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (min_u32_x_tied2, svuint32_t, + z0 = svmin_u32_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_u32_x_untied: +** ( +** movprfx z0, z1 +** umin z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** umin z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u32_x_untied, svuint32_t, + z0 = svmin_u32_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmin_n_u32_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_u32_x_untied: +** mov z0\.s, w0 +** umin z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmin_n_u32_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_u32_x_tied1: +** umin z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_x_tied1, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_u32_x_untied: +** movprfx z0, z1 +** umin z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u32_x_untied, svuint32_t, + z0 = svmin_n_u32_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_u32_x: +** umin z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_u32_x, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_u32_x: +** umin z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (min_128_u32_x, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_255_u32_x: +** umin z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (min_255_u32_x, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, 255), + z0 = svmin_x (p0, z0, 255)) + +/* +** min_256_u32_x: +** mov (z[0-9]+\.s), #256 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_256_u32_x, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, 256), + z0 = svmin_x (p0, z0, 256)) + +/* +** min_m2_u32_x: +** mov (z[0-9]+\.s), #-2 +** umin z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m2_u32_x, svuint32_t, + z0 = svmin_n_u32_x (p0, z0, -2), + z0 = svmin_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u64.c new file mode 100644 index 00000000000..06e6e509920 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u64.c @@ -0,0 +1,293 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_u64_m_tied1: +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_m_tied1, svuint64_t, + z0 = svmin_u64_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_u64_m_tied2, svuint64_t, + z0 = svmin_u64_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_u64_m_untied: +** movprfx z0, z1 +** umin z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_m_untied, svuint64_t, + z0 = svmin_u64_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmin_n_u64_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmin_n_u64_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_m_tied1, svuint64_t, + z0 = svmin_n_u64_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_m_untied, svuint64_t, + z0 = svmin_n_u64_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_u64_m: +** mov (z[0-9]+)\.b, #-1 +** umin z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (min_m1_u64_m, svuint64_t, + z0 = svmin_n_u64_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_z_tied1, svuint64_t, + z0 = svmin_u64_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_z_tied2, svuint64_t, + z0 = svmin_u64_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** umin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** umin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u64_z_untied, svuint64_t, + z0 = svmin_u64_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmin_n_u64_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umin z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmin_n_u64_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_z_tied1, svuint64_t, + z0 = svmin_n_u64_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umin z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_z_untied, svuint64_t, + z0 = svmin_n_u64_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_u64_x_tied1: +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_x_tied1, svuint64_t, + z0 = svmin_u64_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_u64_x_tied2: +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (min_u64_x_tied2, svuint64_t, + z0 = svmin_u64_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_u64_x_untied: +** ( +** movprfx z0, z1 +** umin z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** umin z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u64_x_untied, svuint64_t, + z0 = svmin_u64_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmin_n_u64_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_x0_u64_x_untied: +** mov z0\.d, x0 +** umin z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (min_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmin_n_u64_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_u64_x_tied1: +** umin z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_x_tied1, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_u64_x_untied: +** movprfx z0, z1 +** umin z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u64_x_untied, svuint64_t, + z0 = svmin_n_u64_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_u64_x: +** umin z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_u64_x, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_u64_x: +** umin z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (min_128_u64_x, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_255_u64_x: +** umin z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (min_255_u64_x, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, 255), + z0 = svmin_x (p0, z0, 255)) + +/* +** min_256_u64_x: +** mov (z[0-9]+\.d), #256 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_256_u64_x, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, 256), + z0 = svmin_x (p0, z0, 256)) + +/* +** min_m2_u64_x: +** mov (z[0-9]+\.d), #-2 +** umin z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m2_u64_x, svuint64_t, + z0 = svmin_n_u64_x (p0, z0, -2), + z0 = svmin_x (p0, z0, -2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c new file mode 100644 index 00000000000..2ca274278a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c @@ -0,0 +1,273 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** min_u8_m_tied1: +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_m_tied1, svuint8_t, + z0 = svmin_u8_m (p0, z0, z1), + z0 = svmin_m (p0, z0, z1)) + +/* +** min_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umin z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_m_tied2, svuint8_t, + z0 = svmin_u8_m (p0, z1, z0), + z0 = svmin_m (p0, z1, z0)) + +/* +** min_u8_m_untied: +** movprfx z0, z1 +** umin z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_m_untied, svuint8_t, + z0 = svmin_u8_m (p0, z1, z2), + z0 = svmin_m (p0, z1, z2)) + +/* +** min_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmin_n_u8_m (p0, z0, x0), + z0 = svmin_m (p0, z0, x0)) + +/* +** min_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmin_n_u8_m (p0, z1, x0), + z0 = svmin_m (p0, z1, x0)) + +/* +** min_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_m_tied1, svuint8_t, + z0 = svmin_n_u8_m (p0, z0, 1), + z0 = svmin_m (p0, z0, 1)) + +/* +** min_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_m_untied, svuint8_t, + z0 = svmin_n_u8_m (p0, z1, 1), + z0 = svmin_m (p0, z1, 1)) + +/* +** min_m1_u8_m: +** mov (z[0-9]+\.b), #-1 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_m1_u8_m, svuint8_t, + z0 = svmin_n_u8_m (p0, z0, -1), + z0 = svmin_m (p0, z0, -1)) + +/* +** min_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_z_tied1, svuint8_t, + z0 = svmin_u8_z (p0, z0, z1), + z0 = svmin_z (p0, z0, z1)) + +/* +** min_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_z_tied2, svuint8_t, + z0 = svmin_u8_z (p0, z1, z0), + z0 = svmin_z (p0, z1, z0)) + +/* +** min_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** umin z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** umin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u8_z_untied, svuint8_t, + z0 = svmin_u8_z (p0, z1, z2), + z0 = svmin_z (p0, z1, z2)) + +/* +** min_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmin_n_u8_z (p0, z0, x0), + z0 = svmin_z (p0, z0, x0)) + +/* +** min_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umin z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmin_n_u8_z (p0, z1, x0), + z0 = svmin_z (p0, z1, x0)) + +/* +** min_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_z_tied1, svuint8_t, + z0 = svmin_n_u8_z (p0, z0, 1), + z0 = svmin_z (p0, z0, 1)) + +/* +** min_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umin z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_z_untied, svuint8_t, + z0 = svmin_n_u8_z (p0, z1, 1), + z0 = svmin_z (p0, z1, 1)) + +/* +** min_u8_x_tied1: +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_x_tied1, svuint8_t, + z0 = svmin_u8_x (p0, z0, z1), + z0 = svmin_x (p0, z0, z1)) + +/* +** min_u8_x_tied2: +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (min_u8_x_tied2, svuint8_t, + z0 = svmin_u8_x (p0, z1, z0), + z0 = svmin_x (p0, z1, z0)) + +/* +** min_u8_x_untied: +** ( +** movprfx z0, z1 +** umin z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** umin z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (min_u8_x_untied, svuint8_t, + z0 = svmin_u8_x (p0, z1, z2), + z0 = svmin_x (p0, z1, z2)) + +/* +** min_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** umin z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmin_n_u8_x (p0, z0, x0), + z0 = svmin_x (p0, z0, x0)) + +/* +** min_w0_u8_x_untied: +** mov z0\.b, w0 +** umin z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (min_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmin_n_u8_x (p0, z1, x0), + z0 = svmin_x (p0, z1, x0)) + +/* +** min_1_u8_x_tied1: +** umin z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_x_tied1, svuint8_t, + z0 = svmin_n_u8_x (p0, z0, 1), + z0 = svmin_x (p0, z0, 1)) + +/* +** min_1_u8_x_untied: +** movprfx z0, z1 +** umin z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (min_1_u8_x_untied, svuint8_t, + z0 = svmin_n_u8_x (p0, z1, 1), + z0 = svmin_x (p0, z1, 1)) + +/* +** min_127_u8_x: +** umin z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (min_127_u8_x, svuint8_t, + z0 = svmin_n_u8_x (p0, z0, 127), + z0 = svmin_x (p0, z0, 127)) + +/* +** min_128_u8_x: +** umin z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (min_128_u8_x, svuint8_t, + z0 = svmin_n_u8_x (p0, z0, 128), + z0 = svmin_x (p0, z0, 128)) + +/* +** min_254_u8_x: +** umin z0\.b, z0\.b, #254 +** ret +*/ +TEST_UNIFORM_Z (min_254_u8_x, svuint8_t, + z0 = svmin_n_u8_x (p0, z0, 254), + z0 = svmin_x (p0, z0, 254)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f16.c new file mode 100644 index 00000000000..43caaa14e7b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f16.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnm_f16_m_tied1: +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_m_tied1, svfloat16_t, + z0 = svminnm_f16_m (p0, z0, z1), + z0 = svminnm_m (p0, z0, z1)) + +/* +** minnm_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_m_tied2, svfloat16_t, + z0 = svminnm_f16_m (p0, z1, z0), + z0 = svminnm_m (p0, z1, z0)) + +/* +** minnm_f16_m_untied: +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_m_untied, svfloat16_t, + z0 = svminnm_f16_m (p0, z1, z2), + z0 = svminnm_m (p0, z1, z2)) + +/* +** minnm_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svminnm_n_f16_m (p0, z0, d4), + z0 = svminnm_m (p0, z0, d4)) + +/* +** minnm_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svminnm_n_f16_m (p0, z1, d4), + z0 = svminnm_m (p0, z1, d4)) + +/* +** minnm_0_f16_m_tied1: +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_m_tied1, svfloat16_t, + z0 = svminnm_n_f16_m (p0, z0, 0), + z0 = svminnm_m (p0, z0, 0)) + +/* +** minnm_0_f16_m_untied: +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_m_untied, svfloat16_t, + z0 = svminnm_n_f16_m (p0, z1, 0), + z0 = svminnm_m (p0, z1, 0)) + +/* +** minnm_1_f16_m_tied1: +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_m_tied1, svfloat16_t, + z0 = svminnm_n_f16_m (p0, z0, 1), + z0 = svminnm_m (p0, z0, 1)) + +/* +** minnm_1_f16_m_untied: +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_m_untied, svfloat16_t, + z0 = svminnm_n_f16_m (p0, z1, 1), + z0 = svminnm_m (p0, z1, 1)) + +/* +** minnm_2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f16_m, svfloat16_t, + z0 = svminnm_n_f16_m (p0, z0, 2), + z0 = svminnm_m (p0, z0, 2)) + +/* +** minnm_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_z_tied1, svfloat16_t, + z0 = svminnm_f16_z (p0, z0, z1), + z0 = svminnm_z (p0, z0, z1)) + +/* +** minnm_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_z_tied2, svfloat16_t, + z0 = svminnm_f16_z (p0, z1, z0), + z0 = svminnm_z (p0, z1, z0)) + +/* +** minnm_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fminnm z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_z_untied, svfloat16_t, + z0 = svminnm_f16_z (p0, z1, z2), + z0 = svminnm_z (p0, z1, z2)) + +/* +** minnm_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svminnm_n_f16_z (p0, z0, d4), + z0 = svminnm_z (p0, z0, d4)) + +/* +** minnm_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fminnm z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svminnm_n_f16_z (p0, z1, d4), + z0 = svminnm_z (p0, z1, d4)) + +/* +** minnm_0_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_z_tied1, svfloat16_t, + z0 = svminnm_n_f16_z (p0, z0, 0), + z0 = svminnm_z (p0, z0, 0)) + +/* +** minnm_0_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_z_untied, svfloat16_t, + z0 = svminnm_n_f16_z (p0, z1, 0), + z0 = svminnm_z (p0, z1, 0)) + +/* +** minnm_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_z_tied1, svfloat16_t, + z0 = svminnm_n_f16_z (p0, z0, 1), + z0 = svminnm_z (p0, z0, 1)) + +/* +** minnm_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_z_untied, svfloat16_t, + z0 = svminnm_n_f16_z (p0, z1, 1), + z0 = svminnm_z (p0, z1, 1)) + +/* +** minnm_2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f16_z, svfloat16_t, + z0 = svminnm_n_f16_z (p0, z0, 2), + z0 = svminnm_z (p0, z0, 2)) + +/* +** minnm_f16_x_tied1: +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_x_tied1, svfloat16_t, + z0 = svminnm_f16_x (p0, z0, z1), + z0 = svminnm_x (p0, z0, z1)) + +/* +** minnm_f16_x_tied2: +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_x_tied2, svfloat16_t, + z0 = svminnm_f16_x (p0, z1, z0), + z0 = svminnm_x (p0, z1, z0)) + +/* +** minnm_f16_x_untied: +** ( +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f16_x_untied, svfloat16_t, + z0 = svminnm_f16_x (p0, z1, z2), + z0 = svminnm_x (p0, z1, z2)) + +/* +** minnm_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svminnm_n_f16_x (p0, z0, d4), + z0 = svminnm_x (p0, z0, d4)) + +/* +** minnm_h4_f16_x_untied: +** mov z0\.h, h4 +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (minnm_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svminnm_n_f16_x (p0, z1, d4), + z0 = svminnm_x (p0, z1, d4)) + +/* +** minnm_0_f16_x_tied1: +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z0, 0), + z0 = svminnm_x (p0, z0, 0)) + +/* +** minnm_0_f16_x_untied: +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z1, 0), + z0 = svminnm_x (p0, z1, 0)) + +/* +** minnm_1_f16_x_tied1: +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z0, 1), + z0 = svminnm_x (p0, z0, 1)) + +/* +** minnm_1_f16_x_untied: +** movprfx z0, z1 +** fminnm z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z1, 1), + z0 = svminnm_x (p0, z1, 1)) + +/* +** minnm_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fminnm z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z0, 2), + z0 = svminnm_x (p0, z0, 2)) + +/* +** minnm_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fminnm z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (p0, z1, 2), + z0 = svminnm_x (p0, z1, 2)) + +/* +** ptrue_minnm_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f16_x_tied1, svfloat16_t, + z0 = svminnm_f16_x (svptrue_b16 (), z0, z1), + z0 = svminnm_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_minnm_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f16_x_tied2, svfloat16_t, + z0 = svminnm_f16_x (svptrue_b16 (), z1, z0), + z0 = svminnm_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_minnm_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f16_x_untied, svfloat16_t, + z0 = svminnm_f16_x (svptrue_b16 (), z1, z2), + z0 = svminnm_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_minnm_0_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z0, 0), + z0 = svminnm_x (svptrue_b16 (), z0, 0)) + +/* +** ptrue_minnm_0_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z1, 0), + z0 = svminnm_x (svptrue_b16 (), z1, 0)) + +/* +** ptrue_minnm_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svminnm_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_minnm_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svminnm_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_minnm_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f16_x_tied1, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svminnm_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_minnm_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f16_x_untied, svfloat16_t, + z0 = svminnm_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svminnm_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f32.c new file mode 100644 index 00000000000..4fac8e8ade9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f32.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnm_f32_m_tied1: +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_m_tied1, svfloat32_t, + z0 = svminnm_f32_m (p0, z0, z1), + z0 = svminnm_m (p0, z0, z1)) + +/* +** minnm_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_m_tied2, svfloat32_t, + z0 = svminnm_f32_m (p0, z1, z0), + z0 = svminnm_m (p0, z1, z0)) + +/* +** minnm_f32_m_untied: +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_m_untied, svfloat32_t, + z0 = svminnm_f32_m (p0, z1, z2), + z0 = svminnm_m (p0, z1, z2)) + +/* +** minnm_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_m_tied1, svfloat32_t, float, + z0 = svminnm_n_f32_m (p0, z0, d4), + z0 = svminnm_m (p0, z0, d4)) + +/* +** minnm_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_m_untied, svfloat32_t, float, + z0 = svminnm_n_f32_m (p0, z1, d4), + z0 = svminnm_m (p0, z1, d4)) + +/* +** minnm_0_f32_m_tied1: +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_m_tied1, svfloat32_t, + z0 = svminnm_n_f32_m (p0, z0, 0), + z0 = svminnm_m (p0, z0, 0)) + +/* +** minnm_0_f32_m_untied: +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_m_untied, svfloat32_t, + z0 = svminnm_n_f32_m (p0, z1, 0), + z0 = svminnm_m (p0, z1, 0)) + +/* +** minnm_1_f32_m_tied1: +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_m_tied1, svfloat32_t, + z0 = svminnm_n_f32_m (p0, z0, 1), + z0 = svminnm_m (p0, z0, 1)) + +/* +** minnm_1_f32_m_untied: +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_m_untied, svfloat32_t, + z0 = svminnm_n_f32_m (p0, z1, 1), + z0 = svminnm_m (p0, z1, 1)) + +/* +** minnm_2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f32_m, svfloat32_t, + z0 = svminnm_n_f32_m (p0, z0, 2), + z0 = svminnm_m (p0, z0, 2)) + +/* +** minnm_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_z_tied1, svfloat32_t, + z0 = svminnm_f32_z (p0, z0, z1), + z0 = svminnm_z (p0, z0, z1)) + +/* +** minnm_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_z_tied2, svfloat32_t, + z0 = svminnm_f32_z (p0, z1, z0), + z0 = svminnm_z (p0, z1, z0)) + +/* +** minnm_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fminnm z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_z_untied, svfloat32_t, + z0 = svminnm_f32_z (p0, z1, z2), + z0 = svminnm_z (p0, z1, z2)) + +/* +** minnm_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_z_tied1, svfloat32_t, float, + z0 = svminnm_n_f32_z (p0, z0, d4), + z0 = svminnm_z (p0, z0, d4)) + +/* +** minnm_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fminnm z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_z_untied, svfloat32_t, float, + z0 = svminnm_n_f32_z (p0, z1, d4), + z0 = svminnm_z (p0, z1, d4)) + +/* +** minnm_0_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_z_tied1, svfloat32_t, + z0 = svminnm_n_f32_z (p0, z0, 0), + z0 = svminnm_z (p0, z0, 0)) + +/* +** minnm_0_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_z_untied, svfloat32_t, + z0 = svminnm_n_f32_z (p0, z1, 0), + z0 = svminnm_z (p0, z1, 0)) + +/* +** minnm_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_z_tied1, svfloat32_t, + z0 = svminnm_n_f32_z (p0, z0, 1), + z0 = svminnm_z (p0, z0, 1)) + +/* +** minnm_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_z_untied, svfloat32_t, + z0 = svminnm_n_f32_z (p0, z1, 1), + z0 = svminnm_z (p0, z1, 1)) + +/* +** minnm_2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f32_z, svfloat32_t, + z0 = svminnm_n_f32_z (p0, z0, 2), + z0 = svminnm_z (p0, z0, 2)) + +/* +** minnm_f32_x_tied1: +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_x_tied1, svfloat32_t, + z0 = svminnm_f32_x (p0, z0, z1), + z0 = svminnm_x (p0, z0, z1)) + +/* +** minnm_f32_x_tied2: +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_x_tied2, svfloat32_t, + z0 = svminnm_f32_x (p0, z1, z0), + z0 = svminnm_x (p0, z1, z0)) + +/* +** minnm_f32_x_untied: +** ( +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f32_x_untied, svfloat32_t, + z0 = svminnm_f32_x (p0, z1, z2), + z0 = svminnm_x (p0, z1, z2)) + +/* +** minnm_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_x_tied1, svfloat32_t, float, + z0 = svminnm_n_f32_x (p0, z0, d4), + z0 = svminnm_x (p0, z0, d4)) + +/* +** minnm_s4_f32_x_untied: +** mov z0\.s, s4 +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (minnm_s4_f32_x_untied, svfloat32_t, float, + z0 = svminnm_n_f32_x (p0, z1, d4), + z0 = svminnm_x (p0, z1, d4)) + +/* +** minnm_0_f32_x_tied1: +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z0, 0), + z0 = svminnm_x (p0, z0, 0)) + +/* +** minnm_0_f32_x_untied: +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z1, 0), + z0 = svminnm_x (p0, z1, 0)) + +/* +** minnm_1_f32_x_tied1: +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z0, 1), + z0 = svminnm_x (p0, z0, 1)) + +/* +** minnm_1_f32_x_untied: +** movprfx z0, z1 +** fminnm z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z1, 1), + z0 = svminnm_x (p0, z1, 1)) + +/* +** minnm_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fminnm z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z0, 2), + z0 = svminnm_x (p0, z0, 2)) + +/* +** minnm_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fminnm z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (p0, z1, 2), + z0 = svminnm_x (p0, z1, 2)) + +/* +** ptrue_minnm_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f32_x_tied1, svfloat32_t, + z0 = svminnm_f32_x (svptrue_b32 (), z0, z1), + z0 = svminnm_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_minnm_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f32_x_tied2, svfloat32_t, + z0 = svminnm_f32_x (svptrue_b32 (), z1, z0), + z0 = svminnm_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_minnm_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f32_x_untied, svfloat32_t, + z0 = svminnm_f32_x (svptrue_b32 (), z1, z2), + z0 = svminnm_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_minnm_0_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z0, 0), + z0 = svminnm_x (svptrue_b32 (), z0, 0)) + +/* +** ptrue_minnm_0_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z1, 0), + z0 = svminnm_x (svptrue_b32 (), z1, 0)) + +/* +** ptrue_minnm_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svminnm_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_minnm_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svminnm_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_minnm_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f32_x_tied1, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svminnm_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_minnm_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f32_x_untied, svfloat32_t, + z0 = svminnm_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svminnm_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f64.c new file mode 100644 index 00000000000..67993928f61 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnm_f64.c @@ -0,0 +1,425 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnm_f64_m_tied1: +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_m_tied1, svfloat64_t, + z0 = svminnm_f64_m (p0, z0, z1), + z0 = svminnm_m (p0, z0, z1)) + +/* +** minnm_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_m_tied2, svfloat64_t, + z0 = svminnm_f64_m (p0, z1, z0), + z0 = svminnm_m (p0, z1, z0)) + +/* +** minnm_f64_m_untied: +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_m_untied, svfloat64_t, + z0 = svminnm_f64_m (p0, z1, z2), + z0 = svminnm_m (p0, z1, z2)) + +/* +** minnm_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_m_tied1, svfloat64_t, double, + z0 = svminnm_n_f64_m (p0, z0, d4), + z0 = svminnm_m (p0, z0, d4)) + +/* +** minnm_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_m_untied, svfloat64_t, double, + z0 = svminnm_n_f64_m (p0, z1, d4), + z0 = svminnm_m (p0, z1, d4)) + +/* +** minnm_0_f64_m_tied1: +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_m_tied1, svfloat64_t, + z0 = svminnm_n_f64_m (p0, z0, 0), + z0 = svminnm_m (p0, z0, 0)) + +/* +** minnm_0_f64_m_untied: +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_m_untied, svfloat64_t, + z0 = svminnm_n_f64_m (p0, z1, 0), + z0 = svminnm_m (p0, z1, 0)) + +/* +** minnm_1_f64_m_tied1: +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_m_tied1, svfloat64_t, + z0 = svminnm_n_f64_m (p0, z0, 1), + z0 = svminnm_m (p0, z0, 1)) + +/* +** minnm_1_f64_m_untied: +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_m_untied, svfloat64_t, + z0 = svminnm_n_f64_m (p0, z1, 1), + z0 = svminnm_m (p0, z1, 1)) + +/* +** minnm_2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f64_m, svfloat64_t, + z0 = svminnm_n_f64_m (p0, z0, 2), + z0 = svminnm_m (p0, z0, 2)) + +/* +** minnm_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_z_tied1, svfloat64_t, + z0 = svminnm_f64_z (p0, z0, z1), + z0 = svminnm_z (p0, z0, z1)) + +/* +** minnm_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_z_tied2, svfloat64_t, + z0 = svminnm_f64_z (p0, z1, z0), + z0 = svminnm_z (p0, z1, z0)) + +/* +** minnm_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fminnm z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_z_untied, svfloat64_t, + z0 = svminnm_f64_z (p0, z1, z2), + z0 = svminnm_z (p0, z1, z2)) + +/* +** minnm_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_z_tied1, svfloat64_t, double, + z0 = svminnm_n_f64_z (p0, z0, d4), + z0 = svminnm_z (p0, z0, d4)) + +/* +** minnm_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fminnm z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_z_untied, svfloat64_t, double, + z0 = svminnm_n_f64_z (p0, z1, d4), + z0 = svminnm_z (p0, z1, d4)) + +/* +** minnm_0_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_z_tied1, svfloat64_t, + z0 = svminnm_n_f64_z (p0, z0, 0), + z0 = svminnm_z (p0, z0, 0)) + +/* +** minnm_0_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_z_untied, svfloat64_t, + z0 = svminnm_n_f64_z (p0, z1, 0), + z0 = svminnm_z (p0, z1, 0)) + +/* +** minnm_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_z_tied1, svfloat64_t, + z0 = svminnm_n_f64_z (p0, z0, 1), + z0 = svminnm_z (p0, z0, 1)) + +/* +** minnm_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_z_untied, svfloat64_t, + z0 = svminnm_n_f64_z (p0, z1, 1), + z0 = svminnm_z (p0, z1, 1)) + +/* +** minnm_2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f64_z, svfloat64_t, + z0 = svminnm_n_f64_z (p0, z0, 2), + z0 = svminnm_z (p0, z0, 2)) + +/* +** minnm_f64_x_tied1: +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_x_tied1, svfloat64_t, + z0 = svminnm_f64_x (p0, z0, z1), + z0 = svminnm_x (p0, z0, z1)) + +/* +** minnm_f64_x_tied2: +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_x_tied2, svfloat64_t, + z0 = svminnm_f64_x (p0, z1, z0), + z0 = svminnm_x (p0, z1, z0)) + +/* +** minnm_f64_x_untied: +** ( +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (minnm_f64_x_untied, svfloat64_t, + z0 = svminnm_f64_x (p0, z1, z2), + z0 = svminnm_x (p0, z1, z2)) + +/* +** minnm_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_x_tied1, svfloat64_t, double, + z0 = svminnm_n_f64_x (p0, z0, d4), + z0 = svminnm_x (p0, z0, d4)) + +/* +** minnm_d4_f64_x_untied: +** mov z0\.d, d4 +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (minnm_d4_f64_x_untied, svfloat64_t, double, + z0 = svminnm_n_f64_x (p0, z1, d4), + z0 = svminnm_x (p0, z1, d4)) + +/* +** minnm_0_f64_x_tied1: +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z0, 0), + z0 = svminnm_x (p0, z0, 0)) + +/* +** minnm_0_f64_x_untied: +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, #0\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_0_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z1, 0), + z0 = svminnm_x (p0, z1, 0)) + +/* +** minnm_1_f64_x_tied1: +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z0, 1), + z0 = svminnm_x (p0, z0, 1)) + +/* +** minnm_1_f64_x_untied: +** movprfx z0, z1 +** fminnm z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (minnm_1_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z1, 1), + z0 = svminnm_x (p0, z1, 1)) + +/* +** minnm_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fminnm z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z0, 2), + z0 = svminnm_x (p0, z0, 2)) + +/* +** minnm_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fminnm z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (minnm_2_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (p0, z1, 2), + z0 = svminnm_x (p0, z1, 2)) + +/* +** ptrue_minnm_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f64_x_tied1, svfloat64_t, + z0 = svminnm_f64_x (svptrue_b64 (), z0, z1), + z0 = svminnm_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_minnm_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f64_x_tied2, svfloat64_t, + z0 = svminnm_f64_x (svptrue_b64 (), z1, z0), + z0 = svminnm_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_minnm_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_f64_x_untied, svfloat64_t, + z0 = svminnm_f64_x (svptrue_b64 (), z1, z2), + z0 = svminnm_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_minnm_0_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z0, 0), + z0 = svminnm_x (svptrue_b64 (), z0, 0)) + +/* +** ptrue_minnm_0_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_0_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z1, 0), + z0 = svminnm_x (svptrue_b64 (), z1, 0)) + +/* +** ptrue_minnm_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svminnm_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_minnm_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_1_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svminnm_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_minnm_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f64_x_tied1, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svminnm_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_minnm_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_minnm_2_f64_x_untied, svfloat64_t, + z0 = svminnm_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svminnm_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f16.c new file mode 100644 index 00000000000..827f41bfe18 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnmv_d0_f16_tied: +** fminnmv h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f16_tied, float16_t, svfloat16_t, + d0 = svminnmv_f16 (p0, z0), + d0 = svminnmv (p0, z0)) + +/* +** minnmv_d0_f16_untied: +** fminnmv h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f16_untied, float16_t, svfloat16_t, + d0 = svminnmv_f16 (p0, z1), + d0 = svminnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f32.c new file mode 100644 index 00000000000..2352ec2a3a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnmv_d0_f32_tied: +** fminnmv s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f32_tied, float32_t, svfloat32_t, + d0 = svminnmv_f32 (p0, z0), + d0 = svminnmv (p0, z0)) + +/* +** minnmv_d0_f32_untied: +** fminnmv s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f32_untied, float32_t, svfloat32_t, + d0 = svminnmv_f32 (p0, z1), + d0 = svminnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f64.c new file mode 100644 index 00000000000..3d769a3d5a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minnmv_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minnmv_d0_f64_tied: +** fminnmv d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f64_tied, float64_t, svfloat64_t, + d0 = svminnmv_f64 (p0, z0), + d0 = svminnmv (p0, z0)) + +/* +** minnmv_d0_f64_untied: +** fminnmv d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (minnmv_d0_f64_untied, float64_t, svfloat64_t, + d0 = svminnmv_f64 (p0, z1), + d0 = svminnmv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f16.c new file mode 100644 index 00000000000..190aa16e141 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_d0_f16_tied: +** fminv h0, p0, z0\.h +** ret +*/ +TEST_REDUCTION_D (minv_d0_f16_tied, float16_t, svfloat16_t, + d0 = svminv_f16 (p0, z0), + d0 = svminv (p0, z0)) + +/* +** minv_d0_f16_untied: +** fminv h0, p0, z1\.h +** ret +*/ +TEST_REDUCTION_D (minv_d0_f16_untied, float16_t, svfloat16_t, + d0 = svminv_f16 (p0, z1), + d0 = svminv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f32.c new file mode 100644 index 00000000000..07871b893a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_d0_f32_tied: +** fminv s0, p0, z0\.s +** ret +*/ +TEST_REDUCTION_D (minv_d0_f32_tied, float32_t, svfloat32_t, + d0 = svminv_f32 (p0, z0), + d0 = svminv (p0, z0)) + +/* +** minv_d0_f32_untied: +** fminv s0, p0, z1\.s +** ret +*/ +TEST_REDUCTION_D (minv_d0_f32_untied, float32_t, svfloat32_t, + d0 = svminv_f32 (p0, z1), + d0 = svminv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f64.c new file mode 100644 index 00000000000..7435f306fb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_d0_f64_tied: +** fminv d0, p0, z0\.d +** ret +*/ +TEST_REDUCTION_D (minv_d0_f64_tied, float64_t, svfloat64_t, + d0 = svminv_f64 (p0, z0), + d0 = svminv (p0, z0)) + +/* +** minv_d0_f64_untied: +** fminv d0, p0, z1\.d +** ret +*/ +TEST_REDUCTION_D (minv_d0_f64_untied, float64_t, svfloat64_t, + d0 = svminv_f64 (p0, z1), + d0 = svminv (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s16.c new file mode 100644 index 00000000000..dfb66a9f7ea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_s16: +** sminv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (minv_x0_s16, int16_t, svint16_t, + x0 = svminv_s16 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s32.c new file mode 100644 index 00000000000..c02df5dd3a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_s32: +** sminv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (minv_x0_s32, int32_t, svint32_t, + x0 = svminv_s32 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s64.c new file mode 100644 index 00000000000..784973231ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_s64: +** sminv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (minv_x0_s64, int64_t, svint64_t, + x0 = svminv_s64 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s8.c new file mode 100644 index 00000000000..0b1bce5de31 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_s8: +** sminv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (minv_x0_s8, int8_t, svint8_t, + x0 = svminv_s8 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u16.c new file mode 100644 index 00000000000..b499de33ed1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_u16: +** uminv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (minv_x0_u16, uint16_t, svuint16_t, + x0 = svminv_u16 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u32.c new file mode 100644 index 00000000000..18c9d8c6d97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_u32: +** uminv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (minv_x0_u32, uint32_t, svuint32_t, + x0 = svminv_u32 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u64.c new file mode 100644 index 00000000000..374d5e42689 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_u64: +** uminv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (minv_x0_u64, uint64_t, svuint64_t, + x0 = svminv_u64 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u8.c new file mode 100644 index 00000000000..d9f6f583593 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/minv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** minv_x0_u8: +** uminv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (minv_x0_u8, uint8_t, svuint8_t, + x0 = svminv_u8 (p0, z0), + x0 = svminv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f16.c new file mode 100644 index 00000000000..f22a582efa6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_f16_m_tied1: +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_m_tied1, svfloat16_t, + z0 = svmla_f16_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_m_tied2, svfloat16_t, + z0 = svmla_f16_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_m_tied3, svfloat16_t, + z0 = svmla_f16_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_f16_m_untied: +** movprfx z0, z1 +** fmla z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_m_untied, svfloat16_t, + z0 = svmla_f16_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmla_n_f16_m (p0, z0, z1, d4), + z0 = svmla_m (p0, z0, z1, d4)) + +/* +** mla_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmla_n_f16_m (p0, z1, z2, d4), + z0 = svmla_m (p0, z1, z2, d4)) + +/* +** mla_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_m_tied1, svfloat16_t, + z0 = svmla_n_f16_m (p0, z0, z1, 2), + z0 = svmla_m (p0, z0, z1, 2)) + +/* +** mla_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_m_untied, svfloat16_t, + z0 = svmla_n_f16_m (p0, z1, z2, 2), + z0 = svmla_m (p0, z1, z2, 2)) + +/* +** mla_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_z_tied1, svfloat16_t, + z0 = svmla_f16_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_z_tied2, svfloat16_t, + z0 = svmla_f16_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_z_tied3, svfloat16_t, + z0 = svmla_f16_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f16_z_untied, svfloat16_t, + z0 = svmla_f16_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmla_n_f16_z (p0, z0, z1, d4), + z0 = svmla_z (p0, z0, z1, d4)) + +/* +** mla_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svmla_n_f16_z (p0, z1, z0, d4), + z0 = svmla_z (p0, z1, z0, d4)) + +/* +** mla_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmla_n_f16_z (p0, z1, z2, d4), + z0 = svmla_z (p0, z1, z2, d4)) + +/* +** mla_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_z_tied1, svfloat16_t, + z0 = svmla_n_f16_z (p0, z0, z1, 2), + z0 = svmla_z (p0, z0, z1, 2)) + +/* +** mla_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_z_tied2, svfloat16_t, + z0 = svmla_n_f16_z (p0, z1, z0, 2), + z0 = svmla_z (p0, z1, z0, 2)) + +/* +** mla_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_z_untied, svfloat16_t, + z0 = svmla_n_f16_z (p0, z1, z2, 2), + z0 = svmla_z (p0, z1, z2, 2)) + +/* +** mla_f16_x_tied1: +** fmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_x_tied1, svfloat16_t, + z0 = svmla_f16_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_f16_x_tied2: +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_x_tied2, svfloat16_t, + z0 = svmla_f16_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_f16_x_tied3: +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_f16_x_tied3, svfloat16_t, + z0 = svmla_f16_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_f16_x_untied: +** ( +** movprfx z0, z1 +** fmla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fmad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f16_x_untied, svfloat16_t, + z0 = svmla_f16_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmla_n_f16_x (p0, z0, z1, d4), + z0 = svmla_x (p0, z0, z1, d4)) + +/* +** mla_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svmla_n_f16_x (p0, z1, z0, d4), + z0 = svmla_x (p0, z1, z0, d4)) + +/* +** mla_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mla_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmla_n_f16_x (p0, z1, z2, d4), + z0 = svmla_x (p0, z1, z2, d4)) + +/* +** mla_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_x_tied1, svfloat16_t, + z0 = svmla_n_f16_x (p0, z0, z1, 2), + z0 = svmla_x (p0, z0, z1, 2)) + +/* +** mla_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_x_tied2, svfloat16_t, + z0 = svmla_n_f16_x (p0, z1, z0, 2), + z0 = svmla_x (p0, z1, z0, 2)) + +/* +** mla_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_2_f16_x_untied, svfloat16_t, + z0 = svmla_n_f16_x (p0, z1, z2, 2), + z0 = svmla_x (p0, z1, z2, 2)) + +/* +** ptrue_mla_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f16_x_tied1, svfloat16_t, + z0 = svmla_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svmla_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_mla_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f16_x_tied2, svfloat16_t, + z0 = svmla_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svmla_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_mla_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f16_x_tied3, svfloat16_t, + z0 = svmla_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svmla_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_mla_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f16_x_untied, svfloat16_t, + z0 = svmla_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svmla_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_mla_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f16_x_tied1, svfloat16_t, + z0 = svmla_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svmla_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_mla_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f16_x_tied2, svfloat16_t, + z0 = svmla_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svmla_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_mla_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f16_x_untied, svfloat16_t, + z0 = svmla_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svmla_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f32.c new file mode 100644 index 00000000000..1d95eb0a724 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_f32_m_tied1: +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_m_tied1, svfloat32_t, + z0 = svmla_f32_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_m_tied2, svfloat32_t, + z0 = svmla_f32_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_m_tied3, svfloat32_t, + z0 = svmla_f32_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_f32_m_untied: +** movprfx z0, z1 +** fmla z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_m_untied, svfloat32_t, + z0 = svmla_f32_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmla_n_f32_m (p0, z0, z1, d4), + z0 = svmla_m (p0, z0, z1, d4)) + +/* +** mla_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_m_untied, svfloat32_t, float, + z0 = svmla_n_f32_m (p0, z1, z2, d4), + z0 = svmla_m (p0, z1, z2, d4)) + +/* +** mla_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_m_tied1, svfloat32_t, + z0 = svmla_n_f32_m (p0, z0, z1, 2), + z0 = svmla_m (p0, z0, z1, 2)) + +/* +** mla_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_m_untied, svfloat32_t, + z0 = svmla_n_f32_m (p0, z1, z2, 2), + z0 = svmla_m (p0, z1, z2, 2)) + +/* +** mla_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_z_tied1, svfloat32_t, + z0 = svmla_f32_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_z_tied2, svfloat32_t, + z0 = svmla_f32_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_z_tied3, svfloat32_t, + z0 = svmla_f32_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f32_z_untied, svfloat32_t, + z0 = svmla_f32_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmla_n_f32_z (p0, z0, z1, d4), + z0 = svmla_z (p0, z0, z1, d4)) + +/* +** mla_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_z_tied2, svfloat32_t, float, + z0 = svmla_n_f32_z (p0, z1, z0, d4), + z0 = svmla_z (p0, z1, z0, d4)) + +/* +** mla_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_z_untied, svfloat32_t, float, + z0 = svmla_n_f32_z (p0, z1, z2, d4), + z0 = svmla_z (p0, z1, z2, d4)) + +/* +** mla_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_z_tied1, svfloat32_t, + z0 = svmla_n_f32_z (p0, z0, z1, 2), + z0 = svmla_z (p0, z0, z1, 2)) + +/* +** mla_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_z_tied2, svfloat32_t, + z0 = svmla_n_f32_z (p0, z1, z0, 2), + z0 = svmla_z (p0, z1, z0, 2)) + +/* +** mla_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_z_untied, svfloat32_t, + z0 = svmla_n_f32_z (p0, z1, z2, 2), + z0 = svmla_z (p0, z1, z2, 2)) + +/* +** mla_f32_x_tied1: +** fmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_x_tied1, svfloat32_t, + z0 = svmla_f32_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_f32_x_tied2: +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_x_tied2, svfloat32_t, + z0 = svmla_f32_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_f32_x_tied3: +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_f32_x_tied3, svfloat32_t, + z0 = svmla_f32_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_f32_x_untied: +** ( +** movprfx z0, z1 +** fmla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fmad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f32_x_untied, svfloat32_t, + z0 = svmla_f32_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmla_n_f32_x (p0, z0, z1, d4), + z0 = svmla_x (p0, z0, z1, d4)) + +/* +** mla_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_x_tied2, svfloat32_t, float, + z0 = svmla_n_f32_x (p0, z1, z0, d4), + z0 = svmla_x (p0, z1, z0, d4)) + +/* +** mla_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mla_s4_f32_x_untied, svfloat32_t, float, + z0 = svmla_n_f32_x (p0, z1, z2, d4), + z0 = svmla_x (p0, z1, z2, d4)) + +/* +** mla_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_x_tied1, svfloat32_t, + z0 = svmla_n_f32_x (p0, z0, z1, 2), + z0 = svmla_x (p0, z0, z1, 2)) + +/* +** mla_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_x_tied2, svfloat32_t, + z0 = svmla_n_f32_x (p0, z1, z0, 2), + z0 = svmla_x (p0, z1, z0, 2)) + +/* +** mla_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_2_f32_x_untied, svfloat32_t, + z0 = svmla_n_f32_x (p0, z1, z2, 2), + z0 = svmla_x (p0, z1, z2, 2)) + +/* +** ptrue_mla_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f32_x_tied1, svfloat32_t, + z0 = svmla_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svmla_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_mla_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f32_x_tied2, svfloat32_t, + z0 = svmla_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svmla_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_mla_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f32_x_tied3, svfloat32_t, + z0 = svmla_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svmla_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_mla_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f32_x_untied, svfloat32_t, + z0 = svmla_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svmla_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_mla_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f32_x_tied1, svfloat32_t, + z0 = svmla_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svmla_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_mla_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f32_x_tied2, svfloat32_t, + z0 = svmla_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svmla_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_mla_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f32_x_untied, svfloat32_t, + z0 = svmla_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svmla_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f64.c new file mode 100644 index 00000000000..74fd2926710 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_f64_m_tied1: +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_m_tied1, svfloat64_t, + z0 = svmla_f64_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmla z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_m_tied2, svfloat64_t, + z0 = svmla_f64_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_f64_m_tied3, svfloat64_t, + z0 = svmla_f64_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_f64_m_untied: +** movprfx z0, z1 +** fmla z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_m_untied, svfloat64_t, + z0 = svmla_f64_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmla_n_f64_m (p0, z0, z1, d4), + z0 = svmla_m (p0, z0, z1, d4)) + +/* +** mla_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_m_untied, svfloat64_t, double, + z0 = svmla_n_f64_m (p0, z1, z2, d4), + z0 = svmla_m (p0, z1, z2, d4)) + +/* +** mla_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_m_tied1, svfloat64_t, + z0 = svmla_n_f64_m (p0, z0, z1, 2), + z0 = svmla_m (p0, z0, z1, 2)) + +/* +** mla_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_m_untied, svfloat64_t, + z0 = svmla_n_f64_m (p0, z1, z2, 2), + z0 = svmla_m (p0, z1, z2, 2)) + +/* +** mla_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_z_tied1, svfloat64_t, + z0 = svmla_f64_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_z_tied2, svfloat64_t, + z0 = svmla_f64_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_z_tied3, svfloat64_t, + z0 = svmla_f64_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f64_z_untied, svfloat64_t, + z0 = svmla_f64_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmla_n_f64_z (p0, z0, z1, d4), + z0 = svmla_z (p0, z0, z1, d4)) + +/* +** mla_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_z_tied2, svfloat64_t, double, + z0 = svmla_n_f64_z (p0, z1, z0, d4), + z0 = svmla_z (p0, z1, z0, d4)) + +/* +** mla_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_z_untied, svfloat64_t, double, + z0 = svmla_n_f64_z (p0, z1, z2, d4), + z0 = svmla_z (p0, z1, z2, d4)) + +/* +** mla_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_z_tied1, svfloat64_t, + z0 = svmla_n_f64_z (p0, z0, z1, 2), + z0 = svmla_z (p0, z0, z1, 2)) + +/* +** mla_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_z_tied2, svfloat64_t, + z0 = svmla_n_f64_z (p0, z1, z0, 2), + z0 = svmla_z (p0, z1, z0, 2)) + +/* +** mla_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_z_untied, svfloat64_t, + z0 = svmla_n_f64_z (p0, z1, z2, 2), + z0 = svmla_z (p0, z1, z2, 2)) + +/* +** mla_f64_x_tied1: +** fmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_x_tied1, svfloat64_t, + z0 = svmla_f64_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_f64_x_tied2: +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_x_tied2, svfloat64_t, + z0 = svmla_f64_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_f64_x_tied3: +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_f64_x_tied3, svfloat64_t, + z0 = svmla_f64_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_f64_x_untied: +** ( +** movprfx z0, z1 +** fmla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fmad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_f64_x_untied, svfloat64_t, + z0 = svmla_f64_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmla_n_f64_x (p0, z0, z1, d4), + z0 = svmla_x (p0, z0, z1, d4)) + +/* +** mla_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_x_tied2, svfloat64_t, double, + z0 = svmla_n_f64_x (p0, z1, z0, d4), + z0 = svmla_x (p0, z1, z0, d4)) + +/* +** mla_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mla_d4_f64_x_untied, svfloat64_t, double, + z0 = svmla_n_f64_x (p0, z1, z2, d4), + z0 = svmla_x (p0, z1, z2, d4)) + +/* +** mla_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_x_tied1, svfloat64_t, + z0 = svmla_n_f64_x (p0, z0, z1, 2), + z0 = svmla_x (p0, z0, z1, 2)) + +/* +** mla_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_x_tied2, svfloat64_t, + z0 = svmla_n_f64_x (p0, z1, z0, 2), + z0 = svmla_x (p0, z1, z0, 2)) + +/* +** mla_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_2_f64_x_untied, svfloat64_t, + z0 = svmla_n_f64_x (p0, z1, z2, 2), + z0 = svmla_x (p0, z1, z2, 2)) + +/* +** ptrue_mla_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f64_x_tied1, svfloat64_t, + z0 = svmla_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svmla_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_mla_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f64_x_tied2, svfloat64_t, + z0 = svmla_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svmla_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_mla_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f64_x_tied3, svfloat64_t, + z0 = svmla_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svmla_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_mla_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_f64_x_untied, svfloat64_t, + z0 = svmla_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svmla_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_mla_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f64_x_tied1, svfloat64_t, + z0 = svmla_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svmla_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_mla_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f64_x_tied2, svfloat64_t, + z0 = svmla_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svmla_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_mla_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mla_2_f64_x_untied, svfloat64_t, + z0 = svmla_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svmla_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f16.c new file mode 100644 index 00000000000..949e3bb4773 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f16.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_lane_0_f16_tied1: +** fmla z0\.h, z1\.h, z2\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f16_tied1, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 0), + z0 = svmla_lane (z0, z1, z2, 0)) + +/* +** mla_lane_0_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.h, \1\.h, z2\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f16_tied2, svfloat16_t, + z0 = svmla_lane_f16 (z1, z0, z2, 0), + z0 = svmla_lane (z1, z0, z2, 0)) + +/* +** mla_lane_0_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.h, z2\.h, \1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f16_tied3, svfloat16_t, + z0 = svmla_lane_f16 (z1, z2, z0, 0), + z0 = svmla_lane (z1, z2, z0, 0)) + +/* +** mla_lane_0_f16_untied: +** movprfx z0, z1 +** fmla z0\.h, z2\.h, z3\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f16_untied, svfloat16_t, + z0 = svmla_lane_f16 (z1, z2, z3, 0), + z0 = svmla_lane (z1, z2, z3, 0)) + +/* +** mla_lane_1_f16: +** fmla z0\.h, z1\.h, z2\.h\[1\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_1_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 1), + z0 = svmla_lane (z0, z1, z2, 1)) + +/* +** mla_lane_2_f16: +** fmla z0\.h, z1\.h, z2\.h\[2\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_2_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 2), + z0 = svmla_lane (z0, z1, z2, 2)) + +/* +** mla_lane_3_f16: +** fmla z0\.h, z1\.h, z2\.h\[3\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_3_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 3), + z0 = svmla_lane (z0, z1, z2, 3)) + +/* +** mla_lane_4_f16: +** fmla z0\.h, z1\.h, z2\.h\[4\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_4_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 4), + z0 = svmla_lane (z0, z1, z2, 4)) + +/* +** mla_lane_5_f16: +** fmla z0\.h, z1\.h, z2\.h\[5\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_5_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 5), + z0 = svmla_lane (z0, z1, z2, 5)) + +/* +** mla_lane_6_f16: +** fmla z0\.h, z1\.h, z2\.h\[6\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_6_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 6), + z0 = svmla_lane (z0, z1, z2, 6)) + +/* +** mla_lane_7_f16: +** fmla z0\.h, z1\.h, z2\.h\[7\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_7_f16, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z2, 7), + z0 = svmla_lane (z0, z1, z2, 7)) + +/* +** mla_lane_z7_f16: +** fmla z0\.h, z1\.h, z7\.h\[7\] +** ret +*/ +TEST_DUAL_Z (mla_lane_z7_f16, svfloat16_t, svfloat16_t, + z0 = svmla_lane_f16 (z0, z1, z7, 7), + z0 = svmla_lane (z0, z1, z7, 7)) + +/* +** mla_lane_z8_f16: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmla z0\.h, z1\.h, \1\.h\[7\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mla_lane_z8_f16, svfloat16_t, svfloat16_t, z8, + z0 = svmla_lane_f16 (z0, z1, z8, 7), + z0 = svmla_lane (z0, z1, z8, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f32.c new file mode 100644 index 00000000000..d376532d6dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f32.c @@ -0,0 +1,92 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_lane_0_f32_tied1: +** fmla z0\.s, z1\.s, z2\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f32_tied1, svfloat32_t, + z0 = svmla_lane_f32 (z0, z1, z2, 0), + z0 = svmla_lane (z0, z1, z2, 0)) + +/* +** mla_lane_0_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.s, \1\.s, z2\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f32_tied2, svfloat32_t, + z0 = svmla_lane_f32 (z1, z0, z2, 0), + z0 = svmla_lane (z1, z0, z2, 0)) + +/* +** mla_lane_0_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmla z0\.s, z2\.s, \1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f32_tied3, svfloat32_t, + z0 = svmla_lane_f32 (z1, z2, z0, 0), + z0 = svmla_lane (z1, z2, z0, 0)) + +/* +** mla_lane_0_f32_untied: +** movprfx z0, z1 +** fmla z0\.s, z2\.s, z3\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f32_untied, svfloat32_t, + z0 = svmla_lane_f32 (z1, z2, z3, 0), + z0 = svmla_lane (z1, z2, z3, 0)) + +/* +** mla_lane_1_f32: +** fmla z0\.s, z1\.s, z2\.s\[1\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_1_f32, svfloat32_t, + z0 = svmla_lane_f32 (z0, z1, z2, 1), + z0 = svmla_lane (z0, z1, z2, 1)) + +/* +** mla_lane_2_f32: +** fmla z0\.s, z1\.s, z2\.s\[2\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_2_f32, svfloat32_t, + z0 = svmla_lane_f32 (z0, z1, z2, 2), + z0 = svmla_lane (z0, z1, z2, 2)) + +/* +** mla_lane_3_f32: +** fmla z0\.s, z1\.s, z2\.s\[3\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_3_f32, svfloat32_t, + z0 = svmla_lane_f32 (z0, z1, z2, 3), + z0 = svmla_lane (z0, z1, z2, 3)) + +/* +** mla_lane_z7_f32: +** fmla z0\.s, z1\.s, z7\.s\[3\] +** ret +*/ +TEST_DUAL_Z (mla_lane_z7_f32, svfloat32_t, svfloat32_t, + z0 = svmla_lane_f32 (z0, z1, z7, 3), + z0 = svmla_lane (z0, z1, z7, 3)) + +/* +** mla_lane_z8_f32: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmla z0\.s, z1\.s, \1\.s\[3\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mla_lane_z8_f32, svfloat32_t, svfloat32_t, z8, + z0 = svmla_lane_f32 (z0, z1, z8, 3), + z0 = svmla_lane (z0, z1, z8, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f64.c new file mode 100644 index 00000000000..7c58a8a57e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_lane_f64.c @@ -0,0 +1,83 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_lane_0_f64_tied1: +** fmla z0\.d, z1\.d, z2\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f64_tied1, svfloat64_t, + z0 = svmla_lane_f64 (z0, z1, z2, 0), + z0 = svmla_lane (z0, z1, z2, 0)) + +/* +** mla_lane_0_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmla z0\.d, \1, z2\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f64_tied2, svfloat64_t, + z0 = svmla_lane_f64 (z1, z0, z2, 0), + z0 = svmla_lane (z1, z0, z2, 0)) + +/* +** mla_lane_0_f64_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmla z0\.d, z2\.d, \1\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f64_tied3, svfloat64_t, + z0 = svmla_lane_f64 (z1, z2, z0, 0), + z0 = svmla_lane (z1, z2, z0, 0)) + +/* +** mla_lane_0_f64_untied: +** movprfx z0, z1 +** fmla z0\.d, z2\.d, z3\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_0_f64_untied, svfloat64_t, + z0 = svmla_lane_f64 (z1, z2, z3, 0), + z0 = svmla_lane (z1, z2, z3, 0)) + +/* +** mla_lane_1_f64: +** fmla z0\.d, z1\.d, z2\.d\[1\] +** ret +*/ +TEST_UNIFORM_Z (mla_lane_1_f64, svfloat64_t, + z0 = svmla_lane_f64 (z0, z1, z2, 1), + z0 = svmla_lane (z0, z1, z2, 1)) + +/* +** mla_lane_z7_f64: +** fmla z0\.d, z1\.d, z7\.d\[1\] +** ret +*/ +TEST_DUAL_Z (mla_lane_z7_f64, svfloat64_t, svfloat64_t, + z0 = svmla_lane_f64 (z0, z1, z7, 1), + z0 = svmla_lane (z0, z1, z7, 1)) + +/* +** mla_lane_z15_f64: +** str d15, \[sp, -16\]! +** fmla z0\.d, z1\.d, z15\.d\[1\] +** ldr d15, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mla_lane_z15_f64, svfloat64_t, svfloat64_t, z15, + z0 = svmla_lane_f64 (z0, z1, z15, 1), + z0 = svmla_lane (z0, z1, z15, 1)) + +/* +** mla_lane_z16_f64: +** mov (z[0-9]|z1[0-5])\.d, z16\.d +** fmla z0\.d, z1\.d, \1\.d\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (mla_lane_z16_f64, svfloat64_t, svfloat64_t, z16, + z0 = svmla_lane_f64 (z0, z1, z16, 1), + z0 = svmla_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c new file mode 100644 index 00000000000..f3ed191db6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_s16_m_tied1: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_m_tied1, svint16_t, + z0 = svmla_s16_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_m_tied2, svint16_t, + z0 = svmla_s16_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_s16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_m_tied3, svint16_t, + z0 = svmla_s16_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_s16_m_untied: +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_m_untied, svint16_t, + z0 = svmla_s16_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmla_n_s16_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmla_n_s16_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_s16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_m_tied1, svint16_t, + z0 = svmla_n_s16_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_m_untied, svint16_t, + z0 = svmla_n_s16_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_z_tied1, svint16_t, + z0 = svmla_s16_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_z_tied2, svint16_t, + z0 = svmla_s16_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_s16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_z_tied3, svint16_t, + z0 = svmla_s16_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s16_z_untied, svint16_t, + z0 = svmla_s16_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmla_n_s16_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_s16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_z_tied2, svint16_t, int16_t, + z0 = svmla_n_s16_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmla_n_s16_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_s16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_z_tied1, svint16_t, + z0 = svmla_n_s16_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_s16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_z_tied2, svint16_t, + z0 = svmla_n_s16_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_s16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_z_untied, svint16_t, + z0 = svmla_n_s16_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_s16_x_tied1: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_x_tied1, svint16_t, + z0 = svmla_s16_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_s16_x_tied2: +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_x_tied2, svint16_t, + z0 = svmla_s16_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_s16_x_tied3: +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_s16_x_tied3, svint16_t, + z0 = svmla_s16_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_s16_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** mad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s16_x_untied, svint16_t, + z0 = svmla_s16_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmla_n_s16_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_s16_x_tied2: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_x_tied2, svint16_t, int16_t, + z0 = svmla_n_s16_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_s16_x_untied: +** mov z0\.h, w0 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmla_n_s16_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_x_tied1, svint16_t, + z0 = svmla_n_s16_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_s16_x_tied2: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_x_tied2, svint16_t, + z0 = svmla_n_s16_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_s16_x_untied: +** mov z0\.h, #11 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_s16_x_untied, svint16_t, + z0 = svmla_n_s16_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s32.c new file mode 100644 index 00000000000..5e8001a71d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_s32_m_tied1: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_m_tied1, svint32_t, + z0 = svmla_s32_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_m_tied2, svint32_t, + z0 = svmla_s32_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_s32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_m_tied3, svint32_t, + z0 = svmla_s32_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_s32_m_untied: +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_m_untied, svint32_t, + z0 = svmla_s32_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmla_n_s32_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmla_n_s32_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_s32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_m_tied1, svint32_t, + z0 = svmla_n_s32_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_m_untied, svint32_t, + z0 = svmla_n_s32_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_z_tied1, svint32_t, + z0 = svmla_s32_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_z_tied2, svint32_t, + z0 = svmla_s32_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_s32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_z_tied3, svint32_t, + z0 = svmla_s32_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s32_z_untied, svint32_t, + z0 = svmla_s32_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmla_n_s32_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_s32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_z_tied2, svint32_t, int32_t, + z0 = svmla_n_s32_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmla_n_s32_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_s32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_z_tied1, svint32_t, + z0 = svmla_n_s32_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_s32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_z_tied2, svint32_t, + z0 = svmla_n_s32_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_s32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_z_untied, svint32_t, + z0 = svmla_n_s32_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_s32_x_tied1: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_x_tied1, svint32_t, + z0 = svmla_s32_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_s32_x_tied2: +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_x_tied2, svint32_t, + z0 = svmla_s32_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_s32_x_tied3: +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_s32_x_tied3, svint32_t, + z0 = svmla_s32_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_s32_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** mad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s32_x_untied, svint32_t, + z0 = svmla_s32_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmla_n_s32_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_s32_x_tied2: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_x_tied2, svint32_t, int32_t, + z0 = svmla_n_s32_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_s32_x_untied: +** mov z0\.s, w0 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmla_n_s32_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_x_tied1, svint32_t, + z0 = svmla_n_s32_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_s32_x_tied2: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_x_tied2, svint32_t, + z0 = svmla_n_s32_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_s32_x_untied: +** mov z0\.s, #11 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_s32_x_untied, svint32_t, + z0 = svmla_n_s32_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s64.c new file mode 100644 index 00000000000..7b619e52119 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_s64_m_tied1: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_m_tied1, svint64_t, + z0 = svmla_s64_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mla z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_m_tied2, svint64_t, + z0 = svmla_s64_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_s64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_s64_m_tied3, svint64_t, + z0 = svmla_s64_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_s64_m_untied: +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_m_untied, svint64_t, + z0 = svmla_s64_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmla_n_s64_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmla_n_s64_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_s64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_m_tied1, svint64_t, + z0 = svmla_n_s64_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_m_untied, svint64_t, + z0 = svmla_n_s64_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_z_tied1, svint64_t, + z0 = svmla_s64_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_z_tied2, svint64_t, + z0 = svmla_s64_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_s64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_z_tied3, svint64_t, + z0 = svmla_s64_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s64_z_untied, svint64_t, + z0 = svmla_s64_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmla_n_s64_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_x0_s64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_z_tied2, svint64_t, int64_t, + z0 = svmla_n_s64_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmla_n_s64_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_s64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_z_tied1, svint64_t, + z0 = svmla_n_s64_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_s64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_z_tied2, svint64_t, + z0 = svmla_n_s64_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_s64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_z_untied, svint64_t, + z0 = svmla_n_s64_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_s64_x_tied1: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_x_tied1, svint64_t, + z0 = svmla_s64_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_s64_x_tied2: +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_x_tied2, svint64_t, + z0 = svmla_s64_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_s64_x_tied3: +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_s64_x_tied3, svint64_t, + z0 = svmla_s64_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_s64_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** mad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s64_x_untied, svint64_t, + z0 = svmla_s64_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmla_n_s64_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_x0_s64_x_tied2: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_x_tied2, svint64_t, int64_t, + z0 = svmla_n_s64_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_x0_s64_x_untied: +** mov z0\.d, x0 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmla_n_s64_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_x_tied1, svint64_t, + z0 = svmla_n_s64_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_s64_x_tied2: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_x_tied2, svint64_t, + z0 = svmla_n_s64_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_s64_x_untied: +** mov z0\.d, #11 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_s64_x_untied, svint64_t, + z0 = svmla_n_s64_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c new file mode 100644 index 00000000000..47468947d78 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_s8_m_tied1: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_m_tied1, svint8_t, + z0 = svmla_s8_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_m_tied2, svint8_t, + z0 = svmla_s8_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_s8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_m_tied3, svint8_t, + z0 = svmla_s8_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_s8_m_untied: +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_m_untied, svint8_t, + z0 = svmla_s8_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmla_n_s8_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmla_n_s8_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_s8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_m_tied1, svint8_t, + z0 = svmla_n_s8_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_m_untied, svint8_t, + z0 = svmla_n_s8_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_z_tied1, svint8_t, + z0 = svmla_s8_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_z_tied2, svint8_t, + z0 = svmla_s8_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_s8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_z_tied3, svint8_t, + z0 = svmla_s8_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s8_z_untied, svint8_t, + z0 = svmla_s8_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmla_n_s8_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_s8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_z_tied2, svint8_t, int8_t, + z0 = svmla_n_s8_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmla_n_s8_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_s8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_z_tied1, svint8_t, + z0 = svmla_n_s8_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_s8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_z_tied2, svint8_t, + z0 = svmla_n_s8_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_s8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_z_untied, svint8_t, + z0 = svmla_n_s8_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_s8_x_tied1: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_x_tied1, svint8_t, + z0 = svmla_s8_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_s8_x_tied2: +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_x_tied2, svint8_t, + z0 = svmla_s8_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_s8_x_tied3: +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_s8_x_tied3, svint8_t, + z0 = svmla_s8_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_s8_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** mad z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0, z3 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_s8_x_untied, svint8_t, + z0 = svmla_s8_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmla_n_s8_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_s8_x_tied2: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_x_tied2, svint8_t, int8_t, + z0 = svmla_n_s8_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_s8_x_untied: +** mov z0\.b, w0 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmla_n_s8_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_x_tied1, svint8_t, + z0 = svmla_n_s8_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_s8_x_tied2: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_x_tied2, svint8_t, + z0 = svmla_n_s8_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_s8_x_untied: +** mov z0\.b, #11 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_s8_x_untied, svint8_t, + z0 = svmla_n_s8_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c new file mode 100644 index 00000000000..7238e428f68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_u16_m_tied1: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_m_tied1, svuint16_t, + z0 = svmla_u16_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_m_tied2, svuint16_t, + z0 = svmla_u16_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_u16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_m_tied3, svuint16_t, + z0 = svmla_u16_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_u16_m_untied: +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_m_untied, svuint16_t, + z0 = svmla_u16_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmla_n_u16_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmla_n_u16_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_u16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_m_tied1, svuint16_t, + z0 = svmla_n_u16_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_m_untied, svuint16_t, + z0 = svmla_n_u16_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_z_tied1, svuint16_t, + z0 = svmla_u16_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_z_tied2, svuint16_t, + z0 = svmla_u16_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_u16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_z_tied3, svuint16_t, + z0 = svmla_u16_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u16_z_untied, svuint16_t, + z0 = svmla_u16_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmla_n_u16_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_u16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_z_tied2, svuint16_t, uint16_t, + z0 = svmla_n_u16_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmla_n_u16_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_u16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_z_tied1, svuint16_t, + z0 = svmla_n_u16_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_u16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_z_tied2, svuint16_t, + z0 = svmla_n_u16_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_u16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** mad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_z_untied, svuint16_t, + z0 = svmla_n_u16_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_u16_x_tied1: +** mla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_x_tied1, svuint16_t, + z0 = svmla_u16_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_u16_x_tied2: +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_x_tied2, svuint16_t, + z0 = svmla_u16_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_u16_x_tied3: +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_u16_x_tied3, svuint16_t, + z0 = svmla_u16_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_u16_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** mad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u16_x_untied, svuint16_t, + z0 = svmla_u16_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmla_n_u16_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_u16_x_tied2: +** mov (z[0-9]+\.h), w0 +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_x_tied2, svuint16_t, uint16_t, + z0 = svmla_n_u16_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_u16_x_untied: +** mov z0\.h, w0 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmla_n_u16_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_x_tied1, svuint16_t, + z0 = svmla_n_u16_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_u16_x_tied2: +** mov (z[0-9]+\.h), #11 +** mad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_x_tied2, svuint16_t, + z0 = svmla_n_u16_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_u16_x_untied: +** mov z0\.h, #11 +** mad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mla_11_u16_x_untied, svuint16_t, + z0 = svmla_n_u16_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u32.c new file mode 100644 index 00000000000..7a68bce3d1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_u32_m_tied1: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_m_tied1, svuint32_t, + z0 = svmla_u32_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_m_tied2, svuint32_t, + z0 = svmla_u32_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_u32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_m_tied3, svuint32_t, + z0 = svmla_u32_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_u32_m_untied: +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_m_untied, svuint32_t, + z0 = svmla_u32_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmla_n_u32_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmla_n_u32_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_u32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_m_tied1, svuint32_t, + z0 = svmla_n_u32_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_m_untied, svuint32_t, + z0 = svmla_n_u32_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_z_tied1, svuint32_t, + z0 = svmla_u32_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_z_tied2, svuint32_t, + z0 = svmla_u32_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_u32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_z_tied3, svuint32_t, + z0 = svmla_u32_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u32_z_untied, svuint32_t, + z0 = svmla_u32_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmla_n_u32_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_u32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_z_tied2, svuint32_t, uint32_t, + z0 = svmla_n_u32_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmla_n_u32_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_u32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_z_tied1, svuint32_t, + z0 = svmla_n_u32_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_u32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_z_tied2, svuint32_t, + z0 = svmla_n_u32_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_u32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** mad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_z_untied, svuint32_t, + z0 = svmla_n_u32_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_u32_x_tied1: +** mla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_x_tied1, svuint32_t, + z0 = svmla_u32_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_u32_x_tied2: +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_x_tied2, svuint32_t, + z0 = svmla_u32_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_u32_x_tied3: +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_u32_x_tied3, svuint32_t, + z0 = svmla_u32_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_u32_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** mad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u32_x_untied, svuint32_t, + z0 = svmla_u32_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmla_n_u32_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_u32_x_tied2: +** mov (z[0-9]+\.s), w0 +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_x_tied2, svuint32_t, uint32_t, + z0 = svmla_n_u32_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_u32_x_untied: +** mov z0\.s, w0 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmla_n_u32_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_x_tied1, svuint32_t, + z0 = svmla_n_u32_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_u32_x_tied2: +** mov (z[0-9]+\.s), #11 +** mad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_x_tied2, svuint32_t, + z0 = svmla_n_u32_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_u32_x_untied: +** mov z0\.s, #11 +** mad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mla_11_u32_x_untied, svuint32_t, + z0 = svmla_n_u32_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u64.c new file mode 100644 index 00000000000..6233265c830 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_u64_m_tied1: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_m_tied1, svuint64_t, + z0 = svmla_u64_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mla z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_m_tied2, svuint64_t, + z0 = svmla_u64_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_u64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_u64_m_tied3, svuint64_t, + z0 = svmla_u64_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_u64_m_untied: +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_m_untied, svuint64_t, + z0 = svmla_u64_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmla_n_u64_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmla_n_u64_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_u64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_m_tied1, svuint64_t, + z0 = svmla_n_u64_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_m_untied, svuint64_t, + z0 = svmla_n_u64_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_z_tied1, svuint64_t, + z0 = svmla_u64_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_z_tied2, svuint64_t, + z0 = svmla_u64_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_u64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_z_tied3, svuint64_t, + z0 = svmla_u64_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u64_z_untied, svuint64_t, + z0 = svmla_u64_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmla_n_u64_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_x0_u64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_z_tied2, svuint64_t, uint64_t, + z0 = svmla_n_u64_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmla_n_u64_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_u64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_z_tied1, svuint64_t, + z0 = svmla_n_u64_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_u64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_z_tied2, svuint64_t, + z0 = svmla_n_u64_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_u64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** mad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_z_untied, svuint64_t, + z0 = svmla_n_u64_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_u64_x_tied1: +** mla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_x_tied1, svuint64_t, + z0 = svmla_u64_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_u64_x_tied2: +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_x_tied2, svuint64_t, + z0 = svmla_u64_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_u64_x_tied3: +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_u64_x_tied3, svuint64_t, + z0 = svmla_u64_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_u64_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** mad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u64_x_untied, svuint64_t, + z0 = svmla_u64_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmla_n_u64_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_x0_u64_x_tied2: +** mov (z[0-9]+\.d), x0 +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_x_tied2, svuint64_t, uint64_t, + z0 = svmla_n_u64_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_x0_u64_x_untied: +** mov z0\.d, x0 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mla_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmla_n_u64_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_x_tied1, svuint64_t, + z0 = svmla_n_u64_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_u64_x_tied2: +** mov (z[0-9]+\.d), #11 +** mad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_x_tied2, svuint64_t, + z0 = svmla_n_u64_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_u64_x_untied: +** mov z0\.d, #11 +** mad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mla_11_u64_x_untied, svuint64_t, + z0 = svmla_n_u64_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c new file mode 100644 index 00000000000..832ed41410e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mla_u8_m_tied1: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_m_tied1, svuint8_t, + z0 = svmla_u8_m (p0, z0, z1, z2), + z0 = svmla_m (p0, z0, z1, z2)) + +/* +** mla_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_m_tied2, svuint8_t, + z0 = svmla_u8_m (p0, z1, z0, z2), + z0 = svmla_m (p0, z1, z0, z2)) + +/* +** mla_u8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_m_tied3, svuint8_t, + z0 = svmla_u8_m (p0, z1, z2, z0), + z0 = svmla_m (p0, z1, z2, z0)) + +/* +** mla_u8_m_untied: +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_m_untied, svuint8_t, + z0 = svmla_u8_m (p0, z1, z2, z3), + z0 = svmla_m (p0, z1, z2, z3)) + +/* +** mla_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmla_n_u8_m (p0, z0, z1, x0), + z0 = svmla_m (p0, z0, z1, x0)) + +/* +** mla_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmla_n_u8_m (p0, z1, z2, x0), + z0 = svmla_m (p0, z1, z2, x0)) + +/* +** mla_11_u8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_m_tied1, svuint8_t, + z0 = svmla_n_u8_m (p0, z0, z1, 11), + z0 = svmla_m (p0, z0, z1, 11)) + +/* +** mla_11_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_m_untied, svuint8_t, + z0 = svmla_n_u8_m (p0, z1, z2, 11), + z0 = svmla_m (p0, z1, z2, 11)) + +/* +** mla_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_z_tied1, svuint8_t, + z0 = svmla_u8_z (p0, z0, z1, z2), + z0 = svmla_z (p0, z0, z1, z2)) + +/* +** mla_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_z_tied2, svuint8_t, + z0 = svmla_u8_z (p0, z1, z0, z2), + z0 = svmla_z (p0, z1, z0, z2)) + +/* +** mla_u8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_z_tied3, svuint8_t, + z0 = svmla_u8_z (p0, z1, z2, z0), + z0 = svmla_z (p0, z1, z2, z0)) + +/* +** mla_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u8_z_untied, svuint8_t, + z0 = svmla_u8_z (p0, z1, z2, z3), + z0 = svmla_z (p0, z1, z2, z3)) + +/* +** mla_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmla_n_u8_z (p0, z0, z1, x0), + z0 = svmla_z (p0, z0, z1, x0)) + +/* +** mla_w0_u8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_z_tied2, svuint8_t, uint8_t, + z0 = svmla_n_u8_z (p0, z1, z0, x0), + z0 = svmla_z (p0, z1, z0, x0)) + +/* +** mla_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmla_n_u8_z (p0, z1, z2, x0), + z0 = svmla_z (p0, z1, z2, x0)) + +/* +** mla_11_u8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_z_tied1, svuint8_t, + z0 = svmla_n_u8_z (p0, z0, z1, 11), + z0 = svmla_z (p0, z0, z1, 11)) + +/* +** mla_11_u8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_z_tied2, svuint8_t, + z0 = svmla_n_u8_z (p0, z1, z0, 11), + z0 = svmla_z (p0, z1, z0, 11)) + +/* +** mla_11_u8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mla z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** mad z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_z_untied, svuint8_t, + z0 = svmla_n_u8_z (p0, z1, z2, 11), + z0 = svmla_z (p0, z1, z2, 11)) + +/* +** mla_u8_x_tied1: +** mla z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_x_tied1, svuint8_t, + z0 = svmla_u8_x (p0, z0, z1, z2), + z0 = svmla_x (p0, z0, z1, z2)) + +/* +** mla_u8_x_tied2: +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_x_tied2, svuint8_t, + z0 = svmla_u8_x (p0, z1, z0, z2), + z0 = svmla_x (p0, z1, z0, z2)) + +/* +** mla_u8_x_tied3: +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_u8_x_tied3, svuint8_t, + z0 = svmla_u8_x (p0, z1, z2, z0), + z0 = svmla_x (p0, z1, z2, z0)) + +/* +** mla_u8_x_untied: +** ( +** movprfx z0, z1 +** mla z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** mad z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0, z3 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mla_u8_x_untied, svuint8_t, + z0 = svmla_u8_x (p0, z1, z2, z3), + z0 = svmla_x (p0, z1, z2, z3)) + +/* +** mla_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmla_n_u8_x (p0, z0, z1, x0), + z0 = svmla_x (p0, z0, z1, x0)) + +/* +** mla_w0_u8_x_tied2: +** mov (z[0-9]+\.b), w0 +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_x_tied2, svuint8_t, uint8_t, + z0 = svmla_n_u8_x (p0, z1, z0, x0), + z0 = svmla_x (p0, z1, z0, x0)) + +/* +** mla_w0_u8_x_untied: +** mov z0\.b, w0 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mla_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmla_n_u8_x (p0, z1, z2, x0), + z0 = svmla_x (p0, z1, z2, x0)) + +/* +** mla_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mla z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_x_tied1, svuint8_t, + z0 = svmla_n_u8_x (p0, z0, z1, 11), + z0 = svmla_x (p0, z0, z1, 11)) + +/* +** mla_11_u8_x_tied2: +** mov (z[0-9]+\.b), #11 +** mad z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_x_tied2, svuint8_t, + z0 = svmla_n_u8_x (p0, z1, z0, 11), + z0 = svmla_x (p0, z1, z0, 11)) + +/* +** mla_11_u8_x_untied: +** mov z0\.b, #11 +** mad z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mla_11_u8_x_untied, svuint8_t, + z0 = svmla_n_u8_x (p0, z1, z2, 11), + z0 = svmla_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f16.c new file mode 100644 index 00000000000..87fba3da7ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_f16_m_tied1: +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_m_tied1, svfloat16_t, + z0 = svmls_f16_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_m_tied2, svfloat16_t, + z0 = svmls_f16_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_m_tied3, svfloat16_t, + z0 = svmls_f16_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_f16_m_untied: +** movprfx z0, z1 +** fmls z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_m_untied, svfloat16_t, + z0 = svmls_f16_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmls_n_f16_m (p0, z0, z1, d4), + z0 = svmls_m (p0, z0, z1, d4)) + +/* +** mls_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmls_n_f16_m (p0, z1, z2, d4), + z0 = svmls_m (p0, z1, z2, d4)) + +/* +** mls_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_m_tied1, svfloat16_t, + z0 = svmls_n_f16_m (p0, z0, z1, 2), + z0 = svmls_m (p0, z0, z1, 2)) + +/* +** mls_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_m_untied, svfloat16_t, + z0 = svmls_n_f16_m (p0, z1, z2, 2), + z0 = svmls_m (p0, z1, z2, 2)) + +/* +** mls_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_z_tied1, svfloat16_t, + z0 = svmls_f16_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_z_tied2, svfloat16_t, + z0 = svmls_f16_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_z_tied3, svfloat16_t, + z0 = svmls_f16_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f16_z_untied, svfloat16_t, + z0 = svmls_f16_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmls_n_f16_z (p0, z0, z1, d4), + z0 = svmls_z (p0, z0, z1, d4)) + +/* +** mls_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svmls_n_f16_z (p0, z1, z0, d4), + z0 = svmls_z (p0, z1, z0, d4)) + +/* +** mls_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmls_n_f16_z (p0, z1, z2, d4), + z0 = svmls_z (p0, z1, z2, d4)) + +/* +** mls_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_z_tied1, svfloat16_t, + z0 = svmls_n_f16_z (p0, z0, z1, 2), + z0 = svmls_z (p0, z0, z1, 2)) + +/* +** mls_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_z_tied2, svfloat16_t, + z0 = svmls_n_f16_z (p0, z1, z0, 2), + z0 = svmls_z (p0, z1, z0, 2)) + +/* +** mls_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_z_untied, svfloat16_t, + z0 = svmls_n_f16_z (p0, z1, z2, 2), + z0 = svmls_z (p0, z1, z2, 2)) + +/* +** mls_f16_x_tied1: +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_x_tied1, svfloat16_t, + z0 = svmls_f16_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_f16_x_tied2: +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_x_tied2, svfloat16_t, + z0 = svmls_f16_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_f16_x_tied3: +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_f16_x_tied3, svfloat16_t, + z0 = svmls_f16_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_f16_x_untied: +** ( +** movprfx z0, z1 +** fmls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fmsb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f16_x_untied, svfloat16_t, + z0 = svmls_f16_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmls_n_f16_x (p0, z0, z1, d4), + z0 = svmls_x (p0, z0, z1, d4)) + +/* +** mls_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svmls_n_f16_x (p0, z1, z0, d4), + z0 = svmls_x (p0, z1, z0, d4)) + +/* +** mls_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mls_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmls_n_f16_x (p0, z1, z2, d4), + z0 = svmls_x (p0, z1, z2, d4)) + +/* +** mls_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_x_tied1, svfloat16_t, + z0 = svmls_n_f16_x (p0, z0, z1, 2), + z0 = svmls_x (p0, z0, z1, 2)) + +/* +** mls_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_x_tied2, svfloat16_t, + z0 = svmls_n_f16_x (p0, z1, z0, 2), + z0 = svmls_x (p0, z1, z0, 2)) + +/* +** mls_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_2_f16_x_untied, svfloat16_t, + z0 = svmls_n_f16_x (p0, z1, z2, 2), + z0 = svmls_x (p0, z1, z2, 2)) + +/* +** ptrue_mls_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f16_x_tied1, svfloat16_t, + z0 = svmls_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svmls_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_mls_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f16_x_tied2, svfloat16_t, + z0 = svmls_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svmls_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_mls_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f16_x_tied3, svfloat16_t, + z0 = svmls_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svmls_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_mls_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f16_x_untied, svfloat16_t, + z0 = svmls_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svmls_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_mls_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f16_x_tied1, svfloat16_t, + z0 = svmls_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svmls_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_mls_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f16_x_tied2, svfloat16_t, + z0 = svmls_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svmls_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_mls_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f16_x_untied, svfloat16_t, + z0 = svmls_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svmls_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f32.c new file mode 100644 index 00000000000..04ce1ec46e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_f32_m_tied1: +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_m_tied1, svfloat32_t, + z0 = svmls_f32_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_m_tied2, svfloat32_t, + z0 = svmls_f32_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_m_tied3, svfloat32_t, + z0 = svmls_f32_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_f32_m_untied: +** movprfx z0, z1 +** fmls z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_m_untied, svfloat32_t, + z0 = svmls_f32_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmls_n_f32_m (p0, z0, z1, d4), + z0 = svmls_m (p0, z0, z1, d4)) + +/* +** mls_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_m_untied, svfloat32_t, float, + z0 = svmls_n_f32_m (p0, z1, z2, d4), + z0 = svmls_m (p0, z1, z2, d4)) + +/* +** mls_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_m_tied1, svfloat32_t, + z0 = svmls_n_f32_m (p0, z0, z1, 2), + z0 = svmls_m (p0, z0, z1, 2)) + +/* +** mls_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_m_untied, svfloat32_t, + z0 = svmls_n_f32_m (p0, z1, z2, 2), + z0 = svmls_m (p0, z1, z2, 2)) + +/* +** mls_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_z_tied1, svfloat32_t, + z0 = svmls_f32_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_z_tied2, svfloat32_t, + z0 = svmls_f32_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_z_tied3, svfloat32_t, + z0 = svmls_f32_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f32_z_untied, svfloat32_t, + z0 = svmls_f32_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmls_n_f32_z (p0, z0, z1, d4), + z0 = svmls_z (p0, z0, z1, d4)) + +/* +** mls_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_z_tied2, svfloat32_t, float, + z0 = svmls_n_f32_z (p0, z1, z0, d4), + z0 = svmls_z (p0, z1, z0, d4)) + +/* +** mls_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_z_untied, svfloat32_t, float, + z0 = svmls_n_f32_z (p0, z1, z2, d4), + z0 = svmls_z (p0, z1, z2, d4)) + +/* +** mls_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_z_tied1, svfloat32_t, + z0 = svmls_n_f32_z (p0, z0, z1, 2), + z0 = svmls_z (p0, z0, z1, 2)) + +/* +** mls_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_z_tied2, svfloat32_t, + z0 = svmls_n_f32_z (p0, z1, z0, 2), + z0 = svmls_z (p0, z1, z0, 2)) + +/* +** mls_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_z_untied, svfloat32_t, + z0 = svmls_n_f32_z (p0, z1, z2, 2), + z0 = svmls_z (p0, z1, z2, 2)) + +/* +** mls_f32_x_tied1: +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_x_tied1, svfloat32_t, + z0 = svmls_f32_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_f32_x_tied2: +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_x_tied2, svfloat32_t, + z0 = svmls_f32_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_f32_x_tied3: +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_f32_x_tied3, svfloat32_t, + z0 = svmls_f32_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_f32_x_untied: +** ( +** movprfx z0, z1 +** fmls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fmsb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f32_x_untied, svfloat32_t, + z0 = svmls_f32_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmls_n_f32_x (p0, z0, z1, d4), + z0 = svmls_x (p0, z0, z1, d4)) + +/* +** mls_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_x_tied2, svfloat32_t, float, + z0 = svmls_n_f32_x (p0, z1, z0, d4), + z0 = svmls_x (p0, z1, z0, d4)) + +/* +** mls_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mls_s4_f32_x_untied, svfloat32_t, float, + z0 = svmls_n_f32_x (p0, z1, z2, d4), + z0 = svmls_x (p0, z1, z2, d4)) + +/* +** mls_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_x_tied1, svfloat32_t, + z0 = svmls_n_f32_x (p0, z0, z1, 2), + z0 = svmls_x (p0, z0, z1, 2)) + +/* +** mls_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_x_tied2, svfloat32_t, + z0 = svmls_n_f32_x (p0, z1, z0, 2), + z0 = svmls_x (p0, z1, z0, 2)) + +/* +** mls_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_2_f32_x_untied, svfloat32_t, + z0 = svmls_n_f32_x (p0, z1, z2, 2), + z0 = svmls_x (p0, z1, z2, 2)) + +/* +** ptrue_mls_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f32_x_tied1, svfloat32_t, + z0 = svmls_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svmls_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_mls_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f32_x_tied2, svfloat32_t, + z0 = svmls_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svmls_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_mls_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f32_x_tied3, svfloat32_t, + z0 = svmls_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svmls_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_mls_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f32_x_untied, svfloat32_t, + z0 = svmls_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svmls_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_mls_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f32_x_tied1, svfloat32_t, + z0 = svmls_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svmls_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_mls_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f32_x_tied2, svfloat32_t, + z0 = svmls_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svmls_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_mls_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f32_x_untied, svfloat32_t, + z0 = svmls_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svmls_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f64.c new file mode 100644 index 00000000000..1e2108af671 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_f64_m_tied1: +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_m_tied1, svfloat64_t, + z0 = svmls_f64_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmls z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_m_tied2, svfloat64_t, + z0 = svmls_f64_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_f64_m_tied3, svfloat64_t, + z0 = svmls_f64_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_f64_m_untied: +** movprfx z0, z1 +** fmls z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_m_untied, svfloat64_t, + z0 = svmls_f64_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmls_n_f64_m (p0, z0, z1, d4), + z0 = svmls_m (p0, z0, z1, d4)) + +/* +** mls_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_m_untied, svfloat64_t, double, + z0 = svmls_n_f64_m (p0, z1, z2, d4), + z0 = svmls_m (p0, z1, z2, d4)) + +/* +** mls_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_m_tied1, svfloat64_t, + z0 = svmls_n_f64_m (p0, z0, z1, 2), + z0 = svmls_m (p0, z0, z1, 2)) + +/* +** mls_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_m_untied, svfloat64_t, + z0 = svmls_n_f64_m (p0, z1, z2, 2), + z0 = svmls_m (p0, z1, z2, 2)) + +/* +** mls_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_z_tied1, svfloat64_t, + z0 = svmls_f64_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_z_tied2, svfloat64_t, + z0 = svmls_f64_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_z_tied3, svfloat64_t, + z0 = svmls_f64_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f64_z_untied, svfloat64_t, + z0 = svmls_f64_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmls_n_f64_z (p0, z0, z1, d4), + z0 = svmls_z (p0, z0, z1, d4)) + +/* +** mls_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_z_tied2, svfloat64_t, double, + z0 = svmls_n_f64_z (p0, z1, z0, d4), + z0 = svmls_z (p0, z1, z0, d4)) + +/* +** mls_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_z_untied, svfloat64_t, double, + z0 = svmls_n_f64_z (p0, z1, z2, d4), + z0 = svmls_z (p0, z1, z2, d4)) + +/* +** mls_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_z_tied1, svfloat64_t, + z0 = svmls_n_f64_z (p0, z0, z1, 2), + z0 = svmls_z (p0, z0, z1, 2)) + +/* +** mls_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_z_tied2, svfloat64_t, + z0 = svmls_n_f64_z (p0, z1, z0, 2), + z0 = svmls_z (p0, z1, z0, 2)) + +/* +** mls_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_z_untied, svfloat64_t, + z0 = svmls_n_f64_z (p0, z1, z2, 2), + z0 = svmls_z (p0, z1, z2, 2)) + +/* +** mls_f64_x_tied1: +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_x_tied1, svfloat64_t, + z0 = svmls_f64_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_f64_x_tied2: +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_x_tied2, svfloat64_t, + z0 = svmls_f64_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_f64_x_tied3: +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_f64_x_tied3, svfloat64_t, + z0 = svmls_f64_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_f64_x_untied: +** ( +** movprfx z0, z1 +** fmls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fmsb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_f64_x_untied, svfloat64_t, + z0 = svmls_f64_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmls_n_f64_x (p0, z0, z1, d4), + z0 = svmls_x (p0, z0, z1, d4)) + +/* +** mls_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_x_tied2, svfloat64_t, double, + z0 = svmls_n_f64_x (p0, z1, z0, d4), + z0 = svmls_x (p0, z1, z0, d4)) + +/* +** mls_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mls_d4_f64_x_untied, svfloat64_t, double, + z0 = svmls_n_f64_x (p0, z1, z2, d4), + z0 = svmls_x (p0, z1, z2, d4)) + +/* +** mls_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_x_tied1, svfloat64_t, + z0 = svmls_n_f64_x (p0, z0, z1, 2), + z0 = svmls_x (p0, z0, z1, 2)) + +/* +** mls_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_x_tied2, svfloat64_t, + z0 = svmls_n_f64_x (p0, z1, z0, 2), + z0 = svmls_x (p0, z1, z0, 2)) + +/* +** mls_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_2_f64_x_untied, svfloat64_t, + z0 = svmls_n_f64_x (p0, z1, z2, 2), + z0 = svmls_x (p0, z1, z2, 2)) + +/* +** ptrue_mls_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f64_x_tied1, svfloat64_t, + z0 = svmls_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svmls_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_mls_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f64_x_tied2, svfloat64_t, + z0 = svmls_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svmls_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_mls_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f64_x_tied3, svfloat64_t, + z0 = svmls_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svmls_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_mls_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_f64_x_untied, svfloat64_t, + z0 = svmls_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svmls_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_mls_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f64_x_tied1, svfloat64_t, + z0 = svmls_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svmls_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_mls_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f64_x_tied2, svfloat64_t, + z0 = svmls_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svmls_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_mls_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mls_2_f64_x_untied, svfloat64_t, + z0 = svmls_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svmls_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f16.c new file mode 100644 index 00000000000..832376d0b00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f16.c @@ -0,0 +1,128 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_lane_0_f16_tied1: +** fmls z0\.h, z1\.h, z2\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f16_tied1, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 0), + z0 = svmls_lane (z0, z1, z2, 0)) + +/* +** mls_lane_0_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.h, \1\.h, z2\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f16_tied2, svfloat16_t, + z0 = svmls_lane_f16 (z1, z0, z2, 0), + z0 = svmls_lane (z1, z0, z2, 0)) + +/* +** mls_lane_0_f16_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.h, z2\.h, \1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f16_tied3, svfloat16_t, + z0 = svmls_lane_f16 (z1, z2, z0, 0), + z0 = svmls_lane (z1, z2, z0, 0)) + +/* +** mls_lane_0_f16_untied: +** movprfx z0, z1 +** fmls z0\.h, z2\.h, z3\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f16_untied, svfloat16_t, + z0 = svmls_lane_f16 (z1, z2, z3, 0), + z0 = svmls_lane (z1, z2, z3, 0)) + +/* +** mls_lane_1_f16: +** fmls z0\.h, z1\.h, z2\.h\[1\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_1_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 1), + z0 = svmls_lane (z0, z1, z2, 1)) + +/* +** mls_lane_2_f16: +** fmls z0\.h, z1\.h, z2\.h\[2\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_2_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 2), + z0 = svmls_lane (z0, z1, z2, 2)) + +/* +** mls_lane_3_f16: +** fmls z0\.h, z1\.h, z2\.h\[3\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_3_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 3), + z0 = svmls_lane (z0, z1, z2, 3)) + +/* +** mls_lane_4_f16: +** fmls z0\.h, z1\.h, z2\.h\[4\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_4_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 4), + z0 = svmls_lane (z0, z1, z2, 4)) + +/* +** mls_lane_5_f16: +** fmls z0\.h, z1\.h, z2\.h\[5\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_5_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 5), + z0 = svmls_lane (z0, z1, z2, 5)) + +/* +** mls_lane_6_f16: +** fmls z0\.h, z1\.h, z2\.h\[6\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_6_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 6), + z0 = svmls_lane (z0, z1, z2, 6)) + +/* +** mls_lane_7_f16: +** fmls z0\.h, z1\.h, z2\.h\[7\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_7_f16, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z2, 7), + z0 = svmls_lane (z0, z1, z2, 7)) + +/* +** mls_lane_z7_f16: +** fmls z0\.h, z1\.h, z7\.h\[7\] +** ret +*/ +TEST_DUAL_Z (mls_lane_z7_f16, svfloat16_t, svfloat16_t, + z0 = svmls_lane_f16 (z0, z1, z7, 7), + z0 = svmls_lane (z0, z1, z7, 7)) + +/* +** mls_lane_z8_f16: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmls z0\.h, z1\.h, \1\.h\[7\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mls_lane_z8_f16, svfloat16_t, svfloat16_t, z8, + z0 = svmls_lane_f16 (z0, z1, z8, 7), + z0 = svmls_lane (z0, z1, z8, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f32.c new file mode 100644 index 00000000000..3244b972f8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f32.c @@ -0,0 +1,92 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_lane_0_f32_tied1: +** fmls z0\.s, z1\.s, z2\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f32_tied1, svfloat32_t, + z0 = svmls_lane_f32 (z0, z1, z2, 0), + z0 = svmls_lane (z0, z1, z2, 0)) + +/* +** mls_lane_0_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.s, \1\.s, z2\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f32_tied2, svfloat32_t, + z0 = svmls_lane_f32 (z1, z0, z2, 0), + z0 = svmls_lane (z1, z0, z2, 0)) + +/* +** mls_lane_0_f32_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmls z0\.s, z2\.s, \1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f32_tied3, svfloat32_t, + z0 = svmls_lane_f32 (z1, z2, z0, 0), + z0 = svmls_lane (z1, z2, z0, 0)) + +/* +** mls_lane_0_f32_untied: +** movprfx z0, z1 +** fmls z0\.s, z2\.s, z3\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f32_untied, svfloat32_t, + z0 = svmls_lane_f32 (z1, z2, z3, 0), + z0 = svmls_lane (z1, z2, z3, 0)) + +/* +** mls_lane_1_f32: +** fmls z0\.s, z1\.s, z2\.s\[1\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_1_f32, svfloat32_t, + z0 = svmls_lane_f32 (z0, z1, z2, 1), + z0 = svmls_lane (z0, z1, z2, 1)) + +/* +** mls_lane_2_f32: +** fmls z0\.s, z1\.s, z2\.s\[2\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_2_f32, svfloat32_t, + z0 = svmls_lane_f32 (z0, z1, z2, 2), + z0 = svmls_lane (z0, z1, z2, 2)) + +/* +** mls_lane_3_f32: +** fmls z0\.s, z1\.s, z2\.s\[3\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_3_f32, svfloat32_t, + z0 = svmls_lane_f32 (z0, z1, z2, 3), + z0 = svmls_lane (z0, z1, z2, 3)) + +/* +** mls_lane_z7_f32: +** fmls z0\.s, z1\.s, z7\.s\[3\] +** ret +*/ +TEST_DUAL_Z (mls_lane_z7_f32, svfloat32_t, svfloat32_t, + z0 = svmls_lane_f32 (z0, z1, z7, 3), + z0 = svmls_lane (z0, z1, z7, 3)) + +/* +** mls_lane_z8_f32: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmls z0\.s, z1\.s, \1\.s\[3\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mls_lane_z8_f32, svfloat32_t, svfloat32_t, z8, + z0 = svmls_lane_f32 (z0, z1, z8, 3), + z0 = svmls_lane (z0, z1, z8, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f64.c new file mode 100644 index 00000000000..16f20ca532d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_lane_f64.c @@ -0,0 +1,83 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_lane_0_f64_tied1: +** fmls z0\.d, z1\.d, z2\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f64_tied1, svfloat64_t, + z0 = svmls_lane_f64 (z0, z1, z2, 0), + z0 = svmls_lane (z0, z1, z2, 0)) + +/* +** mls_lane_0_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmls z0\.d, \1, z2\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f64_tied2, svfloat64_t, + z0 = svmls_lane_f64 (z1, z0, z2, 0), + z0 = svmls_lane (z1, z0, z2, 0)) + +/* +** mls_lane_0_f64_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmls z0\.d, z2\.d, \1\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f64_tied3, svfloat64_t, + z0 = svmls_lane_f64 (z1, z2, z0, 0), + z0 = svmls_lane (z1, z2, z0, 0)) + +/* +** mls_lane_0_f64_untied: +** movprfx z0, z1 +** fmls z0\.d, z2\.d, z3\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_0_f64_untied, svfloat64_t, + z0 = svmls_lane_f64 (z1, z2, z3, 0), + z0 = svmls_lane (z1, z2, z3, 0)) + +/* +** mls_lane_1_f64: +** fmls z0\.d, z1\.d, z2\.d\[1\] +** ret +*/ +TEST_UNIFORM_Z (mls_lane_1_f64, svfloat64_t, + z0 = svmls_lane_f64 (z0, z1, z2, 1), + z0 = svmls_lane (z0, z1, z2, 1)) + +/* +** mls_lane_z7_f64: +** fmls z0\.d, z1\.d, z7\.d\[1\] +** ret +*/ +TEST_DUAL_Z (mls_lane_z7_f64, svfloat64_t, svfloat64_t, + z0 = svmls_lane_f64 (z0, z1, z7, 1), + z0 = svmls_lane (z0, z1, z7, 1)) + +/* +** mls_lane_z15_f64: +** str d15, \[sp, -16\]! +** fmls z0\.d, z1\.d, z15\.d\[1\] +** ldr d15, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mls_lane_z15_f64, svfloat64_t, svfloat64_t, z15, + z0 = svmls_lane_f64 (z0, z1, z15, 1), + z0 = svmls_lane (z0, z1, z15, 1)) + +/* +** mls_lane_z16_f64: +** mov (z[0-9]|z1[0-5])\.d, z16\.d +** fmls z0\.d, z1\.d, \1\.d\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (mls_lane_z16_f64, svfloat64_t, svfloat64_t, z16, + z0 = svmls_lane_f64 (z0, z1, z16, 1), + z0 = svmls_lane (z0, z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c new file mode 100644 index 00000000000..e199829c4ad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_s16_m_tied1: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_m_tied1, svint16_t, + z0 = svmls_s16_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_m_tied2, svint16_t, + z0 = svmls_s16_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_s16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_m_tied3, svint16_t, + z0 = svmls_s16_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_s16_m_untied: +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_m_untied, svint16_t, + z0 = svmls_s16_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmls_n_s16_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmls_n_s16_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_s16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_m_tied1, svint16_t, + z0 = svmls_n_s16_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_m_untied, svint16_t, + z0 = svmls_n_s16_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_z_tied1, svint16_t, + z0 = svmls_s16_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_z_tied2, svint16_t, + z0 = svmls_s16_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_s16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_z_tied3, svint16_t, + z0 = svmls_s16_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s16_z_untied, svint16_t, + z0 = svmls_s16_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmls_n_s16_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_s16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_z_tied2, svint16_t, int16_t, + z0 = svmls_n_s16_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmls_n_s16_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_s16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_z_tied1, svint16_t, + z0 = svmls_n_s16_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_s16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_z_tied2, svint16_t, + z0 = svmls_n_s16_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_s16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_z_untied, svint16_t, + z0 = svmls_n_s16_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_s16_x_tied1: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_x_tied1, svint16_t, + z0 = svmls_s16_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_s16_x_tied2: +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_x_tied2, svint16_t, + z0 = svmls_s16_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_s16_x_tied3: +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_s16_x_tied3, svint16_t, + z0 = svmls_s16_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_s16_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** msb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s16_x_untied, svint16_t, + z0 = svmls_s16_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmls_n_s16_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_s16_x_tied2: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_x_tied2, svint16_t, int16_t, + z0 = svmls_n_s16_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_s16_x_untied: +** mov z0\.h, w0 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmls_n_s16_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_x_tied1, svint16_t, + z0 = svmls_n_s16_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_s16_x_tied2: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_x_tied2, svint16_t, + z0 = svmls_n_s16_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_s16_x_untied: +** mov z0\.h, #11 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_s16_x_untied, svint16_t, + z0 = svmls_n_s16_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s32.c new file mode 100644 index 00000000000..fe386d01cd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_s32_m_tied1: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_m_tied1, svint32_t, + z0 = svmls_s32_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_m_tied2, svint32_t, + z0 = svmls_s32_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_s32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_m_tied3, svint32_t, + z0 = svmls_s32_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_s32_m_untied: +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_m_untied, svint32_t, + z0 = svmls_s32_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmls_n_s32_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmls_n_s32_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_s32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_m_tied1, svint32_t, + z0 = svmls_n_s32_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_m_untied, svint32_t, + z0 = svmls_n_s32_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_z_tied1, svint32_t, + z0 = svmls_s32_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_z_tied2, svint32_t, + z0 = svmls_s32_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_s32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_z_tied3, svint32_t, + z0 = svmls_s32_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s32_z_untied, svint32_t, + z0 = svmls_s32_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmls_n_s32_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_s32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_z_tied2, svint32_t, int32_t, + z0 = svmls_n_s32_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmls_n_s32_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_s32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_z_tied1, svint32_t, + z0 = svmls_n_s32_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_s32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_z_tied2, svint32_t, + z0 = svmls_n_s32_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_s32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_z_untied, svint32_t, + z0 = svmls_n_s32_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_s32_x_tied1: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_x_tied1, svint32_t, + z0 = svmls_s32_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_s32_x_tied2: +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_x_tied2, svint32_t, + z0 = svmls_s32_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_s32_x_tied3: +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_s32_x_tied3, svint32_t, + z0 = svmls_s32_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_s32_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** msb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s32_x_untied, svint32_t, + z0 = svmls_s32_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmls_n_s32_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_s32_x_tied2: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_x_tied2, svint32_t, int32_t, + z0 = svmls_n_s32_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_s32_x_untied: +** mov z0\.s, w0 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmls_n_s32_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_x_tied1, svint32_t, + z0 = svmls_n_s32_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_s32_x_tied2: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_x_tied2, svint32_t, + z0 = svmls_n_s32_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_s32_x_untied: +** mov z0\.s, #11 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_s32_x_untied, svint32_t, + z0 = svmls_n_s32_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s64.c new file mode 100644 index 00000000000..2998d733fbc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_s64_m_tied1: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_m_tied1, svint64_t, + z0 = svmls_s64_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mls z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_m_tied2, svint64_t, + z0 = svmls_s64_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_s64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_s64_m_tied3, svint64_t, + z0 = svmls_s64_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_s64_m_untied: +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_m_untied, svint64_t, + z0 = svmls_s64_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmls_n_s64_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmls_n_s64_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_s64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_m_tied1, svint64_t, + z0 = svmls_n_s64_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_m_untied, svint64_t, + z0 = svmls_n_s64_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_z_tied1, svint64_t, + z0 = svmls_s64_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_z_tied2, svint64_t, + z0 = svmls_s64_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_s64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_z_tied3, svint64_t, + z0 = svmls_s64_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s64_z_untied, svint64_t, + z0 = svmls_s64_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmls_n_s64_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_x0_s64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_z_tied2, svint64_t, int64_t, + z0 = svmls_n_s64_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmls_n_s64_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_s64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_z_tied1, svint64_t, + z0 = svmls_n_s64_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_s64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_z_tied2, svint64_t, + z0 = svmls_n_s64_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_s64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_z_untied, svint64_t, + z0 = svmls_n_s64_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_s64_x_tied1: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_x_tied1, svint64_t, + z0 = svmls_s64_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_s64_x_tied2: +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_x_tied2, svint64_t, + z0 = svmls_s64_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_s64_x_tied3: +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_s64_x_tied3, svint64_t, + z0 = svmls_s64_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_s64_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** msb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s64_x_untied, svint64_t, + z0 = svmls_s64_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmls_n_s64_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_x0_s64_x_tied2: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_x_tied2, svint64_t, int64_t, + z0 = svmls_n_s64_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_x0_s64_x_untied: +** mov z0\.d, x0 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmls_n_s64_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_x_tied1, svint64_t, + z0 = svmls_n_s64_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_s64_x_tied2: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_x_tied2, svint64_t, + z0 = svmls_n_s64_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_s64_x_untied: +** mov z0\.d, #11 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_s64_x_untied, svint64_t, + z0 = svmls_n_s64_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c new file mode 100644 index 00000000000..c60c431455f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_s8_m_tied1: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_m_tied1, svint8_t, + z0 = svmls_s8_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_m_tied2, svint8_t, + z0 = svmls_s8_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_s8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_m_tied3, svint8_t, + z0 = svmls_s8_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_s8_m_untied: +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_m_untied, svint8_t, + z0 = svmls_s8_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmls_n_s8_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmls_n_s8_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_s8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_m_tied1, svint8_t, + z0 = svmls_n_s8_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_m_untied, svint8_t, + z0 = svmls_n_s8_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_z_tied1, svint8_t, + z0 = svmls_s8_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_z_tied2, svint8_t, + z0 = svmls_s8_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_s8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_z_tied3, svint8_t, + z0 = svmls_s8_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s8_z_untied, svint8_t, + z0 = svmls_s8_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmls_n_s8_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_s8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_z_tied2, svint8_t, int8_t, + z0 = svmls_n_s8_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmls_n_s8_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_s8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_z_tied1, svint8_t, + z0 = svmls_n_s8_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_s8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_z_tied2, svint8_t, + z0 = svmls_n_s8_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_s8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_z_untied, svint8_t, + z0 = svmls_n_s8_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_s8_x_tied1: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_x_tied1, svint8_t, + z0 = svmls_s8_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_s8_x_tied2: +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_x_tied2, svint8_t, + z0 = svmls_s8_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_s8_x_tied3: +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_s8_x_tied3, svint8_t, + z0 = svmls_s8_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_s8_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** msb z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0, z3 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_s8_x_untied, svint8_t, + z0 = svmls_s8_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmls_n_s8_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_s8_x_tied2: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_x_tied2, svint8_t, int8_t, + z0 = svmls_n_s8_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_s8_x_untied: +** mov z0\.b, w0 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmls_n_s8_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_x_tied1, svint8_t, + z0 = svmls_n_s8_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_s8_x_tied2: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_x_tied2, svint8_t, + z0 = svmls_n_s8_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_s8_x_untied: +** mov z0\.b, #11 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_s8_x_untied, svint8_t, + z0 = svmls_n_s8_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c new file mode 100644 index 00000000000..e8a9f5cd94c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_u16_m_tied1: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_m_tied1, svuint16_t, + z0 = svmls_u16_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_m_tied2, svuint16_t, + z0 = svmls_u16_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_u16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_m_tied3, svuint16_t, + z0 = svmls_u16_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_u16_m_untied: +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_m_untied, svuint16_t, + z0 = svmls_u16_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmls_n_u16_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmls_n_u16_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_u16_m_tied1: +** mov (z[0-9]+\.h), #11 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_m_tied1, svuint16_t, + z0 = svmls_n_u16_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_m_untied, svuint16_t, + z0 = svmls_n_u16_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_z_tied1, svuint16_t, + z0 = svmls_u16_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_z_tied2, svuint16_t, + z0 = svmls_u16_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_u16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_z_tied3, svuint16_t, + z0 = svmls_u16_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u16_z_untied, svuint16_t, + z0 = svmls_u16_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmls_n_u16_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_u16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_z_tied2, svuint16_t, uint16_t, + z0 = svmls_n_u16_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmls_n_u16_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_u16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_z_tied1, svuint16_t, + z0 = svmls_n_u16_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_u16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_z_tied2, svuint16_t, + z0 = svmls_n_u16_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_u16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_z_untied, svuint16_t, + z0 = svmls_n_u16_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_u16_x_tied1: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_x_tied1, svuint16_t, + z0 = svmls_u16_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_u16_x_tied2: +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_x_tied2, svuint16_t, + z0 = svmls_u16_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_u16_x_tied3: +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_u16_x_tied3, svuint16_t, + z0 = svmls_u16_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_u16_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** msb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u16_x_untied, svuint16_t, + z0 = svmls_u16_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmls_n_u16_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_u16_x_tied2: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_x_tied2, svuint16_t, uint16_t, + z0 = svmls_n_u16_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_u16_x_untied: +** mov z0\.h, w0 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmls_n_u16_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** mls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_x_tied1, svuint16_t, + z0 = svmls_n_u16_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_u16_x_tied2: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_x_tied2, svuint16_t, + z0 = svmls_n_u16_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_u16_x_untied: +** mov z0\.h, #11 +** msb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mls_11_u16_x_untied, svuint16_t, + z0 = svmls_n_u16_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u32.c new file mode 100644 index 00000000000..47e885012ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_u32_m_tied1: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_m_tied1, svuint32_t, + z0 = svmls_u32_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_m_tied2, svuint32_t, + z0 = svmls_u32_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_u32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_m_tied3, svuint32_t, + z0 = svmls_u32_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_u32_m_untied: +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_m_untied, svuint32_t, + z0 = svmls_u32_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmls_n_u32_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmls_n_u32_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_u32_m_tied1: +** mov (z[0-9]+\.s), #11 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_m_tied1, svuint32_t, + z0 = svmls_n_u32_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_m_untied, svuint32_t, + z0 = svmls_n_u32_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_z_tied1, svuint32_t, + z0 = svmls_u32_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_z_tied2, svuint32_t, + z0 = svmls_u32_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_u32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_z_tied3, svuint32_t, + z0 = svmls_u32_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u32_z_untied, svuint32_t, + z0 = svmls_u32_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmls_n_u32_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_u32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_z_tied2, svuint32_t, uint32_t, + z0 = svmls_n_u32_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmls_n_u32_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_u32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_z_tied1, svuint32_t, + z0 = svmls_n_u32_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_u32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_z_tied2, svuint32_t, + z0 = svmls_n_u32_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_u32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_z_untied, svuint32_t, + z0 = svmls_n_u32_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_u32_x_tied1: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_x_tied1, svuint32_t, + z0 = svmls_u32_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_u32_x_tied2: +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_x_tied2, svuint32_t, + z0 = svmls_u32_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_u32_x_tied3: +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_u32_x_tied3, svuint32_t, + z0 = svmls_u32_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_u32_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** msb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u32_x_untied, svuint32_t, + z0 = svmls_u32_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmls_n_u32_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_u32_x_tied2: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_x_tied2, svuint32_t, uint32_t, + z0 = svmls_n_u32_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_u32_x_untied: +** mov z0\.s, w0 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmls_n_u32_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** mls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_x_tied1, svuint32_t, + z0 = svmls_n_u32_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_u32_x_tied2: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_x_tied2, svuint32_t, + z0 = svmls_n_u32_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_u32_x_untied: +** mov z0\.s, #11 +** msb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mls_11_u32_x_untied, svuint32_t, + z0 = svmls_n_u32_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u64.c new file mode 100644 index 00000000000..4d441b75920 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_u64_m_tied1: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_m_tied1, svuint64_t, + z0 = svmls_u64_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mls z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_m_tied2, svuint64_t, + z0 = svmls_u64_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_u64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_u64_m_tied3, svuint64_t, + z0 = svmls_u64_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_u64_m_untied: +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_m_untied, svuint64_t, + z0 = svmls_u64_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmls_n_u64_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmls_n_u64_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_u64_m_tied1: +** mov (z[0-9]+\.d), #11 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_m_tied1, svuint64_t, + z0 = svmls_n_u64_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_m_untied, svuint64_t, + z0 = svmls_n_u64_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_z_tied1, svuint64_t, + z0 = svmls_u64_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_z_tied2, svuint64_t, + z0 = svmls_u64_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_u64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_z_tied3, svuint64_t, + z0 = svmls_u64_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u64_z_untied, svuint64_t, + z0 = svmls_u64_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmls_n_u64_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_x0_u64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_z_tied2, svuint64_t, uint64_t, + z0 = svmls_n_u64_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmls_n_u64_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_u64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_z_tied1, svuint64_t, + z0 = svmls_n_u64_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_u64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_z_tied2, svuint64_t, + z0 = svmls_n_u64_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_u64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_z_untied, svuint64_t, + z0 = svmls_n_u64_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_u64_x_tied1: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_x_tied1, svuint64_t, + z0 = svmls_u64_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_u64_x_tied2: +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_x_tied2, svuint64_t, + z0 = svmls_u64_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_u64_x_tied3: +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_u64_x_tied3, svuint64_t, + z0 = svmls_u64_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_u64_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** msb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u64_x_untied, svuint64_t, + z0 = svmls_u64_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmls_n_u64_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_x0_u64_x_tied2: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_x_tied2, svuint64_t, uint64_t, + z0 = svmls_n_u64_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_x0_u64_x_untied: +** mov z0\.d, x0 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mls_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmls_n_u64_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** mls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_x_tied1, svuint64_t, + z0 = svmls_n_u64_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_u64_x_tied2: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_x_tied2, svuint64_t, + z0 = svmls_n_u64_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_u64_x_untied: +** mov z0\.d, #11 +** msb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mls_11_u64_x_untied, svuint64_t, + z0 = svmls_n_u64_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c new file mode 100644 index 00000000000..0489aaa7cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mls_u8_m_tied1: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_m_tied1, svuint8_t, + z0 = svmls_u8_m (p0, z0, z1, z2), + z0 = svmls_m (p0, z0, z1, z2)) + +/* +** mls_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_m_tied2, svuint8_t, + z0 = svmls_u8_m (p0, z1, z0, z2), + z0 = svmls_m (p0, z1, z0, z2)) + +/* +** mls_u8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_m_tied3, svuint8_t, + z0 = svmls_u8_m (p0, z1, z2, z0), + z0 = svmls_m (p0, z1, z2, z0)) + +/* +** mls_u8_m_untied: +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_m_untied, svuint8_t, + z0 = svmls_u8_m (p0, z1, z2, z3), + z0 = svmls_m (p0, z1, z2, z3)) + +/* +** mls_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmls_n_u8_m (p0, z0, z1, x0), + z0 = svmls_m (p0, z0, z1, x0)) + +/* +** mls_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmls_n_u8_m (p0, z1, z2, x0), + z0 = svmls_m (p0, z1, z2, x0)) + +/* +** mls_11_u8_m_tied1: +** mov (z[0-9]+\.b), #11 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_m_tied1, svuint8_t, + z0 = svmls_n_u8_m (p0, z0, z1, 11), + z0 = svmls_m (p0, z0, z1, 11)) + +/* +** mls_11_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_m_untied, svuint8_t, + z0 = svmls_n_u8_m (p0, z1, z2, 11), + z0 = svmls_m (p0, z1, z2, 11)) + +/* +** mls_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_z_tied1, svuint8_t, + z0 = svmls_u8_z (p0, z0, z1, z2), + z0 = svmls_z (p0, z0, z1, z2)) + +/* +** mls_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_z_tied2, svuint8_t, + z0 = svmls_u8_z (p0, z1, z0, z2), + z0 = svmls_z (p0, z1, z0, z2)) + +/* +** mls_u8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_z_tied3, svuint8_t, + z0 = svmls_u8_z (p0, z1, z2, z0), + z0 = svmls_z (p0, z1, z2, z0)) + +/* +** mls_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u8_z_untied, svuint8_t, + z0 = svmls_u8_z (p0, z1, z2, z3), + z0 = svmls_z (p0, z1, z2, z3)) + +/* +** mls_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmls_n_u8_z (p0, z0, z1, x0), + z0 = svmls_z (p0, z0, z1, x0)) + +/* +** mls_w0_u8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_z_tied2, svuint8_t, uint8_t, + z0 = svmls_n_u8_z (p0, z1, z0, x0), + z0 = svmls_z (p0, z1, z0, x0)) + +/* +** mls_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmls_n_u8_z (p0, z1, z2, x0), + z0 = svmls_z (p0, z1, z2, x0)) + +/* +** mls_11_u8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_z_tied1, svuint8_t, + z0 = svmls_n_u8_z (p0, z0, z1, 11), + z0 = svmls_z (p0, z0, z1, 11)) + +/* +** mls_11_u8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_z_tied2, svuint8_t, + z0 = svmls_n_u8_z (p0, z1, z0, 11), + z0 = svmls_z (p0, z1, z0, 11)) + +/* +** mls_11_u8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mls z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, \1, z1\.b +** | +** movprfx z0\.b, p0/z, \1 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_z_untied, svuint8_t, + z0 = svmls_n_u8_z (p0, z1, z2, 11), + z0 = svmls_z (p0, z1, z2, 11)) + +/* +** mls_u8_x_tied1: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_x_tied1, svuint8_t, + z0 = svmls_u8_x (p0, z0, z1, z2), + z0 = svmls_x (p0, z0, z1, z2)) + +/* +** mls_u8_x_tied2: +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_x_tied2, svuint8_t, + z0 = svmls_u8_x (p0, z1, z0, z2), + z0 = svmls_x (p0, z1, z0, z2)) + +/* +** mls_u8_x_tied3: +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_u8_x_tied3, svuint8_t, + z0 = svmls_u8_x (p0, z1, z2, z0), + z0 = svmls_x (p0, z1, z2, z0)) + +/* +** mls_u8_x_untied: +** ( +** movprfx z0, z1 +** mls z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** msb z0\.b, p0/m, z3\.b, z1\.b +** | +** movprfx z0, z3 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mls_u8_x_untied, svuint8_t, + z0 = svmls_u8_x (p0, z1, z2, z3), + z0 = svmls_x (p0, z1, z2, z3)) + +/* +** mls_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmls_n_u8_x (p0, z0, z1, x0), + z0 = svmls_x (p0, z0, z1, x0)) + +/* +** mls_w0_u8_x_tied2: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_x_tied2, svuint8_t, uint8_t, + z0 = svmls_n_u8_x (p0, z1, z0, x0), + z0 = svmls_x (p0, z1, z0, x0)) + +/* +** mls_w0_u8_x_untied: +** mov z0\.b, w0 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mls_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmls_n_u8_x (p0, z1, z2, x0), + z0 = svmls_x (p0, z1, z2, x0)) + +/* +** mls_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** mls z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_x_tied1, svuint8_t, + z0 = svmls_n_u8_x (p0, z0, z1, 11), + z0 = svmls_x (p0, z0, z1, 11)) + +/* +** mls_11_u8_x_tied2: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, \1, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_x_tied2, svuint8_t, + z0 = svmls_n_u8_x (p0, z1, z0, 11), + z0 = svmls_x (p0, z1, z0, 11)) + +/* +** mls_11_u8_x_untied: +** mov z0\.b, #11 +** msb z0\.b, p0/m, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mls_11_u8_x_untied, svuint8_t, + z0 = svmls_n_u8_x (p0, z1, z2, 11), + z0 = svmls_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mov_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mov_b.c new file mode 100644 index 00000000000..6b78f348ffe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mov_b.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mov_b_z_tied1: +** and p0\.b, (?:p3/z, p0\.b, p0\.b|p0/z, p3\.b, p3\.b) +** ret +*/ +TEST_UNIFORM_P (mov_b_z_tied1, + p0 = svmov_b_z (p3, p0), + p0 = svmov_z (p3, p0)) + +/* +** mov_b_z_untied: +** and p0\.b, (?:p3/z, p1\.b, p1\.b|p1/z, p3\.b, p3\.b) +** ret +*/ +TEST_UNIFORM_P (mov_b_z_untied, + p0 = svmov_b_z (p3, p1), + p0 = svmov_z (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f16.c new file mode 100644 index 00000000000..fe11457c4f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_f16_m_tied1: +** fmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_m_tied1, svfloat16_t, + z0 = svmsb_f16_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmsb z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_m_tied2, svfloat16_t, + z0 = svmsb_f16_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmsb z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_m_tied3, svfloat16_t, + z0 = svmsb_f16_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_f16_m_untied: +** movprfx z0, z1 +** fmsb z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_m_untied, svfloat16_t, + z0 = svmsb_f16_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmsb_n_f16_m (p0, z0, z1, d4), + z0 = svmsb_m (p0, z0, z1, d4)) + +/* +** msb_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmsb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmsb_n_f16_m (p0, z1, z2, d4), + z0 = svmsb_m (p0, z1, z2, d4)) + +/* +** msb_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_m_tied1, svfloat16_t, + z0 = svmsb_n_f16_m (p0, z0, z1, 2), + z0 = svmsb_m (p0, z0, z1, 2)) + +/* +** msb_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmsb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_m_untied, svfloat16_t, + z0 = svmsb_n_f16_m (p0, z1, z2, 2), + z0 = svmsb_m (p0, z1, z2, 2)) + +/* +** msb_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_z_tied1, svfloat16_t, + z0 = svmsb_f16_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_z_tied2, svfloat16_t, + z0 = svmsb_f16_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_z_tied3, svfloat16_t, + z0 = svmsb_f16_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmsb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f16_z_untied, svfloat16_t, + z0 = svmsb_f16_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmsb_n_f16_z (p0, z0, z1, d4), + z0 = svmsb_z (p0, z0, z1, d4)) + +/* +** msb_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svmsb_n_f16_z (p0, z1, z0, d4), + z0 = svmsb_z (p0, z1, z0, d4)) + +/* +** msb_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmsb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmsb_n_f16_z (p0, z1, z2, d4), + z0 = svmsb_z (p0, z1, z2, d4)) + +/* +** msb_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_z_tied1, svfloat16_t, + z0 = svmsb_n_f16_z (p0, z0, z1, 2), + z0 = svmsb_z (p0, z0, z1, 2)) + +/* +** msb_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_z_tied2, svfloat16_t, + z0 = svmsb_n_f16_z (p0, z1, z0, 2), + z0 = svmsb_z (p0, z1, z0, 2)) + +/* +** msb_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmsb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fmsb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_z_untied, svfloat16_t, + z0 = svmsb_n_f16_z (p0, z1, z2, 2), + z0 = svmsb_z (p0, z1, z2, 2)) + +/* +** msb_f16_x_tied1: +** fmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_x_tied1, svfloat16_t, + z0 = svmsb_f16_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_f16_x_tied2: +** fmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_x_tied2, svfloat16_t, + z0 = svmsb_f16_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_f16_x_tied3: +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_f16_x_tied3, svfloat16_t, + z0 = svmsb_f16_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_f16_x_untied: +** ( +** movprfx z0, z1 +** fmsb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fmsb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f16_x_untied, svfloat16_t, + z0 = svmsb_f16_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmsb_n_f16_x (p0, z0, z1, d4), + z0 = svmsb_x (p0, z0, z1, d4)) + +/* +** msb_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svmsb_n_f16_x (p0, z1, z0, d4), + z0 = svmsb_x (p0, z1, z0, d4)) + +/* +** msb_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZD (msb_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmsb_n_f16_x (p0, z1, z2, d4), + z0 = svmsb_x (p0, z1, z2, d4)) + +/* +** msb_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_x_tied1, svfloat16_t, + z0 = svmsb_n_f16_x (p0, z0, z1, 2), + z0 = svmsb_x (p0, z0, z1, 2)) + +/* +** msb_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_x_tied2, svfloat16_t, + z0 = svmsb_n_f16_x (p0, z1, z0, 2), + z0 = svmsb_x (p0, z1, z0, 2)) + +/* +** msb_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_2_f16_x_untied, svfloat16_t, + z0 = svmsb_n_f16_x (p0, z1, z2, 2), + z0 = svmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_msb_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f16_x_tied1, svfloat16_t, + z0 = svmsb_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svmsb_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_msb_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f16_x_tied2, svfloat16_t, + z0 = svmsb_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svmsb_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_msb_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f16_x_tied3, svfloat16_t, + z0 = svmsb_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svmsb_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_msb_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f16_x_untied, svfloat16_t, + z0 = svmsb_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svmsb_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_msb_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f16_x_tied1, svfloat16_t, + z0 = svmsb_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svmsb_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_msb_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f16_x_tied2, svfloat16_t, + z0 = svmsb_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svmsb_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_msb_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f16_x_untied, svfloat16_t, + z0 = svmsb_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svmsb_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f32.c new file mode 100644 index 00000000000..f7a9f2767e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_f32_m_tied1: +** fmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_m_tied1, svfloat32_t, + z0 = svmsb_f32_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmsb z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_m_tied2, svfloat32_t, + z0 = svmsb_f32_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmsb z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_m_tied3, svfloat32_t, + z0 = svmsb_f32_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_f32_m_untied: +** movprfx z0, z1 +** fmsb z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_m_untied, svfloat32_t, + z0 = svmsb_f32_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmsb_n_f32_m (p0, z0, z1, d4), + z0 = svmsb_m (p0, z0, z1, d4)) + +/* +** msb_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmsb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_m_untied, svfloat32_t, float, + z0 = svmsb_n_f32_m (p0, z1, z2, d4), + z0 = svmsb_m (p0, z1, z2, d4)) + +/* +** msb_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_m_tied1, svfloat32_t, + z0 = svmsb_n_f32_m (p0, z0, z1, 2), + z0 = svmsb_m (p0, z0, z1, 2)) + +/* +** msb_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmsb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_m_untied, svfloat32_t, + z0 = svmsb_n_f32_m (p0, z1, z2, 2), + z0 = svmsb_m (p0, z1, z2, 2)) + +/* +** msb_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_z_tied1, svfloat32_t, + z0 = svmsb_f32_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_z_tied2, svfloat32_t, + z0 = svmsb_f32_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_z_tied3, svfloat32_t, + z0 = svmsb_f32_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmsb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f32_z_untied, svfloat32_t, + z0 = svmsb_f32_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmsb_n_f32_z (p0, z0, z1, d4), + z0 = svmsb_z (p0, z0, z1, d4)) + +/* +** msb_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_z_tied2, svfloat32_t, float, + z0 = svmsb_n_f32_z (p0, z1, z0, d4), + z0 = svmsb_z (p0, z1, z0, d4)) + +/* +** msb_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmsb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_z_untied, svfloat32_t, float, + z0 = svmsb_n_f32_z (p0, z1, z2, d4), + z0 = svmsb_z (p0, z1, z2, d4)) + +/* +** msb_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_z_tied1, svfloat32_t, + z0 = svmsb_n_f32_z (p0, z0, z1, 2), + z0 = svmsb_z (p0, z0, z1, 2)) + +/* +** msb_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_z_tied2, svfloat32_t, + z0 = svmsb_n_f32_z (p0, z1, z0, 2), + z0 = svmsb_z (p0, z1, z0, 2)) + +/* +** msb_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmsb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fmsb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_z_untied, svfloat32_t, + z0 = svmsb_n_f32_z (p0, z1, z2, 2), + z0 = svmsb_z (p0, z1, z2, 2)) + +/* +** msb_f32_x_tied1: +** fmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_x_tied1, svfloat32_t, + z0 = svmsb_f32_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_f32_x_tied2: +** fmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_x_tied2, svfloat32_t, + z0 = svmsb_f32_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_f32_x_tied3: +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_f32_x_tied3, svfloat32_t, + z0 = svmsb_f32_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_f32_x_untied: +** ( +** movprfx z0, z1 +** fmsb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fmsb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f32_x_untied, svfloat32_t, + z0 = svmsb_f32_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmsb_n_f32_x (p0, z0, z1, d4), + z0 = svmsb_x (p0, z0, z1, d4)) + +/* +** msb_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_x_tied2, svfloat32_t, float, + z0 = svmsb_n_f32_x (p0, z1, z0, d4), + z0 = svmsb_x (p0, z1, z0, d4)) + +/* +** msb_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZD (msb_s4_f32_x_untied, svfloat32_t, float, + z0 = svmsb_n_f32_x (p0, z1, z2, d4), + z0 = svmsb_x (p0, z1, z2, d4)) + +/* +** msb_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_x_tied1, svfloat32_t, + z0 = svmsb_n_f32_x (p0, z0, z1, 2), + z0 = svmsb_x (p0, z0, z1, 2)) + +/* +** msb_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_x_tied2, svfloat32_t, + z0 = svmsb_n_f32_x (p0, z1, z0, 2), + z0 = svmsb_x (p0, z1, z0, 2)) + +/* +** msb_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_2_f32_x_untied, svfloat32_t, + z0 = svmsb_n_f32_x (p0, z1, z2, 2), + z0 = svmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_msb_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f32_x_tied1, svfloat32_t, + z0 = svmsb_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svmsb_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_msb_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f32_x_tied2, svfloat32_t, + z0 = svmsb_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svmsb_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_msb_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f32_x_tied3, svfloat32_t, + z0 = svmsb_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svmsb_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_msb_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f32_x_untied, svfloat32_t, + z0 = svmsb_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svmsb_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_msb_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f32_x_tied1, svfloat32_t, + z0 = svmsb_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svmsb_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_msb_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f32_x_tied2, svfloat32_t, + z0 = svmsb_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svmsb_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_msb_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f32_x_untied, svfloat32_t, + z0 = svmsb_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svmsb_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f64.c new file mode 100644 index 00000000000..e3ff414d81a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_f64_m_tied1: +** fmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_m_tied1, svfloat64_t, + z0 = svmsb_f64_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmsb z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_m_tied2, svfloat64_t, + z0 = svmsb_f64_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_f64_m_tied3, svfloat64_t, + z0 = svmsb_f64_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_f64_m_untied: +** movprfx z0, z1 +** fmsb z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_m_untied, svfloat64_t, + z0 = svmsb_f64_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmsb_n_f64_m (p0, z0, z1, d4), + z0 = svmsb_m (p0, z0, z1, d4)) + +/* +** msb_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_m_untied, svfloat64_t, double, + z0 = svmsb_n_f64_m (p0, z1, z2, d4), + z0 = svmsb_m (p0, z1, z2, d4)) + +/* +** msb_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_m_tied1, svfloat64_t, + z0 = svmsb_n_f64_m (p0, z0, z1, 2), + z0 = svmsb_m (p0, z0, z1, 2)) + +/* +** msb_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_m_untied, svfloat64_t, + z0 = svmsb_n_f64_m (p0, z1, z2, 2), + z0 = svmsb_m (p0, z1, z2, 2)) + +/* +** msb_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_z_tied1, svfloat64_t, + z0 = svmsb_f64_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_z_tied2, svfloat64_t, + z0 = svmsb_f64_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_z_tied3, svfloat64_t, + z0 = svmsb_f64_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmsb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f64_z_untied, svfloat64_t, + z0 = svmsb_f64_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmsb_n_f64_z (p0, z0, z1, d4), + z0 = svmsb_z (p0, z0, z1, d4)) + +/* +** msb_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_z_tied2, svfloat64_t, double, + z0 = svmsb_n_f64_z (p0, z1, z0, d4), + z0 = svmsb_z (p0, z1, z0, d4)) + +/* +** msb_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmsb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_z_untied, svfloat64_t, double, + z0 = svmsb_n_f64_z (p0, z1, z2, d4), + z0 = svmsb_z (p0, z1, z2, d4)) + +/* +** msb_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_z_tied1, svfloat64_t, + z0 = svmsb_n_f64_z (p0, z0, z1, 2), + z0 = svmsb_z (p0, z0, z1, 2)) + +/* +** msb_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_z_tied2, svfloat64_t, + z0 = svmsb_n_f64_z (p0, z1, z0, 2), + z0 = svmsb_z (p0, z1, z0, 2)) + +/* +** msb_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmsb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fmsb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_z_untied, svfloat64_t, + z0 = svmsb_n_f64_z (p0, z1, z2, 2), + z0 = svmsb_z (p0, z1, z2, 2)) + +/* +** msb_f64_x_tied1: +** fmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_x_tied1, svfloat64_t, + z0 = svmsb_f64_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_f64_x_tied2: +** fmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_x_tied2, svfloat64_t, + z0 = svmsb_f64_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_f64_x_tied3: +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_f64_x_tied3, svfloat64_t, + z0 = svmsb_f64_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_f64_x_untied: +** ( +** movprfx z0, z1 +** fmsb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fmsb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_f64_x_untied, svfloat64_t, + z0 = svmsb_f64_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmsb_n_f64_x (p0, z0, z1, d4), + z0 = svmsb_x (p0, z0, z1, d4)) + +/* +** msb_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_x_tied2, svfloat64_t, double, + z0 = svmsb_n_f64_x (p0, z1, z0, d4), + z0 = svmsb_x (p0, z1, z0, d4)) + +/* +** msb_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZD (msb_d4_f64_x_untied, svfloat64_t, double, + z0 = svmsb_n_f64_x (p0, z1, z2, d4), + z0 = svmsb_x (p0, z1, z2, d4)) + +/* +** msb_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_x_tied1, svfloat64_t, + z0 = svmsb_n_f64_x (p0, z0, z1, 2), + z0 = svmsb_x (p0, z0, z1, 2)) + +/* +** msb_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_x_tied2, svfloat64_t, + z0 = svmsb_n_f64_x (p0, z1, z0, 2), + z0 = svmsb_x (p0, z1, z0, 2)) + +/* +** msb_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_2_f64_x_untied, svfloat64_t, + z0 = svmsb_n_f64_x (p0, z1, z2, 2), + z0 = svmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_msb_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f64_x_tied1, svfloat64_t, + z0 = svmsb_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svmsb_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_msb_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f64_x_tied2, svfloat64_t, + z0 = svmsb_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svmsb_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_msb_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f64_x_tied3, svfloat64_t, + z0 = svmsb_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svmsb_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_msb_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_f64_x_untied, svfloat64_t, + z0 = svmsb_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svmsb_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_msb_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f64_x_tied1, svfloat64_t, + z0 = svmsb_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svmsb_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_msb_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f64_x_tied2, svfloat64_t, + z0 = svmsb_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svmsb_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_msb_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_msb_2_f64_x_untied, svfloat64_t, + z0 = svmsb_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svmsb_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c new file mode 100644 index 00000000000..56347cfb918 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_s16_m_tied1: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_m_tied1, svint16_t, + z0 = svmsb_s16_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_m_tied2, svint16_t, + z0 = svmsb_s16_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_s16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_m_tied3, svint16_t, + z0 = svmsb_s16_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_s16_m_untied: +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_m_untied, svint16_t, + z0 = svmsb_s16_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmsb_n_s16_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmsb_n_s16_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_s16_m_tied1: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_m_tied1, svint16_t, + z0 = svmsb_n_s16_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_m_untied, svint16_t, + z0 = svmsb_n_s16_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_z_tied1, svint16_t, + z0 = svmsb_s16_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_z_tied2, svint16_t, + z0 = svmsb_s16_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_s16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_z_tied3, svint16_t, + z0 = svmsb_s16_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s16_z_untied, svint16_t, + z0 = svmsb_s16_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmsb_n_s16_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_s16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_z_tied2, svint16_t, int16_t, + z0 = svmsb_n_s16_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmsb_n_s16_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_s16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_z_tied1, svint16_t, + z0 = svmsb_n_s16_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_s16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_z_tied2, svint16_t, + z0 = svmsb_n_s16_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_s16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_z_untied, svint16_t, + z0 = svmsb_n_s16_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_s16_x_tied1: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_x_tied1, svint16_t, + z0 = svmsb_s16_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_s16_x_tied2: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_x_tied2, svint16_t, + z0 = svmsb_s16_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_s16_x_tied3: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_s16_x_tied3, svint16_t, + z0 = svmsb_s16_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_s16_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** msb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s16_x_untied, svint16_t, + z0 = svmsb_s16_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmsb_n_s16_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_s16_x_tied2: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_x_tied2, svint16_t, int16_t, + z0 = svmsb_n_s16_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_s16_x_untied: +** mov z0\.h, w0 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmsb_n_s16_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_x_tied1, svint16_t, + z0 = svmsb_n_s16_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_s16_x_tied2: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_x_tied2, svint16_t, + z0 = svmsb_n_s16_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_s16_x_untied: +** mov z0\.h, #11 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_11_s16_x_untied, svint16_t, + z0 = svmsb_n_s16_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s32.c new file mode 100644 index 00000000000..fb7a7815b57 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_s32_m_tied1: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_m_tied1, svint32_t, + z0 = svmsb_s32_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_m_tied2, svint32_t, + z0 = svmsb_s32_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_s32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_m_tied3, svint32_t, + z0 = svmsb_s32_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_s32_m_untied: +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_m_untied, svint32_t, + z0 = svmsb_s32_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmsb_n_s32_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmsb_n_s32_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_s32_m_tied1: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_m_tied1, svint32_t, + z0 = svmsb_n_s32_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_m_untied, svint32_t, + z0 = svmsb_n_s32_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_z_tied1, svint32_t, + z0 = svmsb_s32_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_z_tied2, svint32_t, + z0 = svmsb_s32_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_s32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_z_tied3, svint32_t, + z0 = svmsb_s32_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s32_z_untied, svint32_t, + z0 = svmsb_s32_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmsb_n_s32_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_s32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_z_tied2, svint32_t, int32_t, + z0 = svmsb_n_s32_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmsb_n_s32_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_s32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_z_tied1, svint32_t, + z0 = svmsb_n_s32_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_s32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_z_tied2, svint32_t, + z0 = svmsb_n_s32_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_s32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_z_untied, svint32_t, + z0 = svmsb_n_s32_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_s32_x_tied1: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_x_tied1, svint32_t, + z0 = svmsb_s32_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_s32_x_tied2: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_x_tied2, svint32_t, + z0 = svmsb_s32_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_s32_x_tied3: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_s32_x_tied3, svint32_t, + z0 = svmsb_s32_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_s32_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** msb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s32_x_untied, svint32_t, + z0 = svmsb_s32_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmsb_n_s32_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_s32_x_tied2: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_x_tied2, svint32_t, int32_t, + z0 = svmsb_n_s32_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_s32_x_untied: +** mov z0\.s, w0 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmsb_n_s32_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_x_tied1, svint32_t, + z0 = svmsb_n_s32_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_s32_x_tied2: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_x_tied2, svint32_t, + z0 = svmsb_n_s32_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_s32_x_untied: +** mov z0\.s, #11 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_11_s32_x_untied, svint32_t, + z0 = svmsb_n_s32_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s64.c new file mode 100644 index 00000000000..6829fab3655 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_s64_m_tied1: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_m_tied1, svint64_t, + z0 = svmsb_s64_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** msb z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_m_tied2, svint64_t, + z0 = svmsb_s64_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_s64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_s64_m_tied3, svint64_t, + z0 = svmsb_s64_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_s64_m_untied: +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_m_untied, svint64_t, + z0 = svmsb_s64_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmsb_n_s64_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmsb_n_s64_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_s64_m_tied1: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_m_tied1, svint64_t, + z0 = svmsb_n_s64_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_m_untied, svint64_t, + z0 = svmsb_n_s64_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_z_tied1, svint64_t, + z0 = svmsb_s64_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_z_tied2, svint64_t, + z0 = svmsb_s64_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_s64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_z_tied3, svint64_t, + z0 = svmsb_s64_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s64_z_untied, svint64_t, + z0 = svmsb_s64_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmsb_n_s64_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_x0_s64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_z_tied2, svint64_t, int64_t, + z0 = svmsb_n_s64_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmsb_n_s64_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_s64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_z_tied1, svint64_t, + z0 = svmsb_n_s64_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_s64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_z_tied2, svint64_t, + z0 = svmsb_n_s64_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_s64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_z_untied, svint64_t, + z0 = svmsb_n_s64_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_s64_x_tied1: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_x_tied1, svint64_t, + z0 = svmsb_s64_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_s64_x_tied2: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_x_tied2, svint64_t, + z0 = svmsb_s64_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_s64_x_tied3: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_s64_x_tied3, svint64_t, + z0 = svmsb_s64_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_s64_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** msb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s64_x_untied, svint64_t, + z0 = svmsb_s64_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmsb_n_s64_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_x0_s64_x_tied2: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_x_tied2, svint64_t, int64_t, + z0 = svmsb_n_s64_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_x0_s64_x_untied: +** mov z0\.d, x0 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmsb_n_s64_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_x_tied1, svint64_t, + z0 = svmsb_n_s64_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_s64_x_tied2: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_x_tied2, svint64_t, + z0 = svmsb_n_s64_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_s64_x_untied: +** mov z0\.d, #11 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_11_s64_x_untied, svint64_t, + z0 = svmsb_n_s64_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c new file mode 100644 index 00000000000..d7fcafdd0df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_s8_m_tied1: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_m_tied1, svint8_t, + z0 = svmsb_s8_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_m_tied2, svint8_t, + z0 = svmsb_s8_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_s8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_m_tied3, svint8_t, + z0 = svmsb_s8_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_s8_m_untied: +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_m_untied, svint8_t, + z0 = svmsb_s8_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmsb_n_s8_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmsb_n_s8_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_s8_m_tied1: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_m_tied1, svint8_t, + z0 = svmsb_n_s8_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_m_untied, svint8_t, + z0 = svmsb_n_s8_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_z_tied1, svint8_t, + z0 = svmsb_s8_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_z_tied2, svint8_t, + z0 = svmsb_s8_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_s8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_z_tied3, svint8_t, + z0 = svmsb_s8_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s8_z_untied, svint8_t, + z0 = svmsb_s8_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmsb_n_s8_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_s8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_z_tied2, svint8_t, int8_t, + z0 = svmsb_n_s8_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmsb_n_s8_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_s8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_z_tied1, svint8_t, + z0 = svmsb_n_s8_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_s8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_z_tied2, svint8_t, + z0 = svmsb_n_s8_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_s8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_z_untied, svint8_t, + z0 = svmsb_n_s8_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_s8_x_tied1: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_x_tied1, svint8_t, + z0 = svmsb_s8_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_s8_x_tied2: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_x_tied2, svint8_t, + z0 = svmsb_s8_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_s8_x_tied3: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_s8_x_tied3, svint8_t, + z0 = svmsb_s8_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_s8_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** msb z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0, z3 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_s8_x_untied, svint8_t, + z0 = svmsb_s8_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmsb_n_s8_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_s8_x_tied2: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_x_tied2, svint8_t, int8_t, + z0 = svmsb_n_s8_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_s8_x_untied: +** mov z0\.b, w0 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmsb_n_s8_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_x_tied1, svint8_t, + z0 = svmsb_n_s8_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_s8_x_tied2: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_x_tied2, svint8_t, + z0 = svmsb_n_s8_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_s8_x_untied: +** mov z0\.b, #11 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_11_s8_x_untied, svint8_t, + z0 = svmsb_n_s8_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c new file mode 100644 index 00000000000..437a96040e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_u16_m_tied1: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_m_tied1, svuint16_t, + z0 = svmsb_u16_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_m_tied2, svuint16_t, + z0 = svmsb_u16_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_u16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_m_tied3, svuint16_t, + z0 = svmsb_u16_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_u16_m_untied: +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_m_untied, svuint16_t, + z0 = svmsb_u16_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmsb_n_u16_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmsb_n_u16_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_u16_m_tied1: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_m_tied1, svuint16_t, + z0 = svmsb_n_u16_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_m_untied, svuint16_t, + z0 = svmsb_n_u16_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_z_tied1, svuint16_t, + z0 = svmsb_u16_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_z_tied2, svuint16_t, + z0 = svmsb_u16_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_u16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_z_tied3, svuint16_t, + z0 = svmsb_u16_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u16_z_untied, svuint16_t, + z0 = svmsb_u16_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmsb_n_u16_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_u16_z_tied2: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_z_tied2, svuint16_t, uint16_t, + z0 = svmsb_n_u16_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmsb_n_u16_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_u16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_z_tied1, svuint16_t, + z0 = svmsb_n_u16_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_u16_z_tied2: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_z_tied2, svuint16_t, + z0 = svmsb_n_u16_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_u16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** msb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** msb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_z_untied, svuint16_t, + z0 = svmsb_n_u16_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_u16_x_tied1: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_x_tied1, svuint16_t, + z0 = svmsb_u16_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_u16_x_tied2: +** msb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_x_tied2, svuint16_t, + z0 = svmsb_u16_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_u16_x_tied3: +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_u16_x_tied3, svuint16_t, + z0 = svmsb_u16_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_u16_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** msb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u16_x_untied, svuint16_t, + z0 = svmsb_u16_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmsb_n_u16_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_u16_x_tied2: +** mov (z[0-9]+\.h), w0 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_x_tied2, svuint16_t, uint16_t, + z0 = svmsb_n_u16_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_u16_x_untied: +** mov z0\.h, w0 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmsb_n_u16_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_x_tied1, svuint16_t, + z0 = svmsb_n_u16_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_u16_x_tied2: +** mov (z[0-9]+\.h), #11 +** msb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_x_tied2, svuint16_t, + z0 = svmsb_n_u16_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_u16_x_untied: +** mov z0\.h, #11 +** mls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (msb_11_u16_x_untied, svuint16_t, + z0 = svmsb_n_u16_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u32.c new file mode 100644 index 00000000000..aaaf0344aea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u32.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_u32_m_tied1: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_m_tied1, svuint32_t, + z0 = svmsb_u32_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_m_tied2, svuint32_t, + z0 = svmsb_u32_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_u32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_m_tied3, svuint32_t, + z0 = svmsb_u32_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_u32_m_untied: +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_m_untied, svuint32_t, + z0 = svmsb_u32_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmsb_n_u32_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmsb_n_u32_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_u32_m_tied1: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_m_tied1, svuint32_t, + z0 = svmsb_n_u32_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_m_untied, svuint32_t, + z0 = svmsb_n_u32_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_z_tied1, svuint32_t, + z0 = svmsb_u32_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_z_tied2, svuint32_t, + z0 = svmsb_u32_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_u32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_z_tied3, svuint32_t, + z0 = svmsb_u32_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u32_z_untied, svuint32_t, + z0 = svmsb_u32_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmsb_n_u32_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_u32_z_tied2: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_z_tied2, svuint32_t, uint32_t, + z0 = svmsb_n_u32_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmsb_n_u32_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_u32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_z_tied1, svuint32_t, + z0 = svmsb_n_u32_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_u32_z_tied2: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_z_tied2, svuint32_t, + z0 = svmsb_n_u32_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_u32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** msb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** msb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_z_untied, svuint32_t, + z0 = svmsb_n_u32_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_u32_x_tied1: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_x_tied1, svuint32_t, + z0 = svmsb_u32_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_u32_x_tied2: +** msb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_x_tied2, svuint32_t, + z0 = svmsb_u32_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_u32_x_tied3: +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_u32_x_tied3, svuint32_t, + z0 = svmsb_u32_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_u32_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** msb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u32_x_untied, svuint32_t, + z0 = svmsb_u32_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmsb_n_u32_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_u32_x_tied2: +** mov (z[0-9]+\.s), w0 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_x_tied2, svuint32_t, uint32_t, + z0 = svmsb_n_u32_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_u32_x_untied: +** mov z0\.s, w0 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmsb_n_u32_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_x_tied1, svuint32_t, + z0 = svmsb_n_u32_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_u32_x_tied2: +** mov (z[0-9]+\.s), #11 +** msb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_x_tied2, svuint32_t, + z0 = svmsb_n_u32_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_u32_x_untied: +** mov z0\.s, #11 +** mls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (msb_11_u32_x_untied, svuint32_t, + z0 = svmsb_n_u32_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u64.c new file mode 100644 index 00000000000..5c5d3307378 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u64.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_u64_m_tied1: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_m_tied1, svuint64_t, + z0 = svmsb_u64_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** msb z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_m_tied2, svuint64_t, + z0 = svmsb_u64_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_u64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_u64_m_tied3, svuint64_t, + z0 = svmsb_u64_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_u64_m_untied: +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_m_untied, svuint64_t, + z0 = svmsb_u64_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmsb_n_u64_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmsb_n_u64_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_u64_m_tied1: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_m_tied1, svuint64_t, + z0 = svmsb_n_u64_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_m_untied, svuint64_t, + z0 = svmsb_n_u64_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_z_tied1, svuint64_t, + z0 = svmsb_u64_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_z_tied2, svuint64_t, + z0 = svmsb_u64_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_u64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_z_tied3, svuint64_t, + z0 = svmsb_u64_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u64_z_untied, svuint64_t, + z0 = svmsb_u64_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmsb_n_u64_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_x0_u64_z_tied2: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_z_tied2, svuint64_t, uint64_t, + z0 = svmsb_n_u64_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmsb_n_u64_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_u64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_z_tied1, svuint64_t, + z0 = svmsb_n_u64_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_u64_z_tied2: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_z_tied2, svuint64_t, + z0 = svmsb_n_u64_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_u64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** msb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** msb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_z_untied, svuint64_t, + z0 = svmsb_n_u64_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_u64_x_tied1: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_x_tied1, svuint64_t, + z0 = svmsb_u64_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_u64_x_tied2: +** msb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_x_tied2, svuint64_t, + z0 = svmsb_u64_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_u64_x_tied3: +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_u64_x_tied3, svuint64_t, + z0 = svmsb_u64_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_u64_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** msb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u64_x_untied, svuint64_t, + z0 = svmsb_u64_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmsb_n_u64_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_x0_u64_x_tied2: +** mov (z[0-9]+\.d), x0 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_x_tied2, svuint64_t, uint64_t, + z0 = svmsb_n_u64_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_x0_u64_x_untied: +** mov z0\.d, x0 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZX (msb_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmsb_n_u64_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_x_tied1, svuint64_t, + z0 = svmsb_n_u64_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_u64_x_tied2: +** mov (z[0-9]+\.d), #11 +** msb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_x_tied2, svuint64_t, + z0 = svmsb_n_u64_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_u64_x_untied: +** mov z0\.d, #11 +** mls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (msb_11_u64_x_untied, svuint64_t, + z0 = svmsb_n_u64_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c new file mode 100644 index 00000000000..5665ec9e320 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c @@ -0,0 +1,321 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** msb_u8_m_tied1: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_m_tied1, svuint8_t, + z0 = svmsb_u8_m (p0, z0, z1, z2), + z0 = svmsb_m (p0, z0, z1, z2)) + +/* +** msb_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.b, p0/m, \1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_m_tied2, svuint8_t, + z0 = svmsb_u8_m (p0, z1, z0, z2), + z0 = svmsb_m (p0, z1, z0, z2)) + +/* +** msb_u8_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_m_tied3, svuint8_t, + z0 = svmsb_u8_m (p0, z1, z2, z0), + z0 = svmsb_m (p0, z1, z2, z0)) + +/* +** msb_u8_m_untied: +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, z3\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_m_untied, svuint8_t, + z0 = svmsb_u8_m (p0, z1, z2, z3), + z0 = svmsb_m (p0, z1, z2, z3)) + +/* +** msb_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmsb_n_u8_m (p0, z0, z1, x0), + z0 = svmsb_m (p0, z0, z1, x0)) + +/* +** msb_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmsb_n_u8_m (p0, z1, z2, x0), + z0 = svmsb_m (p0, z1, z2, x0)) + +/* +** msb_11_u8_m_tied1: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_m_tied1, svuint8_t, + z0 = svmsb_n_u8_m (p0, z0, z1, 11), + z0 = svmsb_m (p0, z0, z1, 11)) + +/* +** msb_11_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_m_untied, svuint8_t, + z0 = svmsb_n_u8_m (p0, z1, z2, 11), + z0 = svmsb_m (p0, z1, z2, 11)) + +/* +** msb_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_z_tied1, svuint8_t, + z0 = svmsb_u8_z (p0, z0, z1, z2), + z0 = svmsb_z (p0, z0, z1, z2)) + +/* +** msb_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_z_tied2, svuint8_t, + z0 = svmsb_u8_z (p0, z1, z0, z2), + z0 = svmsb_z (p0, z1, z0, z2)) + +/* +** msb_u8_z_tied3: +** movprfx z0\.b, p0/z, z0\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_z_tied3, svuint8_t, + z0 = svmsb_u8_z (p0, z1, z2, z0), + z0 = svmsb_z (p0, z1, z2, z0)) + +/* +** msb_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0\.b, p0/z, z3\.b +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u8_z_untied, svuint8_t, + z0 = svmsb_u8_z (p0, z1, z2, z3), + z0 = svmsb_z (p0, z1, z2, z3)) + +/* +** msb_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmsb_n_u8_z (p0, z0, z1, x0), + z0 = svmsb_z (p0, z0, z1, x0)) + +/* +** msb_w0_u8_z_tied2: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_z_tied2, svuint8_t, uint8_t, + z0 = svmsb_n_u8_z (p0, z1, z0, x0), + z0 = svmsb_z (p0, z1, z0, x0)) + +/* +** msb_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmsb_n_u8_z (p0, z1, z2, x0), + z0 = svmsb_z (p0, z1, z2, x0)) + +/* +** msb_11_u8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_z_tied1, svuint8_t, + z0 = svmsb_n_u8_z (p0, z0, z1, 11), + z0 = svmsb_z (p0, z0, z1, 11)) + +/* +** msb_11_u8_z_tied2: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_z_tied2, svuint8_t, + z0 = svmsb_n_u8_z (p0, z1, z0, 11), + z0 = svmsb_z (p0, z1, z0, 11)) + +/* +** msb_11_u8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** msb z0\.b, p0/m, z2\.b, \1 +** | +** movprfx z0\.b, p0/z, z2\.b +** msb z0\.b, p0/m, z1\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_z_untied, svuint8_t, + z0 = svmsb_n_u8_z (p0, z1, z2, 11), + z0 = svmsb_z (p0, z1, z2, 11)) + +/* +** msb_u8_x_tied1: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_x_tied1, svuint8_t, + z0 = svmsb_u8_x (p0, z0, z1, z2), + z0 = svmsb_x (p0, z0, z1, z2)) + +/* +** msb_u8_x_tied2: +** msb z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_x_tied2, svuint8_t, + z0 = svmsb_u8_x (p0, z1, z0, z2), + z0 = svmsb_x (p0, z1, z0, z2)) + +/* +** msb_u8_x_tied3: +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_u8_x_tied3, svuint8_t, + z0 = svmsb_u8_x (p0, z1, z2, z0), + z0 = svmsb_x (p0, z1, z2, z0)) + +/* +** msb_u8_x_untied: +** ( +** movprfx z0, z1 +** msb z0\.b, p0/m, z2\.b, z3\.b +** | +** movprfx z0, z2 +** msb z0\.b, p0/m, z1\.b, z3\.b +** | +** movprfx z0, z3 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (msb_u8_x_untied, svuint8_t, + z0 = svmsb_u8_x (p0, z1, z2, z3), + z0 = svmsb_x (p0, z1, z2, z3)) + +/* +** msb_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmsb_n_u8_x (p0, z0, z1, x0), + z0 = svmsb_x (p0, z0, z1, x0)) + +/* +** msb_w0_u8_x_tied2: +** mov (z[0-9]+\.b), w0 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_x_tied2, svuint8_t, uint8_t, + z0 = svmsb_n_u8_x (p0, z1, z0, x0), + z0 = svmsb_x (p0, z1, z0, x0)) + +/* +** msb_w0_u8_x_untied: +** mov z0\.b, w0 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_ZX (msb_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmsb_n_u8_x (p0, z1, z2, x0), + z0 = svmsb_x (p0, z1, z2, x0)) + +/* +** msb_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_x_tied1, svuint8_t, + z0 = svmsb_n_u8_x (p0, z0, z1, 11), + z0 = svmsb_x (p0, z0, z1, 11)) + +/* +** msb_11_u8_x_tied2: +** mov (z[0-9]+\.b), #11 +** msb z0\.b, p0/m, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_x_tied2, svuint8_t, + z0 = svmsb_n_u8_x (p0, z1, z0, 11), + z0 = svmsb_x (p0, z1, z0, 11)) + +/* +** msb_11_u8_x_untied: +** mov z0\.b, #11 +** mls z0\.b, p0/m, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (msb_11_u8_x_untied, svuint8_t, + z0 = svmsb_n_u8_x (p0, z1, z2, 11), + z0 = svmsb_x (p0, z1, z2, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16.c new file mode 100644 index 00000000000..ef3de0c5953 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_tied1, svfloat16_t, + z0 = svmul_f16_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_tied2, svfloat16_t, + z0 = svmul_f16_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_untied, svfloat16_t, + z0 = svmul_f16_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_tied1, svfloat16_t, + z0 = svmul_f16_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_tied2, svfloat16_t, + z0 = svmul_f16_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_untied, svfloat16_t, + z0 = svmul_f16_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f16_z_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f16_z_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f16_x_tied1: +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_tied1, svfloat16_t, + z0 = svmul_f16_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f16_x_tied2: +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_tied2, svfloat16_t, + z0 = svmul_f16_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f16_x_untied: +** ( +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_untied, svfloat16_t, + z0 = svmul_f16_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_h4_f16_x_untied: +** mov z0\.h, h4 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f16_x_untied: +** fmov z0\.h, #1\.0(?:e\+0)? +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f16_x_tied1: +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f16_x_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f16_x_tied1: +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f16_x_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f16_x_tied1: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_tied1, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z0, z1), + z0 = svmul_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_mul_f16_x_tied2: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_tied2, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z1, z0), + z0 = svmul_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_mul_f16_x_untied: +** fmul z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_untied, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z1, z2), + z0 = svmul_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_mul_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmul_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_mul_1_f16_x_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmul_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_mul_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svmul_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svmul_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_mul_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmul_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_mul_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmul_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16_notrap.c new file mode 100644 index 00000000000..481fe999c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f16_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_tied1, svfloat16_t, + z0 = svmul_f16_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_tied2, svfloat16_t, + z0 = svmul_f16_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_m_untied, svfloat16_t, + z0 = svmul_f16_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f16_m_tied1: +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_m_tied1, svfloat16_t, + z0 = svmul_n_f16_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f16_m_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_m_untied, svfloat16_t, + z0 = svmul_n_f16_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_tied1, svfloat16_t, + z0 = svmul_f16_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_tied2, svfloat16_t, + z0 = svmul_f16_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_z_untied, svfloat16_t, + z0 = svmul_f16_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f16_z_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f16_z_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_z_tied1, svfloat16_t, + z0 = svmul_n_f16_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_z_untied, svfloat16_t, + z0 = svmul_n_f16_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f16_x_tied1: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_tied1, svfloat16_t, + z0 = svmul_f16_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f16_x_tied2: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_tied2, svfloat16_t, + z0 = svmul_f16_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f16_x_untied: +** fmul z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (mul_f16_x_untied, svfloat16_t, + z0 = svmul_f16_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmul z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmul_n_f16_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_h4_f16_x_untied: +** mov (z[0-9]+\.h), h4 +** fmul z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZD (mul_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmul_n_f16_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f16_x_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f16_x_tied1: +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f16_x_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f16_x_tied1: +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f16_x_untied: +** movprfx z0, z1 +** fmul z0\.h, p0/m, z0\.h, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f16_x_tied1: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_tied1, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z0, z1), + z0 = svmul_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_mul_f16_x_tied2: +** fmul z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_tied2, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z1, z0), + z0 = svmul_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_mul_f16_x_untied: +** fmul z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f16_x_untied, svfloat16_t, + z0 = svmul_f16_x (svptrue_b16 (), z1, z2), + z0 = svmul_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_mul_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmul_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_mul_1_f16_x_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmul z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmul_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_mul_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svmul_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svmul_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_mul_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f16_x_tied1, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmul_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_mul_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f16_x_untied, svfloat16_t, + z0 = svmul_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmul_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32.c new file mode 100644 index 00000000000..5b3df6fde9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_tied1, svfloat32_t, + z0 = svmul_f32_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_tied2, svfloat32_t, + z0 = svmul_f32_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_untied, svfloat32_t, + z0 = svmul_f32_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmul_n_f32_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_m_untied, svfloat32_t, float, + z0 = svmul_n_f32_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_tied1, svfloat32_t, + z0 = svmul_f32_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_tied2, svfloat32_t, + z0 = svmul_f32_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_untied, svfloat32_t, + z0 = svmul_f32_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmul_n_f32_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_z_untied, svfloat32_t, float, + z0 = svmul_n_f32_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f32_z_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f32_z_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f32_x_tied1: +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_tied1, svfloat32_t, + z0 = svmul_f32_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f32_x_tied2: +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_tied2, svfloat32_t, + z0 = svmul_f32_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f32_x_untied: +** ( +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_untied, svfloat32_t, + z0 = svmul_f32_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmul_n_f32_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_s4_f32_x_untied: +** mov z0\.s, s4 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_x_untied, svfloat32_t, float, + z0 = svmul_n_f32_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f32_x_untied: +** fmov z0\.s, #1\.0(?:e\+0)? +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f32_x_tied1: +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f32_x_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f32_x_tied1: +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f32_x_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f32_x_tied1: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_tied1, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z0, z1), + z0 = svmul_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_mul_f32_x_tied2: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_tied2, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z1, z0), + z0 = svmul_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_mul_f32_x_untied: +** fmul z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_untied, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z1, z2), + z0 = svmul_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_mul_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmul_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_mul_1_f32_x_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmul_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_mul_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svmul_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svmul_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_mul_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmul_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_mul_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmul_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32_notrap.c new file mode 100644 index 00000000000..eb2d240efd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f32_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_tied1, svfloat32_t, + z0 = svmul_f32_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_tied2, svfloat32_t, + z0 = svmul_f32_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_m_untied, svfloat32_t, + z0 = svmul_f32_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmul_n_f32_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_m_untied, svfloat32_t, float, + z0 = svmul_n_f32_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f32_m_tied1: +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_m_tied1, svfloat32_t, + z0 = svmul_n_f32_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f32_m_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_m_untied, svfloat32_t, + z0 = svmul_n_f32_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_tied1, svfloat32_t, + z0 = svmul_f32_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_tied2, svfloat32_t, + z0 = svmul_f32_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_z_untied, svfloat32_t, + z0 = svmul_f32_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmul_n_f32_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_z_untied, svfloat32_t, float, + z0 = svmul_n_f32_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f32_z_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f32_z_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_z_tied1, svfloat32_t, + z0 = svmul_n_f32_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_z_untied, svfloat32_t, + z0 = svmul_n_f32_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f32_x_tied1: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_tied1, svfloat32_t, + z0 = svmul_f32_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f32_x_tied2: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_tied2, svfloat32_t, + z0 = svmul_f32_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f32_x_untied: +** fmul z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (mul_f32_x_untied, svfloat32_t, + z0 = svmul_f32_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmul z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmul_n_f32_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_s4_f32_x_untied: +** mov (z[0-9]+\.s), s4 +** fmul z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZD (mul_s4_f32_x_untied, svfloat32_t, float, + z0 = svmul_n_f32_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f32_x_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f32_x_tied1: +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f32_x_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f32_x_tied1: +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f32_x_untied: +** movprfx z0, z1 +** fmul z0\.s, p0/m, z0\.s, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f32_x_tied1: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_tied1, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z0, z1), + z0 = svmul_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_mul_f32_x_tied2: +** fmul z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_tied2, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z1, z0), + z0 = svmul_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_mul_f32_x_untied: +** fmul z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f32_x_untied, svfloat32_t, + z0 = svmul_f32_x (svptrue_b32 (), z1, z2), + z0 = svmul_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_mul_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmul_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_mul_1_f32_x_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmul z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmul_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_mul_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svmul_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svmul_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_mul_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f32_x_tied1, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmul_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_mul_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f32_x_untied, svfloat32_t, + z0 = svmul_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmul_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64.c new file mode 100644 index 00000000000..f5654a9f19d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_tied1, svfloat64_t, + z0 = svmul_f64_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_tied2, svfloat64_t, + z0 = svmul_f64_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_untied, svfloat64_t, + z0 = svmul_f64_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmul_n_f64_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_m_untied, svfloat64_t, double, + z0 = svmul_n_f64_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_tied1, svfloat64_t, + z0 = svmul_f64_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_tied2, svfloat64_t, + z0 = svmul_f64_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_untied, svfloat64_t, + z0 = svmul_f64_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmul_n_f64_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_z_untied, svfloat64_t, double, + z0 = svmul_n_f64_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f64_z_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f64_z_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f64_x_tied1: +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_tied1, svfloat64_t, + z0 = svmul_f64_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f64_x_tied2: +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_tied2, svfloat64_t, + z0 = svmul_f64_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f64_x_untied: +** ( +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_untied, svfloat64_t, + z0 = svmul_f64_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmul_n_f64_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_d4_f64_x_untied: +** mov z0\.d, d4 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_x_untied, svfloat64_t, double, + z0 = svmul_n_f64_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f64_x_untied: +** fmov z0\.d, #1\.0(?:e\+0)? +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f64_x_tied1: +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f64_x_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f64_x_tied1: +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f64_x_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f64_x_tied1: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_tied1, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z0, z1), + z0 = svmul_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_mul_f64_x_tied2: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_tied2, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z1, z0), + z0 = svmul_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_mul_f64_x_untied: +** fmul z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_untied, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z1, z2), + z0 = svmul_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_mul_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmul_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_mul_1_f64_x_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmul_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_mul_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svmul_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svmul_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_mul_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmul_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_mul_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmul_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64_notrap.c new file mode 100644 index 00000000000..d865618d465 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_f64_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_tied1, svfloat64_t, + z0 = svmul_f64_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_tied2, svfloat64_t, + z0 = svmul_f64_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_m_untied, svfloat64_t, + z0 = svmul_f64_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmul_n_f64_m (p0, z0, d4), + z0 = svmul_m (p0, z0, d4)) + +/* +** mul_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_m_untied, svfloat64_t, double, + z0 = svmul_n_f64_m (p0, z1, d4), + z0 = svmul_m (p0, z1, d4)) + +/* +** mul_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 1), + z0 = svmul_m (p0, z0, 1)) + +/* +** mul_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 1), + z0 = svmul_m (p0, z1, 1)) + +/* +** mul_0p5_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 0.5), + z0 = svmul_m (p0, z0, 0.5)) + +/* +** mul_0p5_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 0.5), + z0 = svmul_m (p0, z1, 0.5)) + +/* +** mul_2_f64_m_tied1: +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_m_tied1, svfloat64_t, + z0 = svmul_n_f64_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_f64_m_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_m_untied, svfloat64_t, + z0 = svmul_n_f64_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_tied1, svfloat64_t, + z0 = svmul_f64_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_tied2, svfloat64_t, + z0 = svmul_f64_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_z_untied, svfloat64_t, + z0 = svmul_f64_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmul_n_f64_z (p0, z0, d4), + z0 = svmul_z (p0, z0, d4)) + +/* +** mul_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_z_untied, svfloat64_t, double, + z0 = svmul_n_f64_z (p0, z1, d4), + z0 = svmul_z (p0, z1, d4)) + +/* +** mul_1_f64_z_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 1), + z0 = svmul_z (p0, z0, 1)) + +/* +** mul_1_f64_z_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 1), + z0 = svmul_z (p0, z1, 1)) + +/* +** mul_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 0.5), + z0 = svmul_z (p0, z0, 0.5)) + +/* +** mul_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 0.5), + z0 = svmul_z (p0, z1, 0.5)) + +/* +** mul_2_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_z_tied1, svfloat64_t, + z0 = svmul_n_f64_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_z_untied, svfloat64_t, + z0 = svmul_n_f64_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_f64_x_tied1: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_tied1, svfloat64_t, + z0 = svmul_f64_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_f64_x_tied2: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_tied2, svfloat64_t, + z0 = svmul_f64_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_f64_x_untied: +** fmul z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (mul_f64_x_untied, svfloat64_t, + z0 = svmul_f64_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmul z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmul_n_f64_x (p0, z0, d4), + z0 = svmul_x (p0, z0, d4)) + +/* +** mul_d4_f64_x_untied: +** mov (z[0-9]+\.d), d4 +** fmul z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZD (mul_d4_f64_x_untied, svfloat64_t, double, + z0 = svmul_n_f64_x (p0, z1, d4), + z0 = svmul_x (p0, z1, d4)) + +/* +** mul_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 1), + z0 = svmul_x (p0, z0, 1)) + +/* +** mul_1_f64_x_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (mul_1_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 1), + z0 = svmul_x (p0, z1, 1)) + +/* +** mul_0p5_f64_x_tied1: +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 0.5), + z0 = svmul_x (p0, z0, 0.5)) + +/* +** mul_0p5_f64_x_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (mul_0p5_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 0.5), + z0 = svmul_x (p0, z1, 0.5)) + +/* +** mul_2_f64_x_tied1: +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_f64_x_untied: +** movprfx z0, z1 +** fmul z0\.d, p0/m, z0\.d, #2\.0 +** ret +*/ +TEST_UNIFORM_Z (mul_2_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** ptrue_mul_f64_x_tied1: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_tied1, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z0, z1), + z0 = svmul_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_mul_f64_x_tied2: +** fmul z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_tied2, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z1, z0), + z0 = svmul_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_mul_f64_x_untied: +** fmul z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_f64_x_untied, svfloat64_t, + z0 = svmul_f64_x (svptrue_b64 (), z1, z2), + z0 = svmul_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_mul_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmul_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_mul_1_f64_x_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmul z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_1_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmul_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_mul_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svmul_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_mul_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_0p5_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svmul_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_mul_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f64_x_tied1, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmul_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_mul_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mul_2_f64_x_untied, svfloat64_t, + z0 = svmul_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmul_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f16.c new file mode 100644 index 00000000000..1c7503bfd68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f16.c @@ -0,0 +1,114 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_lane_0_f16_tied1: +** fmul z0\.h, z0\.h, z1\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f16_tied1, svfloat16_t, + z0 = svmul_lane_f16 (z0, z1, 0), + z0 = svmul_lane (z0, z1, 0)) + +/* +** mul_lane_0_f16_tied2: +** fmul z0\.h, z1\.h, z0\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f16_tied2, svfloat16_t, + z0 = svmul_lane_f16 (z1, z0, 0), + z0 = svmul_lane (z1, z0, 0)) + +/* +** mul_lane_0_f16_untied: +** fmul z0\.h, z1\.h, z2\.h\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f16_untied, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 0), + z0 = svmul_lane (z1, z2, 0)) + +/* +** mul_lane_1_f16: +** fmul z0\.h, z1\.h, z2\.h\[1\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_1_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 1), + z0 = svmul_lane (z1, z2, 1)) + +/* +** mul_lane_2_f16: +** fmul z0\.h, z1\.h, z2\.h\[2\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_2_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 2), + z0 = svmul_lane (z1, z2, 2)) + +/* +** mul_lane_3_f16: +** fmul z0\.h, z1\.h, z2\.h\[3\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_3_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 3), + z0 = svmul_lane (z1, z2, 3)) + +/* +** mul_lane_4_f16: +** fmul z0\.h, z1\.h, z2\.h\[4\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_4_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 4), + z0 = svmul_lane (z1, z2, 4)) + +/* +** mul_lane_5_f16: +** fmul z0\.h, z1\.h, z2\.h\[5\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_5_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 5), + z0 = svmul_lane (z1, z2, 5)) + +/* +** mul_lane_6_f16: +** fmul z0\.h, z1\.h, z2\.h\[6\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_6_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 6), + z0 = svmul_lane (z1, z2, 6)) + +/* +** mul_lane_7_f16: +** fmul z0\.h, z1\.h, z2\.h\[7\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_7_f16, svfloat16_t, + z0 = svmul_lane_f16 (z1, z2, 7), + z0 = svmul_lane (z1, z2, 7)) + +/* +** mul_lane_z7_f16: +** fmul z0\.h, z1\.h, z7\.h\[7\] +** ret +*/ +TEST_DUAL_Z (mul_lane_z7_f16, svfloat16_t, svfloat16_t, + z0 = svmul_lane_f16 (z1, z7, 7), + z0 = svmul_lane (z1, z7, 7)) + +/* +** mul_lane_z8_f16: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmul z0\.h, z1\.h, \1\.h\[7\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mul_lane_z8_f16, svfloat16_t, svfloat16_t, z8, + z0 = svmul_lane_f16 (z1, z8, 7), + z0 = svmul_lane (z1, z8, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f32.c new file mode 100644 index 00000000000..5355e7e0b51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f32.c @@ -0,0 +1,78 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_lane_0_f32_tied1: +** fmul z0\.s, z0\.s, z1\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f32_tied1, svfloat32_t, + z0 = svmul_lane_f32 (z0, z1, 0), + z0 = svmul_lane (z0, z1, 0)) + +/* +** mul_lane_0_f32_tied2: +** fmul z0\.s, z1\.s, z0\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f32_tied2, svfloat32_t, + z0 = svmul_lane_f32 (z1, z0, 0), + z0 = svmul_lane (z1, z0, 0)) + +/* +** mul_lane_0_f32_untied: +** fmul z0\.s, z1\.s, z2\.s\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f32_untied, svfloat32_t, + z0 = svmul_lane_f32 (z1, z2, 0), + z0 = svmul_lane (z1, z2, 0)) + +/* +** mul_lane_1_f32: +** fmul z0\.s, z1\.s, z2\.s\[1\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_1_f32, svfloat32_t, + z0 = svmul_lane_f32 (z1, z2, 1), + z0 = svmul_lane (z1, z2, 1)) + +/* +** mul_lane_2_f32: +** fmul z0\.s, z1\.s, z2\.s\[2\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_2_f32, svfloat32_t, + z0 = svmul_lane_f32 (z1, z2, 2), + z0 = svmul_lane (z1, z2, 2)) + +/* +** mul_lane_3_f32: +** fmul z0\.s, z1\.s, z2\.s\[3\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_3_f32, svfloat32_t, + z0 = svmul_lane_f32 (z1, z2, 3), + z0 = svmul_lane (z1, z2, 3)) + +/* +** mul_lane_z7_f32: +** fmul z0\.s, z1\.s, z7\.s\[3\] +** ret +*/ +TEST_DUAL_Z (mul_lane_z7_f32, svfloat32_t, svfloat32_t, + z0 = svmul_lane_f32 (z1, z7, 3), + z0 = svmul_lane (z1, z7, 3)) + +/* +** mul_lane_z8_f32: +** str d8, \[sp, -16\]! +** mov (z[0-7])\.d, z8\.d +** fmul z0\.s, z1\.s, \1\.s\[3\] +** ldr d8, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mul_lane_z8_f32, svfloat32_t, svfloat32_t, z8, + z0 = svmul_lane_f32 (z1, z8, 3), + z0 = svmul_lane (z1, z8, 3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f64.c new file mode 100644 index 00000000000..a53a013c5d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_lane_f64.c @@ -0,0 +1,69 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_lane_0_f64_tied1: +** fmul z0\.d, z0\.d, z1\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f64_tied1, svfloat64_t, + z0 = svmul_lane_f64 (z0, z1, 0), + z0 = svmul_lane (z0, z1, 0)) + +/* +** mul_lane_0_f64_tied2: +** fmul z0\.d, z1\.d, z0\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f64_tied2, svfloat64_t, + z0 = svmul_lane_f64 (z1, z0, 0), + z0 = svmul_lane (z1, z0, 0)) + +/* +** mul_lane_0_f64_untied: +** fmul z0\.d, z1\.d, z2\.d\[0\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_0_f64_untied, svfloat64_t, + z0 = svmul_lane_f64 (z1, z2, 0), + z0 = svmul_lane (z1, z2, 0)) + +/* +** mul_lane_1_f64: +** fmul z0\.d, z1\.d, z2\.d\[1\] +** ret +*/ +TEST_UNIFORM_Z (mul_lane_1_f64, svfloat64_t, + z0 = svmul_lane_f64 (z1, z2, 1), + z0 = svmul_lane (z1, z2, 1)) + +/* +** mul_lane_z7_f64: +** fmul z0\.d, z1\.d, z7\.d\[1\] +** ret +*/ +TEST_DUAL_Z (mul_lane_z7_f64, svfloat64_t, svfloat64_t, + z0 = svmul_lane_f64 (z1, z7, 1), + z0 = svmul_lane (z1, z7, 1)) + +/* +** mul_lane_z15_f64: +** str d15, \[sp, -16\]! +** fmul z0\.d, z1\.d, z15\.d\[1\] +** ldr d15, \[sp\], 16 +** ret +*/ +TEST_DUAL_LANE_REG (mul_lane_z15_f64, svfloat64_t, svfloat64_t, z15, + z0 = svmul_lane_f64 (z1, z15, 1), + z0 = svmul_lane (z1, z15, 1)) + +/* +** mul_lane_z16_f64: +** mov (z[0-9]|z1[0-5])\.d, z16\.d +** fmul z0\.d, z1\.d, \1\.d\[1\] +** ret +*/ +TEST_DUAL_LANE_REG (mul_lane_z16_f64, svfloat64_t, svfloat64_t, z16, + z0 = svmul_lane_f64 (z1, z16, 1), + z0 = svmul_lane (z1, z16, 1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c new file mode 100644 index 00000000000..aa08bc27405 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_s16_m_tied1: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_m_tied1, svint16_t, + z0 = svmul_s16_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_m_tied2, svint16_t, + z0 = svmul_s16_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_s16_m_untied: +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_m_untied, svint16_t, + z0 = svmul_s16_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmul_n_s16_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmul_n_s16_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_s16_m_tied1: +** mov (z[0-9]+\.h), #2 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_m_tied1, svint16_t, + z0 = svmul_n_s16_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #2 +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_m_untied, svint16_t, + z0 = svmul_n_s16_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_s16_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s16_m, svint16_t, + z0 = svmul_n_s16_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_z_tied1, svint16_t, + z0 = svmul_s16_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_z_tied2, svint16_t, + z0 = svmul_s16_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s16_z_untied, svint16_t, + z0 = svmul_s16_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmul_n_s16_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmul_n_s16_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_s16_z_tied1: +** mov (z[0-9]+\.h), #2 +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_z_tied1, svint16_t, + z0 = svmul_n_s16_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_s16_z_untied: +** mov (z[0-9]+\.h), #2 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_z_untied, svint16_t, + z0 = svmul_n_s16_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_s16_x_tied1: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_x_tied1, svint16_t, + z0 = svmul_s16_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_s16_x_tied2: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_s16_x_tied2, svint16_t, + z0 = svmul_s16_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_s16_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s16_x_untied, svint16_t, + z0 = svmul_s16_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmul_n_s16_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_s16_x_untied: +** mov z0\.h, w0 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmul_n_s16_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_s16_x_tied1: +** mul z0\.h, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_x_tied1, svint16_t, + z0 = svmul_n_s16_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_s16_x_untied: +** movprfx z0, z1 +** mul z0\.h, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s16_x_untied, svint16_t, + z0 = svmul_n_s16_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_s16_x: +** mul z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_s16_x: +** mov (z[0-9]+\.h), #128 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_s16_x: +** mov (z[0-9]+\.h), #255 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_s16_x: +** mul z0\.h, z0\.h, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_s16_x: +** mul z0\.h, z0\.h, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_s16_x: +** mul z0\.h, z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_s16_x, svint16_t, + z0 = svmul_n_s16_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c new file mode 100644 index 00000000000..7acf77fdbbf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s32.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_s32_m_tied1: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_m_tied1, svint32_t, + z0 = svmul_s32_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_m_tied2, svint32_t, + z0 = svmul_s32_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_s32_m_untied: +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_m_untied, svint32_t, + z0 = svmul_s32_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmul_n_s32_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmul_n_s32_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_s32_m_tied1: +** mov (z[0-9]+\.s), #2 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_m_tied1, svint32_t, + z0 = svmul_n_s32_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_m_untied, svint32_t, + z0 = svmul_n_s32_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_s32_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s32_m, svint32_t, + z0 = svmul_n_s32_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_z_tied1, svint32_t, + z0 = svmul_s32_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_z_tied2, svint32_t, + z0 = svmul_s32_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s32_z_untied, svint32_t, + z0 = svmul_s32_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmul_n_s32_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmul_n_s32_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_s32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_z_tied1, svint32_t, + z0 = svmul_n_s32_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_s32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_z_untied, svint32_t, + z0 = svmul_n_s32_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_s32_x_tied1: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_x_tied1, svint32_t, + z0 = svmul_s32_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_s32_x_tied2: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_s32_x_tied2, svint32_t, + z0 = svmul_s32_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_s32_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s32_x_untied, svint32_t, + z0 = svmul_s32_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmul_n_s32_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_s32_x_untied: +** mov z0\.s, w0 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmul_n_s32_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_s32_x_tied1: +** mul z0\.s, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_x_tied1, svint32_t, + z0 = svmul_n_s32_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_s32_x_untied: +** movprfx z0, z1 +** mul z0\.s, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s32_x_untied, svint32_t, + z0 = svmul_n_s32_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_s32_x: +** mul z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_s32_x: +** mov (z[0-9]+\.s), #128 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_s32_x: +** mov (z[0-9]+\.s), #255 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_s32_x: +** mul z0\.s, z0\.s, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_s32_x: +** mul z0\.s, z0\.s, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_s32_x: +** mul z0\.s, z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_s32_x, svint32_t, + z0 = svmul_n_s32_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c new file mode 100644 index 00000000000..549105f1efd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s64.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_s64_m_tied1: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_m_tied1, svint64_t, + z0 = svmul_s64_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_s64_m_tied2, svint64_t, + z0 = svmul_s64_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_s64_m_untied: +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_m_untied, svint64_t, + z0 = svmul_s64_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmul_n_s64_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmul_n_s64_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_s64_m_tied1: +** mov (z[0-9]+\.d), #2 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_m_tied1, svint64_t, + z0 = svmul_n_s64_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_m_untied, svint64_t, + z0 = svmul_n_s64_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_s64_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s64_m, svint64_t, + z0 = svmul_n_s64_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_z_tied1, svint64_t, + z0 = svmul_s64_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_z_tied2, svint64_t, + z0 = svmul_s64_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s64_z_untied, svint64_t, + z0 = svmul_s64_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmul_n_s64_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmul_n_s64_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_s64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_z_tied1, svint64_t, + z0 = svmul_n_s64_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_s64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_z_untied, svint64_t, + z0 = svmul_n_s64_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_s64_x_tied1: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_x_tied1, svint64_t, + z0 = svmul_s64_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_s64_x_tied2: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_s64_x_tied2, svint64_t, + z0 = svmul_s64_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_s64_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s64_x_untied, svint64_t, + z0 = svmul_s64_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmul_n_s64_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_x0_s64_x_untied: +** mov z0\.d, x0 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmul_n_s64_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_s64_x_tied1: +** mul z0\.d, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_x_tied1, svint64_t, + z0 = svmul_n_s64_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_s64_x_untied: +** movprfx z0, z1 +** mul z0\.d, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s64_x_untied, svint64_t, + z0 = svmul_n_s64_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_s64_x: +** mul z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_s64_x: +** mov (z[0-9]+\.d), #128 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_s64_x: +** mov (z[0-9]+\.d), #255 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_s64_x: +** mul z0\.d, z0\.d, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_s64_x: +** mul z0\.d, z0\.d, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_s64_x: +** mul z0\.d, z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_s64_x, svint64_t, + z0 = svmul_n_s64_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c new file mode 100644 index 00000000000..012e6f25098 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c @@ -0,0 +1,300 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_s8_m_tied1: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_m_tied1, svint8_t, + z0 = svmul_s8_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_m_tied2, svint8_t, + z0 = svmul_s8_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_s8_m_untied: +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_m_untied, svint8_t, + z0 = svmul_s8_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmul_n_s8_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmul_n_s8_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_s8_m_tied1: +** mov (z[0-9]+\.b), #2 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_m_tied1, svint8_t, + z0 = svmul_n_s8_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #2 +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_m_untied, svint8_t, + z0 = svmul_n_s8_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_s8_m: +** mov (z[0-9]+\.b), #-1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s8_m, svint8_t, + z0 = svmul_n_s8_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_z_tied1, svint8_t, + z0 = svmul_s8_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_z_tied2, svint8_t, + z0 = svmul_s8_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s8_z_untied, svint8_t, + z0 = svmul_s8_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmul_n_s8_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmul_n_s8_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_s8_z_tied1: +** mov (z[0-9]+\.b), #2 +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_z_tied1, svint8_t, + z0 = svmul_n_s8_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_s8_z_untied: +** mov (z[0-9]+\.b), #2 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_z_untied, svint8_t, + z0 = svmul_n_s8_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_s8_x_tied1: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_x_tied1, svint8_t, + z0 = svmul_s8_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_s8_x_tied2: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_s8_x_tied2, svint8_t, + z0 = svmul_s8_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_s8_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_s8_x_untied, svint8_t, + z0 = svmul_s8_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmul_n_s8_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_s8_x_untied: +** mov z0\.b, w0 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmul_n_s8_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_s8_x_tied1: +** mul z0\.b, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_x_tied1, svint8_t, + z0 = svmul_n_s8_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_s8_x_untied: +** movprfx z0, z1 +** mul z0\.b, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_s8_x_untied, svint8_t, + z0 = svmul_n_s8_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_s8_x: +** mul z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_s8_x: +** mul z0\.b, z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_128_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_s8_x: +** mul z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_s8_x: +** mul z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_s8_x: +** mul z0\.b, z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_s8_x: +** mul z0\.b, z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_s8_x, svint8_t, + z0 = svmul_n_s8_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c new file mode 100644 index 00000000000..300987eb6e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_u16_m_tied1: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_m_tied1, svuint16_t, + z0 = svmul_u16_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_m_tied2, svuint16_t, + z0 = svmul_u16_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_u16_m_untied: +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_m_untied, svuint16_t, + z0 = svmul_u16_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmul_n_u16_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmul_n_u16_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_u16_m_tied1: +** mov (z[0-9]+\.h), #2 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_m_tied1, svuint16_t, + z0 = svmul_n_u16_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #2 +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_m_untied, svuint16_t, + z0 = svmul_n_u16_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_u16_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u16_m, svuint16_t, + z0 = svmul_n_u16_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_z_tied1, svuint16_t, + z0 = svmul_u16_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_z_tied2, svuint16_t, + z0 = svmul_u16_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u16_z_untied, svuint16_t, + z0 = svmul_u16_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmul_n_u16_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmul_n_u16_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_u16_z_tied1: +** mov (z[0-9]+\.h), #2 +** movprfx z0\.h, p0/z, z0\.h +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_z_tied1, svuint16_t, + z0 = svmul_n_u16_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_u16_z_untied: +** mov (z[0-9]+\.h), #2 +** ( +** movprfx z0\.h, p0/z, z1\.h +** mul z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_z_untied, svuint16_t, + z0 = svmul_n_u16_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_u16_x_tied1: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_x_tied1, svuint16_t, + z0 = svmul_u16_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_u16_x_tied2: +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mul_u16_x_tied2, svuint16_t, + z0 = svmul_u16_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_u16_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u16_x_untied, svuint16_t, + z0 = svmul_u16_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmul_n_u16_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_u16_x_untied: +** mov z0\.h, w0 +** mul z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmul_n_u16_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_u16_x_tied1: +** mul z0\.h, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_x_tied1, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_u16_x_untied: +** movprfx z0, z1 +** mul z0\.h, z0\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u16_x_untied, svuint16_t, + z0 = svmul_n_u16_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_u16_x: +** mul z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_u16_x: +** mov (z[0-9]+\.h), #128 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_u16_x: +** mov (z[0-9]+\.h), #255 +** mul z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_u16_x: +** mul z0\.h, z0\.h, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_u16_x: +** mul z0\.h, z0\.h, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_u16_x: +** mul z0\.h, z0\.h, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_u16_x, svuint16_t, + z0 = svmul_n_u16_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c new file mode 100644 index 00000000000..288d17b163c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u32.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_u32_m_tied1: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_m_tied1, svuint32_t, + z0 = svmul_u32_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_m_tied2, svuint32_t, + z0 = svmul_u32_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_u32_m_untied: +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_m_untied, svuint32_t, + z0 = svmul_u32_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmul_n_u32_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmul_n_u32_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_u32_m_tied1: +** mov (z[0-9]+\.s), #2 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_m_tied1, svuint32_t, + z0 = svmul_n_u32_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #2 +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_m_untied, svuint32_t, + z0 = svmul_n_u32_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_u32_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u32_m, svuint32_t, + z0 = svmul_n_u32_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_z_tied1, svuint32_t, + z0 = svmul_u32_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_z_tied2, svuint32_t, + z0 = svmul_u32_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u32_z_untied, svuint32_t, + z0 = svmul_u32_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmul_n_u32_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmul_n_u32_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_u32_z_tied1: +** mov (z[0-9]+\.s), #2 +** movprfx z0\.s, p0/z, z0\.s +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_z_tied1, svuint32_t, + z0 = svmul_n_u32_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_u32_z_untied: +** mov (z[0-9]+\.s), #2 +** ( +** movprfx z0\.s, p0/z, z1\.s +** mul z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_z_untied, svuint32_t, + z0 = svmul_n_u32_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_u32_x_tied1: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_x_tied1, svuint32_t, + z0 = svmul_u32_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_u32_x_tied2: +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mul_u32_x_tied2, svuint32_t, + z0 = svmul_u32_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_u32_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u32_x_untied, svuint32_t, + z0 = svmul_u32_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmul_n_u32_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_u32_x_untied: +** mov z0\.s, w0 +** mul z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmul_n_u32_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_u32_x_tied1: +** mul z0\.s, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_x_tied1, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_u32_x_untied: +** movprfx z0, z1 +** mul z0\.s, z0\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u32_x_untied, svuint32_t, + z0 = svmul_n_u32_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_u32_x: +** mul z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_u32_x: +** mov (z[0-9]+\.s), #128 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_u32_x: +** mov (z[0-9]+\.s), #255 +** mul z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_u32_x: +** mul z0\.s, z0\.s, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_u32_x: +** mul z0\.s, z0\.s, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_u32_x: +** mul z0\.s, z0\.s, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_u32_x, svuint32_t, + z0 = svmul_n_u32_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c new file mode 100644 index 00000000000..f6959dbc723 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u64.c @@ -0,0 +1,302 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_u64_m_tied1: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_m_tied1, svuint64_t, + z0 = svmul_u64_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_u64_m_tied2, svuint64_t, + z0 = svmul_u64_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_u64_m_untied: +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_m_untied, svuint64_t, + z0 = svmul_u64_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmul_n_u64_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmul_n_u64_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_u64_m_tied1: +** mov (z[0-9]+\.d), #2 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_m_tied1, svuint64_t, + z0 = svmul_n_u64_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #2 +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_m_untied, svuint64_t, + z0 = svmul_n_u64_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_u64_m: +** mov (z[0-9]+)\.b, #-1 +** mul z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u64_m, svuint64_t, + z0 = svmul_n_u64_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_z_tied1, svuint64_t, + z0 = svmul_u64_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_z_tied2, svuint64_t, + z0 = svmul_u64_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u64_z_untied, svuint64_t, + z0 = svmul_u64_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmul_n_u64_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmul_n_u64_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_u64_z_tied1: +** mov (z[0-9]+\.d), #2 +** movprfx z0\.d, p0/z, z0\.d +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_z_tied1, svuint64_t, + z0 = svmul_n_u64_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_u64_z_untied: +** mov (z[0-9]+\.d), #2 +** ( +** movprfx z0\.d, p0/z, z1\.d +** mul z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_z_untied, svuint64_t, + z0 = svmul_n_u64_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_u64_x_tied1: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_x_tied1, svuint64_t, + z0 = svmul_u64_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_u64_x_tied2: +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mul_u64_x_tied2, svuint64_t, + z0 = svmul_u64_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_u64_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u64_x_untied, svuint64_t, + z0 = svmul_u64_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmul_n_u64_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_x0_u64_x_untied: +** mov z0\.d, x0 +** mul z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mul_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmul_n_u64_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_u64_x_tied1: +** mul z0\.d, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_x_tied1, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_u64_x_untied: +** movprfx z0, z1 +** mul z0\.d, z0\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u64_x_untied, svuint64_t, + z0 = svmul_n_u64_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_u64_x: +** mul z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_u64_x: +** mov (z[0-9]+\.d), #128 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_128_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_u64_x: +** mov (z[0-9]+\.d), #255 +** mul z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_u64_x: +** mul z0\.d, z0\.d, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_u64_x: +** mul z0\.d, z0\.d, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_u64_x: +** mul z0\.d, z0\.d, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_u64_x, svuint64_t, + z0 = svmul_n_u64_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c new file mode 100644 index 00000000000..b2745a48f50 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c @@ -0,0 +1,300 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mul_u8_m_tied1: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_m_tied1, svuint8_t, + z0 = svmul_u8_m (p0, z0, z1), + z0 = svmul_m (p0, z0, z1)) + +/* +** mul_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_m_tied2, svuint8_t, + z0 = svmul_u8_m (p0, z1, z0), + z0 = svmul_m (p0, z1, z0)) + +/* +** mul_u8_m_untied: +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_m_untied, svuint8_t, + z0 = svmul_u8_m (p0, z1, z2), + z0 = svmul_m (p0, z1, z2)) + +/* +** mul_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmul_n_u8_m (p0, z0, x0), + z0 = svmul_m (p0, z0, x0)) + +/* +** mul_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmul_n_u8_m (p0, z1, x0), + z0 = svmul_m (p0, z1, x0)) + +/* +** mul_2_u8_m_tied1: +** mov (z[0-9]+\.b), #2 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_m_tied1, svuint8_t, + z0 = svmul_n_u8_m (p0, z0, 2), + z0 = svmul_m (p0, z0, 2)) + +/* +** mul_2_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #2 +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_m_untied, svuint8_t, + z0 = svmul_n_u8_m (p0, z1, 2), + z0 = svmul_m (p0, z1, 2)) + +/* +** mul_m1_u8_m: +** mov (z[0-9]+\.b), #-1 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u8_m, svuint8_t, + z0 = svmul_n_u8_m (p0, z0, -1), + z0 = svmul_m (p0, z0, -1)) + +/* +** mul_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_z_tied1, svuint8_t, + z0 = svmul_u8_z (p0, z0, z1), + z0 = svmul_z (p0, z0, z1)) + +/* +** mul_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_z_tied2, svuint8_t, + z0 = svmul_u8_z (p0, z1, z0), + z0 = svmul_z (p0, z1, z0)) + +/* +** mul_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u8_z_untied, svuint8_t, + z0 = svmul_u8_z (p0, z1, z2), + z0 = svmul_z (p0, z1, z2)) + +/* +** mul_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmul_n_u8_z (p0, z0, x0), + z0 = svmul_z (p0, z0, x0)) + +/* +** mul_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmul_n_u8_z (p0, z1, x0), + z0 = svmul_z (p0, z1, x0)) + +/* +** mul_2_u8_z_tied1: +** mov (z[0-9]+\.b), #2 +** movprfx z0\.b, p0/z, z0\.b +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_z_tied1, svuint8_t, + z0 = svmul_n_u8_z (p0, z0, 2), + z0 = svmul_z (p0, z0, 2)) + +/* +** mul_2_u8_z_untied: +** mov (z[0-9]+\.b), #2 +** ( +** movprfx z0\.b, p0/z, z1\.b +** mul z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_z_untied, svuint8_t, + z0 = svmul_n_u8_z (p0, z1, 2), + z0 = svmul_z (p0, z1, 2)) + +/* +** mul_u8_x_tied1: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_x_tied1, svuint8_t, + z0 = svmul_u8_x (p0, z0, z1), + z0 = svmul_x (p0, z0, z1)) + +/* +** mul_u8_x_tied2: +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mul_u8_x_tied2, svuint8_t, + z0 = svmul_u8_x (p0, z1, z0), + z0 = svmul_x (p0, z1, z0)) + +/* +** mul_u8_x_untied: +** ( +** movprfx z0, z1 +** mul z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mul_u8_x_untied, svuint8_t, + z0 = svmul_u8_x (p0, z1, z2), + z0 = svmul_x (p0, z1, z2)) + +/* +** mul_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** mul z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmul_n_u8_x (p0, z0, x0), + z0 = svmul_x (p0, z0, x0)) + +/* +** mul_w0_u8_x_untied: +** mov z0\.b, w0 +** mul z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mul_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmul_n_u8_x (p0, z1, x0), + z0 = svmul_x (p0, z1, x0)) + +/* +** mul_2_u8_x_tied1: +** mul z0\.b, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_x_tied1, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, 2), + z0 = svmul_x (p0, z0, 2)) + +/* +** mul_2_u8_x_untied: +** movprfx z0, z1 +** mul z0\.b, z0\.b, #2 +** ret +*/ +TEST_UNIFORM_Z (mul_2_u8_x_untied, svuint8_t, + z0 = svmul_n_u8_x (p0, z1, 2), + z0 = svmul_x (p0, z1, 2)) + +/* +** mul_127_u8_x: +** mul z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (mul_127_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, 127), + z0 = svmul_x (p0, z0, 127)) + +/* +** mul_128_u8_x: +** mul z0\.b, z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_128_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, 128), + z0 = svmul_x (p0, z0, 128)) + +/* +** mul_255_u8_x: +** mul z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_255_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, 255), + z0 = svmul_x (p0, z0, 255)) + +/* +** mul_m1_u8_x: +** mul z0\.b, z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (mul_m1_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, -1), + z0 = svmul_x (p0, z0, -1)) + +/* +** mul_m127_u8_x: +** mul z0\.b, z0\.b, #-127 +** ret +*/ +TEST_UNIFORM_Z (mul_m127_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, -127), + z0 = svmul_x (p0, z0, -127)) + +/* +** mul_m128_u8_x: +** mul z0\.b, z0\.b, #-128 +** ret +*/ +TEST_UNIFORM_Z (mul_m128_u8_x, svuint8_t, + z0 = svmul_n_u8_x (p0, z0, -128), + z0 = svmul_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c new file mode 100644 index 00000000000..a81532f5d89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s16_m_tied1: +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_m_tied1, svint16_t, + z0 = svmulh_s16_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smulh z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_m_tied2, svint16_t, + z0 = svmulh_s16_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_s16_m_untied: +** movprfx z0, z1 +** smulh z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_m_untied, svint16_t, + z0 = svmulh_s16_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svmulh_n_s16_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_m_untied, svint16_t, int16_t, + z0 = svmulh_n_s16_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_s16_m_tied1: +** mov (z[0-9]+\.h), #11 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_m_tied1, svint16_t, + z0 = svmulh_n_s16_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_m_untied, svint16_t, + z0 = svmulh_n_s16_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_z_tied1, svint16_t, + z0 = svmulh_s16_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_z_tied2, svint16_t, + z0 = svmulh_s16_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** smulh z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_z_untied, svint16_t, + z0 = svmulh_s16_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svmulh_n_s16_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smulh z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_z_untied, svint16_t, int16_t, + z0 = svmulh_n_s16_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_s16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_z_tied1, svint16_t, + z0 = svmulh_n_s16_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_s16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** smulh z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_z_untied, svint16_t, + z0 = svmulh_n_s16_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_s16_x_tied1: +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_tied1, svint16_t, + z0 = svmulh_s16_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s16_x_tied2: +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_tied2, svint16_t, + z0 = svmulh_s16_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s16_x_untied: +** ( +** movprfx z0, z1 +** smulh z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s16_x_untied, svint16_t, + z0 = svmulh_s16_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svmulh_n_s16_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s16_x_untied: +** mov z0\.h, w0 +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s16_x_untied, svint16_t, int16_t, + z0 = svmulh_n_s16_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s16_x_tied1: +** mov (z[0-9]+\.h), #11 +** smulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_x_tied1, svint16_t, + z0 = svmulh_n_s16_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s16_x_untied: +** mov z0\.h, #11 +** smulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s16_x_untied, svint16_t, + z0 = svmulh_n_s16_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s32.c new file mode 100644 index 00000000000..078feeb6a32 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s32_m_tied1: +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_m_tied1, svint32_t, + z0 = svmulh_s32_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smulh z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_m_tied2, svint32_t, + z0 = svmulh_s32_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_s32_m_untied: +** movprfx z0, z1 +** smulh z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_m_untied, svint32_t, + z0 = svmulh_s32_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svmulh_n_s32_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_m_untied, svint32_t, int32_t, + z0 = svmulh_n_s32_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_s32_m_tied1: +** mov (z[0-9]+\.s), #11 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_m_tied1, svint32_t, + z0 = svmulh_n_s32_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_m_untied, svint32_t, + z0 = svmulh_n_s32_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_z_tied1, svint32_t, + z0 = svmulh_s32_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_z_tied2, svint32_t, + z0 = svmulh_s32_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** smulh z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_z_untied, svint32_t, + z0 = svmulh_s32_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svmulh_n_s32_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smulh z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_z_untied, svint32_t, int32_t, + z0 = svmulh_n_s32_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_s32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_z_tied1, svint32_t, + z0 = svmulh_n_s32_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_s32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** smulh z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_z_untied, svint32_t, + z0 = svmulh_n_s32_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_s32_x_tied1: +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_tied1, svint32_t, + z0 = svmulh_s32_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s32_x_tied2: +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_tied2, svint32_t, + z0 = svmulh_s32_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s32_x_untied: +** ( +** movprfx z0, z1 +** smulh z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s32_x_untied, svint32_t, + z0 = svmulh_s32_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svmulh_n_s32_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s32_x_untied: +** mov z0\.s, w0 +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s32_x_untied, svint32_t, int32_t, + z0 = svmulh_n_s32_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s32_x_tied1: +** mov (z[0-9]+\.s), #11 +** smulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_x_tied1, svint32_t, + z0 = svmulh_n_s32_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s32_x_untied: +** mov z0\.s, #11 +** smulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s32_x_untied, svint32_t, + z0 = svmulh_n_s32_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s64.c new file mode 100644 index 00000000000..a87d4d5ce0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s64_m_tied1: +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_m_tied1, svint64_t, + z0 = svmulh_s64_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_m_tied2, svint64_t, + z0 = svmulh_s64_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_s64_m_untied: +** movprfx z0, z1 +** smulh z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_m_untied, svint64_t, + z0 = svmulh_s64_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svmulh_n_s64_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_m_untied, svint64_t, int64_t, + z0 = svmulh_n_s64_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_s64_m_tied1: +** mov (z[0-9]+\.d), #11 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_m_tied1, svint64_t, + z0 = svmulh_n_s64_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_m_untied, svint64_t, + z0 = svmulh_n_s64_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_z_tied1, svint64_t, + z0 = svmulh_s64_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_z_tied2, svint64_t, + z0 = svmulh_s64_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** smulh z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_z_untied, svint64_t, + z0 = svmulh_s64_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svmulh_n_s64_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smulh z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_z_untied, svint64_t, int64_t, + z0 = svmulh_n_s64_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_s64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_z_tied1, svint64_t, + z0 = svmulh_n_s64_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_s64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** smulh z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_z_untied, svint64_t, + z0 = svmulh_n_s64_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_s64_x_tied1: +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_tied1, svint64_t, + z0 = svmulh_s64_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s64_x_tied2: +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_tied2, svint64_t, + z0 = svmulh_s64_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s64_x_untied: +** ( +** movprfx z0, z1 +** smulh z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s64_x_untied, svint64_t, + z0 = svmulh_s64_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svmulh_n_s64_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_x0_s64_x_untied: +** mov z0\.d, x0 +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_s64_x_untied, svint64_t, int64_t, + z0 = svmulh_n_s64_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s64_x_tied1: +** mov (z[0-9]+\.d), #11 +** smulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_x_tied1, svint64_t, + z0 = svmulh_n_s64_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s64_x_untied: +** mov z0\.d, #11 +** smulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s64_x_untied, svint64_t, + z0 = svmulh_n_s64_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c new file mode 100644 index 00000000000..f9cd01afdc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_s8_m_tied1: +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_m_tied1, svint8_t, + z0 = svmulh_s8_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** smulh z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_m_tied2, svint8_t, + z0 = svmulh_s8_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_s8_m_untied: +** movprfx z0, z1 +** smulh z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_m_untied, svint8_t, + z0 = svmulh_s8_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svmulh_n_s8_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_m_untied, svint8_t, int8_t, + z0 = svmulh_n_s8_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_s8_m_tied1: +** mov (z[0-9]+\.b), #11 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_m_tied1, svint8_t, + z0 = svmulh_n_s8_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_m_untied, svint8_t, + z0 = svmulh_n_s8_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_z_tied1, svint8_t, + z0 = svmulh_s8_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_z_tied2, svint8_t, + z0 = svmulh_s8_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** smulh z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_z_untied, svint8_t, + z0 = svmulh_s8_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svmulh_n_s8_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smulh z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_z_untied, svint8_t, int8_t, + z0 = svmulh_n_s8_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_s8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_z_tied1, svint8_t, + z0 = svmulh_n_s8_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_s8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** smulh z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_z_untied, svint8_t, + z0 = svmulh_n_s8_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_s8_x_tied1: +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_tied1, svint8_t, + z0 = svmulh_s8_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_s8_x_tied2: +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_tied2, svint8_t, + z0 = svmulh_s8_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_s8_x_untied: +** ( +** movprfx z0, z1 +** smulh z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_s8_x_untied, svint8_t, + z0 = svmulh_s8_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svmulh_n_s8_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_s8_x_untied: +** mov z0\.b, w0 +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_s8_x_untied, svint8_t, int8_t, + z0 = svmulh_n_s8_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_s8_x_tied1: +** mov (z[0-9]+\.b), #11 +** smulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_x_tied1, svint8_t, + z0 = svmulh_n_s8_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_s8_x_untied: +** mov z0\.b, #11 +** smulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_11_s8_x_untied, svint8_t, + z0 = svmulh_n_s8_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c new file mode 100644 index 00000000000..e9173eb243e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u16_m_tied1: +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_m_tied1, svuint16_t, + z0 = svmulh_u16_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umulh z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_m_tied2, svuint16_t, + z0 = svmulh_u16_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_u16_m_untied: +** movprfx z0, z1 +** umulh z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_m_untied, svuint16_t, + z0 = svmulh_u16_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svmulh_n_u16_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svmulh_n_u16_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_u16_m_tied1: +** mov (z[0-9]+\.h), #11 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_m_tied1, svuint16_t, + z0 = svmulh_n_u16_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #11 +** movprfx z0, z1 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_m_untied, svuint16_t, + z0 = svmulh_n_u16_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_z_tied1, svuint16_t, + z0 = svmulh_u16_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_z_tied2, svuint16_t, + z0 = svmulh_u16_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** umulh z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_z_untied, svuint16_t, + z0 = svmulh_u16_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svmulh_n_u16_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umulh z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svmulh_n_u16_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_u16_z_tied1: +** mov (z[0-9]+\.h), #11 +** movprfx z0\.h, p0/z, z0\.h +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_z_tied1, svuint16_t, + z0 = svmulh_n_u16_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_u16_z_untied: +** mov (z[0-9]+\.h), #11 +** ( +** movprfx z0\.h, p0/z, z1\.h +** umulh z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_z_untied, svuint16_t, + z0 = svmulh_n_u16_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_u16_x_tied1: +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_tied1, svuint16_t, + z0 = svmulh_u16_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u16_x_tied2: +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_tied2, svuint16_t, + z0 = svmulh_u16_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u16_x_untied: +** ( +** movprfx z0, z1 +** umulh z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u16_x_untied, svuint16_t, + z0 = svmulh_u16_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svmulh_n_u16_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u16_x_untied: +** mov z0\.h, w0 +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svmulh_n_u16_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u16_x_tied1: +** mov (z[0-9]+\.h), #11 +** umulh z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_x_tied1, svuint16_t, + z0 = svmulh_n_u16_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u16_x_untied: +** mov z0\.h, #11 +** umulh z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u16_x_untied, svuint16_t, + z0 = svmulh_n_u16_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u32.c new file mode 100644 index 00000000000..de1f24f090c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u32.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u32_m_tied1: +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_m_tied1, svuint32_t, + z0 = svmulh_u32_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umulh z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_m_tied2, svuint32_t, + z0 = svmulh_u32_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_u32_m_untied: +** movprfx z0, z1 +** umulh z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_m_untied, svuint32_t, + z0 = svmulh_u32_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svmulh_n_u32_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svmulh_n_u32_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_u32_m_tied1: +** mov (z[0-9]+\.s), #11 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_m_tied1, svuint32_t, + z0 = svmulh_n_u32_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #11 +** movprfx z0, z1 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_m_untied, svuint32_t, + z0 = svmulh_n_u32_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_z_tied1, svuint32_t, + z0 = svmulh_u32_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_z_tied2, svuint32_t, + z0 = svmulh_u32_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** umulh z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_z_untied, svuint32_t, + z0 = svmulh_u32_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svmulh_n_u32_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umulh z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svmulh_n_u32_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_u32_z_tied1: +** mov (z[0-9]+\.s), #11 +** movprfx z0\.s, p0/z, z0\.s +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_z_tied1, svuint32_t, + z0 = svmulh_n_u32_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_u32_z_untied: +** mov (z[0-9]+\.s), #11 +** ( +** movprfx z0\.s, p0/z, z1\.s +** umulh z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_z_untied, svuint32_t, + z0 = svmulh_n_u32_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_u32_x_tied1: +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_tied1, svuint32_t, + z0 = svmulh_u32_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u32_x_tied2: +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_tied2, svuint32_t, + z0 = svmulh_u32_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u32_x_untied: +** ( +** movprfx z0, z1 +** umulh z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u32_x_untied, svuint32_t, + z0 = svmulh_u32_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svmulh_n_u32_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u32_x_untied: +** mov z0\.s, w0 +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svmulh_n_u32_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u32_x_tied1: +** mov (z[0-9]+\.s), #11 +** umulh z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_x_tied1, svuint32_t, + z0 = svmulh_n_u32_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u32_x_untied: +** mov z0\.s, #11 +** umulh z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u32_x_untied, svuint32_t, + z0 = svmulh_n_u32_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u64.c new file mode 100644 index 00000000000..0d7e12a7c84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u64.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u64_m_tied1: +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_m_tied1, svuint64_t, + z0 = svmulh_u64_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_m_tied2, svuint64_t, + z0 = svmulh_u64_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_u64_m_untied: +** movprfx z0, z1 +** umulh z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_m_untied, svuint64_t, + z0 = svmulh_u64_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svmulh_n_u64_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svmulh_n_u64_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_u64_m_tied1: +** mov (z[0-9]+\.d), #11 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_m_tied1, svuint64_t, + z0 = svmulh_n_u64_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #11 +** movprfx z0, z1 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_m_untied, svuint64_t, + z0 = svmulh_n_u64_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_z_tied1, svuint64_t, + z0 = svmulh_u64_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_z_tied2, svuint64_t, + z0 = svmulh_u64_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** umulh z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_z_untied, svuint64_t, + z0 = svmulh_u64_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svmulh_n_u64_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umulh z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svmulh_n_u64_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_u64_z_tied1: +** mov (z[0-9]+\.d), #11 +** movprfx z0\.d, p0/z, z0\.d +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_z_tied1, svuint64_t, + z0 = svmulh_n_u64_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_u64_z_untied: +** mov (z[0-9]+\.d), #11 +** ( +** movprfx z0\.d, p0/z, z1\.d +** umulh z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_z_untied, svuint64_t, + z0 = svmulh_n_u64_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_u64_x_tied1: +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_tied1, svuint64_t, + z0 = svmulh_u64_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u64_x_tied2: +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_tied2, svuint64_t, + z0 = svmulh_u64_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u64_x_untied: +** ( +** movprfx z0, z1 +** umulh z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u64_x_untied, svuint64_t, + z0 = svmulh_u64_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svmulh_n_u64_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_x0_u64_x_untied: +** mov z0\.d, x0 +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (mulh_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svmulh_n_u64_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u64_x_tied1: +** mov (z[0-9]+\.d), #11 +** umulh z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_x_tied1, svuint64_t, + z0 = svmulh_n_u64_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u64_x_untied: +** mov z0\.d, #11 +** umulh z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u64_x_untied, svuint64_t, + z0 = svmulh_n_u64_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c new file mode 100644 index 00000000000..db7b1be1bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c @@ -0,0 +1,237 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulh_u8_m_tied1: +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_m_tied1, svuint8_t, + z0 = svmulh_u8_m (p0, z0, z1), + z0 = svmulh_m (p0, z0, z1)) + +/* +** mulh_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** umulh z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_m_tied2, svuint8_t, + z0 = svmulh_u8_m (p0, z1, z0), + z0 = svmulh_m (p0, z1, z0)) + +/* +** mulh_u8_m_untied: +** movprfx z0, z1 +** umulh z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_m_untied, svuint8_t, + z0 = svmulh_u8_m (p0, z1, z2), + z0 = svmulh_m (p0, z1, z2)) + +/* +** mulh_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svmulh_n_u8_m (p0, z0, x0), + z0 = svmulh_m (p0, z0, x0)) + +/* +** mulh_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svmulh_n_u8_m (p0, z1, x0), + z0 = svmulh_m (p0, z1, x0)) + +/* +** mulh_11_u8_m_tied1: +** mov (z[0-9]+\.b), #11 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_m_tied1, svuint8_t, + z0 = svmulh_n_u8_m (p0, z0, 11), + z0 = svmulh_m (p0, z0, 11)) + +/* +** mulh_11_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #11 +** movprfx z0, z1 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_m_untied, svuint8_t, + z0 = svmulh_n_u8_m (p0, z1, 11), + z0 = svmulh_m (p0, z1, 11)) + +/* +** mulh_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_z_tied1, svuint8_t, + z0 = svmulh_u8_z (p0, z0, z1), + z0 = svmulh_z (p0, z0, z1)) + +/* +** mulh_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_z_tied2, svuint8_t, + z0 = svmulh_u8_z (p0, z1, z0), + z0 = svmulh_z (p0, z1, z0)) + +/* +** mulh_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** umulh z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_z_untied, svuint8_t, + z0 = svmulh_u8_z (p0, z1, z2), + z0 = svmulh_z (p0, z1, z2)) + +/* +** mulh_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svmulh_n_u8_z (p0, z0, x0), + z0 = svmulh_z (p0, z0, x0)) + +/* +** mulh_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umulh z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svmulh_n_u8_z (p0, z1, x0), + z0 = svmulh_z (p0, z1, x0)) + +/* +** mulh_11_u8_z_tied1: +** mov (z[0-9]+\.b), #11 +** movprfx z0\.b, p0/z, z0\.b +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_z_tied1, svuint8_t, + z0 = svmulh_n_u8_z (p0, z0, 11), + z0 = svmulh_z (p0, z0, 11)) + +/* +** mulh_11_u8_z_untied: +** mov (z[0-9]+\.b), #11 +** ( +** movprfx z0\.b, p0/z, z1\.b +** umulh z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_z_untied, svuint8_t, + z0 = svmulh_n_u8_z (p0, z1, 11), + z0 = svmulh_z (p0, z1, 11)) + +/* +** mulh_u8_x_tied1: +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_tied1, svuint8_t, + z0 = svmulh_u8_x (p0, z0, z1), + z0 = svmulh_x (p0, z0, z1)) + +/* +** mulh_u8_x_tied2: +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_tied2, svuint8_t, + z0 = svmulh_u8_x (p0, z1, z0), + z0 = svmulh_x (p0, z1, z0)) + +/* +** mulh_u8_x_untied: +** ( +** movprfx z0, z1 +** umulh z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0, z2 +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (mulh_u8_x_untied, svuint8_t, + z0 = svmulh_u8_x (p0, z1, z2), + z0 = svmulh_x (p0, z1, z2)) + +/* +** mulh_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svmulh_n_u8_x (p0, z0, x0), + z0 = svmulh_x (p0, z0, x0)) + +/* +** mulh_w0_u8_x_untied: +** mov z0\.b, w0 +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (mulh_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svmulh_n_u8_x (p0, z1, x0), + z0 = svmulh_x (p0, z1, x0)) + +/* +** mulh_11_u8_x_tied1: +** mov (z[0-9]+\.b), #11 +** umulh z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_x_tied1, svuint8_t, + z0 = svmulh_n_u8_x (p0, z0, 11), + z0 = svmulh_x (p0, z0, 11)) + +/* +** mulh_11_u8_x_untied: +** mov z0\.b, #11 +** umulh z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (mulh_11_u8_x_untied, svuint8_t, + z0 = svmulh_n_u8_x (p0, z1, 11), + z0 = svmulh_x (p0, z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f16.c new file mode 100644 index 00000000000..ce02c3caa39 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f16.c @@ -0,0 +1,472 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulx_f16_m_tied1: +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_m_tied1, svfloat16_t, + z0 = svmulx_f16_m (p0, z0, z1), + z0 = svmulx_m (p0, z0, z1)) + +/* +** mulx_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_m_tied2, svfloat16_t, + z0 = svmulx_f16_m (p0, z1, z0), + z0 = svmulx_m (p0, z1, z0)) + +/* +** mulx_f16_m_untied: +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_m_untied, svfloat16_t, + z0 = svmulx_f16_m (p0, z1, z2), + z0 = svmulx_m (p0, z1, z2)) + +/* +** mulx_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svmulx_n_f16_m (p0, z0, d4), + z0 = svmulx_m (p0, z0, d4)) + +/* +** mulx_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svmulx_n_f16_m (p0, z1, d4), + z0 = svmulx_m (p0, z1, d4)) + +/* +** mulx_1_f16_m_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_m_tied1, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z0, 1), + z0 = svmulx_m (p0, z0, 1)) + +/* +** mulx_1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_m_untied, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z1, 1), + z0 = svmulx_m (p0, z1, 1)) + +/* +** mulx_0p5_f16_m_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_m_tied1, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z0, 0.5), + z0 = svmulx_m (p0, z0, 0.5)) + +/* +** mulx_0p5_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_m_untied, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z1, 0.5), + z0 = svmulx_m (p0, z1, 0.5)) + +/* +** mulx_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_m_tied1, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z0, 2), + z0 = svmulx_m (p0, z0, 2)) + +/* +** mulx_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_m_untied, svfloat16_t, + z0 = svmulx_n_f16_m (p0, z1, 2), + z0 = svmulx_m (p0, z1, 2)) + +/* +** mulx_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_z_tied1, svfloat16_t, + z0 = svmulx_f16_z (p0, z0, z1), + z0 = svmulx_z (p0, z0, z1)) + +/* +** mulx_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_z_tied2, svfloat16_t, + z0 = svmulx_f16_z (p0, z1, z0), + z0 = svmulx_z (p0, z1, z0)) + +/* +** mulx_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmulx z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_z_untied, svfloat16_t, + z0 = svmulx_f16_z (p0, z1, z2), + z0 = svmulx_z (p0, z1, z2)) + +/* +** mulx_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svmulx_n_f16_z (p0, z0, d4), + z0 = svmulx_z (p0, z0, d4)) + +/* +** mulx_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svmulx_n_f16_z (p0, z1, d4), + z0 = svmulx_z (p0, z1, d4)) + +/* +** mulx_1_f16_z_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_z_tied1, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z0, 1), + z0 = svmulx_z (p0, z0, 1)) + +/* +** mulx_1_f16_z_untied: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_z_untied, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z1, 1), + z0 = svmulx_z (p0, z1, 1)) + +/* +** mulx_0p5_f16_z_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_z_tied1, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z0, 0.5), + z0 = svmulx_z (p0, z0, 0.5)) + +/* +** mulx_0p5_f16_z_untied: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_z_untied, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z1, 0.5), + z0 = svmulx_z (p0, z1, 0.5)) + +/* +** mulx_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_z_tied1, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z0, 2), + z0 = svmulx_z (p0, z0, 2)) + +/* +** mulx_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fmulx z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_z_untied, svfloat16_t, + z0 = svmulx_n_f16_z (p0, z1, 2), + z0 = svmulx_z (p0, z1, 2)) + +/* +** mulx_f16_x_tied1: +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_x_tied1, svfloat16_t, + z0 = svmulx_f16_x (p0, z0, z1), + z0 = svmulx_x (p0, z0, z1)) + +/* +** mulx_f16_x_tied2: +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_x_tied2, svfloat16_t, + z0 = svmulx_f16_x (p0, z1, z0), + z0 = svmulx_x (p0, z1, z0)) + +/* +** mulx_f16_x_untied: +** ( +** movprfx z0, z1 +** fmulx z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f16_x_untied, svfloat16_t, + z0 = svmulx_f16_x (p0, z1, z2), + z0 = svmulx_x (p0, z1, z2)) + +/* +** mulx_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svmulx_n_f16_x (p0, z0, d4), + z0 = svmulx_x (p0, z0, d4)) + +/* +** mulx_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (mulx_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svmulx_n_f16_x (p0, z1, d4), + z0 = svmulx_x (p0, z1, d4)) + +/* +** mulx_1_f16_x_tied1: +** fmov (z[0-9]+\.h), #1\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z0, 1), + z0 = svmulx_x (p0, z0, 1)) + +/* +** mulx_1_f16_x_untied: +** fmov z0\.h, #1\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z1, 1), + z0 = svmulx_x (p0, z1, 1)) + +/* +** mulx_0p5_f16_x_tied1: +** fmov (z[0-9]+\.h), #(?:0\.5|5\.0e-1) +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z0, 0.5), + z0 = svmulx_x (p0, z0, 0.5)) + +/* +** mulx_0p5_f16_x_untied: +** fmov z0\.h, #(?:0\.5|5\.0e-1) +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z1, 0.5), + z0 = svmulx_x (p0, z1, 0.5)) + +/* +** mulx_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z0, 2), + z0 = svmulx_x (p0, z0, 2)) + +/* +** mulx_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fmulx z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (p0, z1, 2), + z0 = svmulx_x (p0, z1, 2)) + +/* +** ptrue_mulx_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f16_x_tied1, svfloat16_t, + z0 = svmulx_f16_x (svptrue_b16 (), z0, z1), + z0 = svmulx_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_mulx_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f16_x_tied2, svfloat16_t, + z0 = svmulx_f16_x (svptrue_b16 (), z1, z0), + z0 = svmulx_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_mulx_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f16_x_untied, svfloat16_t, + z0 = svmulx_f16_x (svptrue_b16 (), z1, z2), + z0 = svmulx_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_mulx_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svmulx_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_mulx_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svmulx_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_mulx_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svmulx_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_mulx_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svmulx_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_mulx_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f16_x_tied1, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svmulx_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_mulx_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f16_x_untied, svfloat16_t, + z0 = svmulx_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svmulx_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f32.c new file mode 100644 index 00000000000..e0d3695932c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f32.c @@ -0,0 +1,472 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulx_f32_m_tied1: +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_m_tied1, svfloat32_t, + z0 = svmulx_f32_m (p0, z0, z1), + z0 = svmulx_m (p0, z0, z1)) + +/* +** mulx_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_m_tied2, svfloat32_t, + z0 = svmulx_f32_m (p0, z1, z0), + z0 = svmulx_m (p0, z1, z0)) + +/* +** mulx_f32_m_untied: +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_m_untied, svfloat32_t, + z0 = svmulx_f32_m (p0, z1, z2), + z0 = svmulx_m (p0, z1, z2)) + +/* +** mulx_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_m_tied1, svfloat32_t, float, + z0 = svmulx_n_f32_m (p0, z0, d4), + z0 = svmulx_m (p0, z0, d4)) + +/* +** mulx_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_m_untied, svfloat32_t, float, + z0 = svmulx_n_f32_m (p0, z1, d4), + z0 = svmulx_m (p0, z1, d4)) + +/* +** mulx_1_f32_m_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_m_tied1, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z0, 1), + z0 = svmulx_m (p0, z0, 1)) + +/* +** mulx_1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_m_untied, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z1, 1), + z0 = svmulx_m (p0, z1, 1)) + +/* +** mulx_0p5_f32_m_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_m_tied1, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z0, 0.5), + z0 = svmulx_m (p0, z0, 0.5)) + +/* +** mulx_0p5_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_m_untied, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z1, 0.5), + z0 = svmulx_m (p0, z1, 0.5)) + +/* +** mulx_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_m_tied1, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z0, 2), + z0 = svmulx_m (p0, z0, 2)) + +/* +** mulx_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_m_untied, svfloat32_t, + z0 = svmulx_n_f32_m (p0, z1, 2), + z0 = svmulx_m (p0, z1, 2)) + +/* +** mulx_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_z_tied1, svfloat32_t, + z0 = svmulx_f32_z (p0, z0, z1), + z0 = svmulx_z (p0, z0, z1)) + +/* +** mulx_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_z_tied2, svfloat32_t, + z0 = svmulx_f32_z (p0, z1, z0), + z0 = svmulx_z (p0, z1, z0)) + +/* +** mulx_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmulx z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_z_untied, svfloat32_t, + z0 = svmulx_f32_z (p0, z1, z2), + z0 = svmulx_z (p0, z1, z2)) + +/* +** mulx_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_z_tied1, svfloat32_t, float, + z0 = svmulx_n_f32_z (p0, z0, d4), + z0 = svmulx_z (p0, z0, d4)) + +/* +** mulx_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_z_untied, svfloat32_t, float, + z0 = svmulx_n_f32_z (p0, z1, d4), + z0 = svmulx_z (p0, z1, d4)) + +/* +** mulx_1_f32_z_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_z_tied1, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z0, 1), + z0 = svmulx_z (p0, z0, 1)) + +/* +** mulx_1_f32_z_untied: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_z_untied, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z1, 1), + z0 = svmulx_z (p0, z1, 1)) + +/* +** mulx_0p5_f32_z_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_z_tied1, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z0, 0.5), + z0 = svmulx_z (p0, z0, 0.5)) + +/* +** mulx_0p5_f32_z_untied: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_z_untied, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z1, 0.5), + z0 = svmulx_z (p0, z1, 0.5)) + +/* +** mulx_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_z_tied1, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z0, 2), + z0 = svmulx_z (p0, z0, 2)) + +/* +** mulx_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fmulx z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_z_untied, svfloat32_t, + z0 = svmulx_n_f32_z (p0, z1, 2), + z0 = svmulx_z (p0, z1, 2)) + +/* +** mulx_f32_x_tied1: +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_x_tied1, svfloat32_t, + z0 = svmulx_f32_x (p0, z0, z1), + z0 = svmulx_x (p0, z0, z1)) + +/* +** mulx_f32_x_tied2: +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_x_tied2, svfloat32_t, + z0 = svmulx_f32_x (p0, z1, z0), + z0 = svmulx_x (p0, z1, z0)) + +/* +** mulx_f32_x_untied: +** ( +** movprfx z0, z1 +** fmulx z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f32_x_untied, svfloat32_t, + z0 = svmulx_f32_x (p0, z1, z2), + z0 = svmulx_x (p0, z1, z2)) + +/* +** mulx_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_x_tied1, svfloat32_t, float, + z0 = svmulx_n_f32_x (p0, z0, d4), + z0 = svmulx_x (p0, z0, d4)) + +/* +** mulx_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (mulx_s4_f32_x_untied, svfloat32_t, float, + z0 = svmulx_n_f32_x (p0, z1, d4), + z0 = svmulx_x (p0, z1, d4)) + +/* +** mulx_1_f32_x_tied1: +** fmov (z[0-9]+\.s), #1\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z0, 1), + z0 = svmulx_x (p0, z0, 1)) + +/* +** mulx_1_f32_x_untied: +** fmov z0\.s, #1\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z1, 1), + z0 = svmulx_x (p0, z1, 1)) + +/* +** mulx_0p5_f32_x_tied1: +** fmov (z[0-9]+\.s), #(?:0\.5|5\.0e-1) +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z0, 0.5), + z0 = svmulx_x (p0, z0, 0.5)) + +/* +** mulx_0p5_f32_x_untied: +** fmov z0\.s, #(?:0\.5|5\.0e-1) +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z1, 0.5), + z0 = svmulx_x (p0, z1, 0.5)) + +/* +** mulx_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z0, 2), + z0 = svmulx_x (p0, z0, 2)) + +/* +** mulx_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fmulx z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (p0, z1, 2), + z0 = svmulx_x (p0, z1, 2)) + +/* +** ptrue_mulx_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f32_x_tied1, svfloat32_t, + z0 = svmulx_f32_x (svptrue_b32 (), z0, z1), + z0 = svmulx_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_mulx_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f32_x_tied2, svfloat32_t, + z0 = svmulx_f32_x (svptrue_b32 (), z1, z0), + z0 = svmulx_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_mulx_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f32_x_untied, svfloat32_t, + z0 = svmulx_f32_x (svptrue_b32 (), z1, z2), + z0 = svmulx_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_mulx_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svmulx_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_mulx_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svmulx_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_mulx_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svmulx_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_mulx_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svmulx_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_mulx_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f32_x_tied1, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svmulx_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_mulx_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f32_x_untied, svfloat32_t, + z0 = svmulx_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svmulx_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f64.c new file mode 100644 index 00000000000..6af5703ffaf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulx_f64.c @@ -0,0 +1,472 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** mulx_f64_m_tied1: +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_m_tied1, svfloat64_t, + z0 = svmulx_f64_m (p0, z0, z1), + z0 = svmulx_m (p0, z0, z1)) + +/* +** mulx_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_m_tied2, svfloat64_t, + z0 = svmulx_f64_m (p0, z1, z0), + z0 = svmulx_m (p0, z1, z0)) + +/* +** mulx_f64_m_untied: +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_m_untied, svfloat64_t, + z0 = svmulx_f64_m (p0, z1, z2), + z0 = svmulx_m (p0, z1, z2)) + +/* +** mulx_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_m_tied1, svfloat64_t, double, + z0 = svmulx_n_f64_m (p0, z0, d4), + z0 = svmulx_m (p0, z0, d4)) + +/* +** mulx_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_m_untied, svfloat64_t, double, + z0 = svmulx_n_f64_m (p0, z1, d4), + z0 = svmulx_m (p0, z1, d4)) + +/* +** mulx_1_f64_m_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_m_tied1, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z0, 1), + z0 = svmulx_m (p0, z0, 1)) + +/* +** mulx_1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_m_untied, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z1, 1), + z0 = svmulx_m (p0, z1, 1)) + +/* +** mulx_0p5_f64_m_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_m_tied1, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z0, 0.5), + z0 = svmulx_m (p0, z0, 0.5)) + +/* +** mulx_0p5_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_m_untied, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z1, 0.5), + z0 = svmulx_m (p0, z1, 0.5)) + +/* +** mulx_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_m_tied1, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z0, 2), + z0 = svmulx_m (p0, z0, 2)) + +/* +** mulx_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_m_untied, svfloat64_t, + z0 = svmulx_n_f64_m (p0, z1, 2), + z0 = svmulx_m (p0, z1, 2)) + +/* +** mulx_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_z_tied1, svfloat64_t, + z0 = svmulx_f64_z (p0, z0, z1), + z0 = svmulx_z (p0, z0, z1)) + +/* +** mulx_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_z_tied2, svfloat64_t, + z0 = svmulx_f64_z (p0, z1, z0), + z0 = svmulx_z (p0, z1, z0)) + +/* +** mulx_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmulx z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_z_untied, svfloat64_t, + z0 = svmulx_f64_z (p0, z1, z2), + z0 = svmulx_z (p0, z1, z2)) + +/* +** mulx_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_z_tied1, svfloat64_t, double, + z0 = svmulx_n_f64_z (p0, z0, d4), + z0 = svmulx_z (p0, z0, d4)) + +/* +** mulx_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_z_untied, svfloat64_t, double, + z0 = svmulx_n_f64_z (p0, z1, d4), + z0 = svmulx_z (p0, z1, d4)) + +/* +** mulx_1_f64_z_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_z_tied1, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z0, 1), + z0 = svmulx_z (p0, z0, 1)) + +/* +** mulx_1_f64_z_untied: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_z_untied, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z1, 1), + z0 = svmulx_z (p0, z1, 1)) + +/* +** mulx_0p5_f64_z_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_z_tied1, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z0, 0.5), + z0 = svmulx_z (p0, z0, 0.5)) + +/* +** mulx_0p5_f64_z_untied: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_z_untied, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z1, 0.5), + z0 = svmulx_z (p0, z1, 0.5)) + +/* +** mulx_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_z_tied1, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z0, 2), + z0 = svmulx_z (p0, z0, 2)) + +/* +** mulx_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fmulx z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_z_untied, svfloat64_t, + z0 = svmulx_n_f64_z (p0, z1, 2), + z0 = svmulx_z (p0, z1, 2)) + +/* +** mulx_f64_x_tied1: +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_x_tied1, svfloat64_t, + z0 = svmulx_f64_x (p0, z0, z1), + z0 = svmulx_x (p0, z0, z1)) + +/* +** mulx_f64_x_tied2: +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_x_tied2, svfloat64_t, + z0 = svmulx_f64_x (p0, z1, z0), + z0 = svmulx_x (p0, z1, z0)) + +/* +** mulx_f64_x_untied: +** ( +** movprfx z0, z1 +** fmulx z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (mulx_f64_x_untied, svfloat64_t, + z0 = svmulx_f64_x (p0, z1, z2), + z0 = svmulx_x (p0, z1, z2)) + +/* +** mulx_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_x_tied1, svfloat64_t, double, + z0 = svmulx_n_f64_x (p0, z0, d4), + z0 = svmulx_x (p0, z0, d4)) + +/* +** mulx_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (mulx_d4_f64_x_untied, svfloat64_t, double, + z0 = svmulx_n_f64_x (p0, z1, d4), + z0 = svmulx_x (p0, z1, d4)) + +/* +** mulx_1_f64_x_tied1: +** fmov (z[0-9]+\.d), #1\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z0, 1), + z0 = svmulx_x (p0, z0, 1)) + +/* +** mulx_1_f64_x_untied: +** fmov z0\.d, #1\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_1_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z1, 1), + z0 = svmulx_x (p0, z1, 1)) + +/* +** mulx_0p5_f64_x_tied1: +** fmov (z[0-9]+\.d), #(?:0\.5|5\.0e-1) +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z0, 0.5), + z0 = svmulx_x (p0, z0, 0.5)) + +/* +** mulx_0p5_f64_x_untied: +** fmov z0\.d, #(?:0\.5|5\.0e-1) +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_0p5_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z1, 0.5), + z0 = svmulx_x (p0, z1, 0.5)) + +/* +** mulx_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z0, 2), + z0 = svmulx_x (p0, z0, 2)) + +/* +** mulx_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fmulx z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (mulx_2_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (p0, z1, 2), + z0 = svmulx_x (p0, z1, 2)) + +/* +** ptrue_mulx_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f64_x_tied1, svfloat64_t, + z0 = svmulx_f64_x (svptrue_b64 (), z0, z1), + z0 = svmulx_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_mulx_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f64_x_tied2, svfloat64_t, + z0 = svmulx_f64_x (svptrue_b64 (), z1, z0), + z0 = svmulx_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_mulx_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_f64_x_untied, svfloat64_t, + z0 = svmulx_f64_x (svptrue_b64 (), z1, z2), + z0 = svmulx_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_mulx_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svmulx_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_mulx_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_1_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svmulx_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_mulx_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svmulx_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_mulx_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_0p5_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svmulx_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_mulx_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f64_x_tied1, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svmulx_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_mulx_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_mulx_2_f64_x_untied, svfloat64_t, + z0 = svmulx_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svmulx_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nand_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nand_b.c new file mode 100644 index 00000000000..c306b80c7a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nand_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nand_b_z_tied1: +** nand p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (nand_b_z_tied1, + p0 = svnand_b_z (p3, p0, p1), + p0 = svnand_z (p3, p0, p1)) + +/* +** nand_b_z_tied2: +** nand p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (nand_b_z_tied2, + p0 = svnand_b_z (p3, p1, p0), + p0 = svnand_z (p3, p1, p0)) + +/* +** nand_b_z_untied: +** nand p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (nand_b_z_untied, + p0 = svnand_b_z (p3, p1, p2), + p0 = svnand_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c new file mode 100644 index 00000000000..c31eba92218 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_f16_m_tied12: +** fneg z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_m_tied12, svfloat16_t, + z0 = svneg_f16_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_f16_m_tied1: +** fneg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_m_tied1, svfloat16_t, + z0 = svneg_f16_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fneg z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_m_tied2, svfloat16_t, + z0 = svneg_f16_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_f16_m_untied: +** movprfx z0, z2 +** fneg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_m_untied, svfloat16_t, + z0 = svneg_f16_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** fneg z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_z_tied1, svfloat16_t, + z0 = svneg_f16_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fneg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_z_untied, svfloat16_t, + z0 = svneg_f16_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_f16_x_tied1: +** fneg z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_x_tied1, svfloat16_t, + z0 = svneg_f16_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_f16_x_untied: +** fneg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_f16_x_untied, svfloat16_t, + z0 = svneg_f16_x (p0, z1), + z0 = svneg_x (p0, z1)) + +/* +** ptrue_neg_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f16_x_tied1, svfloat16_t, + z0 = svneg_f16_x (svptrue_b16 (), z0), + z0 = svneg_x (svptrue_b16 (), z0)) + +/* +** ptrue_neg_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f16_x_untied, svfloat16_t, + z0 = svneg_f16_x (svptrue_b16 (), z1), + z0 = svneg_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c new file mode 100644 index 00000000000..a57d264ad55 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_f32_m_tied12: +** fneg z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_m_tied12, svfloat32_t, + z0 = svneg_f32_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_f32_m_tied1: +** fneg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_m_tied1, svfloat32_t, + z0 = svneg_f32_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fneg z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_m_tied2, svfloat32_t, + z0 = svneg_f32_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_f32_m_untied: +** movprfx z0, z2 +** fneg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_m_untied, svfloat32_t, + z0 = svneg_f32_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fneg z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_z_tied1, svfloat32_t, + z0 = svneg_f32_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fneg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_z_untied, svfloat32_t, + z0 = svneg_f32_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_f32_x_tied1: +** fneg z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_x_tied1, svfloat32_t, + z0 = svneg_f32_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_f32_x_untied: +** fneg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_f32_x_untied, svfloat32_t, + z0 = svneg_f32_x (p0, z1), + z0 = svneg_x (p0, z1)) + +/* +** ptrue_neg_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f32_x_tied1, svfloat32_t, + z0 = svneg_f32_x (svptrue_b32 (), z0), + z0 = svneg_x (svptrue_b32 (), z0)) + +/* +** ptrue_neg_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f32_x_untied, svfloat32_t, + z0 = svneg_f32_x (svptrue_b32 (), z1), + z0 = svneg_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c new file mode 100644 index 00000000000..90cadd4f969 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_f64_m_tied12: +** fneg z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_m_tied12, svfloat64_t, + z0 = svneg_f64_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_f64_m_tied1: +** fneg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_m_tied1, svfloat64_t, + z0 = svneg_f64_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fneg z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (neg_f64_m_tied2, svfloat64_t, + z0 = svneg_f64_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_f64_m_untied: +** movprfx z0, z2 +** fneg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_m_untied, svfloat64_t, + z0 = svneg_f64_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fneg z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (neg_f64_z_tied1, svfloat64_t, + z0 = svneg_f64_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fneg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_z_untied, svfloat64_t, + z0 = svneg_f64_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_f64_x_tied1: +** fneg z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_x_tied1, svfloat64_t, + z0 = svneg_f64_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_f64_x_untied: +** fneg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_f64_x_untied, svfloat64_t, + z0 = svneg_f64_x (p0, z1), + z0 = svneg_x (p0, z1)) + +/* +** ptrue_neg_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f64_x_tied1, svfloat64_t, + z0 = svneg_f64_x (svptrue_b64 (), z0), + z0 = svneg_x (svptrue_b64 (), z0)) + +/* +** ptrue_neg_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_neg_f64_x_untied, svfloat64_t, + z0 = svneg_f64_x (svptrue_b64 (), z1), + z0 = svneg_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c new file mode 100644 index 00000000000..80b2ee0f7ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_s16_m_tied12: +** neg z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_m_tied12, svint16_t, + z0 = svneg_s16_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_s16_m_tied1: +** neg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_m_tied1, svint16_t, + z0 = svneg_s16_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** neg z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_m_tied2, svint16_t, + z0 = svneg_s16_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_s16_m_untied: +** movprfx z0, z2 +** neg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_m_untied, svint16_t, + z0 = svneg_s16_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** neg z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_z_tied1, svint16_t, + z0 = svneg_s16_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** neg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_z_untied, svint16_t, + z0 = svneg_s16_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_s16_x_tied1: +** neg z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_x_tied1, svint16_t, + z0 = svneg_s16_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_s16_x_untied: +** neg z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (neg_s16_x_untied, svint16_t, + z0 = svneg_s16_x (p0, z1), + z0 = svneg_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c new file mode 100644 index 00000000000..b8805034eb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_s32_m_tied12: +** neg z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_m_tied12, svint32_t, + z0 = svneg_s32_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_s32_m_tied1: +** neg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_m_tied1, svint32_t, + z0 = svneg_s32_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** neg z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_m_tied2, svint32_t, + z0 = svneg_s32_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_s32_m_untied: +** movprfx z0, z2 +** neg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_m_untied, svint32_t, + z0 = svneg_s32_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** neg z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_z_tied1, svint32_t, + z0 = svneg_s32_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** neg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_z_untied, svint32_t, + z0 = svneg_s32_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_s32_x_tied1: +** neg z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_x_tied1, svint32_t, + z0 = svneg_s32_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_s32_x_untied: +** neg z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (neg_s32_x_untied, svint32_t, + z0 = svneg_s32_x (p0, z1), + z0 = svneg_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c new file mode 100644 index 00000000000..82abe672350 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_s64_m_tied12: +** neg z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_m_tied12, svint64_t, + z0 = svneg_s64_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_s64_m_tied1: +** neg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_m_tied1, svint64_t, + z0 = svneg_s64_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** neg z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (neg_s64_m_tied2, svint64_t, + z0 = svneg_s64_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_s64_m_untied: +** movprfx z0, z2 +** neg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_m_untied, svint64_t, + z0 = svneg_s64_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** neg z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (neg_s64_z_tied1, svint64_t, + z0 = svneg_s64_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** neg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_z_untied, svint64_t, + z0 = svneg_s64_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_s64_x_tied1: +** neg z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_x_tied1, svint64_t, + z0 = svneg_s64_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_s64_x_untied: +** neg z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (neg_s64_x_untied, svint64_t, + z0 = svneg_s64_x (p0, z1), + z0 = svneg_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c new file mode 100644 index 00000000000..b7c9949ad1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** neg_s8_m_tied12: +** neg z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_m_tied12, svint8_t, + z0 = svneg_s8_m (z0, p0, z0), + z0 = svneg_m (z0, p0, z0)) + +/* +** neg_s8_m_tied1: +** neg z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_m_tied1, svint8_t, + z0 = svneg_s8_m (z0, p0, z1), + z0 = svneg_m (z0, p0, z1)) + +/* +** neg_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** neg z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_m_tied2, svint8_t, + z0 = svneg_s8_m (z1, p0, z0), + z0 = svneg_m (z1, p0, z0)) + +/* +** neg_s8_m_untied: +** movprfx z0, z2 +** neg z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_m_untied, svint8_t, + z0 = svneg_s8_m (z2, p0, z1), + z0 = svneg_m (z2, p0, z1)) + +/* +** neg_s8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** neg z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_z_tied1, svint8_t, + z0 = svneg_s8_z (p0, z0), + z0 = svneg_z (p0, z0)) + +/* +** neg_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** neg z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_z_untied, svint8_t, + z0 = svneg_s8_z (p0, z1), + z0 = svneg_z (p0, z1)) + +/* +** neg_s8_x_tied1: +** neg z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_x_tied1, svint8_t, + z0 = svneg_s8_x (p0, z0), + z0 = svneg_x (p0, z0)) + +/* +** neg_s8_x_untied: +** neg z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (neg_s8_x_untied, svint8_t, + z0 = svneg_s8_x (p0, z1), + z0 = svneg_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f16.c new file mode 100644 index 00000000000..abfe0a0c056 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmad_f16_m_tied1: +** fnmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_m_tied1, svfloat16_t, + z0 = svnmad_f16_m (p0, z0, z1, z2), + z0 = svnmad_m (p0, z0, z1, z2)) + +/* +** nmad_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmad z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_m_tied2, svfloat16_t, + z0 = svnmad_f16_m (p0, z1, z0, z2), + z0 = svnmad_m (p0, z1, z0, z2)) + +/* +** nmad_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmad z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_m_tied3, svfloat16_t, + z0 = svnmad_f16_m (p0, z1, z2, z0), + z0 = svnmad_m (p0, z1, z2, z0)) + +/* +** nmad_f16_m_untied: +** movprfx z0, z1 +** fnmad z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_m_untied, svfloat16_t, + z0 = svnmad_f16_m (p0, z1, z2, z3), + z0 = svnmad_m (p0, z1, z2, z3)) + +/* +** nmad_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svnmad_n_f16_m (p0, z0, z1, d4), + z0 = svnmad_m (p0, z0, z1, d4)) + +/* +** nmad_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fnmad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svnmad_n_f16_m (p0, z1, z2, d4), + z0 = svnmad_m (p0, z1, z2, d4)) + +/* +** nmad_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_m_tied1, svfloat16_t, + z0 = svnmad_n_f16_m (p0, z0, z1, 2), + z0 = svnmad_m (p0, z0, z1, 2)) + +/* +** nmad_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmad z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_m_untied, svfloat16_t, + z0 = svnmad_n_f16_m (p0, z1, z2, 2), + z0 = svnmad_m (p0, z1, z2, 2)) + +/* +** nmad_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_z_tied1, svfloat16_t, + z0 = svnmad_f16_z (p0, z0, z1, z2), + z0 = svnmad_z (p0, z0, z1, z2)) + +/* +** nmad_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_z_tied2, svfloat16_t, + z0 = svnmad_f16_z (p0, z1, z0, z2), + z0 = svnmad_z (p0, z1, z0, z2)) + +/* +** nmad_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_z_tied3, svfloat16_t, + z0 = svnmad_f16_z (p0, z1, z2, z0), + z0 = svnmad_z (p0, z1, z2, z0)) + +/* +** nmad_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_z_untied, svfloat16_t, + z0 = svnmad_f16_z (p0, z1, z2, z3), + z0 = svnmad_z (p0, z1, z2, z3)) + +/* +** nmad_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svnmad_n_f16_z (p0, z0, z1, d4), + z0 = svnmad_z (p0, z0, z1, d4)) + +/* +** nmad_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svnmad_n_f16_z (p0, z1, z0, d4), + z0 = svnmad_z (p0, z1, z0, d4)) + +/* +** nmad_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svnmad_n_f16_z (p0, z1, z2, d4), + z0 = svnmad_z (p0, z1, z2, d4)) + +/* +** nmad_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_z_tied1, svfloat16_t, + z0 = svnmad_n_f16_z (p0, z0, z1, 2), + z0 = svnmad_z (p0, z0, z1, 2)) + +/* +** nmad_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_z_tied2, svfloat16_t, + z0 = svnmad_n_f16_z (p0, z1, z0, 2), + z0 = svnmad_z (p0, z1, z0, 2)) + +/* +** nmad_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmad z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_z_untied, svfloat16_t, + z0 = svnmad_n_f16_z (p0, z1, z2, 2), + z0 = svnmad_z (p0, z1, z2, 2)) + +/* +** nmad_f16_x_tied1: +** fnmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_x_tied1, svfloat16_t, + z0 = svnmad_f16_x (p0, z0, z1, z2), + z0 = svnmad_x (p0, z0, z1, z2)) + +/* +** nmad_f16_x_tied2: +** fnmad z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_x_tied2, svfloat16_t, + z0 = svnmad_f16_x (p0, z1, z0, z2), + z0 = svnmad_x (p0, z1, z0, z2)) + +/* +** nmad_f16_x_tied3: +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_x_tied3, svfloat16_t, + z0 = svnmad_f16_x (p0, z1, z2, z0), + z0 = svnmad_x (p0, z1, z2, z0)) + +/* +** nmad_f16_x_untied: +** ( +** movprfx z0, z1 +** fnmad z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fnmad z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f16_x_untied, svfloat16_t, + z0 = svnmad_f16_x (p0, z1, z2, z3), + z0 = svnmad_x (p0, z1, z2, z3)) + +/* +** nmad_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svnmad_n_f16_x (p0, z0, z1, d4), + z0 = svnmad_x (p0, z0, z1, d4)) + +/* +** nmad_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svnmad_n_f16_x (p0, z1, z0, d4), + z0 = svnmad_x (p0, z1, z0, d4)) + +/* +** nmad_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZD (nmad_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svnmad_n_f16_x (p0, z1, z2, d4), + z0 = svnmad_x (p0, z1, z2, d4)) + +/* +** nmad_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_x_tied1, svfloat16_t, + z0 = svnmad_n_f16_x (p0, z0, z1, 2), + z0 = svnmad_x (p0, z0, z1, 2)) + +/* +** nmad_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmad z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_x_tied2, svfloat16_t, + z0 = svnmad_n_f16_x (p0, z1, z0, 2), + z0 = svnmad_x (p0, z1, z0, 2)) + +/* +** nmad_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f16_x_untied, svfloat16_t, + z0 = svnmad_n_f16_x (p0, z1, z2, 2), + z0 = svnmad_x (p0, z1, z2, 2)) + +/* +** ptrue_nmad_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f16_x_tied1, svfloat16_t, + z0 = svnmad_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svnmad_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_nmad_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f16_x_tied2, svfloat16_t, + z0 = svnmad_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svnmad_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_nmad_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f16_x_tied3, svfloat16_t, + z0 = svnmad_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svnmad_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_nmad_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f16_x_untied, svfloat16_t, + z0 = svnmad_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svnmad_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_nmad_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f16_x_tied1, svfloat16_t, + z0 = svnmad_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svnmad_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_nmad_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f16_x_tied2, svfloat16_t, + z0 = svnmad_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svnmad_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_nmad_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f16_x_untied, svfloat16_t, + z0 = svnmad_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svnmad_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f32.c new file mode 100644 index 00000000000..ab86385c382 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmad_f32_m_tied1: +** fnmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_m_tied1, svfloat32_t, + z0 = svnmad_f32_m (p0, z0, z1, z2), + z0 = svnmad_m (p0, z0, z1, z2)) + +/* +** nmad_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmad z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_m_tied2, svfloat32_t, + z0 = svnmad_f32_m (p0, z1, z0, z2), + z0 = svnmad_m (p0, z1, z0, z2)) + +/* +** nmad_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmad z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_m_tied3, svfloat32_t, + z0 = svnmad_f32_m (p0, z1, z2, z0), + z0 = svnmad_m (p0, z1, z2, z0)) + +/* +** nmad_f32_m_untied: +** movprfx z0, z1 +** fnmad z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_m_untied, svfloat32_t, + z0 = svnmad_f32_m (p0, z1, z2, z3), + z0 = svnmad_m (p0, z1, z2, z3)) + +/* +** nmad_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_m_tied1, svfloat32_t, float, + z0 = svnmad_n_f32_m (p0, z0, z1, d4), + z0 = svnmad_m (p0, z0, z1, d4)) + +/* +** nmad_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fnmad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_m_untied, svfloat32_t, float, + z0 = svnmad_n_f32_m (p0, z1, z2, d4), + z0 = svnmad_m (p0, z1, z2, d4)) + +/* +** nmad_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_m_tied1, svfloat32_t, + z0 = svnmad_n_f32_m (p0, z0, z1, 2), + z0 = svnmad_m (p0, z0, z1, 2)) + +/* +** nmad_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmad z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_m_untied, svfloat32_t, + z0 = svnmad_n_f32_m (p0, z1, z2, 2), + z0 = svnmad_m (p0, z1, z2, 2)) + +/* +** nmad_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_z_tied1, svfloat32_t, + z0 = svnmad_f32_z (p0, z0, z1, z2), + z0 = svnmad_z (p0, z0, z1, z2)) + +/* +** nmad_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_z_tied2, svfloat32_t, + z0 = svnmad_f32_z (p0, z1, z0, z2), + z0 = svnmad_z (p0, z1, z0, z2)) + +/* +** nmad_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_z_tied3, svfloat32_t, + z0 = svnmad_f32_z (p0, z1, z2, z0), + z0 = svnmad_z (p0, z1, z2, z0)) + +/* +** nmad_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_z_untied, svfloat32_t, + z0 = svnmad_f32_z (p0, z1, z2, z3), + z0 = svnmad_z (p0, z1, z2, z3)) + +/* +** nmad_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_z_tied1, svfloat32_t, float, + z0 = svnmad_n_f32_z (p0, z0, z1, d4), + z0 = svnmad_z (p0, z0, z1, d4)) + +/* +** nmad_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_z_tied2, svfloat32_t, float, + z0 = svnmad_n_f32_z (p0, z1, z0, d4), + z0 = svnmad_z (p0, z1, z0, d4)) + +/* +** nmad_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_z_untied, svfloat32_t, float, + z0 = svnmad_n_f32_z (p0, z1, z2, d4), + z0 = svnmad_z (p0, z1, z2, d4)) + +/* +** nmad_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_z_tied1, svfloat32_t, + z0 = svnmad_n_f32_z (p0, z0, z1, 2), + z0 = svnmad_z (p0, z0, z1, 2)) + +/* +** nmad_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_z_tied2, svfloat32_t, + z0 = svnmad_n_f32_z (p0, z1, z0, 2), + z0 = svnmad_z (p0, z1, z0, 2)) + +/* +** nmad_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmad z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_z_untied, svfloat32_t, + z0 = svnmad_n_f32_z (p0, z1, z2, 2), + z0 = svnmad_z (p0, z1, z2, 2)) + +/* +** nmad_f32_x_tied1: +** fnmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_x_tied1, svfloat32_t, + z0 = svnmad_f32_x (p0, z0, z1, z2), + z0 = svnmad_x (p0, z0, z1, z2)) + +/* +** nmad_f32_x_tied2: +** fnmad z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_x_tied2, svfloat32_t, + z0 = svnmad_f32_x (p0, z1, z0, z2), + z0 = svnmad_x (p0, z1, z0, z2)) + +/* +** nmad_f32_x_tied3: +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_x_tied3, svfloat32_t, + z0 = svnmad_f32_x (p0, z1, z2, z0), + z0 = svnmad_x (p0, z1, z2, z0)) + +/* +** nmad_f32_x_untied: +** ( +** movprfx z0, z1 +** fnmad z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fnmad z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f32_x_untied, svfloat32_t, + z0 = svnmad_f32_x (p0, z1, z2, z3), + z0 = svnmad_x (p0, z1, z2, z3)) + +/* +** nmad_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_x_tied1, svfloat32_t, float, + z0 = svnmad_n_f32_x (p0, z0, z1, d4), + z0 = svnmad_x (p0, z0, z1, d4)) + +/* +** nmad_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_x_tied2, svfloat32_t, float, + z0 = svnmad_n_f32_x (p0, z1, z0, d4), + z0 = svnmad_x (p0, z1, z0, d4)) + +/* +** nmad_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZD (nmad_s4_f32_x_untied, svfloat32_t, float, + z0 = svnmad_n_f32_x (p0, z1, z2, d4), + z0 = svnmad_x (p0, z1, z2, d4)) + +/* +** nmad_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_x_tied1, svfloat32_t, + z0 = svnmad_n_f32_x (p0, z0, z1, 2), + z0 = svnmad_x (p0, z0, z1, 2)) + +/* +** nmad_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmad z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_x_tied2, svfloat32_t, + z0 = svnmad_n_f32_x (p0, z1, z0, 2), + z0 = svnmad_x (p0, z1, z0, 2)) + +/* +** nmad_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f32_x_untied, svfloat32_t, + z0 = svnmad_n_f32_x (p0, z1, z2, 2), + z0 = svnmad_x (p0, z1, z2, 2)) + +/* +** ptrue_nmad_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f32_x_tied1, svfloat32_t, + z0 = svnmad_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svnmad_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_nmad_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f32_x_tied2, svfloat32_t, + z0 = svnmad_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svnmad_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_nmad_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f32_x_tied3, svfloat32_t, + z0 = svnmad_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svnmad_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_nmad_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f32_x_untied, svfloat32_t, + z0 = svnmad_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svnmad_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_nmad_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f32_x_tied1, svfloat32_t, + z0 = svnmad_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svnmad_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_nmad_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f32_x_tied2, svfloat32_t, + z0 = svnmad_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svnmad_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_nmad_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f32_x_untied, svfloat32_t, + z0 = svnmad_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svnmad_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f64.c new file mode 100644 index 00000000000..c236ff5a1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmad_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmad_f64_m_tied1: +** fnmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_m_tied1, svfloat64_t, + z0 = svnmad_f64_m (p0, z0, z1, z2), + z0 = svnmad_m (p0, z0, z1, z2)) + +/* +** nmad_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmad z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_m_tied2, svfloat64_t, + z0 = svnmad_f64_m (p0, z1, z0, z2), + z0 = svnmad_m (p0, z1, z0, z2)) + +/* +** nmad_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_m_tied3, svfloat64_t, + z0 = svnmad_f64_m (p0, z1, z2, z0), + z0 = svnmad_m (p0, z1, z2, z0)) + +/* +** nmad_f64_m_untied: +** movprfx z0, z1 +** fnmad z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_m_untied, svfloat64_t, + z0 = svnmad_f64_m (p0, z1, z2, z3), + z0 = svnmad_m (p0, z1, z2, z3)) + +/* +** nmad_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_m_tied1, svfloat64_t, double, + z0 = svnmad_n_f64_m (p0, z0, z1, d4), + z0 = svnmad_m (p0, z0, z1, d4)) + +/* +** nmad_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fnmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_m_untied, svfloat64_t, double, + z0 = svnmad_n_f64_m (p0, z1, z2, d4), + z0 = svnmad_m (p0, z1, z2, d4)) + +/* +** nmad_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_m_tied1, svfloat64_t, + z0 = svnmad_n_f64_m (p0, z0, z1, 2), + z0 = svnmad_m (p0, z0, z1, 2)) + +/* +** nmad_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmad z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_m_untied, svfloat64_t, + z0 = svnmad_n_f64_m (p0, z1, z2, 2), + z0 = svnmad_m (p0, z1, z2, 2)) + +/* +** nmad_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_z_tied1, svfloat64_t, + z0 = svnmad_f64_z (p0, z0, z1, z2), + z0 = svnmad_z (p0, z0, z1, z2)) + +/* +** nmad_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_z_tied2, svfloat64_t, + z0 = svnmad_f64_z (p0, z1, z0, z2), + z0 = svnmad_z (p0, z1, z0, z2)) + +/* +** nmad_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_z_tied3, svfloat64_t, + z0 = svnmad_f64_z (p0, z1, z2, z0), + z0 = svnmad_z (p0, z1, z2, z0)) + +/* +** nmad_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_z_untied, svfloat64_t, + z0 = svnmad_f64_z (p0, z1, z2, z3), + z0 = svnmad_z (p0, z1, z2, z3)) + +/* +** nmad_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_z_tied1, svfloat64_t, double, + z0 = svnmad_n_f64_z (p0, z0, z1, d4), + z0 = svnmad_z (p0, z0, z1, d4)) + +/* +** nmad_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_z_tied2, svfloat64_t, double, + z0 = svnmad_n_f64_z (p0, z1, z0, d4), + z0 = svnmad_z (p0, z1, z0, d4)) + +/* +** nmad_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_z_untied, svfloat64_t, double, + z0 = svnmad_n_f64_z (p0, z1, z2, d4), + z0 = svnmad_z (p0, z1, z2, d4)) + +/* +** nmad_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_z_tied1, svfloat64_t, + z0 = svnmad_n_f64_z (p0, z0, z1, 2), + z0 = svnmad_z (p0, z0, z1, 2)) + +/* +** nmad_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_z_tied2, svfloat64_t, + z0 = svnmad_n_f64_z (p0, z1, z0, 2), + z0 = svnmad_z (p0, z1, z0, 2)) + +/* +** nmad_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmad z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_z_untied, svfloat64_t, + z0 = svnmad_n_f64_z (p0, z1, z2, 2), + z0 = svnmad_z (p0, z1, z2, 2)) + +/* +** nmad_f64_x_tied1: +** fnmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_x_tied1, svfloat64_t, + z0 = svnmad_f64_x (p0, z0, z1, z2), + z0 = svnmad_x (p0, z0, z1, z2)) + +/* +** nmad_f64_x_tied2: +** fnmad z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_x_tied2, svfloat64_t, + z0 = svnmad_f64_x (p0, z1, z0, z2), + z0 = svnmad_x (p0, z1, z0, z2)) + +/* +** nmad_f64_x_tied3: +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_x_tied3, svfloat64_t, + z0 = svnmad_f64_x (p0, z1, z2, z0), + z0 = svnmad_x (p0, z1, z2, z0)) + +/* +** nmad_f64_x_untied: +** ( +** movprfx z0, z1 +** fnmad z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fnmad z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmad_f64_x_untied, svfloat64_t, + z0 = svnmad_f64_x (p0, z1, z2, z3), + z0 = svnmad_x (p0, z1, z2, z3)) + +/* +** nmad_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_x_tied1, svfloat64_t, double, + z0 = svnmad_n_f64_x (p0, z0, z1, d4), + z0 = svnmad_x (p0, z0, z1, d4)) + +/* +** nmad_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_x_tied2, svfloat64_t, double, + z0 = svnmad_n_f64_x (p0, z1, z0, d4), + z0 = svnmad_x (p0, z1, z0, d4)) + +/* +** nmad_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZD (nmad_d4_f64_x_untied, svfloat64_t, double, + z0 = svnmad_n_f64_x (p0, z1, z2, d4), + z0 = svnmad_x (p0, z1, z2, d4)) + +/* +** nmad_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_x_tied1, svfloat64_t, + z0 = svnmad_n_f64_x (p0, z0, z1, 2), + z0 = svnmad_x (p0, z0, z1, 2)) + +/* +** nmad_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmad z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_x_tied2, svfloat64_t, + z0 = svnmad_n_f64_x (p0, z1, z0, 2), + z0 = svnmad_x (p0, z1, z0, 2)) + +/* +** nmad_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmad_2_f64_x_untied, svfloat64_t, + z0 = svnmad_n_f64_x (p0, z1, z2, 2), + z0 = svnmad_x (p0, z1, z2, 2)) + +/* +** ptrue_nmad_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f64_x_tied1, svfloat64_t, + z0 = svnmad_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svnmad_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_nmad_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f64_x_tied2, svfloat64_t, + z0 = svnmad_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svnmad_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_nmad_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f64_x_tied3, svfloat64_t, + z0 = svnmad_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svnmad_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_nmad_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_f64_x_untied, svfloat64_t, + z0 = svnmad_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svnmad_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_nmad_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f64_x_tied1, svfloat64_t, + z0 = svnmad_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svnmad_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_nmad_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f64_x_tied2, svfloat64_t, + z0 = svnmad_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svnmad_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_nmad_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmad_2_f64_x_untied, svfloat64_t, + z0 = svnmad_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svnmad_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f16.c new file mode 100644 index 00000000000..f7ac377fdc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmla_f16_m_tied1: +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_m_tied1, svfloat16_t, + z0 = svnmla_f16_m (p0, z0, z1, z2), + z0 = svnmla_m (p0, z0, z1, z2)) + +/* +** nmla_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmla z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_m_tied2, svfloat16_t, + z0 = svnmla_f16_m (p0, z1, z0, z2), + z0 = svnmla_m (p0, z1, z0, z2)) + +/* +** nmla_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmla z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_m_tied3, svfloat16_t, + z0 = svnmla_f16_m (p0, z1, z2, z0), + z0 = svnmla_m (p0, z1, z2, z0)) + +/* +** nmla_f16_m_untied: +** movprfx z0, z1 +** fnmla z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_m_untied, svfloat16_t, + z0 = svnmla_f16_m (p0, z1, z2, z3), + z0 = svnmla_m (p0, z1, z2, z3)) + +/* +** nmla_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svnmla_n_f16_m (p0, z0, z1, d4), + z0 = svnmla_m (p0, z0, z1, d4)) + +/* +** nmla_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fnmla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svnmla_n_f16_m (p0, z1, z2, d4), + z0 = svnmla_m (p0, z1, z2, d4)) + +/* +** nmla_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_m_tied1, svfloat16_t, + z0 = svnmla_n_f16_m (p0, z0, z1, 2), + z0 = svnmla_m (p0, z0, z1, 2)) + +/* +** nmla_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmla z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_m_untied, svfloat16_t, + z0 = svnmla_n_f16_m (p0, z1, z2, 2), + z0 = svnmla_m (p0, z1, z2, 2)) + +/* +** nmla_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_z_tied1, svfloat16_t, + z0 = svnmla_f16_z (p0, z0, z1, z2), + z0 = svnmla_z (p0, z0, z1, z2)) + +/* +** nmla_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_z_tied2, svfloat16_t, + z0 = svnmla_f16_z (p0, z1, z0, z2), + z0 = svnmla_z (p0, z1, z0, z2)) + +/* +** nmla_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_z_tied3, svfloat16_t, + z0 = svnmla_f16_z (p0, z1, z2, z0), + z0 = svnmla_z (p0, z1, z2, z0)) + +/* +** nmla_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_z_untied, svfloat16_t, + z0 = svnmla_f16_z (p0, z1, z2, z3), + z0 = svnmla_z (p0, z1, z2, z3)) + +/* +** nmla_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svnmla_n_f16_z (p0, z0, z1, d4), + z0 = svnmla_z (p0, z0, z1, d4)) + +/* +** nmla_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svnmla_n_f16_z (p0, z1, z0, d4), + z0 = svnmla_z (p0, z1, z0, d4)) + +/* +** nmla_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svnmla_n_f16_z (p0, z1, z2, d4), + z0 = svnmla_z (p0, z1, z2, d4)) + +/* +** nmla_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_z_tied1, svfloat16_t, + z0 = svnmla_n_f16_z (p0, z0, z1, 2), + z0 = svnmla_z (p0, z0, z1, 2)) + +/* +** nmla_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_z_tied2, svfloat16_t, + z0 = svnmla_n_f16_z (p0, z1, z0, 2), + z0 = svnmla_z (p0, z1, z0, 2)) + +/* +** nmla_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmla z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmad z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_z_untied, svfloat16_t, + z0 = svnmla_n_f16_z (p0, z1, z2, 2), + z0 = svnmla_z (p0, z1, z2, 2)) + +/* +** nmla_f16_x_tied1: +** fnmla z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_x_tied1, svfloat16_t, + z0 = svnmla_f16_x (p0, z0, z1, z2), + z0 = svnmla_x (p0, z0, z1, z2)) + +/* +** nmla_f16_x_tied2: +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_x_tied2, svfloat16_t, + z0 = svnmla_f16_x (p0, z1, z0, z2), + z0 = svnmla_x (p0, z1, z0, z2)) + +/* +** nmla_f16_x_tied3: +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_x_tied3, svfloat16_t, + z0 = svnmla_f16_x (p0, z1, z2, z0), + z0 = svnmla_x (p0, z1, z2, z0)) + +/* +** nmla_f16_x_untied: +** ( +** movprfx z0, z1 +** fnmla z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fnmad z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f16_x_untied, svfloat16_t, + z0 = svnmla_f16_x (p0, z1, z2, z3), + z0 = svnmla_x (p0, z1, z2, z3)) + +/* +** nmla_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svnmla_n_f16_x (p0, z0, z1, d4), + z0 = svnmla_x (p0, z0, z1, d4)) + +/* +** nmla_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fnmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svnmla_n_f16_x (p0, z1, z0, d4), + z0 = svnmla_x (p0, z1, z0, d4)) + +/* +** nmla_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmla_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svnmla_n_f16_x (p0, z1, z2, d4), + z0 = svnmla_x (p0, z1, z2, d4)) + +/* +** nmla_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmla z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_x_tied1, svfloat16_t, + z0 = svnmla_n_f16_x (p0, z0, z1, 2), + z0 = svnmla_x (p0, z0, z1, 2)) + +/* +** nmla_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmad z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_x_tied2, svfloat16_t, + z0 = svnmla_n_f16_x (p0, z1, z0, 2), + z0 = svnmla_x (p0, z1, z0, 2)) + +/* +** nmla_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fnmad z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f16_x_untied, svfloat16_t, + z0 = svnmla_n_f16_x (p0, z1, z2, 2), + z0 = svnmla_x (p0, z1, z2, 2)) + +/* +** ptrue_nmla_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f16_x_tied1, svfloat16_t, + z0 = svnmla_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svnmla_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_nmla_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f16_x_tied2, svfloat16_t, + z0 = svnmla_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svnmla_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_nmla_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f16_x_tied3, svfloat16_t, + z0 = svnmla_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svnmla_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_nmla_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f16_x_untied, svfloat16_t, + z0 = svnmla_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svnmla_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_nmla_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f16_x_tied1, svfloat16_t, + z0 = svnmla_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svnmla_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_nmla_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f16_x_tied2, svfloat16_t, + z0 = svnmla_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svnmla_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_nmla_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f16_x_untied, svfloat16_t, + z0 = svnmla_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svnmla_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f32.c new file mode 100644 index 00000000000..ef9542d7405 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmla_f32_m_tied1: +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_m_tied1, svfloat32_t, + z0 = svnmla_f32_m (p0, z0, z1, z2), + z0 = svnmla_m (p0, z0, z1, z2)) + +/* +** nmla_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmla z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_m_tied2, svfloat32_t, + z0 = svnmla_f32_m (p0, z1, z0, z2), + z0 = svnmla_m (p0, z1, z0, z2)) + +/* +** nmla_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmla z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_m_tied3, svfloat32_t, + z0 = svnmla_f32_m (p0, z1, z2, z0), + z0 = svnmla_m (p0, z1, z2, z0)) + +/* +** nmla_f32_m_untied: +** movprfx z0, z1 +** fnmla z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_m_untied, svfloat32_t, + z0 = svnmla_f32_m (p0, z1, z2, z3), + z0 = svnmla_m (p0, z1, z2, z3)) + +/* +** nmla_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_m_tied1, svfloat32_t, float, + z0 = svnmla_n_f32_m (p0, z0, z1, d4), + z0 = svnmla_m (p0, z0, z1, d4)) + +/* +** nmla_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fnmla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_m_untied, svfloat32_t, float, + z0 = svnmla_n_f32_m (p0, z1, z2, d4), + z0 = svnmla_m (p0, z1, z2, d4)) + +/* +** nmla_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_m_tied1, svfloat32_t, + z0 = svnmla_n_f32_m (p0, z0, z1, 2), + z0 = svnmla_m (p0, z0, z1, 2)) + +/* +** nmla_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmla z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_m_untied, svfloat32_t, + z0 = svnmla_n_f32_m (p0, z1, z2, 2), + z0 = svnmla_m (p0, z1, z2, 2)) + +/* +** nmla_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_z_tied1, svfloat32_t, + z0 = svnmla_f32_z (p0, z0, z1, z2), + z0 = svnmla_z (p0, z0, z1, z2)) + +/* +** nmla_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_z_tied2, svfloat32_t, + z0 = svnmla_f32_z (p0, z1, z0, z2), + z0 = svnmla_z (p0, z1, z0, z2)) + +/* +** nmla_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_z_tied3, svfloat32_t, + z0 = svnmla_f32_z (p0, z1, z2, z0), + z0 = svnmla_z (p0, z1, z2, z0)) + +/* +** nmla_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_z_untied, svfloat32_t, + z0 = svnmla_f32_z (p0, z1, z2, z3), + z0 = svnmla_z (p0, z1, z2, z3)) + +/* +** nmla_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_z_tied1, svfloat32_t, float, + z0 = svnmla_n_f32_z (p0, z0, z1, d4), + z0 = svnmla_z (p0, z0, z1, d4)) + +/* +** nmla_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_z_tied2, svfloat32_t, float, + z0 = svnmla_n_f32_z (p0, z1, z0, d4), + z0 = svnmla_z (p0, z1, z0, d4)) + +/* +** nmla_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_z_untied, svfloat32_t, float, + z0 = svnmla_n_f32_z (p0, z1, z2, d4), + z0 = svnmla_z (p0, z1, z2, d4)) + +/* +** nmla_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_z_tied1, svfloat32_t, + z0 = svnmla_n_f32_z (p0, z0, z1, 2), + z0 = svnmla_z (p0, z0, z1, 2)) + +/* +** nmla_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_z_tied2, svfloat32_t, + z0 = svnmla_n_f32_z (p0, z1, z0, 2), + z0 = svnmla_z (p0, z1, z0, 2)) + +/* +** nmla_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmla z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmad z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_z_untied, svfloat32_t, + z0 = svnmla_n_f32_z (p0, z1, z2, 2), + z0 = svnmla_z (p0, z1, z2, 2)) + +/* +** nmla_f32_x_tied1: +** fnmla z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_x_tied1, svfloat32_t, + z0 = svnmla_f32_x (p0, z0, z1, z2), + z0 = svnmla_x (p0, z0, z1, z2)) + +/* +** nmla_f32_x_tied2: +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_x_tied2, svfloat32_t, + z0 = svnmla_f32_x (p0, z1, z0, z2), + z0 = svnmla_x (p0, z1, z0, z2)) + +/* +** nmla_f32_x_tied3: +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_x_tied3, svfloat32_t, + z0 = svnmla_f32_x (p0, z1, z2, z0), + z0 = svnmla_x (p0, z1, z2, z0)) + +/* +** nmla_f32_x_untied: +** ( +** movprfx z0, z1 +** fnmla z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fnmad z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f32_x_untied, svfloat32_t, + z0 = svnmla_f32_x (p0, z1, z2, z3), + z0 = svnmla_x (p0, z1, z2, z3)) + +/* +** nmla_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_x_tied1, svfloat32_t, float, + z0 = svnmla_n_f32_x (p0, z0, z1, d4), + z0 = svnmla_x (p0, z0, z1, d4)) + +/* +** nmla_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fnmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_x_tied2, svfloat32_t, float, + z0 = svnmla_n_f32_x (p0, z1, z0, d4), + z0 = svnmla_x (p0, z1, z0, d4)) + +/* +** nmla_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmla_s4_f32_x_untied, svfloat32_t, float, + z0 = svnmla_n_f32_x (p0, z1, z2, d4), + z0 = svnmla_x (p0, z1, z2, d4)) + +/* +** nmla_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmla z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_x_tied1, svfloat32_t, + z0 = svnmla_n_f32_x (p0, z0, z1, 2), + z0 = svnmla_x (p0, z0, z1, 2)) + +/* +** nmla_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmad z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_x_tied2, svfloat32_t, + z0 = svnmla_n_f32_x (p0, z1, z0, 2), + z0 = svnmla_x (p0, z1, z0, 2)) + +/* +** nmla_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fnmad z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f32_x_untied, svfloat32_t, + z0 = svnmla_n_f32_x (p0, z1, z2, 2), + z0 = svnmla_x (p0, z1, z2, 2)) + +/* +** ptrue_nmla_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f32_x_tied1, svfloat32_t, + z0 = svnmla_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svnmla_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_nmla_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f32_x_tied2, svfloat32_t, + z0 = svnmla_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svnmla_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_nmla_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f32_x_tied3, svfloat32_t, + z0 = svnmla_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svnmla_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_nmla_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f32_x_untied, svfloat32_t, + z0 = svnmla_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svnmla_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_nmla_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f32_x_tied1, svfloat32_t, + z0 = svnmla_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svnmla_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_nmla_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f32_x_tied2, svfloat32_t, + z0 = svnmla_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svnmla_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_nmla_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f32_x_untied, svfloat32_t, + z0 = svnmla_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svnmla_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f64.c new file mode 100644 index 00000000000..441821f606b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmla_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmla_f64_m_tied1: +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_m_tied1, svfloat64_t, + z0 = svnmla_f64_m (p0, z0, z1, z2), + z0 = svnmla_m (p0, z0, z1, z2)) + +/* +** nmla_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmla z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_m_tied2, svfloat64_t, + z0 = svnmla_f64_m (p0, z1, z0, z2), + z0 = svnmla_m (p0, z1, z0, z2)) + +/* +** nmla_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_m_tied3, svfloat64_t, + z0 = svnmla_f64_m (p0, z1, z2, z0), + z0 = svnmla_m (p0, z1, z2, z0)) + +/* +** nmla_f64_m_untied: +** movprfx z0, z1 +** fnmla z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_m_untied, svfloat64_t, + z0 = svnmla_f64_m (p0, z1, z2, z3), + z0 = svnmla_m (p0, z1, z2, z3)) + +/* +** nmla_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_m_tied1, svfloat64_t, double, + z0 = svnmla_n_f64_m (p0, z0, z1, d4), + z0 = svnmla_m (p0, z0, z1, d4)) + +/* +** nmla_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fnmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_m_untied, svfloat64_t, double, + z0 = svnmla_n_f64_m (p0, z1, z2, d4), + z0 = svnmla_m (p0, z1, z2, d4)) + +/* +** nmla_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_m_tied1, svfloat64_t, + z0 = svnmla_n_f64_m (p0, z0, z1, 2), + z0 = svnmla_m (p0, z0, z1, 2)) + +/* +** nmla_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmla z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_m_untied, svfloat64_t, + z0 = svnmla_n_f64_m (p0, z1, z2, 2), + z0 = svnmla_m (p0, z1, z2, 2)) + +/* +** nmla_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_z_tied1, svfloat64_t, + z0 = svnmla_f64_z (p0, z0, z1, z2), + z0 = svnmla_z (p0, z0, z1, z2)) + +/* +** nmla_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_z_tied2, svfloat64_t, + z0 = svnmla_f64_z (p0, z1, z0, z2), + z0 = svnmla_z (p0, z1, z0, z2)) + +/* +** nmla_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_z_tied3, svfloat64_t, + z0 = svnmla_f64_z (p0, z1, z2, z0), + z0 = svnmla_z (p0, z1, z2, z0)) + +/* +** nmla_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_z_untied, svfloat64_t, + z0 = svnmla_f64_z (p0, z1, z2, z3), + z0 = svnmla_z (p0, z1, z2, z3)) + +/* +** nmla_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_z_tied1, svfloat64_t, double, + z0 = svnmla_n_f64_z (p0, z0, z1, d4), + z0 = svnmla_z (p0, z0, z1, d4)) + +/* +** nmla_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_z_tied2, svfloat64_t, double, + z0 = svnmla_n_f64_z (p0, z1, z0, d4), + z0 = svnmla_z (p0, z1, z0, d4)) + +/* +** nmla_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_z_untied, svfloat64_t, double, + z0 = svnmla_n_f64_z (p0, z1, z2, d4), + z0 = svnmla_z (p0, z1, z2, d4)) + +/* +** nmla_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_z_tied1, svfloat64_t, + z0 = svnmla_n_f64_z (p0, z0, z1, 2), + z0 = svnmla_z (p0, z0, z1, 2)) + +/* +** nmla_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_z_tied2, svfloat64_t, + z0 = svnmla_n_f64_z (p0, z1, z0, 2), + z0 = svnmla_z (p0, z1, z0, 2)) + +/* +** nmla_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmla z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmad z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_z_untied, svfloat64_t, + z0 = svnmla_n_f64_z (p0, z1, z2, 2), + z0 = svnmla_z (p0, z1, z2, 2)) + +/* +** nmla_f64_x_tied1: +** fnmla z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_x_tied1, svfloat64_t, + z0 = svnmla_f64_x (p0, z0, z1, z2), + z0 = svnmla_x (p0, z0, z1, z2)) + +/* +** nmla_f64_x_tied2: +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_x_tied2, svfloat64_t, + z0 = svnmla_f64_x (p0, z1, z0, z2), + z0 = svnmla_x (p0, z1, z0, z2)) + +/* +** nmla_f64_x_tied3: +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_x_tied3, svfloat64_t, + z0 = svnmla_f64_x (p0, z1, z2, z0), + z0 = svnmla_x (p0, z1, z2, z0)) + +/* +** nmla_f64_x_untied: +** ( +** movprfx z0, z1 +** fnmla z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fnmad z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmla_f64_x_untied, svfloat64_t, + z0 = svnmla_f64_x (p0, z1, z2, z3), + z0 = svnmla_x (p0, z1, z2, z3)) + +/* +** nmla_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_x_tied1, svfloat64_t, double, + z0 = svnmla_n_f64_x (p0, z0, z1, d4), + z0 = svnmla_x (p0, z0, z1, d4)) + +/* +** nmla_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fnmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_x_tied2, svfloat64_t, double, + z0 = svnmla_n_f64_x (p0, z1, z0, d4), + z0 = svnmla_x (p0, z1, z0, d4)) + +/* +** nmla_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmla_d4_f64_x_untied, svfloat64_t, double, + z0 = svnmla_n_f64_x (p0, z1, z2, d4), + z0 = svnmla_x (p0, z1, z2, d4)) + +/* +** nmla_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmla z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_x_tied1, svfloat64_t, + z0 = svnmla_n_f64_x (p0, z0, z1, 2), + z0 = svnmla_x (p0, z0, z1, 2)) + +/* +** nmla_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmad z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_x_tied2, svfloat64_t, + z0 = svnmla_n_f64_x (p0, z1, z0, 2), + z0 = svnmla_x (p0, z1, z0, 2)) + +/* +** nmla_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fnmad z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmla_2_f64_x_untied, svfloat64_t, + z0 = svnmla_n_f64_x (p0, z1, z2, 2), + z0 = svnmla_x (p0, z1, z2, 2)) + +/* +** ptrue_nmla_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f64_x_tied1, svfloat64_t, + z0 = svnmla_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svnmla_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_nmla_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f64_x_tied2, svfloat64_t, + z0 = svnmla_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svnmla_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_nmla_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f64_x_tied3, svfloat64_t, + z0 = svnmla_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svnmla_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_nmla_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_f64_x_untied, svfloat64_t, + z0 = svnmla_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svnmla_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_nmla_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f64_x_tied1, svfloat64_t, + z0 = svnmla_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svnmla_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_nmla_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f64_x_tied2, svfloat64_t, + z0 = svnmla_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svnmla_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_nmla_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmla_2_f64_x_untied, svfloat64_t, + z0 = svnmla_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svnmla_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f16.c new file mode 100644 index 00000000000..8aa6c750970 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmls_f16_m_tied1: +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_m_tied1, svfloat16_t, + z0 = svnmls_f16_m (p0, z0, z1, z2), + z0 = svnmls_m (p0, z0, z1, z2)) + +/* +** nmls_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmls z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_m_tied2, svfloat16_t, + z0 = svnmls_f16_m (p0, z1, z0, z2), + z0 = svnmls_m (p0, z1, z0, z2)) + +/* +** nmls_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmls z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_m_tied3, svfloat16_t, + z0 = svnmls_f16_m (p0, z1, z2, z0), + z0 = svnmls_m (p0, z1, z2, z0)) + +/* +** nmls_f16_m_untied: +** movprfx z0, z1 +** fnmls z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_m_untied, svfloat16_t, + z0 = svnmls_f16_m (p0, z1, z2, z3), + z0 = svnmls_m (p0, z1, z2, z3)) + +/* +** nmls_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svnmls_n_f16_m (p0, z0, z1, d4), + z0 = svnmls_m (p0, z0, z1, d4)) + +/* +** nmls_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fnmls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svnmls_n_f16_m (p0, z1, z2, d4), + z0 = svnmls_m (p0, z1, z2, d4)) + +/* +** nmls_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_m_tied1, svfloat16_t, + z0 = svnmls_n_f16_m (p0, z0, z1, 2), + z0 = svnmls_m (p0, z0, z1, 2)) + +/* +** nmls_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmls z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_m_untied, svfloat16_t, + z0 = svnmls_n_f16_m (p0, z1, z2, 2), + z0 = svnmls_m (p0, z1, z2, 2)) + +/* +** nmls_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_z_tied1, svfloat16_t, + z0 = svnmls_f16_z (p0, z0, z1, z2), + z0 = svnmls_z (p0, z0, z1, z2)) + +/* +** nmls_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_z_tied2, svfloat16_t, + z0 = svnmls_f16_z (p0, z1, z0, z2), + z0 = svnmls_z (p0, z1, z0, z2)) + +/* +** nmls_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_z_tied3, svfloat16_t, + z0 = svnmls_f16_z (p0, z1, z2, z0), + z0 = svnmls_z (p0, z1, z2, z0)) + +/* +** nmls_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_z_untied, svfloat16_t, + z0 = svnmls_f16_z (p0, z1, z2, z3), + z0 = svnmls_z (p0, z1, z2, z3)) + +/* +** nmls_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svnmls_n_f16_z (p0, z0, z1, d4), + z0 = svnmls_z (p0, z0, z1, d4)) + +/* +** nmls_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svnmls_n_f16_z (p0, z1, z0, d4), + z0 = svnmls_z (p0, z1, z0, d4)) + +/* +** nmls_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svnmls_n_f16_z (p0, z1, z2, d4), + z0 = svnmls_z (p0, z1, z2, d4)) + +/* +** nmls_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_z_tied1, svfloat16_t, + z0 = svnmls_n_f16_z (p0, z0, z1, 2), + z0 = svnmls_z (p0, z0, z1, 2)) + +/* +** nmls_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_z_tied2, svfloat16_t, + z0 = svnmls_n_f16_z (p0, z1, z0, 2), + z0 = svnmls_z (p0, z1, z0, 2)) + +/* +** nmls_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmls z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, \1, z1\.h +** | +** movprfx z0\.h, p0/z, \1 +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_z_untied, svfloat16_t, + z0 = svnmls_n_f16_z (p0, z1, z2, 2), + z0 = svnmls_z (p0, z1, z2, 2)) + +/* +** nmls_f16_x_tied1: +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_x_tied1, svfloat16_t, + z0 = svnmls_f16_x (p0, z0, z1, z2), + z0 = svnmls_x (p0, z0, z1, z2)) + +/* +** nmls_f16_x_tied2: +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_x_tied2, svfloat16_t, + z0 = svnmls_f16_x (p0, z1, z0, z2), + z0 = svnmls_x (p0, z1, z0, z2)) + +/* +** nmls_f16_x_tied3: +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_x_tied3, svfloat16_t, + z0 = svnmls_f16_x (p0, z1, z2, z0), + z0 = svnmls_x (p0, z1, z2, z0)) + +/* +** nmls_f16_x_untied: +** ( +** movprfx z0, z1 +** fnmls z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fnmsb z0\.h, p0/m, z3\.h, z1\.h +** | +** movprfx z0, z3 +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f16_x_untied, svfloat16_t, + z0 = svnmls_f16_x (p0, z1, z2, z3), + z0 = svnmls_x (p0, z1, z2, z3)) + +/* +** nmls_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svnmls_n_f16_x (p0, z0, z1, d4), + z0 = svnmls_x (p0, z0, z1, d4)) + +/* +** nmls_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fnmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svnmls_n_f16_x (p0, z1, z0, d4), + z0 = svnmls_x (p0, z1, z0, d4)) + +/* +** nmls_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (nmls_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svnmls_n_f16_x (p0, z1, z2, d4), + z0 = svnmls_x (p0, z1, z2, d4)) + +/* +** nmls_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmls z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_x_tied1, svfloat16_t, + z0 = svnmls_n_f16_x (p0, z0, z1, 2), + z0 = svnmls_x (p0, z0, z1, 2)) + +/* +** nmls_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmsb z0\.h, p0/m, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_x_tied2, svfloat16_t, + z0 = svnmls_n_f16_x (p0, z1, z0, 2), + z0 = svnmls_x (p0, z1, z0, 2)) + +/* +** nmls_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fnmsb z0\.h, p0/m, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f16_x_untied, svfloat16_t, + z0 = svnmls_n_f16_x (p0, z1, z2, 2), + z0 = svnmls_x (p0, z1, z2, 2)) + +/* +** ptrue_nmls_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f16_x_tied1, svfloat16_t, + z0 = svnmls_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svnmls_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_nmls_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f16_x_tied2, svfloat16_t, + z0 = svnmls_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svnmls_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_nmls_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f16_x_tied3, svfloat16_t, + z0 = svnmls_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svnmls_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_nmls_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f16_x_untied, svfloat16_t, + z0 = svnmls_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svnmls_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_nmls_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f16_x_tied1, svfloat16_t, + z0 = svnmls_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svnmls_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_nmls_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f16_x_tied2, svfloat16_t, + z0 = svnmls_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svnmls_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_nmls_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f16_x_untied, svfloat16_t, + z0 = svnmls_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svnmls_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f32.c new file mode 100644 index 00000000000..42ea13faca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmls_f32_m_tied1: +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_m_tied1, svfloat32_t, + z0 = svnmls_f32_m (p0, z0, z1, z2), + z0 = svnmls_m (p0, z0, z1, z2)) + +/* +** nmls_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmls z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_m_tied2, svfloat32_t, + z0 = svnmls_f32_m (p0, z1, z0, z2), + z0 = svnmls_m (p0, z1, z0, z2)) + +/* +** nmls_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmls z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_m_tied3, svfloat32_t, + z0 = svnmls_f32_m (p0, z1, z2, z0), + z0 = svnmls_m (p0, z1, z2, z0)) + +/* +** nmls_f32_m_untied: +** movprfx z0, z1 +** fnmls z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_m_untied, svfloat32_t, + z0 = svnmls_f32_m (p0, z1, z2, z3), + z0 = svnmls_m (p0, z1, z2, z3)) + +/* +** nmls_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_m_tied1, svfloat32_t, float, + z0 = svnmls_n_f32_m (p0, z0, z1, d4), + z0 = svnmls_m (p0, z0, z1, d4)) + +/* +** nmls_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fnmls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_m_untied, svfloat32_t, float, + z0 = svnmls_n_f32_m (p0, z1, z2, d4), + z0 = svnmls_m (p0, z1, z2, d4)) + +/* +** nmls_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_m_tied1, svfloat32_t, + z0 = svnmls_n_f32_m (p0, z0, z1, 2), + z0 = svnmls_m (p0, z0, z1, 2)) + +/* +** nmls_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmls z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_m_untied, svfloat32_t, + z0 = svnmls_n_f32_m (p0, z1, z2, 2), + z0 = svnmls_m (p0, z1, z2, 2)) + +/* +** nmls_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_z_tied1, svfloat32_t, + z0 = svnmls_f32_z (p0, z0, z1, z2), + z0 = svnmls_z (p0, z0, z1, z2)) + +/* +** nmls_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_z_tied2, svfloat32_t, + z0 = svnmls_f32_z (p0, z1, z0, z2), + z0 = svnmls_z (p0, z1, z0, z2)) + +/* +** nmls_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_z_tied3, svfloat32_t, + z0 = svnmls_f32_z (p0, z1, z2, z0), + z0 = svnmls_z (p0, z1, z2, z0)) + +/* +** nmls_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_z_untied, svfloat32_t, + z0 = svnmls_f32_z (p0, z1, z2, z3), + z0 = svnmls_z (p0, z1, z2, z3)) + +/* +** nmls_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_z_tied1, svfloat32_t, float, + z0 = svnmls_n_f32_z (p0, z0, z1, d4), + z0 = svnmls_z (p0, z0, z1, d4)) + +/* +** nmls_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_z_tied2, svfloat32_t, float, + z0 = svnmls_n_f32_z (p0, z1, z0, d4), + z0 = svnmls_z (p0, z1, z0, d4)) + +/* +** nmls_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_z_untied, svfloat32_t, float, + z0 = svnmls_n_f32_z (p0, z1, z2, d4), + z0 = svnmls_z (p0, z1, z2, d4)) + +/* +** nmls_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_z_tied1, svfloat32_t, + z0 = svnmls_n_f32_z (p0, z0, z1, 2), + z0 = svnmls_z (p0, z0, z1, 2)) + +/* +** nmls_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_z_tied2, svfloat32_t, + z0 = svnmls_n_f32_z (p0, z1, z0, 2), + z0 = svnmls_z (p0, z1, z0, 2)) + +/* +** nmls_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmls z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, \1, z1\.s +** | +** movprfx z0\.s, p0/z, \1 +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_z_untied, svfloat32_t, + z0 = svnmls_n_f32_z (p0, z1, z2, 2), + z0 = svnmls_z (p0, z1, z2, 2)) + +/* +** nmls_f32_x_tied1: +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_x_tied1, svfloat32_t, + z0 = svnmls_f32_x (p0, z0, z1, z2), + z0 = svnmls_x (p0, z0, z1, z2)) + +/* +** nmls_f32_x_tied2: +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_x_tied2, svfloat32_t, + z0 = svnmls_f32_x (p0, z1, z0, z2), + z0 = svnmls_x (p0, z1, z0, z2)) + +/* +** nmls_f32_x_tied3: +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_x_tied3, svfloat32_t, + z0 = svnmls_f32_x (p0, z1, z2, z0), + z0 = svnmls_x (p0, z1, z2, z0)) + +/* +** nmls_f32_x_untied: +** ( +** movprfx z0, z1 +** fnmls z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fnmsb z0\.s, p0/m, z3\.s, z1\.s +** | +** movprfx z0, z3 +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f32_x_untied, svfloat32_t, + z0 = svnmls_f32_x (p0, z1, z2, z3), + z0 = svnmls_x (p0, z1, z2, z3)) + +/* +** nmls_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_x_tied1, svfloat32_t, float, + z0 = svnmls_n_f32_x (p0, z0, z1, d4), + z0 = svnmls_x (p0, z0, z1, d4)) + +/* +** nmls_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fnmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_x_tied2, svfloat32_t, float, + z0 = svnmls_n_f32_x (p0, z1, z0, d4), + z0 = svnmls_x (p0, z1, z0, d4)) + +/* +** nmls_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (nmls_s4_f32_x_untied, svfloat32_t, float, + z0 = svnmls_n_f32_x (p0, z1, z2, d4), + z0 = svnmls_x (p0, z1, z2, d4)) + +/* +** nmls_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmls z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_x_tied1, svfloat32_t, + z0 = svnmls_n_f32_x (p0, z0, z1, 2), + z0 = svnmls_x (p0, z0, z1, 2)) + +/* +** nmls_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmsb z0\.s, p0/m, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_x_tied2, svfloat32_t, + z0 = svnmls_n_f32_x (p0, z1, z0, 2), + z0 = svnmls_x (p0, z1, z0, 2)) + +/* +** nmls_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fnmsb z0\.s, p0/m, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f32_x_untied, svfloat32_t, + z0 = svnmls_n_f32_x (p0, z1, z2, 2), + z0 = svnmls_x (p0, z1, z2, 2)) + +/* +** ptrue_nmls_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f32_x_tied1, svfloat32_t, + z0 = svnmls_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svnmls_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_nmls_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f32_x_tied2, svfloat32_t, + z0 = svnmls_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svnmls_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_nmls_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f32_x_tied3, svfloat32_t, + z0 = svnmls_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svnmls_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_nmls_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f32_x_untied, svfloat32_t, + z0 = svnmls_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svnmls_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_nmls_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f32_x_tied1, svfloat32_t, + z0 = svnmls_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svnmls_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_nmls_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f32_x_tied2, svfloat32_t, + z0 = svnmls_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svnmls_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_nmls_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f32_x_untied, svfloat32_t, + z0 = svnmls_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svnmls_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f64.c new file mode 100644 index 00000000000..994c2a74eeb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmls_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmls_f64_m_tied1: +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_m_tied1, svfloat64_t, + z0 = svnmls_f64_m (p0, z0, z1, z2), + z0 = svnmls_m (p0, z0, z1, z2)) + +/* +** nmls_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmls z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_m_tied2, svfloat64_t, + z0 = svnmls_f64_m (p0, z1, z0, z2), + z0 = svnmls_m (p0, z1, z0, z2)) + +/* +** nmls_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_m_tied3, svfloat64_t, + z0 = svnmls_f64_m (p0, z1, z2, z0), + z0 = svnmls_m (p0, z1, z2, z0)) + +/* +** nmls_f64_m_untied: +** movprfx z0, z1 +** fnmls z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_m_untied, svfloat64_t, + z0 = svnmls_f64_m (p0, z1, z2, z3), + z0 = svnmls_m (p0, z1, z2, z3)) + +/* +** nmls_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_m_tied1, svfloat64_t, double, + z0 = svnmls_n_f64_m (p0, z0, z1, d4), + z0 = svnmls_m (p0, z0, z1, d4)) + +/* +** nmls_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fnmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_m_untied, svfloat64_t, double, + z0 = svnmls_n_f64_m (p0, z1, z2, d4), + z0 = svnmls_m (p0, z1, z2, d4)) + +/* +** nmls_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_m_tied1, svfloat64_t, + z0 = svnmls_n_f64_m (p0, z0, z1, 2), + z0 = svnmls_m (p0, z0, z1, 2)) + +/* +** nmls_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmls z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_m_untied, svfloat64_t, + z0 = svnmls_n_f64_m (p0, z1, z2, 2), + z0 = svnmls_m (p0, z1, z2, 2)) + +/* +** nmls_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_z_tied1, svfloat64_t, + z0 = svnmls_f64_z (p0, z0, z1, z2), + z0 = svnmls_z (p0, z0, z1, z2)) + +/* +** nmls_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_z_tied2, svfloat64_t, + z0 = svnmls_f64_z (p0, z1, z0, z2), + z0 = svnmls_z (p0, z1, z0, z2)) + +/* +** nmls_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_z_tied3, svfloat64_t, + z0 = svnmls_f64_z (p0, z1, z2, z0), + z0 = svnmls_z (p0, z1, z2, z0)) + +/* +** nmls_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_z_untied, svfloat64_t, + z0 = svnmls_f64_z (p0, z1, z2, z3), + z0 = svnmls_z (p0, z1, z2, z3)) + +/* +** nmls_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_z_tied1, svfloat64_t, double, + z0 = svnmls_n_f64_z (p0, z0, z1, d4), + z0 = svnmls_z (p0, z0, z1, d4)) + +/* +** nmls_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_z_tied2, svfloat64_t, double, + z0 = svnmls_n_f64_z (p0, z1, z0, d4), + z0 = svnmls_z (p0, z1, z0, d4)) + +/* +** nmls_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_z_untied, svfloat64_t, double, + z0 = svnmls_n_f64_z (p0, z1, z2, d4), + z0 = svnmls_z (p0, z1, z2, d4)) + +/* +** nmls_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_z_tied1, svfloat64_t, + z0 = svnmls_n_f64_z (p0, z0, z1, 2), + z0 = svnmls_z (p0, z0, z1, 2)) + +/* +** nmls_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_z_tied2, svfloat64_t, + z0 = svnmls_n_f64_z (p0, z1, z0, 2), + z0 = svnmls_z (p0, z1, z0, 2)) + +/* +** nmls_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmls z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, \1, z1\.d +** | +** movprfx z0\.d, p0/z, \1 +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_z_untied, svfloat64_t, + z0 = svnmls_n_f64_z (p0, z1, z2, 2), + z0 = svnmls_z (p0, z1, z2, 2)) + +/* +** nmls_f64_x_tied1: +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_x_tied1, svfloat64_t, + z0 = svnmls_f64_x (p0, z0, z1, z2), + z0 = svnmls_x (p0, z0, z1, z2)) + +/* +** nmls_f64_x_tied2: +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_x_tied2, svfloat64_t, + z0 = svnmls_f64_x (p0, z1, z0, z2), + z0 = svnmls_x (p0, z1, z0, z2)) + +/* +** nmls_f64_x_tied3: +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_x_tied3, svfloat64_t, + z0 = svnmls_f64_x (p0, z1, z2, z0), + z0 = svnmls_x (p0, z1, z2, z0)) + +/* +** nmls_f64_x_untied: +** ( +** movprfx z0, z1 +** fnmls z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fnmsb z0\.d, p0/m, z3\.d, z1\.d +** | +** movprfx z0, z3 +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmls_f64_x_untied, svfloat64_t, + z0 = svnmls_f64_x (p0, z1, z2, z3), + z0 = svnmls_x (p0, z1, z2, z3)) + +/* +** nmls_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_x_tied1, svfloat64_t, double, + z0 = svnmls_n_f64_x (p0, z0, z1, d4), + z0 = svnmls_x (p0, z0, z1, d4)) + +/* +** nmls_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fnmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_x_tied2, svfloat64_t, double, + z0 = svnmls_n_f64_x (p0, z1, z0, d4), + z0 = svnmls_x (p0, z1, z0, d4)) + +/* +** nmls_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (nmls_d4_f64_x_untied, svfloat64_t, double, + z0 = svnmls_n_f64_x (p0, z1, z2, d4), + z0 = svnmls_x (p0, z1, z2, d4)) + +/* +** nmls_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmls z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_x_tied1, svfloat64_t, + z0 = svnmls_n_f64_x (p0, z0, z1, 2), + z0 = svnmls_x (p0, z0, z1, 2)) + +/* +** nmls_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmsb z0\.d, p0/m, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_x_tied2, svfloat64_t, + z0 = svnmls_n_f64_x (p0, z1, z0, 2), + z0 = svnmls_x (p0, z1, z0, 2)) + +/* +** nmls_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fnmsb z0\.d, p0/m, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (nmls_2_f64_x_untied, svfloat64_t, + z0 = svnmls_n_f64_x (p0, z1, z2, 2), + z0 = svnmls_x (p0, z1, z2, 2)) + +/* +** ptrue_nmls_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f64_x_tied1, svfloat64_t, + z0 = svnmls_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svnmls_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_nmls_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f64_x_tied2, svfloat64_t, + z0 = svnmls_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svnmls_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_nmls_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f64_x_tied3, svfloat64_t, + z0 = svnmls_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svnmls_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_nmls_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_f64_x_untied, svfloat64_t, + z0 = svnmls_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svnmls_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_nmls_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f64_x_tied1, svfloat64_t, + z0 = svnmls_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svnmls_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_nmls_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f64_x_tied2, svfloat64_t, + z0 = svnmls_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svnmls_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_nmls_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmls_2_f64_x_untied, svfloat64_t, + z0 = svnmls_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svnmls_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f16.c new file mode 100644 index 00000000000..c1140148522 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f16.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmsb_f16_m_tied1: +** fnmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_m_tied1, svfloat16_t, + z0 = svnmsb_f16_m (p0, z0, z1, z2), + z0 = svnmsb_m (p0, z0, z1, z2)) + +/* +** nmsb_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, \1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_m_tied2, svfloat16_t, + z0 = svnmsb_f16_m (p0, z1, z0, z2), + z0 = svnmsb_m (p0, z1, z0, z2)) + +/* +** nmsb_f16_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, z2\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_m_tied3, svfloat16_t, + z0 = svnmsb_f16_m (p0, z1, z2, z0), + z0 = svnmsb_m (p0, z1, z2, z0)) + +/* +** nmsb_f16_m_untied: +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, z2\.h, z3\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_m_untied, svfloat16_t, + z0 = svnmsb_f16_m (p0, z1, z2, z3), + z0 = svnmsb_m (p0, z1, z2, z3)) + +/* +** nmsb_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_m (p0, z0, z1, d4), + z0 = svnmsb_m (p0, z0, z1, d4)) + +/* +** nmsb_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_m (p0, z1, z2, d4), + z0 = svnmsb_m (p0, z1, z2, d4)) + +/* +** nmsb_2_f16_m_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_m_tied1, svfloat16_t, + z0 = svnmsb_n_f16_m (p0, z0, z1, 2), + z0 = svnmsb_m (p0, z0, z1, 2)) + +/* +** nmsb_2_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, z2\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_m_untied, svfloat16_t, + z0 = svnmsb_n_f16_m (p0, z1, z2, 2), + z0 = svnmsb_m (p0, z1, z2, 2)) + +/* +** nmsb_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_z_tied1, svfloat16_t, + z0 = svnmsb_f16_z (p0, z0, z1, z2), + z0 = svnmsb_z (p0, z0, z1, z2)) + +/* +** nmsb_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_z_tied2, svfloat16_t, + z0 = svnmsb_f16_z (p0, z1, z0, z2), + z0 = svnmsb_z (p0, z1, z0, z2)) + +/* +** nmsb_f16_z_tied3: +** movprfx z0\.h, p0/z, z0\.h +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_z_tied3, svfloat16_t, + z0 = svnmsb_f16_z (p0, z1, z2, z0), + z0 = svnmsb_z (p0, z1, z2, z0)) + +/* +** nmsb_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmsb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0\.h, p0/z, z3\.h +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_z_untied, svfloat16_t, + z0 = svnmsb_f16_z (p0, z1, z2, z3), + z0 = svnmsb_z (p0, z1, z2, z3)) + +/* +** nmsb_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_z (p0, z0, z1, d4), + z0 = svnmsb_z (p0, z0, z1, d4)) + +/* +** nmsb_h4_f16_z_tied2: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_z_tied2, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_z (p0, z1, z0, d4), + z0 = svnmsb_z (p0, z1, z0, d4)) + +/* +** nmsb_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmsb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_z (p0, z1, z2, d4), + z0 = svnmsb_z (p0, z1, z2, d4)) + +/* +** nmsb_2_f16_z_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_z_tied1, svfloat16_t, + z0 = svnmsb_n_f16_z (p0, z0, z1, 2), + z0 = svnmsb_z (p0, z0, z1, 2)) + +/* +** nmsb_2_f16_z_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_z_tied2, svfloat16_t, + z0 = svnmsb_n_f16_z (p0, z1, z0, 2), + z0 = svnmsb_z (p0, z1, z0, 2)) + +/* +** nmsb_2_f16_z_untied: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fnmsb z0\.h, p0/m, z2\.h, \1 +** | +** movprfx z0\.h, p0/z, z2\.h +** fnmsb z0\.h, p0/m, z1\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_z_untied, svfloat16_t, + z0 = svnmsb_n_f16_z (p0, z1, z2, 2), + z0 = svnmsb_z (p0, z1, z2, 2)) + +/* +** nmsb_f16_x_tied1: +** fnmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_x_tied1, svfloat16_t, + z0 = svnmsb_f16_x (p0, z0, z1, z2), + z0 = svnmsb_x (p0, z0, z1, z2)) + +/* +** nmsb_f16_x_tied2: +** fnmsb z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_x_tied2, svfloat16_t, + z0 = svnmsb_f16_x (p0, z1, z0, z2), + z0 = svnmsb_x (p0, z1, z0, z2)) + +/* +** nmsb_f16_x_tied3: +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_x_tied3, svfloat16_t, + z0 = svnmsb_f16_x (p0, z1, z2, z0), + z0 = svnmsb_x (p0, z1, z2, z0)) + +/* +** nmsb_f16_x_untied: +** ( +** movprfx z0, z1 +** fnmsb z0\.h, p0/m, z2\.h, z3\.h +** | +** movprfx z0, z2 +** fnmsb z0\.h, p0/m, z1\.h, z3\.h +** | +** movprfx z0, z3 +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f16_x_untied, svfloat16_t, + z0 = svnmsb_f16_x (p0, z1, z2, z3), + z0 = svnmsb_x (p0, z1, z2, z3)) + +/* +** nmsb_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_x (p0, z0, z1, d4), + z0 = svnmsb_x (p0, z0, z1, d4)) + +/* +** nmsb_h4_f16_x_tied2: +** mov (z[0-9]+\.h), h4 +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_x_tied2, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_x (p0, z1, z0, d4), + z0 = svnmsb_x (p0, z1, z0, d4)) + +/* +** nmsb_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_ZD (nmsb_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svnmsb_n_f16_x (p0, z1, z2, d4), + z0 = svnmsb_x (p0, z1, z2, d4)) + +/* +** nmsb_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_x_tied1, svfloat16_t, + z0 = svnmsb_n_f16_x (p0, z0, z1, 2), + z0 = svnmsb_x (p0, z0, z1, 2)) + +/* +** nmsb_2_f16_x_tied2: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fnmsb z0\.h, p0/m, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_x_tied2, svfloat16_t, + z0 = svnmsb_n_f16_x (p0, z1, z0, 2), + z0 = svnmsb_x (p0, z1, z0, 2)) + +/* +** nmsb_2_f16_x_untied: +** fmov z0\.h, #2\.0(?:e\+0)? +** fnmls z0\.h, p0/m, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f16_x_untied, svfloat16_t, + z0 = svnmsb_n_f16_x (p0, z1, z2, 2), + z0 = svnmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_nmsb_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f16_x_tied1, svfloat16_t, + z0 = svnmsb_f16_x (svptrue_b16 (), z0, z1, z2), + z0 = svnmsb_x (svptrue_b16 (), z0, z1, z2)) + +/* +** ptrue_nmsb_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f16_x_tied2, svfloat16_t, + z0 = svnmsb_f16_x (svptrue_b16 (), z1, z0, z2), + z0 = svnmsb_x (svptrue_b16 (), z1, z0, z2)) + +/* +** ptrue_nmsb_f16_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f16_x_tied3, svfloat16_t, + z0 = svnmsb_f16_x (svptrue_b16 (), z1, z2, z0), + z0 = svnmsb_x (svptrue_b16 (), z1, z2, z0)) + +/* +** ptrue_nmsb_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f16_x_untied, svfloat16_t, + z0 = svnmsb_f16_x (svptrue_b16 (), z1, z2, z3), + z0 = svnmsb_x (svptrue_b16 (), z1, z2, z3)) + +/* +** ptrue_nmsb_2_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f16_x_tied1, svfloat16_t, + z0 = svnmsb_n_f16_x (svptrue_b16 (), z0, z1, 2), + z0 = svnmsb_x (svptrue_b16 (), z0, z1, 2)) + +/* +** ptrue_nmsb_2_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f16_x_tied2, svfloat16_t, + z0 = svnmsb_n_f16_x (svptrue_b16 (), z1, z0, 2), + z0 = svnmsb_x (svptrue_b16 (), z1, z0, 2)) + +/* +** ptrue_nmsb_2_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f16_x_untied, svfloat16_t, + z0 = svnmsb_n_f16_x (svptrue_b16 (), z1, z2, 2), + z0 = svnmsb_x (svptrue_b16 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f32.c new file mode 100644 index 00000000000..c2204e040ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f32.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmsb_f32_m_tied1: +** fnmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_m_tied1, svfloat32_t, + z0 = svnmsb_f32_m (p0, z0, z1, z2), + z0 = svnmsb_m (p0, z0, z1, z2)) + +/* +** nmsb_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, \1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_m_tied2, svfloat32_t, + z0 = svnmsb_f32_m (p0, z1, z0, z2), + z0 = svnmsb_m (p0, z1, z0, z2)) + +/* +** nmsb_f32_m_tied3: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, z2\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_m_tied3, svfloat32_t, + z0 = svnmsb_f32_m (p0, z1, z2, z0), + z0 = svnmsb_m (p0, z1, z2, z0)) + +/* +** nmsb_f32_m_untied: +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, z2\.s, z3\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_m_untied, svfloat32_t, + z0 = svnmsb_f32_m (p0, z1, z2, z3), + z0 = svnmsb_m (p0, z1, z2, z3)) + +/* +** nmsb_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_m_tied1, svfloat32_t, float, + z0 = svnmsb_n_f32_m (p0, z0, z1, d4), + z0 = svnmsb_m (p0, z0, z1, d4)) + +/* +** nmsb_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_m_untied, svfloat32_t, float, + z0 = svnmsb_n_f32_m (p0, z1, z2, d4), + z0 = svnmsb_m (p0, z1, z2, d4)) + +/* +** nmsb_2_f32_m_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_m_tied1, svfloat32_t, + z0 = svnmsb_n_f32_m (p0, z0, z1, 2), + z0 = svnmsb_m (p0, z0, z1, 2)) + +/* +** nmsb_2_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, z2\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_m_untied, svfloat32_t, + z0 = svnmsb_n_f32_m (p0, z1, z2, 2), + z0 = svnmsb_m (p0, z1, z2, 2)) + +/* +** nmsb_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_z_tied1, svfloat32_t, + z0 = svnmsb_f32_z (p0, z0, z1, z2), + z0 = svnmsb_z (p0, z0, z1, z2)) + +/* +** nmsb_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_z_tied2, svfloat32_t, + z0 = svnmsb_f32_z (p0, z1, z0, z2), + z0 = svnmsb_z (p0, z1, z0, z2)) + +/* +** nmsb_f32_z_tied3: +** movprfx z0\.s, p0/z, z0\.s +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_z_tied3, svfloat32_t, + z0 = svnmsb_f32_z (p0, z1, z2, z0), + z0 = svnmsb_z (p0, z1, z2, z0)) + +/* +** nmsb_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmsb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0\.s, p0/z, z3\.s +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_z_untied, svfloat32_t, + z0 = svnmsb_f32_z (p0, z1, z2, z3), + z0 = svnmsb_z (p0, z1, z2, z3)) + +/* +** nmsb_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_z_tied1, svfloat32_t, float, + z0 = svnmsb_n_f32_z (p0, z0, z1, d4), + z0 = svnmsb_z (p0, z0, z1, d4)) + +/* +** nmsb_s4_f32_z_tied2: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_z_tied2, svfloat32_t, float, + z0 = svnmsb_n_f32_z (p0, z1, z0, d4), + z0 = svnmsb_z (p0, z1, z0, d4)) + +/* +** nmsb_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmsb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_z_untied, svfloat32_t, float, + z0 = svnmsb_n_f32_z (p0, z1, z2, d4), + z0 = svnmsb_z (p0, z1, z2, d4)) + +/* +** nmsb_2_f32_z_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_z_tied1, svfloat32_t, + z0 = svnmsb_n_f32_z (p0, z0, z1, 2), + z0 = svnmsb_z (p0, z0, z1, 2)) + +/* +** nmsb_2_f32_z_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_z_tied2, svfloat32_t, + z0 = svnmsb_n_f32_z (p0, z1, z0, 2), + z0 = svnmsb_z (p0, z1, z0, 2)) + +/* +** nmsb_2_f32_z_untied: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fnmsb z0\.s, p0/m, z2\.s, \1 +** | +** movprfx z0\.s, p0/z, z2\.s +** fnmsb z0\.s, p0/m, z1\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_z_untied, svfloat32_t, + z0 = svnmsb_n_f32_z (p0, z1, z2, 2), + z0 = svnmsb_z (p0, z1, z2, 2)) + +/* +** nmsb_f32_x_tied1: +** fnmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_x_tied1, svfloat32_t, + z0 = svnmsb_f32_x (p0, z0, z1, z2), + z0 = svnmsb_x (p0, z0, z1, z2)) + +/* +** nmsb_f32_x_tied2: +** fnmsb z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_x_tied2, svfloat32_t, + z0 = svnmsb_f32_x (p0, z1, z0, z2), + z0 = svnmsb_x (p0, z1, z0, z2)) + +/* +** nmsb_f32_x_tied3: +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_x_tied3, svfloat32_t, + z0 = svnmsb_f32_x (p0, z1, z2, z0), + z0 = svnmsb_x (p0, z1, z2, z0)) + +/* +** nmsb_f32_x_untied: +** ( +** movprfx z0, z1 +** fnmsb z0\.s, p0/m, z2\.s, z3\.s +** | +** movprfx z0, z2 +** fnmsb z0\.s, p0/m, z1\.s, z3\.s +** | +** movprfx z0, z3 +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f32_x_untied, svfloat32_t, + z0 = svnmsb_f32_x (p0, z1, z2, z3), + z0 = svnmsb_x (p0, z1, z2, z3)) + +/* +** nmsb_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_x_tied1, svfloat32_t, float, + z0 = svnmsb_n_f32_x (p0, z0, z1, d4), + z0 = svnmsb_x (p0, z0, z1, d4)) + +/* +** nmsb_s4_f32_x_tied2: +** mov (z[0-9]+\.s), s4 +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_x_tied2, svfloat32_t, float, + z0 = svnmsb_n_f32_x (p0, z1, z0, d4), + z0 = svnmsb_x (p0, z1, z0, d4)) + +/* +** nmsb_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_ZD (nmsb_s4_f32_x_untied, svfloat32_t, float, + z0 = svnmsb_n_f32_x (p0, z1, z2, d4), + z0 = svnmsb_x (p0, z1, z2, d4)) + +/* +** nmsb_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_x_tied1, svfloat32_t, + z0 = svnmsb_n_f32_x (p0, z0, z1, 2), + z0 = svnmsb_x (p0, z0, z1, 2)) + +/* +** nmsb_2_f32_x_tied2: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fnmsb z0\.s, p0/m, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_x_tied2, svfloat32_t, + z0 = svnmsb_n_f32_x (p0, z1, z0, 2), + z0 = svnmsb_x (p0, z1, z0, 2)) + +/* +** nmsb_2_f32_x_untied: +** fmov z0\.s, #2\.0(?:e\+0)? +** fnmls z0\.s, p0/m, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f32_x_untied, svfloat32_t, + z0 = svnmsb_n_f32_x (p0, z1, z2, 2), + z0 = svnmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_nmsb_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f32_x_tied1, svfloat32_t, + z0 = svnmsb_f32_x (svptrue_b32 (), z0, z1, z2), + z0 = svnmsb_x (svptrue_b32 (), z0, z1, z2)) + +/* +** ptrue_nmsb_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f32_x_tied2, svfloat32_t, + z0 = svnmsb_f32_x (svptrue_b32 (), z1, z0, z2), + z0 = svnmsb_x (svptrue_b32 (), z1, z0, z2)) + +/* +** ptrue_nmsb_f32_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f32_x_tied3, svfloat32_t, + z0 = svnmsb_f32_x (svptrue_b32 (), z1, z2, z0), + z0 = svnmsb_x (svptrue_b32 (), z1, z2, z0)) + +/* +** ptrue_nmsb_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f32_x_untied, svfloat32_t, + z0 = svnmsb_f32_x (svptrue_b32 (), z1, z2, z3), + z0 = svnmsb_x (svptrue_b32 (), z1, z2, z3)) + +/* +** ptrue_nmsb_2_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f32_x_tied1, svfloat32_t, + z0 = svnmsb_n_f32_x (svptrue_b32 (), z0, z1, 2), + z0 = svnmsb_x (svptrue_b32 (), z0, z1, 2)) + +/* +** ptrue_nmsb_2_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f32_x_tied2, svfloat32_t, + z0 = svnmsb_n_f32_x (svptrue_b32 (), z1, z0, 2), + z0 = svnmsb_x (svptrue_b32 (), z1, z0, 2)) + +/* +** ptrue_nmsb_2_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f32_x_untied, svfloat32_t, + z0 = svnmsb_n_f32_x (svptrue_b32 (), z1, z2, 2), + z0 = svnmsb_x (svptrue_b32 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f64.c new file mode 100644 index 00000000000..56592d3ae2e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nmsb_f64.c @@ -0,0 +1,398 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nmsb_f64_m_tied1: +** fnmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_m_tied1, svfloat64_t, + z0 = svnmsb_f64_m (p0, z0, z1, z2), + z0 = svnmsb_m (p0, z0, z1, z2)) + +/* +** nmsb_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, \1, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_m_tied2, svfloat64_t, + z0 = svnmsb_f64_m (p0, z1, z0, z2), + z0 = svnmsb_m (p0, z1, z0, z2)) + +/* +** nmsb_f64_m_tied3: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_m_tied3, svfloat64_t, + z0 = svnmsb_f64_m (p0, z1, z2, z0), + z0 = svnmsb_m (p0, z1, z2, z0)) + +/* +** nmsb_f64_m_untied: +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, z2\.d, z3\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_m_untied, svfloat64_t, + z0 = svnmsb_f64_m (p0, z1, z2, z3), + z0 = svnmsb_m (p0, z1, z2, z3)) + +/* +** nmsb_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_m_tied1, svfloat64_t, double, + z0 = svnmsb_n_f64_m (p0, z0, z1, d4), + z0 = svnmsb_m (p0, z0, z1, d4)) + +/* +** nmsb_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_m_untied, svfloat64_t, double, + z0 = svnmsb_n_f64_m (p0, z1, z2, d4), + z0 = svnmsb_m (p0, z1, z2, d4)) + +/* +** nmsb_2_f64_m_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_m_tied1, svfloat64_t, + z0 = svnmsb_n_f64_m (p0, z0, z1, 2), + z0 = svnmsb_m (p0, z0, z1, 2)) + +/* +** nmsb_2_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, z2\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_m_untied, svfloat64_t, + z0 = svnmsb_n_f64_m (p0, z1, z2, 2), + z0 = svnmsb_m (p0, z1, z2, 2)) + +/* +** nmsb_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_z_tied1, svfloat64_t, + z0 = svnmsb_f64_z (p0, z0, z1, z2), + z0 = svnmsb_z (p0, z0, z1, z2)) + +/* +** nmsb_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_z_tied2, svfloat64_t, + z0 = svnmsb_f64_z (p0, z1, z0, z2), + z0 = svnmsb_z (p0, z1, z0, z2)) + +/* +** nmsb_f64_z_tied3: +** movprfx z0\.d, p0/z, z0\.d +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_z_tied3, svfloat64_t, + z0 = svnmsb_f64_z (p0, z1, z2, z0), + z0 = svnmsb_z (p0, z1, z2, z0)) + +/* +** nmsb_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmsb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0\.d, p0/z, z3\.d +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_z_untied, svfloat64_t, + z0 = svnmsb_f64_z (p0, z1, z2, z3), + z0 = svnmsb_z (p0, z1, z2, z3)) + +/* +** nmsb_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_z_tied1, svfloat64_t, double, + z0 = svnmsb_n_f64_z (p0, z0, z1, d4), + z0 = svnmsb_z (p0, z0, z1, d4)) + +/* +** nmsb_d4_f64_z_tied2: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_z_tied2, svfloat64_t, double, + z0 = svnmsb_n_f64_z (p0, z1, z0, d4), + z0 = svnmsb_z (p0, z1, z0, d4)) + +/* +** nmsb_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmsb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_z_untied, svfloat64_t, double, + z0 = svnmsb_n_f64_z (p0, z1, z2, d4), + z0 = svnmsb_z (p0, z1, z2, d4)) + +/* +** nmsb_2_f64_z_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_z_tied1, svfloat64_t, + z0 = svnmsb_n_f64_z (p0, z0, z1, 2), + z0 = svnmsb_z (p0, z0, z1, 2)) + +/* +** nmsb_2_f64_z_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_z_tied2, svfloat64_t, + z0 = svnmsb_n_f64_z (p0, z1, z0, 2), + z0 = svnmsb_z (p0, z1, z0, 2)) + +/* +** nmsb_2_f64_z_untied: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fnmsb z0\.d, p0/m, z2\.d, \1 +** | +** movprfx z0\.d, p0/z, z2\.d +** fnmsb z0\.d, p0/m, z1\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_z_untied, svfloat64_t, + z0 = svnmsb_n_f64_z (p0, z1, z2, 2), + z0 = svnmsb_z (p0, z1, z2, 2)) + +/* +** nmsb_f64_x_tied1: +** fnmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_x_tied1, svfloat64_t, + z0 = svnmsb_f64_x (p0, z0, z1, z2), + z0 = svnmsb_x (p0, z0, z1, z2)) + +/* +** nmsb_f64_x_tied2: +** fnmsb z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_x_tied2, svfloat64_t, + z0 = svnmsb_f64_x (p0, z1, z0, z2), + z0 = svnmsb_x (p0, z1, z0, z2)) + +/* +** nmsb_f64_x_tied3: +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_x_tied3, svfloat64_t, + z0 = svnmsb_f64_x (p0, z1, z2, z0), + z0 = svnmsb_x (p0, z1, z2, z0)) + +/* +** nmsb_f64_x_untied: +** ( +** movprfx z0, z1 +** fnmsb z0\.d, p0/m, z2\.d, z3\.d +** | +** movprfx z0, z2 +** fnmsb z0\.d, p0/m, z1\.d, z3\.d +** | +** movprfx z0, z3 +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (nmsb_f64_x_untied, svfloat64_t, + z0 = svnmsb_f64_x (p0, z1, z2, z3), + z0 = svnmsb_x (p0, z1, z2, z3)) + +/* +** nmsb_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_x_tied1, svfloat64_t, double, + z0 = svnmsb_n_f64_x (p0, z0, z1, d4), + z0 = svnmsb_x (p0, z0, z1, d4)) + +/* +** nmsb_d4_f64_x_tied2: +** mov (z[0-9]+\.d), d4 +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_x_tied2, svfloat64_t, double, + z0 = svnmsb_n_f64_x (p0, z1, z0, d4), + z0 = svnmsb_x (p0, z1, z0, d4)) + +/* +** nmsb_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_ZD (nmsb_d4_f64_x_untied, svfloat64_t, double, + z0 = svnmsb_n_f64_x (p0, z1, z2, d4), + z0 = svnmsb_x (p0, z1, z2, d4)) + +/* +** nmsb_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_x_tied1, svfloat64_t, + z0 = svnmsb_n_f64_x (p0, z0, z1, 2), + z0 = svnmsb_x (p0, z0, z1, 2)) + +/* +** nmsb_2_f64_x_tied2: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fnmsb z0\.d, p0/m, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_x_tied2, svfloat64_t, + z0 = svnmsb_n_f64_x (p0, z1, z0, 2), + z0 = svnmsb_x (p0, z1, z0, 2)) + +/* +** nmsb_2_f64_x_untied: +** fmov z0\.d, #2\.0(?:e\+0)? +** fnmls z0\.d, p0/m, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (nmsb_2_f64_x_untied, svfloat64_t, + z0 = svnmsb_n_f64_x (p0, z1, z2, 2), + z0 = svnmsb_x (p0, z1, z2, 2)) + +/* +** ptrue_nmsb_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f64_x_tied1, svfloat64_t, + z0 = svnmsb_f64_x (svptrue_b64 (), z0, z1, z2), + z0 = svnmsb_x (svptrue_b64 (), z0, z1, z2)) + +/* +** ptrue_nmsb_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f64_x_tied2, svfloat64_t, + z0 = svnmsb_f64_x (svptrue_b64 (), z1, z0, z2), + z0 = svnmsb_x (svptrue_b64 (), z1, z0, z2)) + +/* +** ptrue_nmsb_f64_x_tied3: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f64_x_tied3, svfloat64_t, + z0 = svnmsb_f64_x (svptrue_b64 (), z1, z2, z0), + z0 = svnmsb_x (svptrue_b64 (), z1, z2, z0)) + +/* +** ptrue_nmsb_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_f64_x_untied, svfloat64_t, + z0 = svnmsb_f64_x (svptrue_b64 (), z1, z2, z3), + z0 = svnmsb_x (svptrue_b64 (), z1, z2, z3)) + +/* +** ptrue_nmsb_2_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f64_x_tied1, svfloat64_t, + z0 = svnmsb_n_f64_x (svptrue_b64 (), z0, z1, 2), + z0 = svnmsb_x (svptrue_b64 (), z0, z1, 2)) + +/* +** ptrue_nmsb_2_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f64_x_tied2, svfloat64_t, + z0 = svnmsb_n_f64_x (svptrue_b64 (), z1, z0, 2), + z0 = svnmsb_x (svptrue_b64 (), z1, z0, 2)) + +/* +** ptrue_nmsb_2_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_nmsb_2_f64_x_untied, svfloat64_t, + z0 = svnmsb_n_f64_x (svptrue_b64 (), z1, z2, 2), + z0 = svnmsb_x (svptrue_b64 (), z1, z2, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nor_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nor_b.c new file mode 100644 index 00000000000..997e34537eb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/nor_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** nor_b_z_tied1: +** nor p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (nor_b_z_tied1, + p0 = svnor_b_z (p3, p0, p1), + p0 = svnor_z (p3, p0, p1)) + +/* +** nor_b_z_tied2: +** nor p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (nor_b_z_tied2, + p0 = svnor_b_z (p3, p1, p0), + p0 = svnor_z (p3, p1, p0)) + +/* +** nor_b_z_untied: +** nor p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (nor_b_z_untied, + p0 = svnor_b_z (p3, p1, p2), + p0 = svnor_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_b.c new file mode 100644 index 00000000000..23a3a6aae70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_b.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_b_z_tied1: +** not p0\.b, p3/z, p0\.b +** ret +*/ +TEST_UNIFORM_P (not_b_z_tied1, + p0 = svnot_b_z (p3, p0), + p0 = svnot_z (p3, p0)) + +/* +** not_b_z_untied: +** not p0\.b, p3/z, p1\.b +** ret +*/ +TEST_UNIFORM_P (not_b_z_untied, + p0 = svnot_b_z (p3, p1), + p0 = svnot_z (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c new file mode 100644 index 00000000000..bacd6b12cc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_s16_m_tied12: +** not z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_m_tied12, svint16_t, + z0 = svnot_s16_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_s16_m_tied1: +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_m_tied1, svint16_t, + z0 = svnot_s16_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_m_tied2, svint16_t, + z0 = svnot_s16_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_s16_m_untied: +** movprfx z0, z2 +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_m_untied, svint16_t, + z0 = svnot_s16_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** not z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_z_tied1, svint16_t, + z0 = svnot_s16_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_z_untied, svint16_t, + z0 = svnot_s16_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_s16_x_tied1: +** not z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_x_tied1, svint16_t, + z0 = svnot_s16_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_s16_x_untied: +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_s16_x_untied, svint16_t, + z0 = svnot_s16_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c new file mode 100644 index 00000000000..8b15d6e91c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_s32_m_tied12: +** not z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_m_tied12, svint32_t, + z0 = svnot_s32_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_s32_m_tied1: +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_m_tied1, svint32_t, + z0 = svnot_s32_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_m_tied2, svint32_t, + z0 = svnot_s32_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_s32_m_untied: +** movprfx z0, z2 +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_m_untied, svint32_t, + z0 = svnot_s32_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** not z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_z_tied1, svint32_t, + z0 = svnot_s32_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_z_untied, svint32_t, + z0 = svnot_s32_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_s32_x_tied1: +** not z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_x_tied1, svint32_t, + z0 = svnot_s32_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_s32_x_untied: +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_s32_x_untied, svint32_t, + z0 = svnot_s32_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c new file mode 100644 index 00000000000..8e7f7b9e876 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_s64_m_tied12: +** not z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_m_tied12, svint64_t, + z0 = svnot_s64_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_s64_m_tied1: +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_m_tied1, svint64_t, + z0 = svnot_s64_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** not z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (not_s64_m_tied2, svint64_t, + z0 = svnot_s64_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_s64_m_untied: +** movprfx z0, z2 +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_m_untied, svint64_t, + z0 = svnot_s64_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** not z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (not_s64_z_tied1, svint64_t, + z0 = svnot_s64_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_z_untied, svint64_t, + z0 = svnot_s64_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_s64_x_tied1: +** not z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_x_tied1, svint64_t, + z0 = svnot_s64_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_s64_x_untied: +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_s64_x_untied, svint64_t, + z0 = svnot_s64_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c new file mode 100644 index 00000000000..e807f08f810 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_s8_m_tied12: +** not z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_m_tied12, svint8_t, + z0 = svnot_s8_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_s8_m_tied1: +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_m_tied1, svint8_t, + z0 = svnot_s8_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_m_tied2, svint8_t, + z0 = svnot_s8_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_s8_m_untied: +** movprfx z0, z2 +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_m_untied, svint8_t, + z0 = svnot_s8_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_s8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** not z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_z_tied1, svint8_t, + z0 = svnot_s8_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_z_untied, svint8_t, + z0 = svnot_s8_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_s8_x_tied1: +** not z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_x_tied1, svint8_t, + z0 = svnot_s8_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_s8_x_untied: +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_s8_x_untied, svint8_t, + z0 = svnot_s8_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c new file mode 100644 index 00000000000..c812005f118 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_u16_m_tied12: +** not z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_m_tied12, svuint16_t, + z0 = svnot_u16_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_u16_m_tied1: +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_m_tied1, svuint16_t, + z0 = svnot_u16_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_m_tied2, svuint16_t, + z0 = svnot_u16_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_u16_m_untied: +** movprfx z0, z2 +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_m_untied, svuint16_t, + z0 = svnot_u16_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** not z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_z_tied1, svuint16_t, + z0 = svnot_u16_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_z_untied, svuint16_t, + z0 = svnot_u16_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_u16_x_tied1: +** not z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_x_tied1, svuint16_t, + z0 = svnot_u16_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_u16_x_untied: +** not z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (not_u16_x_untied, svuint16_t, + z0 = svnot_u16_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c new file mode 100644 index 00000000000..7b7e9ca2189 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_u32_m_tied12: +** not z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_m_tied12, svuint32_t, + z0 = svnot_u32_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_u32_m_tied1: +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_m_tied1, svuint32_t, + z0 = svnot_u32_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_m_tied2, svuint32_t, + z0 = svnot_u32_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_u32_m_untied: +** movprfx z0, z2 +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_m_untied, svuint32_t, + z0 = svnot_u32_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** not z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_z_tied1, svuint32_t, + z0 = svnot_u32_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_z_untied, svuint32_t, + z0 = svnot_u32_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_u32_x_tied1: +** not z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_x_tied1, svuint32_t, + z0 = svnot_u32_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_u32_x_untied: +** not z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (not_u32_x_untied, svuint32_t, + z0 = svnot_u32_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c new file mode 100644 index 00000000000..27b92ad84d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_u64_m_tied12: +** not z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_m_tied12, svuint64_t, + z0 = svnot_u64_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_u64_m_tied1: +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_m_tied1, svuint64_t, + z0 = svnot_u64_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** not z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (not_u64_m_tied2, svuint64_t, + z0 = svnot_u64_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_u64_m_untied: +** movprfx z0, z2 +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_m_untied, svuint64_t, + z0 = svnot_u64_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** not z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (not_u64_z_tied1, svuint64_t, + z0 = svnot_u64_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_z_untied, svuint64_t, + z0 = svnot_u64_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_u64_x_tied1: +** not z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_x_tied1, svuint64_t, + z0 = svnot_u64_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_u64_x_untied: +** not z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (not_u64_x_untied, svuint64_t, + z0 = svnot_u64_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c new file mode 100644 index 00000000000..bd2f36cade8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** not_u8_m_tied12: +** not z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_m_tied12, svuint8_t, + z0 = svnot_u8_m (z0, p0, z0), + z0 = svnot_m (z0, p0, z0)) + +/* +** not_u8_m_tied1: +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_m_tied1, svuint8_t, + z0 = svnot_u8_m (z0, p0, z1), + z0 = svnot_m (z0, p0, z1)) + +/* +** not_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** not z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_m_tied2, svuint8_t, + z0 = svnot_u8_m (z1, p0, z0), + z0 = svnot_m (z1, p0, z0)) + +/* +** not_u8_m_untied: +** movprfx z0, z2 +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_m_untied, svuint8_t, + z0 = svnot_u8_m (z2, p0, z1), + z0 = svnot_m (z2, p0, z1)) + +/* +** not_u8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** not z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_z_tied1, svuint8_t, + z0 = svnot_u8_z (p0, z0), + z0 = svnot_z (p0, z0)) + +/* +** not_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_z_untied, svuint8_t, + z0 = svnot_u8_z (p0, z1), + z0 = svnot_z (p0, z1)) + +/* +** not_u8_x_tied1: +** not z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_x_tied1, svuint8_t, + z0 = svnot_u8_x (p0, z0), + z0 = svnot_x (p0, z0)) + +/* +** not_u8_x_untied: +** not z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (not_u8_x_untied, svuint8_t, + z0 = svnot_u8_x (p0, z1), + z0 = svnot_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orn_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orn_b.c new file mode 100644 index 00000000000..423a18bc71b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orn_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orn_b_z_tied1: +** orn p0\.b, p3/z, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (orn_b_z_tied1, + p0 = svorn_b_z (p3, p0, p1), + p0 = svorn_z (p3, p0, p1)) + +/* +** orn_b_z_tied2: +** orn p0\.b, p3/z, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (orn_b_z_tied2, + p0 = svorn_b_z (p3, p1, p0), + p0 = svorn_z (p3, p1, p0)) + +/* +** orn_b_z_untied: +** orn p0\.b, p3/z, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (orn_b_z_untied, + p0 = svorn_b_z (p3, p1, p2), + p0 = svorn_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_b.c new file mode 100644 index 00000000000..fba9ba7df6c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_b_z_tied1: +** orr p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (orr_b_z_tied1, + p0 = svorr_b_z (p3, p0, p1), + p0 = svorr_z (p3, p0, p1)) + +/* +** orr_b_z_tied2: +** orr p0\.b, p3/z, (p0\.b, p1\.b|p1\.b, p0\.b) +** ret +*/ +TEST_UNIFORM_P (orr_b_z_tied2, + p0 = svorr_b_z (p3, p1, p0), + p0 = svorr_z (p3, p1, p0)) + +/* +** orr_b_z_untied: +** orr p0\.b, p3/z, (p1\.b, p2\.b|p2\.b, p1\.b) +** ret +*/ +TEST_UNIFORM_P (orr_b_z_untied, + p0 = svorr_b_z (p3, p1, p2), + p0 = svorr_z (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c new file mode 100644 index 00000000000..62b707a9c69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c @@ -0,0 +1,376 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_s16_m_tied1: +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_s16_m_tied1, svint16_t, + z0 = svorr_s16_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_s16_m_tied2, svint16_t, + z0 = svorr_s16_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_s16_m_untied: +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (orr_s16_m_untied, svint16_t, + z0 = svorr_s16_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svorr_n_s16_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_m_untied, svint16_t, int16_t, + z0 = svorr_n_s16_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_m_tied1, svint16_t, + z0 = svorr_n_s16_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_m_untied, svint16_t, + z0 = svorr_n_s16_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_s16_m: +** mov (z[0-9]+\.h), #-2 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_s16_m, svint16_t, + z0 = svorr_n_s16_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_s16_z_tied1, svint16_t, + z0 = svorr_s16_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_s16_z_tied2, svint16_t, + z0 = svorr_s16_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_s16_z_untied, svint16_t, + z0 = svorr_s16_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svorr_n_s16_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_z_untied, svint16_t, int16_t, + z0 = svorr_n_s16_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_z_tied1, svint16_t, + z0 = svorr_n_s16_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_z_untied, svint16_t, + z0 = svorr_n_s16_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_s16_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s16_x_tied1, svint16_t, + z0 = svorr_s16_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_s16_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s16_x_tied2, svint16_t, + z0 = svorr_s16_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_s16_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s16_x_untied, svint16_t, + z0 = svorr_s16_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_s16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svorr_n_s16_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_s16_x_untied: +** mov (z[0-9]+)\.h, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s16_x_untied, svint16_t, int16_t, + z0 = svorr_n_s16_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_s16_x_tied1: +** orr z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_x_tied1, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_s16_x_untied: +** movprfx z0, z1 +** orr z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s16_x_untied, svint16_t, + z0 = svorr_n_s16_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_s16_x: +** orr z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_s16_x: +** orr z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_s16_x: +** orr z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_s16_x: +** orr z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* +** orr_257_s16_x: +** orr z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (orr_257_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_s16_x: +** orr z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_s16_x: +** orr z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_s16_x: +** orr z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_s16_x: +** orr z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_s16_x: +** orr z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_s16_x: +** orr z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_s16_x: +** orr z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_s16_x: +** orr z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_s16_x: +** orr z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_s16_x: +** mov (z[0-9]+)\.h, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_s16_x, svint16_t, + z0 = svorr_n_s16_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s32.c new file mode 100644 index 00000000000..2e0e1e8883d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s32.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_s32_m_tied1: +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_s32_m_tied1, svint32_t, + z0 = svorr_s32_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_s32_m_tied2, svint32_t, + z0 = svorr_s32_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_s32_m_untied: +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (orr_s32_m_untied, svint32_t, + z0 = svorr_s32_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svorr_n_s32_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_m_untied, svint32_t, int32_t, + z0 = svorr_n_s32_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_m_tied1, svint32_t, + z0 = svorr_n_s32_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_m_untied, svint32_t, + z0 = svorr_n_s32_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_s32_m: +** mov (z[0-9]+\.s), #-2 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_s32_m, svint32_t, + z0 = svorr_n_s32_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_s32_z_tied1, svint32_t, + z0 = svorr_s32_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_s32_z_tied2, svint32_t, + z0 = svorr_s32_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_s32_z_untied, svint32_t, + z0 = svorr_s32_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svorr_n_s32_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_z_untied, svint32_t, int32_t, + z0 = svorr_n_s32_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_z_tied1, svint32_t, + z0 = svorr_n_s32_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_z_untied, svint32_t, + z0 = svorr_n_s32_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_s32_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s32_x_tied1, svint32_t, + z0 = svorr_s32_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_s32_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s32_x_tied2, svint32_t, + z0 = svorr_s32_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_s32_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s32_x_untied, svint32_t, + z0 = svorr_s32_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_s32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svorr_n_s32_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_s32_x_untied: +** mov (z[0-9]+)\.s, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s32_x_untied, svint32_t, int32_t, + z0 = svorr_n_s32_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_s32_x_tied1: +** orr z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_x_tied1, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_s32_x_untied: +** movprfx z0, z1 +** orr z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s32_x_untied, svint32_t, + z0 = svorr_n_s32_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_s32_x: +** orr z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_s32_x: +** orr z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_s32_x: +** orr z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_s32_x: +** orr z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (orr_257_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_s32_x: +** orr z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_s32_x: +** orr z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_s32_x: +** orr z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_s32_x: +** orr z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_s32_x: +** orr z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_s32_x: +** orr z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_s32_x: +** orr z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_s32_x: +** orr z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_s32_x: +** orr z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_s32_x: +** mov (z[0-9]+)\.s, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_s32_x, svint32_t, + z0 = svorr_n_s32_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s64.c new file mode 100644 index 00000000000..1538fdd14b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s64.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_s64_m_tied1: +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_s64_m_tied1, svint64_t, + z0 = svorr_s64_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_s64_m_tied2, svint64_t, + z0 = svorr_s64_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_s64_m_untied: +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (orr_s64_m_untied, svint64_t, + z0 = svorr_s64_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svorr_n_s64_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_m_untied, svint64_t, int64_t, + z0 = svorr_n_s64_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_m_tied1, svint64_t, + z0 = svorr_n_s64_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_m_untied, svint64_t, + z0 = svorr_n_s64_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_s64_m: +** mov (z[0-9]+\.d), #-2 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_s64_m, svint64_t, + z0 = svorr_n_s64_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_s64_z_tied1, svint64_t, + z0 = svorr_s64_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_s64_z_tied2, svint64_t, + z0 = svorr_s64_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_s64_z_untied, svint64_t, + z0 = svorr_s64_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svorr_n_s64_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_z_untied, svint64_t, int64_t, + z0 = svorr_n_s64_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_z_tied1, svint64_t, + z0 = svorr_n_s64_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_z_untied, svint64_t, + z0 = svorr_n_s64_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_s64_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s64_x_tied1, svint64_t, + z0 = svorr_s64_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_s64_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s64_x_tied2, svint64_t, + z0 = svorr_s64_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_s64_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s64_x_untied, svint64_t, + z0 = svorr_s64_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svorr_n_s64_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_s64_x_untied, svint64_t, int64_t, + z0 = svorr_n_s64_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_s64_x_tied1: +** orr z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_x_tied1, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_s64_x_untied: +** movprfx z0, z1 +** orr z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s64_x_untied, svint64_t, + z0 = svorr_n_s64_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_s64_x: +** orr z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_s64_x: +** orr z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_s64_x: +** orr z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_s64_x: +** orr z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (orr_257_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_s64_x: +** orr z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_s64_x: +** orr z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_s64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_s64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_s64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_s64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_s64_x: +** orr z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_s64_x: +** orr z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_s64_x: +** orr z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_s64_x: +** mov (z[0-9]+\.d), #5 +** orr z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_s64_x, svint64_t, + z0 = svorr_n_s64_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c new file mode 100644 index 00000000000..b6483b6e76e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c @@ -0,0 +1,295 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_s8_m_tied1: +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_s8_m_tied1, svint8_t, + z0 = svorr_s8_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_s8_m_tied2, svint8_t, + z0 = svorr_s8_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_s8_m_untied: +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (orr_s8_m_untied, svint8_t, + z0 = svorr_s8_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svorr_n_s8_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_m_untied, svint8_t, int8_t, + z0 = svorr_n_s8_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_m_tied1, svint8_t, + z0 = svorr_n_s8_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_m_untied, svint8_t, + z0 = svorr_n_s8_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_s8_m: +** mov (z[0-9]+\.b), #-2 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_s8_m, svint8_t, + z0 = svorr_n_s8_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_s8_z_tied1, svint8_t, + z0 = svorr_s8_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_s8_z_tied2, svint8_t, + z0 = svorr_s8_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_s8_z_untied, svint8_t, + z0 = svorr_s8_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svorr_n_s8_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_z_untied, svint8_t, int8_t, + z0 = svorr_n_s8_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_z_tied1, svint8_t, + z0 = svorr_n_s8_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_z_untied, svint8_t, + z0 = svorr_n_s8_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_s8_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s8_x_tied1, svint8_t, + z0 = svorr_s8_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_s8_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s8_x_tied2, svint8_t, + z0 = svorr_s8_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_s8_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_s8_x_untied, svint8_t, + z0 = svorr_s8_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_s8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svorr_n_s8_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_s8_x_untied: +** mov (z[0-9]+)\.b, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_s8_x_untied, svint8_t, int8_t, + z0 = svorr_n_s8_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_s8_x_tied1: +** orr z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_x_tied1, svint8_t, + z0 = svorr_n_s8_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_s8_x_untied: +** movprfx z0, z1 +** orr z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_s8_x_untied, svint8_t, + z0 = svorr_n_s8_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_s8_x: +** orr z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_s8_x: +** orr z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_s8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (orr_255_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_m127_s8_x: +** orr z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_s8_x: +** orr z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_5_s8_x: +** mov (z[0-9]+)\.b, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_s8_x, svint8_t, + z0 = svorr_n_s8_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c new file mode 100644 index 00000000000..000a0444c9b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c @@ -0,0 +1,376 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_u16_m_tied1: +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_u16_m_tied1, svuint16_t, + z0 = svorr_u16_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_u16_m_tied2, svuint16_t, + z0 = svorr_u16_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_u16_m_untied: +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (orr_u16_m_untied, svuint16_t, + z0 = svorr_u16_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svorr_n_u16_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svorr_n_u16_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_m_tied1, svuint16_t, + z0 = svorr_n_u16_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_m_untied, svuint16_t, + z0 = svorr_n_u16_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_u16_m: +** mov (z[0-9]+\.h), #-2 +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_u16_m, svuint16_t, + z0 = svorr_n_u16_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_u16_z_tied1, svuint16_t, + z0 = svorr_u16_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (orr_u16_z_tied2, svuint16_t, + z0 = svorr_u16_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_u16_z_untied, svuint16_t, + z0 = svorr_u16_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svorr_n_u16_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svorr_n_u16_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** orr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_z_tied1, svuint16_t, + z0 = svorr_n_u16_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** orr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** orr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_z_untied, svuint16_t, + z0 = svorr_n_u16_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_u16_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u16_x_tied1, svuint16_t, + z0 = svorr_u16_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_u16_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u16_x_tied2, svuint16_t, + z0 = svorr_u16_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_u16_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u16_x_untied, svuint16_t, + z0 = svorr_u16_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_u16_x_tied1: +** mov (z[0-9]+)\.h, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svorr_n_u16_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_u16_x_untied: +** mov (z[0-9]+)\.h, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svorr_n_u16_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_u16_x_tied1: +** orr z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_x_tied1, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_u16_x_untied: +** movprfx z0, z1 +** orr z0\.h, z0\.h, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u16_x_untied, svuint16_t, + z0 = svorr_n_u16_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_u16_x: +** orr z0\.h, z0\.h, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_u16_x: +** orr z0\.h, z0\.h, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_u16_x: +** orr z0\.h, z0\.h, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_u16_x: +** orr z0\.h, z0\.h, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* +** orr_257_u16_x: +** orr z0\.h, z0\.h, #0x101 +** ret +*/ +TEST_UNIFORM_Z (orr_257_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_u16_x: +** orr z0\.h, z0\.h, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_u16_x: +** orr z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_u16_x: +** orr z0\.h, z0\.h, #0xff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_u16_x: +** orr z0\.h, z0\.h, #0xff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_u16_x: +** orr z0\.h, z0\.h, #0xff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_u16_x: +** orr z0\.h, z0\.h, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_u16_x: +** orr z0\.h, z0\.h, #0xfeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_u16_x: +** orr z0\.h, z0\.h, #0xfe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_u16_x: +** orr z0\.h, z0\.h, #0x8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_u16_x: +** mov (z[0-9]+)\.h, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_u16_x, svuint16_t, + z0 = svorr_n_u16_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u32.c new file mode 100644 index 00000000000..8e2351d162b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u32.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_u32_m_tied1: +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_u32_m_tied1, svuint32_t, + z0 = svorr_u32_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_u32_m_tied2, svuint32_t, + z0 = svorr_u32_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_u32_m_untied: +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (orr_u32_m_untied, svuint32_t, + z0 = svorr_u32_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svorr_n_u32_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svorr_n_u32_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_m_tied1, svuint32_t, + z0 = svorr_n_u32_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_m_untied, svuint32_t, + z0 = svorr_n_u32_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_u32_m: +** mov (z[0-9]+\.s), #-2 +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_u32_m, svuint32_t, + z0 = svorr_n_u32_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_u32_z_tied1, svuint32_t, + z0 = svorr_u32_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (orr_u32_z_tied2, svuint32_t, + z0 = svorr_u32_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_u32_z_untied, svuint32_t, + z0 = svorr_u32_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svorr_n_u32_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svorr_n_u32_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** orr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_z_tied1, svuint32_t, + z0 = svorr_n_u32_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** orr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** orr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_z_untied, svuint32_t, + z0 = svorr_n_u32_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_u32_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u32_x_tied1, svuint32_t, + z0 = svorr_u32_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_u32_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u32_x_tied2, svuint32_t, + z0 = svorr_u32_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_u32_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u32_x_untied, svuint32_t, + z0 = svorr_u32_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_u32_x_tied1: +** mov (z[0-9]+)\.s, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svorr_n_u32_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_u32_x_untied: +** mov (z[0-9]+)\.s, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svorr_n_u32_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_u32_x_tied1: +** orr z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_x_tied1, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_u32_x_untied: +** movprfx z0, z1 +** orr z0\.s, z0\.s, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u32_x_untied, svuint32_t, + z0 = svorr_n_u32_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_u32_x: +** orr z0\.s, z0\.s, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_u32_x: +** orr z0\.s, z0\.s, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_u32_x: +** orr z0\.s, z0\.s, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_u32_x: +** orr z0\.s, z0\.s, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (orr_257_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_u32_x: +** orr z0\.s, z0\.s, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_u32_x: +** orr z0\.s, z0\.s, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_u32_x: +** orr z0\.s, z0\.s, #0xffffff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_u32_x: +** orr z0\.s, z0\.s, #0xffffff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_u32_x: +** orr z0\.s, z0\.s, #0xffffff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_u32_x: +** orr z0\.s, z0\.s, #0xffffff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_u32_x: +** orr z0\.s, z0\.s, #0xfffffeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_u32_x: +** orr z0\.s, z0\.s, #0xfffffe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_u32_x: +** orr z0\.s, z0\.s, #0xffff8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_u32_x: +** mov (z[0-9]+)\.s, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_u32_x, svuint32_t, + z0 = svorr_n_u32_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u64.c new file mode 100644 index 00000000000..323e2101e47 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u64.c @@ -0,0 +1,372 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_u64_m_tied1: +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_u64_m_tied1, svuint64_t, + z0 = svorr_u64_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_u64_m_tied2, svuint64_t, + z0 = svorr_u64_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_u64_m_untied: +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (orr_u64_m_untied, svuint64_t, + z0 = svorr_u64_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svorr_n_u64_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svorr_n_u64_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_m_tied1, svuint64_t, + z0 = svorr_n_u64_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_m_untied, svuint64_t, + z0 = svorr_n_u64_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_u64_m: +** mov (z[0-9]+\.d), #-2 +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_u64_m, svuint64_t, + z0 = svorr_n_u64_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_u64_z_tied1, svuint64_t, + z0 = svorr_u64_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (orr_u64_z_tied2, svuint64_t, + z0 = svorr_u64_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_u64_z_untied, svuint64_t, + z0 = svorr_u64_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svorr_n_u64_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svorr_n_u64_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** orr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_z_tied1, svuint64_t, + z0 = svorr_n_u64_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** orr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** orr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_z_untied, svuint64_t, + z0 = svorr_n_u64_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_u64_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u64_x_tied1, svuint64_t, + z0 = svorr_u64_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_u64_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u64_x_tied2, svuint64_t, + z0 = svorr_u64_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_u64_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u64_x_untied, svuint64_t, + z0 = svorr_u64_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svorr_n_u64_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** orr z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svorr_n_u64_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_u64_x_tied1: +** orr z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_x_tied1, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_u64_x_untied: +** movprfx z0, z1 +** orr z0\.d, z0\.d, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u64_x_untied, svuint64_t, + z0 = svorr_n_u64_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_u64_x: +** orr z0\.d, z0\.d, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_u64_x: +** orr z0\.d, z0\.d, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_u64_x: +** orr z0\.d, z0\.d, #0xff +** ret +*/ +TEST_UNIFORM_Z (orr_255_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_256_u64_x: +** orr z0\.d, z0\.d, #0x100 +** ret +*/ +TEST_UNIFORM_Z (orr_256_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 256), + z0 = svorr_x (p0, z0, 256)) + +/* TODO: Bad code and needs fixing. */ +TEST_UNIFORM_Z (orr_257_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 257), + z0 = svorr_x (p0, z0, 257)) + +/* +** orr_512_u64_x: +** orr z0\.d, z0\.d, #0x200 +** ret +*/ +TEST_UNIFORM_Z (orr_512_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 512), + z0 = svorr_x (p0, z0, 512)) + +/* +** orr_65280_u64_x: +** orr z0\.d, z0\.d, #0xff00 +** ret +*/ +TEST_UNIFORM_Z (orr_65280_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 0xff00), + z0 = svorr_x (p0, z0, 0xff00)) + +/* +** orr_m127_u64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_u64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_m255_u64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff01 +** ret +*/ +TEST_UNIFORM_Z (orr_m255_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -255), + z0 = svorr_x (p0, z0, -255)) + +/* +** orr_m256_u64_x: +** orr z0\.d, z0\.d, #0xffffffffffffff00 +** ret +*/ +TEST_UNIFORM_Z (orr_m256_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -256), + z0 = svorr_x (p0, z0, -256)) + +/* +** orr_m257_u64_x: +** orr z0\.d, z0\.d, #0xfffffffffffffeff +** ret +*/ +TEST_UNIFORM_Z (orr_m257_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -257), + z0 = svorr_x (p0, z0, -257)) + +/* +** orr_m512_u64_x: +** orr z0\.d, z0\.d, #0xfffffffffffffe00 +** ret +*/ +TEST_UNIFORM_Z (orr_m512_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -512), + z0 = svorr_x (p0, z0, -512)) + +/* +** orr_m32768_u64_x: +** orr z0\.d, z0\.d, #0xffffffffffff8000 +** ret +*/ +TEST_UNIFORM_Z (orr_m32768_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, -0x8000), + z0 = svorr_x (p0, z0, -0x8000)) + +/* +** orr_5_u64_x: +** mov (z[0-9]+\.d), #5 +** orr z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_u64_x, svuint64_t, + z0 = svorr_n_u64_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c new file mode 100644 index 00000000000..efe5591b472 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c @@ -0,0 +1,295 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orr_u8_m_tied1: +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_u8_m_tied1, svuint8_t, + z0 = svorr_u8_m (p0, z0, z1), + z0 = svorr_m (p0, z0, z1)) + +/* +** orr_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_u8_m_tied2, svuint8_t, + z0 = svorr_u8_m (p0, z1, z0), + z0 = svorr_m (p0, z1, z0)) + +/* +** orr_u8_m_untied: +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (orr_u8_m_untied, svuint8_t, + z0 = svorr_u8_m (p0, z1, z2), + z0 = svorr_m (p0, z1, z2)) + +/* +** orr_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svorr_n_u8_m (p0, z0, x0), + z0 = svorr_m (p0, z0, x0)) + +/* +** orr_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svorr_n_u8_m (p0, z1, x0), + z0 = svorr_m (p0, z1, x0)) + +/* +** orr_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_m_tied1, svuint8_t, + z0 = svorr_n_u8_m (p0, z0, 1), + z0 = svorr_m (p0, z0, 1)) + +/* +** orr_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_m_untied, svuint8_t, + z0 = svorr_n_u8_m (p0, z1, 1), + z0 = svorr_m (p0, z1, 1)) + +/* +** orr_m2_u8_m: +** mov (z[0-9]+\.b), #-2 +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_m2_u8_m, svuint8_t, + z0 = svorr_n_u8_m (p0, z0, -2), + z0 = svorr_m (p0, z0, -2)) + +/* +** orr_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_u8_z_tied1, svuint8_t, + z0 = svorr_u8_z (p0, z0, z1), + z0 = svorr_z (p0, z0, z1)) + +/* +** orr_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (orr_u8_z_tied2, svuint8_t, + z0 = svorr_u8_z (p0, z1, z0), + z0 = svorr_z (p0, z1, z0)) + +/* +** orr_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_u8_z_untied, svuint8_t, + z0 = svorr_u8_z (p0, z1, z2), + z0 = svorr_z (p0, z1, z2)) + +/* +** orr_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svorr_n_u8_z (p0, z0, x0), + z0 = svorr_z (p0, z0, x0)) + +/* +** orr_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svorr_n_u8_z (p0, z1, x0), + z0 = svorr_z (p0, z1, x0)) + +/* +** orr_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** orr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_z_tied1, svuint8_t, + z0 = svorr_n_u8_z (p0, z0, 1), + z0 = svorr_z (p0, z0, 1)) + +/* +** orr_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** orr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** orr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_z_untied, svuint8_t, + z0 = svorr_n_u8_z (p0, z1, 1), + z0 = svorr_z (p0, z1, 1)) + +/* +** orr_u8_x_tied1: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u8_x_tied1, svuint8_t, + z0 = svorr_u8_x (p0, z0, z1), + z0 = svorr_x (p0, z0, z1)) + +/* +** orr_u8_x_tied2: +** orr z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u8_x_tied2, svuint8_t, + z0 = svorr_u8_x (p0, z1, z0), + z0 = svorr_x (p0, z1, z0)) + +/* +** orr_u8_x_untied: +** orr z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_u8_x_untied, svuint8_t, + z0 = svorr_u8_x (p0, z1, z2), + z0 = svorr_x (p0, z1, z2)) + +/* +** orr_w0_u8_x_tied1: +** mov (z[0-9]+)\.b, w0 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svorr_n_u8_x (p0, z0, x0), + z0 = svorr_x (p0, z0, x0)) + +/* +** orr_w0_u8_x_untied: +** mov (z[0-9]+)\.b, w0 +** orr z0\.d, (z1\.d, \1\.d|\1\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (orr_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svorr_n_u8_x (p0, z1, x0), + z0 = svorr_x (p0, z1, x0)) + +/* +** orr_1_u8_x_tied1: +** orr z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_x_tied1, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, 1), + z0 = svorr_x (p0, z0, 1)) + +/* +** orr_1_u8_x_untied: +** movprfx z0, z1 +** orr z0\.b, z0\.b, #0x1 +** ret +*/ +TEST_UNIFORM_Z (orr_1_u8_x_untied, svuint8_t, + z0 = svorr_n_u8_x (p0, z1, 1), + z0 = svorr_x (p0, z1, 1)) + +/* +** orr_127_u8_x: +** orr z0\.b, z0\.b, #0x7f +** ret +*/ +TEST_UNIFORM_Z (orr_127_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, 127), + z0 = svorr_x (p0, z0, 127)) + +/* +** orr_128_u8_x: +** orr z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_128_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, 128), + z0 = svorr_x (p0, z0, 128)) + +/* +** orr_255_u8_x: +** mov z0\.b, #-1 +** ret +*/ +TEST_UNIFORM_Z (orr_255_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, 255), + z0 = svorr_x (p0, z0, 255)) + +/* +** orr_m127_u8_x: +** orr z0\.b, z0\.b, #0x81 +** ret +*/ +TEST_UNIFORM_Z (orr_m127_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, -127), + z0 = svorr_x (p0, z0, -127)) + +/* +** orr_m128_u8_x: +** orr z0\.b, z0\.b, #0x80 +** ret +*/ +TEST_UNIFORM_Z (orr_m128_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, -128), + z0 = svorr_x (p0, z0, -128)) + +/* +** orr_5_u8_x: +** mov (z[0-9]+)\.b, #5 +** orr z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (orr_5_u8_x, svuint8_t, + z0 = svorr_n_u8_x (p0, z0, 5), + z0 = svorr_x (p0, z0, 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s16.c new file mode 100644 index 00000000000..c9b268d3da3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_s16: +** orv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (orv_x0_s16, int16_t, svint16_t, + x0 = svorv_s16 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s32.c new file mode 100644 index 00000000000..df4025f545b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_s32: +** orv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (orv_x0_s32, int32_t, svint32_t, + x0 = svorv_s32 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s64.c new file mode 100644 index 00000000000..76a835ce374 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_s64: +** orv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (orv_x0_s64, int64_t, svint64_t, + x0 = svorv_s64 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s8.c new file mode 100644 index 00000000000..3f2031d9c6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_s8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_s8: +** orv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (orv_x0_s8, int8_t, svint8_t, + x0 = svorv_s8 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u16.c new file mode 100644 index 00000000000..28bfbecb038 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u16.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_u16: +** orv h([0-9]+), p0, z0\.h +** umov w0, v\1\.h\[0\] +** ret +*/ +TEST_REDUCTION_X (orv_x0_u16, uint16_t, svuint16_t, + x0 = svorv_u16 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u32.c new file mode 100644 index 00000000000..1988d56231d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u32.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_u32: +** orv (s[0-9]+), p0, z0\.s +** fmov w0, \1 +** ret +*/ +TEST_REDUCTION_X (orv_x0_u32, uint32_t, svuint32_t, + x0 = svorv_u32 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u64.c new file mode 100644 index 00000000000..c8a8429a705 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u64.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_u64: +** orv (d[0-9]+), p0, z0\.d +** fmov x0, \1 +** ret +*/ +TEST_REDUCTION_X (orv_x0_u64, uint64_t, svuint64_t, + x0 = svorv_u64 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u8.c new file mode 100644 index 00000000000..bcab32d8b38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orv_u8.c @@ -0,0 +1,13 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** orv_x0_u8: +** orv b([0-9]+), p0, z0\.b +** umov w0, v\1\.b\[0\] +** ret +*/ +TEST_REDUCTION_X (orv_x0_u8, uint8_t, svuint8_t, + x0 = svorv_u8 (p0, z0), + x0 = svorv (p0, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfalse.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfalse.c new file mode 100644 index 00000000000..a74a59283af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfalse.c @@ -0,0 +1,13 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pfalse_b: +** pfalse p0\.b +** ret +*/ +TEST_P (pfalse_b, + p0 = svpfalse_b (), + p0 = svpfalse ()); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c new file mode 100644 index 00000000000..a32099656cc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pfirst_b.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pfirst_b_tied1: +** pfirst p0\.b, p3, p0\.b +** ret +*/ +TEST_UNIFORM_P (pfirst_b_tied1, + p0 = svpfirst_b (p3, p0), + p0 = svpfirst (p3, p0)) + +/* +** pfirst_b_untied: +** mov p0\.b, p1\.b +** pfirst p0\.b, p3, p0\.b +** ret +*/ +TEST_UNIFORM_P (pfirst_b_untied, + p0 = svpfirst_b (p3, p1), + p0 = svpfirst (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c new file mode 100644 index 00000000000..ad0efe5e711 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pnext_b16_tied1: +** pnext p0\.h, p3, p0\.h +** ret +*/ +TEST_UNIFORM_P (pnext_b16_tied1, + p0 = svpnext_b16 (p3, p0), + p0 = svpnext_b16 (p3, p0)) + +/* +** pnext_b16_untied: +** mov p0\.b, p1\.b +** pnext p0\.h, p3, p0\.h +** ret +*/ +TEST_UNIFORM_P (pnext_b16_untied, + p0 = svpnext_b16 (p3, p1), + p0 = svpnext_b16 (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c new file mode 100644 index 00000000000..a0030fae18d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b32.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pnext_b32_tied1: +** pnext p0\.s, p3, p0\.s +** ret +*/ +TEST_UNIFORM_P (pnext_b32_tied1, + p0 = svpnext_b32 (p3, p0), + p0 = svpnext_b32 (p3, p0)) + +/* +** pnext_b32_untied: +** mov p0\.b, p1\.b +** pnext p0\.s, p3, p0\.s +** ret +*/ +TEST_UNIFORM_P (pnext_b32_untied, + p0 = svpnext_b32 (p3, p1), + p0 = svpnext_b32 (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c new file mode 100644 index 00000000000..59db2f04f2a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b64.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pnext_b64_tied1: +** pnext p0\.d, p3, p0\.d +** ret +*/ +TEST_UNIFORM_P (pnext_b64_tied1, + p0 = svpnext_b64 (p3, p0), + p0 = svpnext_b64 (p3, p0)) + +/* +** pnext_b64_untied: +** mov p0\.b, p1\.b +** pnext p0\.d, p3, p0\.d +** ret +*/ +TEST_UNIFORM_P (pnext_b64_untied, + p0 = svpnext_b64 (p3, p1), + p0 = svpnext_b64 (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c new file mode 100644 index 00000000000..cfc2e907c25 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/pnext_b8.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** pnext_b8_tied1: +** pnext p0\.b, p3, p0\.b +** ret +*/ +TEST_UNIFORM_P (pnext_b8_tied1, + p0 = svpnext_b8 (p3, p0), + p0 = svpnext_b8 (p3, p0)) + +/* +** pnext_b8_untied: +** mov p0\.b, p1\.b +** pnext p0\.b, p3, p0\.b +** ret +*/ +TEST_UNIFORM_P (pnext_b8_untied, + p0 = svpnext_b8 (p3, p1), + p0 = svpnext_b8 (p3, p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb.c new file mode 100644 index 00000000000..a9168e391f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb.c @@ -0,0 +1,245 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfb_base: +** prfb pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_base, uint8_t, + svprfb (p0, x0, SV_PLDL1KEEP), + svprfb (p0, x0, SV_PLDL1KEEP)) + +/* +** prfb_u8_index: +** prfb pldl1keep, p0, \[x0, x1\] +** ret +*/ +TEST_PREFETCH (prfb_u8_index, uint8_t, + svprfb (p0, x0 + x1, SV_PLDL1KEEP), + svprfb (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfb_u8_1: +** add (x[0-9+]), x0, #?1 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u8_1, uint8_t, + svprfb (p0, x0 + 1, SV_PLDL1KEEP), + svprfb (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfb_u16_index: +** add (x[0-9+]), x0, x1, lsl #?1 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u16_index, uint16_t, + svprfb (p0, x0 + x1, SV_PLDL1KEEP), + svprfb (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfb_u16_1: +** add (x[0-9+]), x0, #?2 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u16_1, uint16_t, + svprfb (p0, x0 + 1, SV_PLDL1KEEP), + svprfb (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfb_u32_index: +** add (x[0-9+]), x0, x1, lsl #?2 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u32_index, uint32_t, + svprfb (p0, x0 + x1, SV_PLDL1KEEP), + svprfb (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfb_u32_1: +** add (x[0-9+]), x0, #?4 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u32_1, uint32_t, + svprfb (p0, x0 + 1, SV_PLDL1KEEP), + svprfb (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfb_u64_index: +** add (x[0-9+]), x0, x1, lsl #?3 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u64_index, uint64_t, + svprfb (p0, x0 + x1, SV_PLDL1KEEP), + svprfb (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfb_u64_1: +** add (x[0-9+]), x0, #?8 +** prfb pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfb_u64_1, uint64_t, + svprfb (p0, x0 + 1, SV_PLDL1KEEP), + svprfb (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfb_pldl1strm: +** prfb pldl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pldl1strm, uint8_t, + svprfb (p0, x0, SV_PLDL1STRM), + svprfb (p0, x0, SV_PLDL1STRM)) + +/* +** prfb_pldl2keep: +** prfb pldl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pldl2keep, uint8_t, + svprfb (p0, x0, SV_PLDL2KEEP), + svprfb (p0, x0, SV_PLDL2KEEP)) + +/* +** prfb_pldl2strm: +** prfb pldl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pldl2strm, uint8_t, + svprfb (p0, x0, SV_PLDL2STRM), + svprfb (p0, x0, SV_PLDL2STRM)) + +/* +** prfb_pldl3keep: +** prfb pldl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pldl3keep, uint8_t, + svprfb (p0, x0, SV_PLDL3KEEP), + svprfb (p0, x0, SV_PLDL3KEEP)) + +/* +** prfb_pldl3strm: +** prfb pldl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pldl3strm, uint8_t, + svprfb (p0, x0, SV_PLDL3STRM), + svprfb (p0, x0, SV_PLDL3STRM)) + +/* +** prfb_pstl1keep: +** prfb pstl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl1keep, uint8_t, + svprfb (p0, x0, SV_PSTL1KEEP), + svprfb (p0, x0, SV_PSTL1KEEP)) + +/* +** prfb_pstl1strm: +** prfb pstl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl1strm, uint8_t, + svprfb (p0, x0, SV_PSTL1STRM), + svprfb (p0, x0, SV_PSTL1STRM)) + +/* +** prfb_pstl2keep: +** prfb pstl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl2keep, uint8_t, + svprfb (p0, x0, SV_PSTL2KEEP), + svprfb (p0, x0, SV_PSTL2KEEP)) + +/* +** prfb_pstl2strm: +** prfb pstl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl2strm, uint8_t, + svprfb (p0, x0, SV_PSTL2STRM), + svprfb (p0, x0, SV_PSTL2STRM)) + +/* +** prfb_pstl3keep: +** prfb pstl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl3keep, uint8_t, + svprfb (p0, x0, SV_PSTL3KEEP), + svprfb (p0, x0, SV_PSTL3KEEP)) + +/* +** prfb_pstl3strm: +** prfb pstl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_pstl3strm, uint8_t, + svprfb (p0, x0, SV_PSTL3STRM), + svprfb (p0, x0, SV_PSTL3STRM)) + +/* +** prfb_vnum_0: +** prfb pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_vnum_0, uint8_t, + svprfb_vnum (p0, x0, 0, SV_PLDL1KEEP), + svprfb_vnum (p0, x0, 0, SV_PLDL1KEEP)) + +/* +** prfb_vnum_1: +** incb x0 +** prfb pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_vnum_1, uint16_t, + svprfb_vnum (p0, x0, 1, SV_PLDL1KEEP), + svprfb_vnum (p0, x0, 1, SV_PLDL1KEEP)) + +/* +** prfb_vnum_2: +** incb x0, all, mul #2 +** prfb pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_vnum_2, uint32_t, + svprfb_vnum (p0, x0, 2, SV_PLDL1KEEP), + svprfb_vnum (p0, x0, 2, SV_PLDL1KEEP)) + +/* +** prfb_vnum_3: +** incb x0, all, mul #3 +** prfb pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfb_vnum_3, uint64_t, + svprfb_vnum (p0, x0, 3, SV_PLDL1KEEP), + svprfb_vnum (p0, x0, 3, SV_PLDL1KEEP)) + +/* +** prfb_vnum_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** prfb pldl1keep, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** prfb zldl1keep, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_PREFETCH (prfb_vnum_x1, uint64_t, + svprfb_vnum (p0, x0, x1, SV_PLDL1KEEP), + svprfb_vnum (p0, x0, x1, SV_PLDL1KEEP)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb_gather.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb_gather.c new file mode 100644 index 00000000000..c05910837df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfb_gather.c @@ -0,0 +1,223 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfb_gather_u32base: +** prfb pldl1keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_u32base, svuint32_t, + svprfb_gather_u32base (p0, z0, SV_PLDL1KEEP), + svprfb_gather (p0, z0, SV_PLDL1KEEP)) + +/* +** prfb_gather_u64base: +** prfb pldl1strm, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_u64base, svuint64_t, + svprfb_gather_u64base (p0, z0, SV_PLDL1STRM), + svprfb_gather (p0, z0, SV_PLDL1STRM)) + +/* +** prfb_gather_x0_u32base_offset: +** prfb pldl2keep, p0, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_x0_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, x0, SV_PLDL2KEEP), + svprfb_gather_offset (p0, z0, x0, SV_PLDL2KEEP)) + +/* +** prfb_gather_m1_u32base_offset: +** mov (x[0-9]+), #?-1 +** prfb pldl2strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_m1_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, -1, SV_PLDL2STRM), + svprfb_gather_offset (p0, z0, -1, SV_PLDL2STRM)) + +/* +** prfb_gather_0_u32base_offset: +** prfb pldl3keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_0_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, 0, SV_PLDL3KEEP), + svprfb_gather_offset (p0, z0, 0, SV_PLDL3KEEP)) + +/* +** prfb_gather_5_u32base_offset: +** prfb pldl3strm, p0, \[z0\.s, #5\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_5_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, 5, SV_PLDL3STRM), + svprfb_gather_offset (p0, z0, 5, SV_PLDL3STRM)) + +/* +** prfb_gather_31_u32base_offset: +** prfb pstl1keep, p0, \[z0\.s, #31\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_31_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, 31, SV_PSTL1KEEP), + svprfb_gather_offset (p0, z0, 31, SV_PSTL1KEEP)) + +/* +** prfb_gather_32_u32base_offset: +** mov (x[0-9]+), #?32 +** prfb pstl1strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_32_u32base_offset, svuint32_t, + svprfb_gather_u32base_offset (p0, z0, 32, SV_PSTL1STRM), + svprfb_gather_offset (p0, z0, 32, SV_PSTL1STRM)) + +/* +** prfb_gather_x0_u64base_offset: +** prfb pstl2keep, p0, \[x0, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_x0_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, x0, SV_PSTL2KEEP), + svprfb_gather_offset (p0, z0, x0, SV_PSTL2KEEP)) + +/* +** prfb_gather_m1_u64base_offset: +** mov (x[0-9]+), #?-1 +** prfb pstl2strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_m1_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, -1, SV_PSTL2STRM), + svprfb_gather_offset (p0, z0, -1, SV_PSTL2STRM)) + +/* +** prfb_gather_0_u64base_offset: +** prfb pstl3keep, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_0_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, 0, SV_PSTL3KEEP), + svprfb_gather_offset (p0, z0, 0, SV_PSTL3KEEP)) + +/* +** prfb_gather_5_u64base_offset: +** prfb pstl3strm, p0, \[z0\.d, #5\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_5_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, 5, SV_PSTL3STRM), + svprfb_gather_offset (p0, z0, 5, SV_PSTL3STRM)) + +/* +** prfb_gather_31_u64base_offset: +** prfb pldl1keep, p0, \[z0\.d, #31\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_31_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, 31, SV_PLDL1KEEP), + svprfb_gather_offset (p0, z0, 31, SV_PLDL1KEEP)) + +/* +** prfb_gather_32_u64base_offset: +** mov (x[0-9]+), #?32 +** prfb pldl1strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfb_gather_32_u64base_offset, svuint64_t, + svprfb_gather_u64base_offset (p0, z0, 32, SV_PLDL1STRM), + svprfb_gather_offset (p0, z0, 32, SV_PLDL1STRM)) + +/* +** prfb_gather_x0_s32offset: +** prfb pldl2keep, p0, \[x0, z0\.s, sxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_x0_s32offset, svint32_t, + svprfb_gather_s32offset (p0, x0, z0, SV_PLDL2KEEP), + svprfb_gather_offset (p0, x0, z0, SV_PLDL2KEEP)) + +/* +** prfb_gather_s32offset: +** prfb pldl2strm, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_s32offset, svint32_t, + svprfb_gather_s32offset (p0, x0, z1, SV_PLDL2STRM), + svprfb_gather_offset (p0, x0, z1, SV_PLDL2STRM)) + +/* +** prfb_gather_x0_u32offset: +** prfb pldl3keep, p0, \[x0, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_x0_u32offset, svuint32_t, + svprfb_gather_u32offset (p0, x0, z0, SV_PLDL3KEEP), + svprfb_gather_offset (p0, x0, z0, SV_PLDL3KEEP)) + +/* +** prfb_gather_u32offset: +** prfb pldl3strm, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_u32offset, svuint32_t, + svprfb_gather_u32offset (p0, x0, z1, SV_PLDL3STRM), + svprfb_gather_offset (p0, x0, z1, SV_PLDL3STRM)) + +/* +** prfb_gather_x0_s64offset: +** prfb pstl1keep, p0, \[x0, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_x0_s64offset, svint64_t, + svprfb_gather_s64offset (p0, x0, z0, SV_PSTL1KEEP), + svprfb_gather_offset (p0, x0, z0, SV_PSTL1KEEP)) + +/* +** prfb_gather_s64offset: +** prfb pstl1strm, p0, \[x0, z1\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_s64offset, svint64_t, + svprfb_gather_s64offset (p0, x0, z1, SV_PSTL1STRM), + svprfb_gather_offset (p0, x0, z1, SV_PSTL1STRM)) + +/* +** prfb_gather_ext_s64offset: +** prfb pstl1strm, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_ext_s64offset, svint64_t, + svprfb_gather_s64offset (p0, x0, svextw_s64_x (p0, z1), SV_PSTL1STRM), + svprfb_gather_offset (p0, x0, svextw_x (p0, z1), SV_PSTL1STRM)) + +/* +** prfb_gather_x0_u64offset: +** prfb pstl2keep, p0, \[x0, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_x0_u64offset, svuint64_t, + svprfb_gather_u64offset (p0, x0, z0, SV_PSTL2KEEP), + svprfb_gather_offset (p0, x0, z0, SV_PSTL2KEEP)) + +/* +** prfb_gather_u64offset: +** prfb pstl2strm, p0, \[x0, z1\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_u64offset, svuint64_t, + svprfb_gather_u64offset (p0, x0, z1, SV_PSTL2STRM), + svprfb_gather_offset (p0, x0, z1, SV_PSTL2STRM)) + +/* +** prfb_gather_ext_u64offset: +** prfb pstl2strm, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfb_gather_ext_u64offset, svuint64_t, + svprfb_gather_u64offset (p0, x0, svextw_u64_x (p0, z1), SV_PSTL2STRM), + svprfb_gather_offset (p0, x0, svextw_x (p0, z1), SV_PSTL2STRM)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd.c new file mode 100644 index 00000000000..16881ea2431 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd.c @@ -0,0 +1,245 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfd_base: +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_base, uint8_t, + svprfd (p0, x0, SV_PLDL1KEEP), + svprfd (p0, x0, SV_PLDL1KEEP)) + +/* +** prfd_u8_index: +** add (x[0-9+]), (x0, x1|x1, x0) +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_u8_index, uint8_t, + svprfd (p0, x0 + x1, SV_PLDL1KEEP), + svprfd (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfd_u8_1: +** add (x[0-9+]), x0, #?1 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u8_1, uint8_t, + svprfd (p0, x0 + 1, SV_PLDL1KEEP), + svprfd (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfd_u16_index: +** add (x[0-9+]), x0, x1, lsl #?1 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u16_index, uint16_t, + svprfd (p0, x0 + x1, SV_PLDL1KEEP), + svprfd (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfd_u16_1: +** add (x[0-9+]), x0, #?2 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u16_1, uint16_t, + svprfd (p0, x0 + 1, SV_PLDL1KEEP), + svprfd (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfd_u32_index: +** add (x[0-9+]), x0, x1, lsl #?2 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u32_index, uint32_t, + svprfd (p0, x0 + x1, SV_PLDL1KEEP), + svprfd (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfd_u32_1: +** add (x[0-9+]), x0, #?4 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u32_1, uint32_t, + svprfd (p0, x0 + 1, SV_PLDL1KEEP), + svprfd (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfd_u64_index: +** prfd pldl1keep, p0, \[x0, x1, lsl #?3\] +** ret +*/ +TEST_PREFETCH (prfd_u64_index, uint64_t, + svprfd (p0, x0 + x1, SV_PLDL1KEEP), + svprfd (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfd_u64_1: +** add (x[0-9+]), x0, #?8 +** prfd pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfd_u64_1, uint64_t, + svprfd (p0, x0 + 1, SV_PLDL1KEEP), + svprfd (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfd_pldl1strm: +** prfd pldl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pldl1strm, uint8_t, + svprfd (p0, x0, SV_PLDL1STRM), + svprfd (p0, x0, SV_PLDL1STRM)) + +/* +** prfd_pldl2keep: +** prfd pldl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pldl2keep, uint8_t, + svprfd (p0, x0, SV_PLDL2KEEP), + svprfd (p0, x0, SV_PLDL2KEEP)) + +/* +** prfd_pldl2strm: +** prfd pldl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pldl2strm, uint8_t, + svprfd (p0, x0, SV_PLDL2STRM), + svprfd (p0, x0, SV_PLDL2STRM)) + +/* +** prfd_pldl3keep: +** prfd pldl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pldl3keep, uint8_t, + svprfd (p0, x0, SV_PLDL3KEEP), + svprfd (p0, x0, SV_PLDL3KEEP)) + +/* +** prfd_pldl3strm: +** prfd pldl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pldl3strm, uint8_t, + svprfd (p0, x0, SV_PLDL3STRM), + svprfd (p0, x0, SV_PLDL3STRM)) + +/* +** prfd_pstl1keep: +** prfd pstl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl1keep, uint8_t, + svprfd (p0, x0, SV_PSTL1KEEP), + svprfd (p0, x0, SV_PSTL1KEEP)) + +/* +** prfd_pstl1strm: +** prfd pstl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl1strm, uint8_t, + svprfd (p0, x0, SV_PSTL1STRM), + svprfd (p0, x0, SV_PSTL1STRM)) + +/* +** prfd_pstl2keep: +** prfd pstl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl2keep, uint8_t, + svprfd (p0, x0, SV_PSTL2KEEP), + svprfd (p0, x0, SV_PSTL2KEEP)) + +/* +** prfd_pstl2strm: +** prfd pstl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl2strm, uint8_t, + svprfd (p0, x0, SV_PSTL2STRM), + svprfd (p0, x0, SV_PSTL2STRM)) + +/* +** prfd_pstl3keep: +** prfd pstl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl3keep, uint8_t, + svprfd (p0, x0, SV_PSTL3KEEP), + svprfd (p0, x0, SV_PSTL3KEEP)) + +/* +** prfd_pstl3strm: +** prfd pstl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_pstl3strm, uint8_t, + svprfd (p0, x0, SV_PSTL3STRM), + svprfd (p0, x0, SV_PSTL3STRM)) + +/* +** prfd_vnum_0: +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_vnum_0, uint8_t, + svprfd_vnum (p0, x0, 0, SV_PLDL1KEEP), + svprfd_vnum (p0, x0, 0, SV_PLDL1KEEP)) + +/* +** prfd_vnum_1: +** incb x0 +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_vnum_1, uint16_t, + svprfd_vnum (p0, x0, 1, SV_PLDL1KEEP), + svprfd_vnum (p0, x0, 1, SV_PLDL1KEEP)) + +/* +** prfd_vnum_2: +** incb x0, all, mul #2 +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_vnum_2, uint32_t, + svprfd_vnum (p0, x0, 2, SV_PLDL1KEEP), + svprfd_vnum (p0, x0, 2, SV_PLDL1KEEP)) + +/* +** prfd_vnum_3: +** incb x0, all, mul #3 +** prfd pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfd_vnum_3, uint64_t, + svprfd_vnum (p0, x0, 3, SV_PLDL1KEEP), + svprfd_vnum (p0, x0, 3, SV_PLDL1KEEP)) + +/* +** prfd_vnum_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** prfd pldl1keep, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** prfd zldl1keep, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_PREFETCH (prfd_vnum_x1, uint64_t, + svprfd_vnum (p0, x0, x1, SV_PLDL1KEEP), + svprfd_vnum (p0, x0, x1, SV_PLDL1KEEP)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd_gather.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd_gather.c new file mode 100644 index 00000000000..aa1323fee0a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfd_gather.c @@ -0,0 +1,225 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfd_gather_u32base: +** prfd pldl1keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_u32base, svuint32_t, + svprfd_gather_u32base (p0, z0, SV_PLDL1KEEP), + svprfd_gather (p0, z0, SV_PLDL1KEEP)) + +/* +** prfd_gather_u64base: +** prfd pldl1strm, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_u64base, svuint64_t, + svprfd_gather_u64base (p0, z0, SV_PLDL1STRM), + svprfd_gather (p0, z0, SV_PLDL1STRM)) + +/* +** prfd_gather_x0_u32base_index: +** lsl (x[0-9]+), x0, #?3 +** prfb pldl2keep, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_x0_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, x0, SV_PLDL2KEEP), + svprfd_gather_index (p0, z0, x0, SV_PLDL2KEEP)) + +/* +** prfd_gather_m1_u32base_index: +** mov (x[0-9]+), #?-8 +** prfb pldl2strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_m1_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, -1, SV_PLDL2STRM), + svprfd_gather_index (p0, z0, -1, SV_PLDL2STRM)) + +/* +** prfd_gather_0_u32base_index: +** prfd pldl3keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_0_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, 0, SV_PLDL3KEEP), + svprfd_gather_index (p0, z0, 0, SV_PLDL3KEEP)) + +/* +** prfd_gather_5_u32base_index: +** prfd pldl3strm, p0, \[z0\.s, #40\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_5_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, 5, SV_PLDL3STRM), + svprfd_gather_index (p0, z0, 5, SV_PLDL3STRM)) + +/* +** prfd_gather_31_u32base_index: +** prfd pstl1keep, p0, \[z0\.s, #248\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_31_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, 31, SV_PSTL1KEEP), + svprfd_gather_index (p0, z0, 31, SV_PSTL1KEEP)) + +/* +** prfd_gather_32_u32base_index: +** mov (x[0-9]+), #?256 +** prfb pstl1strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_32_u32base_index, svuint32_t, + svprfd_gather_u32base_index (p0, z0, 32, SV_PSTL1STRM), + svprfd_gather_index (p0, z0, 32, SV_PSTL1STRM)) + +/* +** prfd_gather_x0_u64base_index: +** lsl (x[0-9]+), x0, #?3 +** prfb pstl2keep, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_x0_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, x0, SV_PSTL2KEEP), + svprfd_gather_index (p0, z0, x0, SV_PSTL2KEEP)) + +/* +** prfd_gather_m1_u64base_index: +** mov (x[0-9]+), #?-8 +** prfb pstl2strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_m1_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, -1, SV_PSTL2STRM), + svprfd_gather_index (p0, z0, -1, SV_PSTL2STRM)) + +/* +** prfd_gather_0_u64base_index: +** prfd pstl3keep, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_0_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, 0, SV_PSTL3KEEP), + svprfd_gather_index (p0, z0, 0, SV_PSTL3KEEP)) + +/* +** prfd_gather_5_u64base_index: +** prfd pstl3strm, p0, \[z0\.d, #40\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_5_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, 5, SV_PSTL3STRM), + svprfd_gather_index (p0, z0, 5, SV_PSTL3STRM)) + +/* +** prfd_gather_31_u64base_index: +** prfd pldl1keep, p0, \[z0\.d, #248\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_31_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, 31, SV_PLDL1KEEP), + svprfd_gather_index (p0, z0, 31, SV_PLDL1KEEP)) + +/* +** prfd_gather_32_u64base_index: +** mov (x[0-9]+), #?256 +** prfb pldl1strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfd_gather_32_u64base_index, svuint64_t, + svprfd_gather_u64base_index (p0, z0, 32, SV_PLDL1STRM), + svprfd_gather_index (p0, z0, 32, SV_PLDL1STRM)) + +/* +** prfd_gather_x0_s32index: +** prfd pldl2keep, p0, \[x0, z0\.s, sxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_x0_s32index, svint32_t, + svprfd_gather_s32index (p0, x0, z0, SV_PLDL2KEEP), + svprfd_gather_index (p0, x0, z0, SV_PLDL2KEEP)) + +/* +** prfd_gather_s32index: +** prfd pldl2strm, p0, \[x0, z1\.s, sxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_s32index, svint32_t, + svprfd_gather_s32index (p0, x0, z1, SV_PLDL2STRM), + svprfd_gather_index (p0, x0, z1, SV_PLDL2STRM)) + +/* +** prfd_gather_x0_u32index: +** prfd pldl3keep, p0, \[x0, z0\.s, uxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_x0_u32index, svuint32_t, + svprfd_gather_u32index (p0, x0, z0, SV_PLDL3KEEP), + svprfd_gather_index (p0, x0, z0, SV_PLDL3KEEP)) + +/* +** prfd_gather_u32index: +** prfd pldl3strm, p0, \[x0, z1\.s, uxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_u32index, svuint32_t, + svprfd_gather_u32index (p0, x0, z1, SV_PLDL3STRM), + svprfd_gather_index (p0, x0, z1, SV_PLDL3STRM)) + +/* +** prfd_gather_x0_s64index: +** prfd pstl1keep, p0, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_x0_s64index, svint64_t, + svprfd_gather_s64index (p0, x0, z0, SV_PSTL1KEEP), + svprfd_gather_index (p0, x0, z0, SV_PSTL1KEEP)) + +/* +** prfd_gather_s64index: +** prfd pstl1strm, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_s64index, svint64_t, + svprfd_gather_s64index (p0, x0, z1, SV_PSTL1STRM), + svprfd_gather_index (p0, x0, z1, SV_PSTL1STRM)) + +/* +** prfd_gather_ext_s64index: +** prfd pstl1strm, p0, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_ext_s64index, svint64_t, + svprfd_gather_s64index (p0, x0, svextw_s64_x (p0, z1), SV_PSTL1STRM), + svprfd_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL1STRM)) + +/* +** prfd_gather_x0_u64index: +** prfd pstl2keep, p0, \[x0, z0\.d, lsl 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_x0_u64index, svuint64_t, + svprfd_gather_u64index (p0, x0, z0, SV_PSTL2KEEP), + svprfd_gather_index (p0, x0, z0, SV_PSTL2KEEP)) + +/* +** prfd_gather_u64index: +** prfd pstl2strm, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_u64index, svuint64_t, + svprfd_gather_u64index (p0, x0, z1, SV_PSTL2STRM), + svprfd_gather_index (p0, x0, z1, SV_PSTL2STRM)) + +/* +** prfd_gather_ext_u64index: +** prfd pstl2strm, p0, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfd_gather_ext_u64index, svuint64_t, + svprfd_gather_u64index (p0, x0, svextw_u64_x (p0, z1), SV_PSTL2STRM), + svprfd_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL2STRM)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh.c new file mode 100644 index 00000000000..19088c7d53a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh.c @@ -0,0 +1,245 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfh_base: +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_base, uint8_t, + svprfh (p0, x0, SV_PLDL1KEEP), + svprfh (p0, x0, SV_PLDL1KEEP)) + +/* +** prfh_u8_index: +** add (x[0-9+]), (x0, x1|x1, x0) +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_u8_index, uint8_t, + svprfh (p0, x0 + x1, SV_PLDL1KEEP), + svprfh (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfh_u8_1: +** add (x[0-9+]), x0, #?1 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u8_1, uint8_t, + svprfh (p0, x0 + 1, SV_PLDL1KEEP), + svprfh (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfh_u16_index: +** prfh pldl1keep, p0, \[x0, x1, lsl #?1\] +** ret +*/ +TEST_PREFETCH (prfh_u16_index, uint16_t, + svprfh (p0, x0 + x1, SV_PLDL1KEEP), + svprfh (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfh_u16_1: +** add (x[0-9+]), x0, #?2 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u16_1, uint16_t, + svprfh (p0, x0 + 1, SV_PLDL1KEEP), + svprfh (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfh_u32_index: +** add (x[0-9+]), x0, x1, lsl #?2 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u32_index, uint32_t, + svprfh (p0, x0 + x1, SV_PLDL1KEEP), + svprfh (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfh_u32_1: +** add (x[0-9+]), x0, #?4 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u32_1, uint32_t, + svprfh (p0, x0 + 1, SV_PLDL1KEEP), + svprfh (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfh_u64_index: +** add (x[0-9+]), x0, x1, lsl #?3 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u64_index, uint64_t, + svprfh (p0, x0 + x1, SV_PLDL1KEEP), + svprfh (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfh_u64_1: +** add (x[0-9+]), x0, #?8 +** prfh pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfh_u64_1, uint64_t, + svprfh (p0, x0 + 1, SV_PLDL1KEEP), + svprfh (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfh_pldl1strm: +** prfh pldl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pldl1strm, uint8_t, + svprfh (p0, x0, SV_PLDL1STRM), + svprfh (p0, x0, SV_PLDL1STRM)) + +/* +** prfh_pldl2keep: +** prfh pldl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pldl2keep, uint8_t, + svprfh (p0, x0, SV_PLDL2KEEP), + svprfh (p0, x0, SV_PLDL2KEEP)) + +/* +** prfh_pldl2strm: +** prfh pldl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pldl2strm, uint8_t, + svprfh (p0, x0, SV_PLDL2STRM), + svprfh (p0, x0, SV_PLDL2STRM)) + +/* +** prfh_pldl3keep: +** prfh pldl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pldl3keep, uint8_t, + svprfh (p0, x0, SV_PLDL3KEEP), + svprfh (p0, x0, SV_PLDL3KEEP)) + +/* +** prfh_pldl3strm: +** prfh pldl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pldl3strm, uint8_t, + svprfh (p0, x0, SV_PLDL3STRM), + svprfh (p0, x0, SV_PLDL3STRM)) + +/* +** prfh_pstl1keep: +** prfh pstl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl1keep, uint8_t, + svprfh (p0, x0, SV_PSTL1KEEP), + svprfh (p0, x0, SV_PSTL1KEEP)) + +/* +** prfh_pstl1strm: +** prfh pstl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl1strm, uint8_t, + svprfh (p0, x0, SV_PSTL1STRM), + svprfh (p0, x0, SV_PSTL1STRM)) + +/* +** prfh_pstl2keep: +** prfh pstl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl2keep, uint8_t, + svprfh (p0, x0, SV_PSTL2KEEP), + svprfh (p0, x0, SV_PSTL2KEEP)) + +/* +** prfh_pstl2strm: +** prfh pstl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl2strm, uint8_t, + svprfh (p0, x0, SV_PSTL2STRM), + svprfh (p0, x0, SV_PSTL2STRM)) + +/* +** prfh_pstl3keep: +** prfh pstl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl3keep, uint8_t, + svprfh (p0, x0, SV_PSTL3KEEP), + svprfh (p0, x0, SV_PSTL3KEEP)) + +/* +** prfh_pstl3strm: +** prfh pstl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_pstl3strm, uint8_t, + svprfh (p0, x0, SV_PSTL3STRM), + svprfh (p0, x0, SV_PSTL3STRM)) + +/* +** prfh_vnum_0: +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_vnum_0, uint8_t, + svprfh_vnum (p0, x0, 0, SV_PLDL1KEEP), + svprfh_vnum (p0, x0, 0, SV_PLDL1KEEP)) + +/* +** prfh_vnum_1: +** incb x0 +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_vnum_1, uint16_t, + svprfh_vnum (p0, x0, 1, SV_PLDL1KEEP), + svprfh_vnum (p0, x0, 1, SV_PLDL1KEEP)) + +/* +** prfh_vnum_2: +** incb x0, all, mul #2 +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_vnum_2, uint32_t, + svprfh_vnum (p0, x0, 2, SV_PLDL1KEEP), + svprfh_vnum (p0, x0, 2, SV_PLDL1KEEP)) + +/* +** prfh_vnum_3: +** incb x0, all, mul #3 +** prfh pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfh_vnum_3, uint64_t, + svprfh_vnum (p0, x0, 3, SV_PLDL1KEEP), + svprfh_vnum (p0, x0, 3, SV_PLDL1KEEP)) + +/* +** prfh_vnum_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** prfh pldl1keep, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** prfh zldl1keep, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_PREFETCH (prfh_vnum_x1, uint64_t, + svprfh_vnum (p0, x0, x1, SV_PLDL1KEEP), + svprfh_vnum (p0, x0, x1, SV_PLDL1KEEP)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh_gather.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh_gather.c new file mode 100644 index 00000000000..8b0deb269dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfh_gather.c @@ -0,0 +1,225 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfh_gather_u32base: +** prfh pldl1keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_u32base, svuint32_t, + svprfh_gather_u32base (p0, z0, SV_PLDL1KEEP), + svprfh_gather (p0, z0, SV_PLDL1KEEP)) + +/* +** prfh_gather_u64base: +** prfh pldl1strm, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_u64base, svuint64_t, + svprfh_gather_u64base (p0, z0, SV_PLDL1STRM), + svprfh_gather (p0, z0, SV_PLDL1STRM)) + +/* +** prfh_gather_x0_u32base_index: +** lsl (x[0-9]+), x0, #?1 +** prfb pldl2keep, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_x0_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, x0, SV_PLDL2KEEP), + svprfh_gather_index (p0, z0, x0, SV_PLDL2KEEP)) + +/* +** prfh_gather_m1_u32base_index: +** mov (x[0-9]+), #?-2 +** prfb pldl2strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_m1_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, -1, SV_PLDL2STRM), + svprfh_gather_index (p0, z0, -1, SV_PLDL2STRM)) + +/* +** prfh_gather_0_u32base_index: +** prfh pldl3keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_0_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, 0, SV_PLDL3KEEP), + svprfh_gather_index (p0, z0, 0, SV_PLDL3KEEP)) + +/* +** prfh_gather_5_u32base_index: +** prfh pldl3strm, p0, \[z0\.s, #10\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_5_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, 5, SV_PLDL3STRM), + svprfh_gather_index (p0, z0, 5, SV_PLDL3STRM)) + +/* +** prfh_gather_31_u32base_index: +** prfh pstl1keep, p0, \[z0\.s, #62\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_31_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, 31, SV_PSTL1KEEP), + svprfh_gather_index (p0, z0, 31, SV_PSTL1KEEP)) + +/* +** prfh_gather_32_u32base_index: +** mov (x[0-9]+), #?64 +** prfb pstl1strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_32_u32base_index, svuint32_t, + svprfh_gather_u32base_index (p0, z0, 32, SV_PSTL1STRM), + svprfh_gather_index (p0, z0, 32, SV_PSTL1STRM)) + +/* +** prfh_gather_x0_u64base_index: +** lsl (x[0-9]+), x0, #?1 +** prfb pstl2keep, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_x0_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, x0, SV_PSTL2KEEP), + svprfh_gather_index (p0, z0, x0, SV_PSTL2KEEP)) + +/* +** prfh_gather_m1_u64base_index: +** mov (x[0-9]+), #?-2 +** prfb pstl2strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_m1_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, -1, SV_PSTL2STRM), + svprfh_gather_index (p0, z0, -1, SV_PSTL2STRM)) + +/* +** prfh_gather_0_u64base_index: +** prfh pstl3keep, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_0_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, 0, SV_PSTL3KEEP), + svprfh_gather_index (p0, z0, 0, SV_PSTL3KEEP)) + +/* +** prfh_gather_5_u64base_index: +** prfh pstl3strm, p0, \[z0\.d, #10\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_5_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, 5, SV_PSTL3STRM), + svprfh_gather_index (p0, z0, 5, SV_PSTL3STRM)) + +/* +** prfh_gather_31_u64base_index: +** prfh pldl1keep, p0, \[z0\.d, #62\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_31_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, 31, SV_PLDL1KEEP), + svprfh_gather_index (p0, z0, 31, SV_PLDL1KEEP)) + +/* +** prfh_gather_32_u64base_index: +** mov (x[0-9]+), #?64 +** prfb pldl1strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfh_gather_32_u64base_index, svuint64_t, + svprfh_gather_u64base_index (p0, z0, 32, SV_PLDL1STRM), + svprfh_gather_index (p0, z0, 32, SV_PLDL1STRM)) + +/* +** prfh_gather_x0_s32index: +** prfh pldl2keep, p0, \[x0, z0\.s, sxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_x0_s32index, svint32_t, + svprfh_gather_s32index (p0, x0, z0, SV_PLDL2KEEP), + svprfh_gather_index (p0, x0, z0, SV_PLDL2KEEP)) + +/* +** prfh_gather_s32index: +** prfh pldl2strm, p0, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_s32index, svint32_t, + svprfh_gather_s32index (p0, x0, z1, SV_PLDL2STRM), + svprfh_gather_index (p0, x0, z1, SV_PLDL2STRM)) + +/* +** prfh_gather_x0_u32index: +** prfh pldl3keep, p0, \[x0, z0\.s, uxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_x0_u32index, svuint32_t, + svprfh_gather_u32index (p0, x0, z0, SV_PLDL3KEEP), + svprfh_gather_index (p0, x0, z0, SV_PLDL3KEEP)) + +/* +** prfh_gather_u32index: +** prfh pldl3strm, p0, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_u32index, svuint32_t, + svprfh_gather_u32index (p0, x0, z1, SV_PLDL3STRM), + svprfh_gather_index (p0, x0, z1, SV_PLDL3STRM)) + +/* +** prfh_gather_x0_s64index: +** prfh pstl1keep, p0, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_x0_s64index, svint64_t, + svprfh_gather_s64index (p0, x0, z0, SV_PSTL1KEEP), + svprfh_gather_index (p0, x0, z0, SV_PSTL1KEEP)) + +/* +** prfh_gather_s64index: +** prfh pstl1strm, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_s64index, svint64_t, + svprfh_gather_s64index (p0, x0, z1, SV_PSTL1STRM), + svprfh_gather_index (p0, x0, z1, SV_PSTL1STRM)) + +/* +** prfh_gather_ext_s64index: +** prfh pstl1strm, p0, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_ext_s64index, svint64_t, + svprfh_gather_s64index (p0, x0, svextw_s64_x (p0, z1), SV_PSTL1STRM), + svprfh_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL1STRM)) + +/* +** prfh_gather_x0_u64index: +** prfh pstl2keep, p0, \[x0, z0\.d, lsl 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_x0_u64index, svuint64_t, + svprfh_gather_u64index (p0, x0, z0, SV_PSTL2KEEP), + svprfh_gather_index (p0, x0, z0, SV_PSTL2KEEP)) + +/* +** prfh_gather_u64index: +** prfh pstl2strm, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_u64index, svuint64_t, + svprfh_gather_u64index (p0, x0, z1, SV_PSTL2STRM), + svprfh_gather_index (p0, x0, z1, SV_PSTL2STRM)) + +/* +** prfh_gather_ext_u64index: +** prfh pstl2strm, p0, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfh_gather_ext_u64index, svuint64_t, + svprfh_gather_u64index (p0, x0, svextw_u64_x (p0, z1), SV_PSTL2STRM), + svprfh_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL2STRM)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw.c new file mode 100644 index 00000000000..35de6712fe2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw.c @@ -0,0 +1,245 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfw_base: +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_base, uint8_t, + svprfw (p0, x0, SV_PLDL1KEEP), + svprfw (p0, x0, SV_PLDL1KEEP)) + +/* +** prfw_u8_index: +** add (x[0-9+]), (x0, x1|x1, x0) +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_u8_index, uint8_t, + svprfw (p0, x0 + x1, SV_PLDL1KEEP), + svprfw (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfw_u8_1: +** add (x[0-9+]), x0, #?1 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u8_1, uint8_t, + svprfw (p0, x0 + 1, SV_PLDL1KEEP), + svprfw (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfw_u16_index: +** add (x[0-9+]), x0, x1, lsl #?1 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u16_index, uint16_t, + svprfw (p0, x0 + x1, SV_PLDL1KEEP), + svprfw (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfw_u16_1: +** add (x[0-9+]), x0, #?2 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u16_1, uint16_t, + svprfw (p0, x0 + 1, SV_PLDL1KEEP), + svprfw (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfw_u32_index: +** prfw pldl1keep, p0, \[x0, x1, lsl #?2\] +** ret +*/ +TEST_PREFETCH (prfw_u32_index, uint32_t, + svprfw (p0, x0 + x1, SV_PLDL1KEEP), + svprfw (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfw_u32_1: +** add (x[0-9+]), x0, #?4 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u32_1, uint32_t, + svprfw (p0, x0 + 1, SV_PLDL1KEEP), + svprfw (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfw_u64_index: +** add (x[0-9+]), x0, x1, lsl #?3 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u64_index, uint64_t, + svprfw (p0, x0 + x1, SV_PLDL1KEEP), + svprfw (p0, x0 + x1, SV_PLDL1KEEP)) + +/* +** prfw_u64_1: +** add (x[0-9+]), x0, #?8 +** prfw pldl1keep, p0, \[\1\] +** ret +*/ +TEST_PREFETCH (prfw_u64_1, uint64_t, + svprfw (p0, x0 + 1, SV_PLDL1KEEP), + svprfw (p0, x0 + 1, SV_PLDL1KEEP)) + +/* +** prfw_pldl1strm: +** prfw pldl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pldl1strm, uint8_t, + svprfw (p0, x0, SV_PLDL1STRM), + svprfw (p0, x0, SV_PLDL1STRM)) + +/* +** prfw_pldl2keep: +** prfw pldl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pldl2keep, uint8_t, + svprfw (p0, x0, SV_PLDL2KEEP), + svprfw (p0, x0, SV_PLDL2KEEP)) + +/* +** prfw_pldl2strm: +** prfw pldl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pldl2strm, uint8_t, + svprfw (p0, x0, SV_PLDL2STRM), + svprfw (p0, x0, SV_PLDL2STRM)) + +/* +** prfw_pldl3keep: +** prfw pldl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pldl3keep, uint8_t, + svprfw (p0, x0, SV_PLDL3KEEP), + svprfw (p0, x0, SV_PLDL3KEEP)) + +/* +** prfw_pldl3strm: +** prfw pldl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pldl3strm, uint8_t, + svprfw (p0, x0, SV_PLDL3STRM), + svprfw (p0, x0, SV_PLDL3STRM)) + +/* +** prfw_pstl1keep: +** prfw pstl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl1keep, uint8_t, + svprfw (p0, x0, SV_PSTL1KEEP), + svprfw (p0, x0, SV_PSTL1KEEP)) + +/* +** prfw_pstl1strm: +** prfw pstl1strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl1strm, uint8_t, + svprfw (p0, x0, SV_PSTL1STRM), + svprfw (p0, x0, SV_PSTL1STRM)) + +/* +** prfw_pstl2keep: +** prfw pstl2keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl2keep, uint8_t, + svprfw (p0, x0, SV_PSTL2KEEP), + svprfw (p0, x0, SV_PSTL2KEEP)) + +/* +** prfw_pstl2strm: +** prfw pstl2strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl2strm, uint8_t, + svprfw (p0, x0, SV_PSTL2STRM), + svprfw (p0, x0, SV_PSTL2STRM)) + +/* +** prfw_pstl3keep: +** prfw pstl3keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl3keep, uint8_t, + svprfw (p0, x0, SV_PSTL3KEEP), + svprfw (p0, x0, SV_PSTL3KEEP)) + +/* +** prfw_pstl3strm: +** prfw pstl3strm, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_pstl3strm, uint8_t, + svprfw (p0, x0, SV_PSTL3STRM), + svprfw (p0, x0, SV_PSTL3STRM)) + +/* +** prfw_vnum_0: +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_vnum_0, uint8_t, + svprfw_vnum (p0, x0, 0, SV_PLDL1KEEP), + svprfw_vnum (p0, x0, 0, SV_PLDL1KEEP)) + +/* +** prfw_vnum_1: +** incb x0 +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_vnum_1, uint16_t, + svprfw_vnum (p0, x0, 1, SV_PLDL1KEEP), + svprfw_vnum (p0, x0, 1, SV_PLDL1KEEP)) + +/* +** prfw_vnum_2: +** incb x0, all, mul #2 +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_vnum_2, uint32_t, + svprfw_vnum (p0, x0, 2, SV_PLDL1KEEP), + svprfw_vnum (p0, x0, 2, SV_PLDL1KEEP)) + +/* +** prfw_vnum_3: +** incb x0, all, mul #3 +** prfw pldl1keep, p0, \[x0\] +** ret +*/ +TEST_PREFETCH (prfw_vnum_3, uint64_t, + svprfw_vnum (p0, x0, 3, SV_PLDL1KEEP), + svprfw_vnum (p0, x0, 3, SV_PLDL1KEEP)) + +/* +** prfw_vnum_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** prfw pldl1keep, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** prfw zldl1keep, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_PREFETCH (prfw_vnum_x1, uint64_t, + svprfw_vnum (p0, x0, x1, SV_PLDL1KEEP), + svprfw_vnum (p0, x0, x1, SV_PLDL1KEEP)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw_gather.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw_gather.c new file mode 100644 index 00000000000..18436bb974b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/prfw_gather.c @@ -0,0 +1,225 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** prfw_gather_u32base: +** prfw pldl1keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_u32base, svuint32_t, + svprfw_gather_u32base (p0, z0, SV_PLDL1KEEP), + svprfw_gather (p0, z0, SV_PLDL1KEEP)) + +/* +** prfw_gather_u64base: +** prfw pldl1strm, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_u64base, svuint64_t, + svprfw_gather_u64base (p0, z0, SV_PLDL1STRM), + svprfw_gather (p0, z0, SV_PLDL1STRM)) + +/* +** prfw_gather_x0_u32base_index: +** lsl (x[0-9]+), x0, #?2 +** prfb pldl2keep, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_x0_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, x0, SV_PLDL2KEEP), + svprfw_gather_index (p0, z0, x0, SV_PLDL2KEEP)) + +/* +** prfw_gather_m1_u32base_index: +** mov (x[0-9]+), #?-4 +** prfb pldl2strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_m1_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, -1, SV_PLDL2STRM), + svprfw_gather_index (p0, z0, -1, SV_PLDL2STRM)) + +/* +** prfw_gather_0_u32base_index: +** prfw pldl3keep, p0, \[z0\.s\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_0_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, 0, SV_PLDL3KEEP), + svprfw_gather_index (p0, z0, 0, SV_PLDL3KEEP)) + +/* +** prfw_gather_5_u32base_index: +** prfw pldl3strm, p0, \[z0\.s, #20\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_5_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, 5, SV_PLDL3STRM), + svprfw_gather_index (p0, z0, 5, SV_PLDL3STRM)) + +/* +** prfw_gather_31_u32base_index: +** prfw pstl1keep, p0, \[z0\.s, #124\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_31_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, 31, SV_PSTL1KEEP), + svprfw_gather_index (p0, z0, 31, SV_PSTL1KEEP)) + +/* +** prfw_gather_32_u32base_index: +** mov (x[0-9]+), #?128 +** prfb pstl1strm, p0, \[\1, z0\.s, uxtw\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_32_u32base_index, svuint32_t, + svprfw_gather_u32base_index (p0, z0, 32, SV_PSTL1STRM), + svprfw_gather_index (p0, z0, 32, SV_PSTL1STRM)) + +/* +** prfw_gather_x0_u64base_index: +** lsl (x[0-9]+), x0, #?2 +** prfb pstl2keep, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_x0_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, x0, SV_PSTL2KEEP), + svprfw_gather_index (p0, z0, x0, SV_PSTL2KEEP)) + +/* +** prfw_gather_m1_u64base_index: +** mov (x[0-9]+), #?-4 +** prfb pstl2strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_m1_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, -1, SV_PSTL2STRM), + svprfw_gather_index (p0, z0, -1, SV_PSTL2STRM)) + +/* +** prfw_gather_0_u64base_index: +** prfw pstl3keep, p0, \[z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_0_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, 0, SV_PSTL3KEEP), + svprfw_gather_index (p0, z0, 0, SV_PSTL3KEEP)) + +/* +** prfw_gather_5_u64base_index: +** prfw pstl3strm, p0, \[z0\.d, #20\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_5_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, 5, SV_PSTL3STRM), + svprfw_gather_index (p0, z0, 5, SV_PSTL3STRM)) + +/* +** prfw_gather_31_u64base_index: +** prfw pldl1keep, p0, \[z0\.d, #124\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_31_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, 31, SV_PLDL1KEEP), + svprfw_gather_index (p0, z0, 31, SV_PLDL1KEEP)) + +/* +** prfw_gather_32_u64base_index: +** mov (x[0-9]+), #?128 +** prfb pldl1strm, p0, \[\1, z0\.d\] +** ret +*/ +TEST_PREFETCH_GATHER_ZS (prfw_gather_32_u64base_index, svuint64_t, + svprfw_gather_u64base_index (p0, z0, 32, SV_PLDL1STRM), + svprfw_gather_index (p0, z0, 32, SV_PLDL1STRM)) + +/* +** prfw_gather_x0_s32index: +** prfw pldl2keep, p0, \[x0, z0\.s, sxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_x0_s32index, svint32_t, + svprfw_gather_s32index (p0, x0, z0, SV_PLDL2KEEP), + svprfw_gather_index (p0, x0, z0, SV_PLDL2KEEP)) + +/* +** prfw_gather_s32index: +** prfw pldl2strm, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_s32index, svint32_t, + svprfw_gather_s32index (p0, x0, z1, SV_PLDL2STRM), + svprfw_gather_index (p0, x0, z1, SV_PLDL2STRM)) + +/* +** prfw_gather_x0_u32index: +** prfw pldl3keep, p0, \[x0, z0\.s, uxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_x0_u32index, svuint32_t, + svprfw_gather_u32index (p0, x0, z0, SV_PLDL3KEEP), + svprfw_gather_index (p0, x0, z0, SV_PLDL3KEEP)) + +/* +** prfw_gather_u32index: +** prfw pldl3strm, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_u32index, svuint32_t, + svprfw_gather_u32index (p0, x0, z1, SV_PLDL3STRM), + svprfw_gather_index (p0, x0, z1, SV_PLDL3STRM)) + +/* +** prfw_gather_x0_s64index: +** prfw pstl1keep, p0, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_x0_s64index, svint64_t, + svprfw_gather_s64index (p0, x0, z0, SV_PSTL1KEEP), + svprfw_gather_index (p0, x0, z0, SV_PSTL1KEEP)) + +/* +** prfw_gather_s64index: +** prfw pstl1strm, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_s64index, svint64_t, + svprfw_gather_s64index (p0, x0, z1, SV_PSTL1STRM), + svprfw_gather_index (p0, x0, z1, SV_PSTL1STRM)) + +/* +** prfw_gather_ext_s64index: +** prfw pstl1strm, p0, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_ext_s64index, svint64_t, + svprfw_gather_s64index (p0, x0, svextw_s64_x (p0, z1), SV_PSTL1STRM), + svprfw_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL1STRM)) + +/* +** prfw_gather_x0_u64index: +** prfw pstl2keep, p0, \[x0, z0\.d, lsl 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_x0_u64index, svuint64_t, + svprfw_gather_u64index (p0, x0, z0, SV_PSTL2KEEP), + svprfw_gather_index (p0, x0, z0, SV_PSTL2KEEP)) + +/* +** prfw_gather_u64index: +** prfw pstl2strm, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_u64index, svuint64_t, + svprfw_gather_u64index (p0, x0, z1, SV_PSTL2STRM), + svprfw_gather_index (p0, x0, z1, SV_PSTL2STRM)) + +/* +** prfw_gather_ext_u64index: +** prfw pstl2strm, p0, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_PREFETCH_GATHER_SZ (prfw_gather_ext_u64index, svuint64_t, + svprfw_gather_u64index (p0, x0, svextw_u64_x (p0, z1), SV_PSTL2STRM), + svprfw_gather_index (p0, x0, svextw_x (p0, z1), SV_PSTL2STRM)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_any.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_any.c new file mode 100644 index 00000000000..33280d3887b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_any.c @@ -0,0 +1,77 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** test_bool_any: +** ptest p0, p1\.b +** cset [wx]0, any +** ret +*/ +TEST_PTEST (test_bool_any, bool, + x0 = svptest_any (p0, p1)); + +/* +** test_bool_none: +** ptest p0, p1\.b +** cset [wx]0, none +** ret +*/ +TEST_PTEST (test_bool_none, bool, + x0 = !svptest_any (p0, p1)); + +/* +** test_int_any: +** ptest p0, p1\.b +** cset [wx]0, any +** ret +*/ +TEST_PTEST (test_int_any, int, + x0 = svptest_any (p0, p1)); + +/* +** test_int_none: +** ptest p0, p1\.b +** cset [wx]0, none +** ret +*/ +TEST_PTEST (test_int_none, int, + x0 = !svptest_any (p0, p1)); + +/* +** test_int64_t_any: +** ptest p0, p1\.b +** cset [wx]0, any +** ret +*/ +TEST_PTEST (test_int64_t_any, int64_t, + x0 = svptest_any (p0, p1)); + +/* +** test_int64_t_none: +** ptest p0, p1\.b +** cset [wx]0, none +** ret +*/ +TEST_PTEST (test_int64_t_none, int64_t, + x0 = !svptest_any (p0, p1)); + +/* +** sel_any: +** ptest p0, p1\.b +** csel x0, (x0, x1, any|x1, x0, none) +** ret +*/ +TEST_PTEST (sel_any, int64_t, + x0 = svptest_any (p0, p1) ? x0 : x1); + +/* +** sel_none: +** ptest p0, p1\.b +** csel x0, (x0, x1, none|x1, x0, any) +** ret +*/ +TEST_PTEST (sel_none, int64_t, + x0 = !svptest_any (p0, p1) ? x0 : x1); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_first.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_first.c new file mode 100644 index 00000000000..991dabd3ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_first.c @@ -0,0 +1,77 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** test_bool_first: +** ptest p0, p1\.b +** cset [wx]0, first +** ret +*/ +TEST_PTEST (test_bool_first, bool, + x0 = svptest_first (p0, p1)); + +/* +** test_bool_nfrst: +** ptest p0, p1\.b +** cset [wx]0, nfrst +** ret +*/ +TEST_PTEST (test_bool_nfrst, bool, + x0 = !svptest_first (p0, p1)); + +/* +** test_int_first: +** ptest p0, p1\.b +** cset [wx]0, first +** ret +*/ +TEST_PTEST (test_int_first, int, + x0 = svptest_first (p0, p1)); + +/* +** test_int_nfrst: +** ptest p0, p1\.b +** cset [wx]0, nfrst +** ret +*/ +TEST_PTEST (test_int_nfrst, int, + x0 = !svptest_first (p0, p1)); + +/* +** test_int64_t_first: +** ptest p0, p1\.b +** cset [wx]0, first +** ret +*/ +TEST_PTEST (test_int64_t_first, int64_t, + x0 = svptest_first (p0, p1)); + +/* +** test_int64_t_nfrst: +** ptest p0, p1\.b +** cset [wx]0, nfrst +** ret +*/ +TEST_PTEST (test_int64_t_nfrst, int64_t, + x0 = !svptest_first (p0, p1)); + +/* +** sel_first: +** ptest p0, p1\.b +** csel x0, (x0, x1, first|x1, x0, nfrst) +** ret +*/ +TEST_PTEST (sel_first, int64_t, + x0 = svptest_first (p0, p1) ? x0 : x1); + +/* +** sel_nfrst: +** ptest p0, p1\.b +** csel x0, (x0, x1, nfrst|x1, x0, first) +** ret +*/ +TEST_PTEST (sel_nfrst, int64_t, + x0 = !svptest_first (p0, p1) ? x0 : x1); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_last.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_last.c new file mode 100644 index 00000000000..b952a414949 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptest_last.c @@ -0,0 +1,77 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" +#include + +/* +** test_bool_last: +** ptest p0, p1\.b +** cset [wx]0, last +** ret +*/ +TEST_PTEST (test_bool_last, bool, + x0 = svptest_last (p0, p1)); + +/* +** test_bool_nlast: +** ptest p0, p1\.b +** cset [wx]0, nlast +** ret +*/ +TEST_PTEST (test_bool_nlast, bool, + x0 = !svptest_last (p0, p1)); + +/* +** test_int_last: +** ptest p0, p1\.b +** cset [wx]0, last +** ret +*/ +TEST_PTEST (test_int_last, int, + x0 = svptest_last (p0, p1)); + +/* +** test_int_nlast: +** ptest p0, p1\.b +** cset [wx]0, nlast +** ret +*/ +TEST_PTEST (test_int_nlast, int, + x0 = !svptest_last (p0, p1)); + +/* +** test_int64_t_last: +** ptest p0, p1\.b +** cset [wx]0, last +** ret +*/ +TEST_PTEST (test_int64_t_last, int64_t, + x0 = svptest_last (p0, p1)); + +/* +** test_int64_t_nlast: +** ptest p0, p1\.b +** cset [wx]0, nlast +** ret +*/ +TEST_PTEST (test_int64_t_nlast, int64_t, + x0 = !svptest_last (p0, p1)); + +/* +** sel_last: +** ptest p0, p1\.b +** csel x0, (x0, x1, last|x1, x0, nlast) +** ret +*/ +TEST_PTEST (sel_last, int64_t, + x0 = svptest_last (p0, p1) ? x0 : x1); + +/* +** sel_nlast: +** ptest p0, p1\.b +** csel x0, (x0, x1, nlast|x1, x0, last) +** ret +*/ +TEST_PTEST (sel_nlast, int64_t, + x0 = !svptest_last (p0, p1) ? x0 : x1); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue.c new file mode 100644 index 00000000000..9c86170cb1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue.c @@ -0,0 +1,40 @@ +/* { dg-additional-options "-msve-vector-bits=scalable" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ptrue_b8: +** ptrue p0\.b, all +** ret +*/ +TEST_P (ptrue_b8, + p0 = svptrue_b8 (), + p0 = svptrue_b8 ()); + +/* +** ptrue_b16: +** ptrue p0\.h, all +** ret +*/ +TEST_P (ptrue_b16, + p0 = svptrue_b16 (), + p0 = svptrue_b16 ()); + +/* +** ptrue_b32: +** ptrue p0\.s, all +** ret +*/ +TEST_P (ptrue_b32, + p0 = svptrue_b32 (), + p0 = svptrue_b32 ()); + +/* +** ptrue_b64: +** ptrue p0\.d, all +** ret +*/ +TEST_P (ptrue_b64, + p0 = svptrue_b64 (), + p0 = svptrue_b64 ()); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b16.c new file mode 100644 index 00000000000..d7f83f5c623 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b16.c @@ -0,0 +1,156 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ptrue_pat_pow2_b16: +** ptrue p0\.h, pow2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_pow2_b16, + p0 = svptrue_pat_b16 (SV_POW2), + p0 = svptrue_pat_b16 (SV_POW2)) + +/* +** ptrue_pat_vl1_b16: +** ptrue p0\.[bhsd], vl1 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl1_b16, + p0 = svptrue_pat_b16 (SV_VL1), + p0 = svptrue_pat_b16 (SV_VL1)) + +/* +** ptrue_pat_vl2_b16: +** ptrue p0\.h, vl2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl2_b16, + p0 = svptrue_pat_b16 (SV_VL2), + p0 = svptrue_pat_b16 (SV_VL2)) + +/* +** ptrue_pat_vl3_b16: +** ptrue p0\.h, vl3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl3_b16, + p0 = svptrue_pat_b16 (SV_VL3), + p0 = svptrue_pat_b16 (SV_VL3)) + +/* +** ptrue_pat_vl4_b16: +** ptrue p0\.h, vl4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl4_b16, + p0 = svptrue_pat_b16 (SV_VL4), + p0 = svptrue_pat_b16 (SV_VL4)) + +/* +** ptrue_pat_vl5_b16: +** ptrue p0\.h, vl5 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl5_b16, + p0 = svptrue_pat_b16 (SV_VL5), + p0 = svptrue_pat_b16 (SV_VL5)) + +/* +** ptrue_pat_vl6_b16: +** ptrue p0\.h, vl6 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl6_b16, + p0 = svptrue_pat_b16 (SV_VL6), + p0 = svptrue_pat_b16 (SV_VL6)) + +/* +** ptrue_pat_vl7_b16: +** ptrue p0\.h, vl7 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl7_b16, + p0 = svptrue_pat_b16 (SV_VL7), + p0 = svptrue_pat_b16 (SV_VL7)) + +/* +** ptrue_pat_vl8_b16: +** ptrue p0\.h, vl8 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl8_b16, + p0 = svptrue_pat_b16 (SV_VL8), + p0 = svptrue_pat_b16 (SV_VL8)) + +/* +** ptrue_pat_vl16_b16: +** ptrue p0\.[bhsd], vl16 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl16_b16, + p0 = svptrue_pat_b16 (SV_VL16), + p0 = svptrue_pat_b16 (SV_VL16)) + +/* +** ptrue_pat_vl32_b16: +** ptrue p0\.h, vl32 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl32_b16, + p0 = svptrue_pat_b16 (SV_VL32), + p0 = svptrue_pat_b16 (SV_VL32)) + +/* +** ptrue_pat_vl64_b16: +** ptrue p0\.h, vl64 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl64_b16, + p0 = svptrue_pat_b16 (SV_VL64), + p0 = svptrue_pat_b16 (SV_VL64)) + +/* +** ptrue_pat_vl128_b16: +** ptrue p0\.[bhsd], vl128 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl128_b16, + p0 = svptrue_pat_b16 (SV_VL128), + p0 = svptrue_pat_b16 (SV_VL128)) + +/* +** ptrue_pat_vl256_b16: +** ptrue p0\.h, vl256 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl256_b16, + p0 = svptrue_pat_b16 (SV_VL256), + p0 = svptrue_pat_b16 (SV_VL256)) + +/* +** ptrue_pat_mul4_b16: +** ptrue p0\.h, mul4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul4_b16, + p0 = svptrue_pat_b16 (SV_MUL4), + p0 = svptrue_pat_b16 (SV_MUL4)) + +/* +** ptrue_pat_mul3_b16: +** ptrue p0\.h, mul3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul3_b16, + p0 = svptrue_pat_b16 (SV_MUL3), + p0 = svptrue_pat_b16 (SV_MUL3)) + +/* +** ptrue_pat_all_b16: +** ptrue p0\.h[^\n]* +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_all_b16, + p0 = svptrue_pat_b16 (SV_ALL), + p0 = svptrue_pat_b16 (SV_ALL)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b32.c new file mode 100644 index 00000000000..11cf5aebb4d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b32.c @@ -0,0 +1,156 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ptrue_pat_pow2_b32: +** ptrue p0\.s, pow2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_pow2_b32, + p0 = svptrue_pat_b32 (SV_POW2), + p0 = svptrue_pat_b32 (SV_POW2)) + +/* +** ptrue_pat_vl1_b32: +** ptrue p0\.[bhsd], vl1 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl1_b32, + p0 = svptrue_pat_b32 (SV_VL1), + p0 = svptrue_pat_b32 (SV_VL1)) + +/* +** ptrue_pat_vl2_b32: +** ptrue p0\.s, vl2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl2_b32, + p0 = svptrue_pat_b32 (SV_VL2), + p0 = svptrue_pat_b32 (SV_VL2)) + +/* +** ptrue_pat_vl3_b32: +** ptrue p0\.s, vl3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl3_b32, + p0 = svptrue_pat_b32 (SV_VL3), + p0 = svptrue_pat_b32 (SV_VL3)) + +/* +** ptrue_pat_vl4_b32: +** ptrue p0\.s, vl4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl4_b32, + p0 = svptrue_pat_b32 (SV_VL4), + p0 = svptrue_pat_b32 (SV_VL4)) + +/* +** ptrue_pat_vl5_b32: +** ptrue p0\.s, vl5 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl5_b32, + p0 = svptrue_pat_b32 (SV_VL5), + p0 = svptrue_pat_b32 (SV_VL5)) + +/* +** ptrue_pat_vl6_b32: +** ptrue p0\.s, vl6 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl6_b32, + p0 = svptrue_pat_b32 (SV_VL6), + p0 = svptrue_pat_b32 (SV_VL6)) + +/* +** ptrue_pat_vl7_b32: +** ptrue p0\.s, vl7 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl7_b32, + p0 = svptrue_pat_b32 (SV_VL7), + p0 = svptrue_pat_b32 (SV_VL7)) + +/* +** ptrue_pat_vl8_b32: +** ptrue p0\.s, vl8 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl8_b32, + p0 = svptrue_pat_b32 (SV_VL8), + p0 = svptrue_pat_b32 (SV_VL8)) + +/* +** ptrue_pat_vl16_b32: +** ptrue p0\.[bhsd], vl16 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl16_b32, + p0 = svptrue_pat_b32 (SV_VL16), + p0 = svptrue_pat_b32 (SV_VL16)) + +/* +** ptrue_pat_vl32_b32: +** ptrue p0\.s, vl32 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl32_b32, + p0 = svptrue_pat_b32 (SV_VL32), + p0 = svptrue_pat_b32 (SV_VL32)) + +/* +** ptrue_pat_vl64_b32: +** ptrue p0\.s, vl64 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl64_b32, + p0 = svptrue_pat_b32 (SV_VL64), + p0 = svptrue_pat_b32 (SV_VL64)) + +/* +** ptrue_pat_vl128_b32: +** ptrue p0\.[bhsd], vl128 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl128_b32, + p0 = svptrue_pat_b32 (SV_VL128), + p0 = svptrue_pat_b32 (SV_VL128)) + +/* +** ptrue_pat_vl256_b32: +** ptrue p0\.s, vl256 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl256_b32, + p0 = svptrue_pat_b32 (SV_VL256), + p0 = svptrue_pat_b32 (SV_VL256)) + +/* +** ptrue_pat_mul4_b32: +** ptrue p0\.s, mul4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul4_b32, + p0 = svptrue_pat_b32 (SV_MUL4), + p0 = svptrue_pat_b32 (SV_MUL4)) + +/* +** ptrue_pat_mul3_b32: +** ptrue p0\.s, mul3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul3_b32, + p0 = svptrue_pat_b32 (SV_MUL3), + p0 = svptrue_pat_b32 (SV_MUL3)) + +/* +** ptrue_pat_all_b32: +** ptrue p0\.s[^\n]* +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_all_b32, + p0 = svptrue_pat_b32 (SV_ALL), + p0 = svptrue_pat_b32 (SV_ALL)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b64.c new file mode 100644 index 00000000000..4c4202bb334 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b64.c @@ -0,0 +1,156 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ptrue_pat_pow2_b64: +** ptrue p0\.d, pow2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_pow2_b64, + p0 = svptrue_pat_b64 (SV_POW2), + p0 = svptrue_pat_b64 (SV_POW2)) + +/* +** ptrue_pat_vl1_b64: +** ptrue p0\.[bhsd], vl1 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl1_b64, + p0 = svptrue_pat_b64 (SV_VL1), + p0 = svptrue_pat_b64 (SV_VL1)) + +/* +** ptrue_pat_vl2_b64: +** ptrue p0\.d, vl2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl2_b64, + p0 = svptrue_pat_b64 (SV_VL2), + p0 = svptrue_pat_b64 (SV_VL2)) + +/* +** ptrue_pat_vl3_b64: +** ptrue p0\.d, vl3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl3_b64, + p0 = svptrue_pat_b64 (SV_VL3), + p0 = svptrue_pat_b64 (SV_VL3)) + +/* +** ptrue_pat_vl4_b64: +** ptrue p0\.d, vl4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl4_b64, + p0 = svptrue_pat_b64 (SV_VL4), + p0 = svptrue_pat_b64 (SV_VL4)) + +/* +** ptrue_pat_vl5_b64: +** ptrue p0\.d, vl5 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl5_b64, + p0 = svptrue_pat_b64 (SV_VL5), + p0 = svptrue_pat_b64 (SV_VL5)) + +/* +** ptrue_pat_vl6_b64: +** ptrue p0\.d, vl6 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl6_b64, + p0 = svptrue_pat_b64 (SV_VL6), + p0 = svptrue_pat_b64 (SV_VL6)) + +/* +** ptrue_pat_vl7_b64: +** ptrue p0\.d, vl7 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl7_b64, + p0 = svptrue_pat_b64 (SV_VL7), + p0 = svptrue_pat_b64 (SV_VL7)) + +/* +** ptrue_pat_vl8_b64: +** ptrue p0\.d, vl8 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl8_b64, + p0 = svptrue_pat_b64 (SV_VL8), + p0 = svptrue_pat_b64 (SV_VL8)) + +/* +** ptrue_pat_vl16_b64: +** ptrue p0\.[bhsd], vl16 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl16_b64, + p0 = svptrue_pat_b64 (SV_VL16), + p0 = svptrue_pat_b64 (SV_VL16)) + +/* +** ptrue_pat_vl32_b64: +** ptrue p0\.d, vl32 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl32_b64, + p0 = svptrue_pat_b64 (SV_VL32), + p0 = svptrue_pat_b64 (SV_VL32)) + +/* +** ptrue_pat_vl64_b64: +** ptrue p0\.d, vl64 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl64_b64, + p0 = svptrue_pat_b64 (SV_VL64), + p0 = svptrue_pat_b64 (SV_VL64)) + +/* +** ptrue_pat_vl128_b64: +** ptrue p0\.[bhsd], vl128 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl128_b64, + p0 = svptrue_pat_b64 (SV_VL128), + p0 = svptrue_pat_b64 (SV_VL128)) + +/* +** ptrue_pat_vl256_b64: +** ptrue p0\.d, vl256 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl256_b64, + p0 = svptrue_pat_b64 (SV_VL256), + p0 = svptrue_pat_b64 (SV_VL256)) + +/* +** ptrue_pat_mul4_b64: +** ptrue p0\.d, mul4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul4_b64, + p0 = svptrue_pat_b64 (SV_MUL4), + p0 = svptrue_pat_b64 (SV_MUL4)) + +/* +** ptrue_pat_mul3_b64: +** ptrue p0\.d, mul3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul3_b64, + p0 = svptrue_pat_b64 (SV_MUL3), + p0 = svptrue_pat_b64 (SV_MUL3)) + +/* +** ptrue_pat_all_b64: +** ptrue p0\.d[^\n]* +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_all_b64, + p0 = svptrue_pat_b64 (SV_ALL), + p0 = svptrue_pat_b64 (SV_ALL)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b8.c new file mode 100644 index 00000000000..49fb8c5554a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ptrue_pat_b8.c @@ -0,0 +1,156 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** ptrue_pat_pow2_b8: +** ptrue p0\.b, pow2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_pow2_b8, + p0 = svptrue_pat_b8 (SV_POW2), + p0 = svptrue_pat_b8 (SV_POW2)) + +/* +** ptrue_pat_vl1_b8: +** ptrue p0\.[bhsd], vl1 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl1_b8, + p0 = svptrue_pat_b8 (SV_VL1), + p0 = svptrue_pat_b8 (SV_VL1)) + +/* +** ptrue_pat_vl2_b8: +** ptrue p0\.b, vl2 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl2_b8, + p0 = svptrue_pat_b8 (SV_VL2), + p0 = svptrue_pat_b8 (SV_VL2)) + +/* +** ptrue_pat_vl3_b8: +** ptrue p0\.b, vl3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl3_b8, + p0 = svptrue_pat_b8 (SV_VL3), + p0 = svptrue_pat_b8 (SV_VL3)) + +/* +** ptrue_pat_vl4_b8: +** ptrue p0\.b, vl4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl4_b8, + p0 = svptrue_pat_b8 (SV_VL4), + p0 = svptrue_pat_b8 (SV_VL4)) + +/* +** ptrue_pat_vl5_b8: +** ptrue p0\.b, vl5 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl5_b8, + p0 = svptrue_pat_b8 (SV_VL5), + p0 = svptrue_pat_b8 (SV_VL5)) + +/* +** ptrue_pat_vl6_b8: +** ptrue p0\.b, vl6 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl6_b8, + p0 = svptrue_pat_b8 (SV_VL6), + p0 = svptrue_pat_b8 (SV_VL6)) + +/* +** ptrue_pat_vl7_b8: +** ptrue p0\.b, vl7 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl7_b8, + p0 = svptrue_pat_b8 (SV_VL7), + p0 = svptrue_pat_b8 (SV_VL7)) + +/* +** ptrue_pat_vl8_b8: +** ptrue p0\.b, vl8 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl8_b8, + p0 = svptrue_pat_b8 (SV_VL8), + p0 = svptrue_pat_b8 (SV_VL8)) + +/* +** ptrue_pat_vl16_b8: +** ptrue p0\.[bhsd], vl16 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl16_b8, + p0 = svptrue_pat_b8 (SV_VL16), + p0 = svptrue_pat_b8 (SV_VL16)) + +/* +** ptrue_pat_vl32_b8: +** ptrue p0\.b, vl32 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl32_b8, + p0 = svptrue_pat_b8 (SV_VL32), + p0 = svptrue_pat_b8 (SV_VL32)) + +/* +** ptrue_pat_vl64_b8: +** ptrue p0\.b, vl64 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl64_b8, + p0 = svptrue_pat_b8 (SV_VL64), + p0 = svptrue_pat_b8 (SV_VL64)) + +/* +** ptrue_pat_vl128_b8: +** ptrue p0\.[bhsd], vl128 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl128_b8, + p0 = svptrue_pat_b8 (SV_VL128), + p0 = svptrue_pat_b8 (SV_VL128)) + +/* +** ptrue_pat_vl256_b8: +** ptrue p0\.b, vl256 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_vl256_b8, + p0 = svptrue_pat_b8 (SV_VL256), + p0 = svptrue_pat_b8 (SV_VL256)) + +/* +** ptrue_pat_mul4_b8: +** ptrue p0\.b, mul4 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul4_b8, + p0 = svptrue_pat_b8 (SV_MUL4), + p0 = svptrue_pat_b8 (SV_MUL4)) + +/* +** ptrue_pat_mul3_b8: +** ptrue p0\.b, mul3 +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_mul3_b8, + p0 = svptrue_pat_b8 (SV_MUL3), + p0 = svptrue_pat_b8 (SV_MUL3)) + +/* +** ptrue_pat_all_b8: +** ptrue p0\.b[^\n]* +** ret +*/ +TEST_UNIFORM_P (ptrue_pat_all_b8, + p0 = svptrue_pat_b8 (SV_ALL), + p0 = svptrue_pat_b8 (SV_ALL)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s16.c new file mode 100644 index 00000000000..03255c41cd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s16.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_s16_tied1: +** sqadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_s16_tied1, svint16_t, + z0 = svqadd_s16 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_s16_tied2: +** sqadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_s16_tied2, svint16_t, + z0 = svqadd_s16 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_s16_untied: +** sqadd z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_s16_untied, svint16_t, + z0 = svqadd_s16 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_s16_tied1: +** mov (z[0-9]+\.h), w0 +** sqadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s16_tied1, svint16_t, int16_t, + z0 = svqadd_n_s16 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_s16_untied: +** mov (z[0-9]+\.h), w0 +** sqadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s16_untied, svint16_t, int16_t, + z0 = svqadd_n_s16 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_s16_tied1: +** sqadd z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s16_tied1, svint16_t, + z0 = svqadd_n_s16 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_s16_untied: +** movprfx z0, z1 +** sqadd z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s16_untied, svint16_t, + z0 = svqadd_n_s16 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_s16: +** sqadd z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_s16, svint16_t, + z0 = svqadd_n_s16 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_s16: +** sqadd z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_s16, svint16_t, + z0 = svqadd_n_s16 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_s16: +** sqadd z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_s16, svint16_t, + z0 = svqadd_n_s16 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_s16: +** sqsub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_s16, svint16_t, + z0 = svqadd_n_s16 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_s16: +** sqsub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_s16, svint16_t, + z0 = svqadd_n_s16 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_s16: +** sqsub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_s16, svint16_t, + z0 = svqadd_n_s16 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s32.c new file mode 100644 index 00000000000..197cc38401d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s32.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_s32_tied1: +** sqadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_s32_tied1, svint32_t, + z0 = svqadd_s32 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_s32_tied2: +** sqadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_s32_tied2, svint32_t, + z0 = svqadd_s32 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_s32_untied: +** sqadd z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_s32_untied, svint32_t, + z0 = svqadd_s32 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_s32_tied1: +** mov (z[0-9]+\.s), w0 +** sqadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s32_tied1, svint32_t, int32_t, + z0 = svqadd_n_s32 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_s32_untied: +** mov (z[0-9]+\.s), w0 +** sqadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s32_untied, svint32_t, int32_t, + z0 = svqadd_n_s32 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_s32_tied1: +** sqadd z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s32_tied1, svint32_t, + z0 = svqadd_n_s32 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_s32_untied: +** movprfx z0, z1 +** sqadd z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s32_untied, svint32_t, + z0 = svqadd_n_s32 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_s32: +** sqadd z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_s32, svint32_t, + z0 = svqadd_n_s32 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_s32: +** sqadd z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_s32, svint32_t, + z0 = svqadd_n_s32 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_s32: +** sqadd z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_s32, svint32_t, + z0 = svqadd_n_s32 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_s32: +** sqsub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_s32, svint32_t, + z0 = svqadd_n_s32 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_s32: +** sqsub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_s32, svint32_t, + z0 = svqadd_n_s32 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_s32: +** sqsub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_s32, svint32_t, + z0 = svqadd_n_s32 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s64.c new file mode 100644 index 00000000000..0218866eaf7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s64.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_s64_tied1: +** sqadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_s64_tied1, svint64_t, + z0 = svqadd_s64 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_s64_tied2: +** sqadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_s64_tied2, svint64_t, + z0 = svqadd_s64 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_s64_untied: +** sqadd z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_s64_untied, svint64_t, + z0 = svqadd_s64 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_x0_s64_tied1: +** mov (z[0-9]+\.d), x0 +** sqadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (qadd_x0_s64_tied1, svint64_t, int64_t, + z0 = svqadd_n_s64 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_x0_s64_untied: +** mov (z[0-9]+\.d), x0 +** sqadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (qadd_x0_s64_untied, svint64_t, int64_t, + z0 = svqadd_n_s64 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_s64_tied1: +** sqadd z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s64_tied1, svint64_t, + z0 = svqadd_n_s64 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_s64_untied: +** movprfx z0, z1 +** sqadd z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s64_untied, svint64_t, + z0 = svqadd_n_s64 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_s64: +** sqadd z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_s64, svint64_t, + z0 = svqadd_n_s64 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_s64: +** sqadd z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_s64, svint64_t, + z0 = svqadd_n_s64 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_s64: +** sqadd z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_s64, svint64_t, + z0 = svqadd_n_s64 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_s64: +** sqsub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_s64, svint64_t, + z0 = svqadd_n_s64 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_s64: +** sqsub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_s64, svint64_t, + z0 = svqadd_n_s64 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_s64: +** sqsub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_s64, svint64_t, + z0 = svqadd_n_s64 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s8.c new file mode 100644 index 00000000000..c8b88fa82f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_s8.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_s8_tied1: +** sqadd z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_s8_tied1, svint8_t, + z0 = svqadd_s8 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_s8_tied2: +** sqadd z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_s8_tied2, svint8_t, + z0 = svqadd_s8 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_s8_untied: +** sqadd z0\.b, (z1\.b, z2\.b|z2\.b, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_s8_untied, svint8_t, + z0 = svqadd_s8 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_s8_tied1: +** mov (z[0-9]+\.b), w0 +** sqadd z0\.b, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s8_tied1, svint8_t, int8_t, + z0 = svqadd_n_s8 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_s8_untied: +** mov (z[0-9]+\.b), w0 +** sqadd z0\.b, (z1\.b, \1|\1, z1\.b) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_s8_untied, svint8_t, int8_t, + z0 = svqadd_n_s8 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_s8_tied1: +** sqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s8_tied1, svint8_t, + z0 = svqadd_n_s8 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_s8_untied: +** movprfx z0, z1 +** sqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_s8_untied, svint8_t, + z0 = svqadd_n_s8 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_s8: +** sqadd z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_s8, svint8_t, + z0 = svqadd_n_s8 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_s8: +** sqsub z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_s8, svint8_t, + z0 = svqadd_n_s8 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_s8: +** sqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_s8, svint8_t, + z0 = svqadd_n_s8 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_s8: +** sqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_s8, svint8_t, + z0 = svqadd_n_s8 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_s8: +** sqsub z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_s8, svint8_t, + z0 = svqadd_n_s8 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_s8: +** sqsub z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_s8, svint8_t, + z0 = svqadd_n_s8 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u16.c new file mode 100644 index 00000000000..dd7bc5b6a11 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u16.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_u16_tied1: +** uqadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_u16_tied1, svuint16_t, + z0 = svqadd_u16 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_u16_tied2: +** uqadd z0\.h, (z0\.h, z1\.h|z1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_u16_tied2, svuint16_t, + z0 = svqadd_u16 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_u16_untied: +** uqadd z0\.h, (z1\.h, z2\.h|z2\.h, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_u16_untied, svuint16_t, + z0 = svqadd_u16 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** uqadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svqadd_n_u16 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** uqadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u16_untied, svuint16_t, uint16_t, + z0 = svqadd_n_u16 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_u16_tied1: +** uqadd z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u16_tied1, svuint16_t, + z0 = svqadd_n_u16 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_u16_untied: +** movprfx z0, z1 +** uqadd z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u16_untied, svuint16_t, + z0 = svqadd_n_u16 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_u16: +** uqadd z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_u16: +** uqadd z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_u16: +** uqadd z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** uqadd z0\.h, (z0\.h, \1\.h|\1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_u16: +** mov (z[0-9]+\.h), #-127 +** uqadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_u16: +** mov (z[0-9]+\.h), #-128 +** uqadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_u16, svuint16_t, + z0 = svqadd_n_u16 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u32.c new file mode 100644 index 00000000000..0f846e44e5b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u32.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_u32_tied1: +** uqadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_u32_tied1, svuint32_t, + z0 = svqadd_u32 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_u32_tied2: +** uqadd z0\.s, (z0\.s, z1\.s|z1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_u32_tied2, svuint32_t, + z0 = svqadd_u32 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_u32_untied: +** uqadd z0\.s, (z1\.s, z2\.s|z2\.s, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_u32_untied, svuint32_t, + z0 = svqadd_u32 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** uqadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svqadd_n_u32 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** uqadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u32_untied, svuint32_t, uint32_t, + z0 = svqadd_n_u32 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_u32_tied1: +** uqadd z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u32_tied1, svuint32_t, + z0 = svqadd_n_u32 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_u32_untied: +** movprfx z0, z1 +** uqadd z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u32_untied, svuint32_t, + z0 = svqadd_n_u32 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_u32: +** uqadd z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_u32: +** uqadd z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_u32: +** uqadd z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** uqadd z0\.s, (z0\.s, \1\.s|\1\.s, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_u32: +** mov (z[0-9]+\.s), #-127 +** uqadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_u32: +** mov (z[0-9]+\.s), #-128 +** uqadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_u32, svuint32_t, + z0 = svqadd_n_u32 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u64.c new file mode 100644 index 00000000000..454fb1d639a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u64.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_u64_tied1: +** uqadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_u64_tied1, svuint64_t, + z0 = svqadd_u64 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_u64_tied2: +** uqadd z0\.d, (z0\.d, z1\.d|z1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_u64_tied2, svuint64_t, + z0 = svqadd_u64 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_u64_untied: +** uqadd z0\.d, (z1\.d, z2\.d|z2\.d, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_u64_untied, svuint64_t, + z0 = svqadd_u64 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** uqadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_ZX (qadd_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svqadd_n_u64 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** uqadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_ZX (qadd_x0_u64_untied, svuint64_t, uint64_t, + z0 = svqadd_n_u64 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_u64_tied1: +** uqadd z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u64_tied1, svuint64_t, + z0 = svqadd_n_u64 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_u64_untied: +** movprfx z0, z1 +** uqadd z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u64_untied, svuint64_t, + z0 = svqadd_n_u64 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_u64: +** uqadd z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_u64: +** uqadd z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_u64: +** uqadd z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** uqadd z0\.d, (z0\.d, \1\.d|\1\.d, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_u64: +** mov (z[0-9]+\.d), #-127 +** uqadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_u64: +** mov (z[0-9]+\.d), #-128 +** uqadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_u64, svuint64_t, + z0 = svqadd_n_u64 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u8.c new file mode 100644 index 00000000000..e86b8988c8e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qadd_u8.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qadd_u8_tied1: +** uqadd z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_u8_tied1, svuint8_t, + z0 = svqadd_u8 (z0, z1), + z0 = svqadd (z0, z1)) + +/* +** qadd_u8_tied2: +** uqadd z0\.b, (z0\.b, z1\.b|z1\.b, z0\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_u8_tied2, svuint8_t, + z0 = svqadd_u8 (z1, z0), + z0 = svqadd (z1, z0)) + +/* +** qadd_u8_untied: +** uqadd z0\.b, (z1\.b, z2\.b|z2\.b, z1\.b) +** ret +*/ +TEST_UNIFORM_Z (qadd_u8_untied, svuint8_t, + z0 = svqadd_u8 (z1, z2), + z0 = svqadd (z1, z2)) + +/* +** qadd_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** uqadd z0\.b, (z0\.b, \1|\1, z0\.b) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svqadd_n_u8 (z0, x0), + z0 = svqadd (z0, x0)) + +/* +** qadd_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** uqadd z0\.b, (z1\.b, \1|\1, z1\.b) +** ret +*/ +TEST_UNIFORM_ZX (qadd_w0_u8_untied, svuint8_t, uint8_t, + z0 = svqadd_n_u8 (z1, x0), + z0 = svqadd (z1, x0)) + +/* +** qadd_1_u8_tied1: +** uqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u8_tied1, svuint8_t, + z0 = svqadd_n_u8 (z0, 1), + z0 = svqadd (z0, 1)) + +/* +** qadd_1_u8_untied: +** movprfx z0, z1 +** uqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qadd_1_u8_untied, svuint8_t, + z0 = svqadd_n_u8 (z1, 1), + z0 = svqadd (z1, 1)) + +/* +** qadd_127_u8: +** uqadd z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qadd_127_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, 127), + z0 = svqadd (z0, 127)) + +/* +** qadd_128_u8: +** uqadd z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_128_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, 128), + z0 = svqadd (z0, 128)) + +/* +** qadd_255_u8: +** uqadd z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_255_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, 255), + z0 = svqadd (z0, 255)) + +/* +** qadd_m1_u8: +** uqadd z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (qadd_m1_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, -1), + z0 = svqadd (z0, -1)) + +/* +** qadd_m127_u8: +** uqadd z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (qadd_m127_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, -127), + z0 = svqadd (z0, -127)) + +/* +** qadd_m128_u8: +** uqadd z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qadd_m128_u8, svuint8_t, + z0 = svqadd_n_u8 (z0, -128), + z0 = svqadd (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s32.c new file mode 100644 index 00000000000..22b3afef7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_pat_n_1_s32_tied: +** sqdecb x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_s32_tied, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqdecb_pat (x0, SV_POW2, 1)) + +/* +** qdecb_pat_n_1_s32_untied: +** mov w0, w1 +** sqdecb x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_s32_untied, int32_t, + x0 = svqdecb_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqdecb_pat (x1, SV_POW2, 1)) + +/* +** qdecb_pat_n_2_s32: +** sqdecb x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_2_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqdecb_pat (x0, SV_POW2, 2)) + +/* +** qdecb_pat_n_7_s32: +** sqdecb x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_7_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqdecb_pat (x0, SV_POW2, 7)) + +/* +** qdecb_pat_n_15_s32: +** sqdecb x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_15_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqdecb_pat (x0, SV_POW2, 15)) + +/* +** qdecb_pat_n_16_s32: +** sqdecb x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_16_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqdecb_pat (x0, SV_POW2, 16)) + +/* +** qdecb_pat_n_vl1_s32: +** sqdecb x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl1_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqdecb_pat (x0, SV_VL1, 16)) + +/* +** qdecb_pat_n_vl2_s32: +** sqdecb x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl2_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqdecb_pat (x0, SV_VL2, 16)) + +/* +** qdecb_pat_n_vl3_s32: +** sqdecb x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl3_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqdecb_pat (x0, SV_VL3, 16)) + +/* +** qdecb_pat_n_vl4_s32: +** sqdecb x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl4_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqdecb_pat (x0, SV_VL4, 16)) + +/* +** qdecb_pat_n_vl5_s32: +** sqdecb x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl5_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqdecb_pat (x0, SV_VL5, 16)) + +/* +** qdecb_pat_n_vl6_s32: +** sqdecb x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl6_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqdecb_pat (x0, SV_VL6, 16)) + +/* +** qdecb_pat_n_vl7_s32: +** sqdecb x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl7_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqdecb_pat (x0, SV_VL7, 16)) + +/* +** qdecb_pat_n_vl8_s32: +** sqdecb x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl8_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqdecb_pat (x0, SV_VL8, 16)) + +/* +** qdecb_pat_n_vl16_s32: +** sqdecb x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl16_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqdecb_pat (x0, SV_VL16, 16)) + +/* +** qdecb_pat_n_vl32_s32: +** sqdecb x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl32_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqdecb_pat (x0, SV_VL32, 16)) + +/* +** qdecb_pat_n_vl64_s32: +** sqdecb x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl64_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqdecb_pat (x0, SV_VL64, 16)) + +/* +** qdecb_pat_n_vl128_s32: +** sqdecb x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl128_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqdecb_pat (x0, SV_VL128, 16)) + +/* +** qdecb_pat_n_vl256_s32: +** sqdecb x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl256_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqdecb_pat (x0, SV_VL256, 16)) + +/* +** qdecb_pat_n_mul4_s32: +** sqdecb x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul4_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqdecb_pat (x0, SV_MUL4, 16)) + +/* +** qdecb_pat_n_mul3_s32: +** sqdecb x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul3_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqdecb_pat (x0, SV_MUL3, 16)) + +/* +** qdecb_pat_n_all_s32: +** sqdecb x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_all_s32, int32_t, + x0 = svqdecb_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqdecb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s64.c new file mode 100644 index 00000000000..1380e6c8e7e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_pat_n_1_s64_tied: +** sqdecb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_s64_tied, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqdecb_pat (x0, SV_POW2, 1)) + +/* +** qdecb_pat_n_1_s64_untied: +** mov x0, x1 +** sqdecb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_s64_untied, int64_t, + x0 = svqdecb_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqdecb_pat (x1, SV_POW2, 1)) + +/* +** qdecb_pat_n_2_s64: +** sqdecb x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_2_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqdecb_pat (x0, SV_POW2, 2)) + +/* +** qdecb_pat_n_7_s64: +** sqdecb x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_7_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqdecb_pat (x0, SV_POW2, 7)) + +/* +** qdecb_pat_n_15_s64: +** sqdecb x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_15_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqdecb_pat (x0, SV_POW2, 15)) + +/* +** qdecb_pat_n_16_s64: +** sqdecb x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_16_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqdecb_pat (x0, SV_POW2, 16)) + +/* +** qdecb_pat_n_vl1_s64: +** sqdecb x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl1_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqdecb_pat (x0, SV_VL1, 16)) + +/* +** qdecb_pat_n_vl2_s64: +** sqdecb x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl2_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqdecb_pat (x0, SV_VL2, 16)) + +/* +** qdecb_pat_n_vl3_s64: +** sqdecb x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl3_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqdecb_pat (x0, SV_VL3, 16)) + +/* +** qdecb_pat_n_vl4_s64: +** sqdecb x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl4_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqdecb_pat (x0, SV_VL4, 16)) + +/* +** qdecb_pat_n_vl5_s64: +** sqdecb x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl5_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqdecb_pat (x0, SV_VL5, 16)) + +/* +** qdecb_pat_n_vl6_s64: +** sqdecb x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl6_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqdecb_pat (x0, SV_VL6, 16)) + +/* +** qdecb_pat_n_vl7_s64: +** sqdecb x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl7_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqdecb_pat (x0, SV_VL7, 16)) + +/* +** qdecb_pat_n_vl8_s64: +** sqdecb x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl8_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqdecb_pat (x0, SV_VL8, 16)) + +/* +** qdecb_pat_n_vl16_s64: +** sqdecb x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl16_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqdecb_pat (x0, SV_VL16, 16)) + +/* +** qdecb_pat_n_vl32_s64: +** sqdecb x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl32_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqdecb_pat (x0, SV_VL32, 16)) + +/* +** qdecb_pat_n_vl64_s64: +** sqdecb x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl64_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqdecb_pat (x0, SV_VL64, 16)) + +/* +** qdecb_pat_n_vl128_s64: +** sqdecb x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl128_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqdecb_pat (x0, SV_VL128, 16)) + +/* +** qdecb_pat_n_vl256_s64: +** sqdecb x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl256_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqdecb_pat (x0, SV_VL256, 16)) + +/* +** qdecb_pat_n_mul4_s64: +** sqdecb x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul4_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqdecb_pat (x0, SV_MUL4, 16)) + +/* +** qdecb_pat_n_mul3_s64: +** sqdecb x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul3_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqdecb_pat (x0, SV_MUL3, 16)) + +/* +** qdecb_pat_n_all_s64: +** sqdecb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_all_s64, int64_t, + x0 = svqdecb_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqdecb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u32.c new file mode 100644 index 00000000000..3db3da86628 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_pat_n_1_u32_tied: +** uqdecb w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_u32_tied, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqdecb_pat (x0, SV_POW2, 1)) + +/* +** qdecb_pat_n_1_u32_untied: +** mov w0, w1 +** uqdecb w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_u32_untied, uint32_t, + x0 = svqdecb_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqdecb_pat (x1, SV_POW2, 1)) + +/* +** qdecb_pat_n_2_u32: +** uqdecb w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_2_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqdecb_pat (x0, SV_POW2, 2)) + +/* +** qdecb_pat_n_7_u32: +** uqdecb w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_7_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqdecb_pat (x0, SV_POW2, 7)) + +/* +** qdecb_pat_n_15_u32: +** uqdecb w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_15_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqdecb_pat (x0, SV_POW2, 15)) + +/* +** qdecb_pat_n_16_u32: +** uqdecb w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_16_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqdecb_pat (x0, SV_POW2, 16)) + +/* +** qdecb_pat_n_vl1_u32: +** uqdecb w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl1_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqdecb_pat (x0, SV_VL1, 16)) + +/* +** qdecb_pat_n_vl2_u32: +** uqdecb w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl2_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqdecb_pat (x0, SV_VL2, 16)) + +/* +** qdecb_pat_n_vl3_u32: +** uqdecb w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl3_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqdecb_pat (x0, SV_VL3, 16)) + +/* +** qdecb_pat_n_vl4_u32: +** uqdecb w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl4_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqdecb_pat (x0, SV_VL4, 16)) + +/* +** qdecb_pat_n_vl5_u32: +** uqdecb w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl5_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqdecb_pat (x0, SV_VL5, 16)) + +/* +** qdecb_pat_n_vl6_u32: +** uqdecb w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl6_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqdecb_pat (x0, SV_VL6, 16)) + +/* +** qdecb_pat_n_vl7_u32: +** uqdecb w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl7_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqdecb_pat (x0, SV_VL7, 16)) + +/* +** qdecb_pat_n_vl8_u32: +** uqdecb w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl8_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqdecb_pat (x0, SV_VL8, 16)) + +/* +** qdecb_pat_n_vl16_u32: +** uqdecb w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl16_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqdecb_pat (x0, SV_VL16, 16)) + +/* +** qdecb_pat_n_vl32_u32: +** uqdecb w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl32_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqdecb_pat (x0, SV_VL32, 16)) + +/* +** qdecb_pat_n_vl64_u32: +** uqdecb w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl64_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqdecb_pat (x0, SV_VL64, 16)) + +/* +** qdecb_pat_n_vl128_u32: +** uqdecb w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl128_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqdecb_pat (x0, SV_VL128, 16)) + +/* +** qdecb_pat_n_vl256_u32: +** uqdecb w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl256_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqdecb_pat (x0, SV_VL256, 16)) + +/* +** qdecb_pat_n_mul4_u32: +** uqdecb w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul4_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqdecb_pat (x0, SV_MUL4, 16)) + +/* +** qdecb_pat_n_mul3_u32: +** uqdecb w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul3_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqdecb_pat (x0, SV_MUL3, 16)) + +/* +** qdecb_pat_n_all_u32: +** uqdecb w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_all_u32, uint32_t, + x0 = svqdecb_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqdecb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u64.c new file mode 100644 index 00000000000..2f4c3c7aa9f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_pat_n_1_u64_tied: +** uqdecb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_u64_tied, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqdecb_pat (x0, SV_POW2, 1)) + +/* +** qdecb_pat_n_1_u64_untied: +** mov x0, x1 +** uqdecb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_1_u64_untied, uint64_t, + x0 = svqdecb_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqdecb_pat (x1, SV_POW2, 1)) + +/* +** qdecb_pat_n_2_u64: +** uqdecb x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_2_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqdecb_pat (x0, SV_POW2, 2)) + +/* +** qdecb_pat_n_7_u64: +** uqdecb x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_7_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqdecb_pat (x0, SV_POW2, 7)) + +/* +** qdecb_pat_n_15_u64: +** uqdecb x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_15_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqdecb_pat (x0, SV_POW2, 15)) + +/* +** qdecb_pat_n_16_u64: +** uqdecb x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_16_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqdecb_pat (x0, SV_POW2, 16)) + +/* +** qdecb_pat_n_vl1_u64: +** uqdecb x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl1_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqdecb_pat (x0, SV_VL1, 16)) + +/* +** qdecb_pat_n_vl2_u64: +** uqdecb x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl2_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqdecb_pat (x0, SV_VL2, 16)) + +/* +** qdecb_pat_n_vl3_u64: +** uqdecb x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl3_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqdecb_pat (x0, SV_VL3, 16)) + +/* +** qdecb_pat_n_vl4_u64: +** uqdecb x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl4_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqdecb_pat (x0, SV_VL4, 16)) + +/* +** qdecb_pat_n_vl5_u64: +** uqdecb x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl5_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqdecb_pat (x0, SV_VL5, 16)) + +/* +** qdecb_pat_n_vl6_u64: +** uqdecb x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl6_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqdecb_pat (x0, SV_VL6, 16)) + +/* +** qdecb_pat_n_vl7_u64: +** uqdecb x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl7_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqdecb_pat (x0, SV_VL7, 16)) + +/* +** qdecb_pat_n_vl8_u64: +** uqdecb x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl8_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqdecb_pat (x0, SV_VL8, 16)) + +/* +** qdecb_pat_n_vl16_u64: +** uqdecb x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl16_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqdecb_pat (x0, SV_VL16, 16)) + +/* +** qdecb_pat_n_vl32_u64: +** uqdecb x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl32_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqdecb_pat (x0, SV_VL32, 16)) + +/* +** qdecb_pat_n_vl64_u64: +** uqdecb x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl64_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqdecb_pat (x0, SV_VL64, 16)) + +/* +** qdecb_pat_n_vl128_u64: +** uqdecb x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl128_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqdecb_pat (x0, SV_VL128, 16)) + +/* +** qdecb_pat_n_vl256_u64: +** uqdecb x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_vl256_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqdecb_pat (x0, SV_VL256, 16)) + +/* +** qdecb_pat_n_mul4_u64: +** uqdecb x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul4_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqdecb_pat (x0, SV_MUL4, 16)) + +/* +** qdecb_pat_n_mul3_u64: +** uqdecb x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_mul3_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqdecb_pat (x0, SV_MUL3, 16)) + +/* +** qdecb_pat_n_all_u64: +** uqdecb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_pat_n_all_u64, uint64_t, + x0 = svqdecb_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqdecb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s32.c new file mode 100644 index 00000000000..11180654e1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_n_1_s32_tied: +** sqdecb x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_s32_tied, int32_t, + x0 = svqdecb_n_s32 (x0, 1), + x0 = svqdecb (x0, 1)) + +/* +** qdecb_n_1_s32_untied: +** mov w0, w1 +** sqdecb x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_s32_untied, int32_t, + x0 = svqdecb_n_s32 (x1, 1), + x0 = svqdecb (x1, 1)) + +/* +** qdecb_n_2_s32: +** sqdecb x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_2_s32, int32_t, + x0 = svqdecb_n_s32 (x0, 2), + x0 = svqdecb (x0, 2)) + +/* +** qdecb_n_7_s32: +** sqdecb x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_7_s32, int32_t, + x0 = svqdecb_n_s32 (x0, 7), + x0 = svqdecb (x0, 7)) + +/* +** qdecb_n_15_s32: +** sqdecb x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_15_s32, int32_t, + x0 = svqdecb_n_s32 (x0, 15), + x0 = svqdecb (x0, 15)) + +/* +** qdecb_n_16_s32: +** sqdecb x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_16_s32, int32_t, + x0 = svqdecb_n_s32 (x0, 16), + x0 = svqdecb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s64.c new file mode 100644 index 00000000000..17b76565591 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_n_1_s64_tied: +** sqdecb x0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_s64_tied, int64_t, + x0 = svqdecb_n_s64 (x0, 1), + x0 = svqdecb (x0, 1)) + +/* +** qdecb_n_1_s64_untied: +** mov x0, x1 +** sqdecb x0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_s64_untied, int64_t, + x0 = svqdecb_n_s64 (x1, 1), + x0 = svqdecb (x1, 1)) + +/* +** qdecb_n_2_s64: +** sqdecb x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_2_s64, int64_t, + x0 = svqdecb_n_s64 (x0, 2), + x0 = svqdecb (x0, 2)) + +/* +** qdecb_n_7_s64: +** sqdecb x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_7_s64, int64_t, + x0 = svqdecb_n_s64 (x0, 7), + x0 = svqdecb (x0, 7)) + +/* +** qdecb_n_15_s64: +** sqdecb x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_15_s64, int64_t, + x0 = svqdecb_n_s64 (x0, 15), + x0 = svqdecb (x0, 15)) + +/* +** qdecb_n_16_s64: +** sqdecb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_16_s64, int64_t, + x0 = svqdecb_n_s64 (x0, 16), + x0 = svqdecb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u32.c new file mode 100644 index 00000000000..b31e04de551 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_n_1_u32_tied: +** uqdecb w0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_u32_tied, uint32_t, + x0 = svqdecb_n_u32 (x0, 1), + x0 = svqdecb (x0, 1)) + +/* +** qdecb_n_1_u32_untied: +** mov w0, w1 +** uqdecb w0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_u32_untied, uint32_t, + x0 = svqdecb_n_u32 (x1, 1), + x0 = svqdecb (x1, 1)) + +/* +** qdecb_n_2_u32: +** uqdecb w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_2_u32, uint32_t, + x0 = svqdecb_n_u32 (x0, 2), + x0 = svqdecb (x0, 2)) + +/* +** qdecb_n_7_u32: +** uqdecb w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_7_u32, uint32_t, + x0 = svqdecb_n_u32 (x0, 7), + x0 = svqdecb (x0, 7)) + +/* +** qdecb_n_15_u32: +** uqdecb w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_15_u32, uint32_t, + x0 = svqdecb_n_u32 (x0, 15), + x0 = svqdecb (x0, 15)) + +/* +** qdecb_n_16_u32: +** uqdecb w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_16_u32, uint32_t, + x0 = svqdecb_n_u32 (x0, 16), + x0 = svqdecb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u64.c new file mode 100644 index 00000000000..aab6faba988 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecb_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecb_n_1_u64_tied: +** uqdecb x0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_u64_tied, uint64_t, + x0 = svqdecb_n_u64 (x0, 1), + x0 = svqdecb (x0, 1)) + +/* +** qdecb_n_1_u64_untied: +** mov x0, x1 +** uqdecb x0 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_1_u64_untied, uint64_t, + x0 = svqdecb_n_u64 (x1, 1), + x0 = svqdecb (x1, 1)) + +/* +** qdecb_n_2_u64: +** uqdecb x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_2_u64, uint64_t, + x0 = svqdecb_n_u64 (x0, 2), + x0 = svqdecb (x0, 2)) + +/* +** qdecb_n_7_u64: +** uqdecb x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_7_u64, uint64_t, + x0 = svqdecb_n_u64 (x0, 7), + x0 = svqdecb (x0, 7)) + +/* +** qdecb_n_15_u64: +** uqdecb x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_15_u64, uint64_t, + x0 = svqdecb_n_u64 (x0, 15), + x0 = svqdecb (x0, 15)) + +/* +** qdecb_n_16_u64: +** uqdecb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecb_n_16_u64, uint64_t, + x0 = svqdecb_n_u64 (x0, 16), + x0 = svqdecb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s32.c new file mode 100644 index 00000000000..bc491d397a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_pat_n_1_s32_tied: +** sqdecd x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_s32_tied, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqdecd_pat (x0, SV_POW2, 1)) + +/* +** qdecd_pat_n_1_s32_untied: +** mov w0, w1 +** sqdecd x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_s32_untied, int32_t, + x0 = svqdecd_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqdecd_pat (x1, SV_POW2, 1)) + +/* +** qdecd_pat_n_2_s32: +** sqdecd x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_2_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqdecd_pat (x0, SV_POW2, 2)) + +/* +** qdecd_pat_n_7_s32: +** sqdecd x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_7_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqdecd_pat (x0, SV_POW2, 7)) + +/* +** qdecd_pat_n_15_s32: +** sqdecd x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_15_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqdecd_pat (x0, SV_POW2, 15)) + +/* +** qdecd_pat_n_16_s32: +** sqdecd x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_16_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqdecd_pat (x0, SV_POW2, 16)) + +/* +** qdecd_pat_n_vl1_s32: +** sqdecd x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl1_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqdecd_pat (x0, SV_VL1, 16)) + +/* +** qdecd_pat_n_vl2_s32: +** sqdecd x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl2_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqdecd_pat (x0, SV_VL2, 16)) + +/* +** qdecd_pat_n_vl3_s32: +** sqdecd x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl3_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqdecd_pat (x0, SV_VL3, 16)) + +/* +** qdecd_pat_n_vl4_s32: +** sqdecd x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl4_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqdecd_pat (x0, SV_VL4, 16)) + +/* +** qdecd_pat_n_vl5_s32: +** sqdecd x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl5_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqdecd_pat (x0, SV_VL5, 16)) + +/* +** qdecd_pat_n_vl6_s32: +** sqdecd x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl6_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqdecd_pat (x0, SV_VL6, 16)) + +/* +** qdecd_pat_n_vl7_s32: +** sqdecd x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl7_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqdecd_pat (x0, SV_VL7, 16)) + +/* +** qdecd_pat_n_vl8_s32: +** sqdecd x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl8_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqdecd_pat (x0, SV_VL8, 16)) + +/* +** qdecd_pat_n_vl16_s32: +** sqdecd x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl16_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqdecd_pat (x0, SV_VL16, 16)) + +/* +** qdecd_pat_n_vl32_s32: +** sqdecd x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl32_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqdecd_pat (x0, SV_VL32, 16)) + +/* +** qdecd_pat_n_vl64_s32: +** sqdecd x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl64_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqdecd_pat (x0, SV_VL64, 16)) + +/* +** qdecd_pat_n_vl128_s32: +** sqdecd x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl128_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqdecd_pat (x0, SV_VL128, 16)) + +/* +** qdecd_pat_n_vl256_s32: +** sqdecd x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl256_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqdecd_pat (x0, SV_VL256, 16)) + +/* +** qdecd_pat_n_mul4_s32: +** sqdecd x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul4_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqdecd_pat (x0, SV_MUL4, 16)) + +/* +** qdecd_pat_n_mul3_s32: +** sqdecd x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul3_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqdecd_pat (x0, SV_MUL3, 16)) + +/* +** qdecd_pat_n_all_s32: +** sqdecd x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_all_s32, int32_t, + x0 = svqdecd_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqdecd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s64.c new file mode 100644 index 00000000000..3970ff05828 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_s64.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_pat_1_s64_tied: +** sqdecd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_1_s64_tied, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_POW2, 1), + z0 = svqdecd_pat (z0, SV_POW2, 1)) + +/* +** qdecd_pat_1_s64_untied: +** movprfx z0, z1 +** sqdecd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_1_s64_untied, svint64_t, + z0 = svqdecd_pat_s64 (z1, SV_POW2, 1), + z0 = svqdecd_pat (z1, SV_POW2, 1)) + +/* +** qdecd_pat_2_s64: +** sqdecd z0\.d, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_2_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_POW2, 2), + z0 = svqdecd_pat (z0, SV_POW2, 2)) + +/* +** qdecd_pat_7_s64: +** sqdecd z0\.d, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_7_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_POW2, 7), + z0 = svqdecd_pat (z0, SV_POW2, 7)) + +/* +** qdecd_pat_15_s64: +** sqdecd z0\.d, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_15_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_POW2, 15), + z0 = svqdecd_pat (z0, SV_POW2, 15)) + +/* +** qdecd_pat_16_s64: +** sqdecd z0\.d, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_16_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_POW2, 16), + z0 = svqdecd_pat (z0, SV_POW2, 16)) + +/* +** qdecd_pat_vl1_s64: +** sqdecd z0\.d, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl1_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL1, 16), + z0 = svqdecd_pat (z0, SV_VL1, 16)) + +/* +** qdecd_pat_vl2_s64: +** sqdecd z0\.d, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl2_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL2, 16), + z0 = svqdecd_pat (z0, SV_VL2, 16)) + +/* +** qdecd_pat_vl3_s64: +** sqdecd z0\.d, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl3_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL3, 16), + z0 = svqdecd_pat (z0, SV_VL3, 16)) + +/* +** qdecd_pat_vl4_s64: +** sqdecd z0\.d, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl4_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL4, 16), + z0 = svqdecd_pat (z0, SV_VL4, 16)) + +/* +** qdecd_pat_vl5_s64: +** sqdecd z0\.d, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl5_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL5, 16), + z0 = svqdecd_pat (z0, SV_VL5, 16)) + +/* +** qdecd_pat_vl6_s64: +** sqdecd z0\.d, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl6_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL6, 16), + z0 = svqdecd_pat (z0, SV_VL6, 16)) + +/* +** qdecd_pat_vl7_s64: +** sqdecd z0\.d, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl7_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL7, 16), + z0 = svqdecd_pat (z0, SV_VL7, 16)) + +/* +** qdecd_pat_vl8_s64: +** sqdecd z0\.d, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl8_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL8, 16), + z0 = svqdecd_pat (z0, SV_VL8, 16)) + +/* +** qdecd_pat_vl16_s64: +** sqdecd z0\.d, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl16_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL16, 16), + z0 = svqdecd_pat (z0, SV_VL16, 16)) + +/* +** qdecd_pat_vl32_s64: +** sqdecd z0\.d, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl32_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL32, 16), + z0 = svqdecd_pat (z0, SV_VL32, 16)) + +/* +** qdecd_pat_vl64_s64: +** sqdecd z0\.d, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl64_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL64, 16), + z0 = svqdecd_pat (z0, SV_VL64, 16)) + +/* +** qdecd_pat_vl128_s64: +** sqdecd z0\.d, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl128_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL128, 16), + z0 = svqdecd_pat (z0, SV_VL128, 16)) + +/* +** qdecd_pat_vl256_s64: +** sqdecd z0\.d, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl256_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_VL256, 16), + z0 = svqdecd_pat (z0, SV_VL256, 16)) + +/* +** qdecd_pat_mul4_s64: +** sqdecd z0\.d, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_mul4_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_MUL4, 16), + z0 = svqdecd_pat (z0, SV_MUL4, 16)) + +/* +** qdecd_pat_mul3_s64: +** sqdecd z0\.d, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_mul3_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_MUL3, 16), + z0 = svqdecd_pat (z0, SV_MUL3, 16)) + +/* +** qdecd_pat_all_s64: +** sqdecd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_all_s64, svint64_t, + z0 = svqdecd_pat_s64 (z0, SV_ALL, 16), + z0 = svqdecd_pat (z0, SV_ALL, 16)) + +/* +** qdecd_pat_n_1_s64_tied: +** sqdecd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_s64_tied, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqdecd_pat (x0, SV_POW2, 1)) + +/* +** qdecd_pat_n_1_s64_untied: +** mov x0, x1 +** sqdecd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_s64_untied, int64_t, + x0 = svqdecd_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqdecd_pat (x1, SV_POW2, 1)) + +/* +** qdecd_pat_n_2_s64: +** sqdecd x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_2_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqdecd_pat (x0, SV_POW2, 2)) + +/* +** qdecd_pat_n_7_s64: +** sqdecd x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_7_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqdecd_pat (x0, SV_POW2, 7)) + +/* +** qdecd_pat_n_15_s64: +** sqdecd x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_15_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqdecd_pat (x0, SV_POW2, 15)) + +/* +** qdecd_pat_n_16_s64: +** sqdecd x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_16_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqdecd_pat (x0, SV_POW2, 16)) + +/* +** qdecd_pat_n_vl1_s64: +** sqdecd x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl1_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqdecd_pat (x0, SV_VL1, 16)) + +/* +** qdecd_pat_n_vl2_s64: +** sqdecd x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl2_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqdecd_pat (x0, SV_VL2, 16)) + +/* +** qdecd_pat_n_vl3_s64: +** sqdecd x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl3_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqdecd_pat (x0, SV_VL3, 16)) + +/* +** qdecd_pat_n_vl4_s64: +** sqdecd x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl4_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqdecd_pat (x0, SV_VL4, 16)) + +/* +** qdecd_pat_n_vl5_s64: +** sqdecd x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl5_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqdecd_pat (x0, SV_VL5, 16)) + +/* +** qdecd_pat_n_vl6_s64: +** sqdecd x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl6_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqdecd_pat (x0, SV_VL6, 16)) + +/* +** qdecd_pat_n_vl7_s64: +** sqdecd x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl7_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqdecd_pat (x0, SV_VL7, 16)) + +/* +** qdecd_pat_n_vl8_s64: +** sqdecd x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl8_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqdecd_pat (x0, SV_VL8, 16)) + +/* +** qdecd_pat_n_vl16_s64: +** sqdecd x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl16_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqdecd_pat (x0, SV_VL16, 16)) + +/* +** qdecd_pat_n_vl32_s64: +** sqdecd x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl32_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqdecd_pat (x0, SV_VL32, 16)) + +/* +** qdecd_pat_n_vl64_s64: +** sqdecd x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl64_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqdecd_pat (x0, SV_VL64, 16)) + +/* +** qdecd_pat_n_vl128_s64: +** sqdecd x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl128_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqdecd_pat (x0, SV_VL128, 16)) + +/* +** qdecd_pat_n_vl256_s64: +** sqdecd x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl256_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqdecd_pat (x0, SV_VL256, 16)) + +/* +** qdecd_pat_n_mul4_s64: +** sqdecd x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul4_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqdecd_pat (x0, SV_MUL4, 16)) + +/* +** qdecd_pat_n_mul3_s64: +** sqdecd x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul3_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqdecd_pat (x0, SV_MUL3, 16)) + +/* +** qdecd_pat_n_all_s64: +** sqdecd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_all_s64, int64_t, + x0 = svqdecd_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqdecd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u32.c new file mode 100644 index 00000000000..b33e402f294 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_pat_n_1_u32_tied: +** uqdecd w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_u32_tied, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqdecd_pat (x0, SV_POW2, 1)) + +/* +** qdecd_pat_n_1_u32_untied: +** mov w0, w1 +** uqdecd w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_u32_untied, uint32_t, + x0 = svqdecd_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqdecd_pat (x1, SV_POW2, 1)) + +/* +** qdecd_pat_n_2_u32: +** uqdecd w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_2_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqdecd_pat (x0, SV_POW2, 2)) + +/* +** qdecd_pat_n_7_u32: +** uqdecd w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_7_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqdecd_pat (x0, SV_POW2, 7)) + +/* +** qdecd_pat_n_15_u32: +** uqdecd w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_15_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqdecd_pat (x0, SV_POW2, 15)) + +/* +** qdecd_pat_n_16_u32: +** uqdecd w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_16_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqdecd_pat (x0, SV_POW2, 16)) + +/* +** qdecd_pat_n_vl1_u32: +** uqdecd w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl1_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqdecd_pat (x0, SV_VL1, 16)) + +/* +** qdecd_pat_n_vl2_u32: +** uqdecd w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl2_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqdecd_pat (x0, SV_VL2, 16)) + +/* +** qdecd_pat_n_vl3_u32: +** uqdecd w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl3_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqdecd_pat (x0, SV_VL3, 16)) + +/* +** qdecd_pat_n_vl4_u32: +** uqdecd w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl4_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqdecd_pat (x0, SV_VL4, 16)) + +/* +** qdecd_pat_n_vl5_u32: +** uqdecd w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl5_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqdecd_pat (x0, SV_VL5, 16)) + +/* +** qdecd_pat_n_vl6_u32: +** uqdecd w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl6_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqdecd_pat (x0, SV_VL6, 16)) + +/* +** qdecd_pat_n_vl7_u32: +** uqdecd w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl7_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqdecd_pat (x0, SV_VL7, 16)) + +/* +** qdecd_pat_n_vl8_u32: +** uqdecd w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl8_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqdecd_pat (x0, SV_VL8, 16)) + +/* +** qdecd_pat_n_vl16_u32: +** uqdecd w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl16_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqdecd_pat (x0, SV_VL16, 16)) + +/* +** qdecd_pat_n_vl32_u32: +** uqdecd w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl32_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqdecd_pat (x0, SV_VL32, 16)) + +/* +** qdecd_pat_n_vl64_u32: +** uqdecd w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl64_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqdecd_pat (x0, SV_VL64, 16)) + +/* +** qdecd_pat_n_vl128_u32: +** uqdecd w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl128_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqdecd_pat (x0, SV_VL128, 16)) + +/* +** qdecd_pat_n_vl256_u32: +** uqdecd w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl256_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqdecd_pat (x0, SV_VL256, 16)) + +/* +** qdecd_pat_n_mul4_u32: +** uqdecd w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul4_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqdecd_pat (x0, SV_MUL4, 16)) + +/* +** qdecd_pat_n_mul3_u32: +** uqdecd w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul3_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqdecd_pat (x0, SV_MUL3, 16)) + +/* +** qdecd_pat_n_all_u32: +** uqdecd w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_all_u32, uint32_t, + x0 = svqdecd_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqdecd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u64.c new file mode 100644 index 00000000000..f0d1bd35748 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_pat_u64.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_pat_1_u64_tied: +** uqdecd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_1_u64_tied, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_POW2, 1), + z0 = svqdecd_pat (z0, SV_POW2, 1)) + +/* +** qdecd_pat_1_u64_untied: +** movprfx z0, z1 +** uqdecd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_1_u64_untied, svuint64_t, + z0 = svqdecd_pat_u64 (z1, SV_POW2, 1), + z0 = svqdecd_pat (z1, SV_POW2, 1)) + +/* +** qdecd_pat_2_u64: +** uqdecd z0\.d, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_2_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_POW2, 2), + z0 = svqdecd_pat (z0, SV_POW2, 2)) + +/* +** qdecd_pat_7_u64: +** uqdecd z0\.d, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_7_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_POW2, 7), + z0 = svqdecd_pat (z0, SV_POW2, 7)) + +/* +** qdecd_pat_15_u64: +** uqdecd z0\.d, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_15_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_POW2, 15), + z0 = svqdecd_pat (z0, SV_POW2, 15)) + +/* +** qdecd_pat_16_u64: +** uqdecd z0\.d, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_16_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_POW2, 16), + z0 = svqdecd_pat (z0, SV_POW2, 16)) + +/* +** qdecd_pat_vl1_u64: +** uqdecd z0\.d, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl1_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL1, 16), + z0 = svqdecd_pat (z0, SV_VL1, 16)) + +/* +** qdecd_pat_vl2_u64: +** uqdecd z0\.d, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl2_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL2, 16), + z0 = svqdecd_pat (z0, SV_VL2, 16)) + +/* +** qdecd_pat_vl3_u64: +** uqdecd z0\.d, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl3_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL3, 16), + z0 = svqdecd_pat (z0, SV_VL3, 16)) + +/* +** qdecd_pat_vl4_u64: +** uqdecd z0\.d, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl4_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL4, 16), + z0 = svqdecd_pat (z0, SV_VL4, 16)) + +/* +** qdecd_pat_vl5_u64: +** uqdecd z0\.d, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl5_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL5, 16), + z0 = svqdecd_pat (z0, SV_VL5, 16)) + +/* +** qdecd_pat_vl6_u64: +** uqdecd z0\.d, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl6_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL6, 16), + z0 = svqdecd_pat (z0, SV_VL6, 16)) + +/* +** qdecd_pat_vl7_u64: +** uqdecd z0\.d, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl7_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL7, 16), + z0 = svqdecd_pat (z0, SV_VL7, 16)) + +/* +** qdecd_pat_vl8_u64: +** uqdecd z0\.d, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl8_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL8, 16), + z0 = svqdecd_pat (z0, SV_VL8, 16)) + +/* +** qdecd_pat_vl16_u64: +** uqdecd z0\.d, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl16_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL16, 16), + z0 = svqdecd_pat (z0, SV_VL16, 16)) + +/* +** qdecd_pat_vl32_u64: +** uqdecd z0\.d, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl32_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL32, 16), + z0 = svqdecd_pat (z0, SV_VL32, 16)) + +/* +** qdecd_pat_vl64_u64: +** uqdecd z0\.d, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl64_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL64, 16), + z0 = svqdecd_pat (z0, SV_VL64, 16)) + +/* +** qdecd_pat_vl128_u64: +** uqdecd z0\.d, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl128_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL128, 16), + z0 = svqdecd_pat (z0, SV_VL128, 16)) + +/* +** qdecd_pat_vl256_u64: +** uqdecd z0\.d, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_vl256_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_VL256, 16), + z0 = svqdecd_pat (z0, SV_VL256, 16)) + +/* +** qdecd_pat_mul4_u64: +** uqdecd z0\.d, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_mul4_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_MUL4, 16), + z0 = svqdecd_pat (z0, SV_MUL4, 16)) + +/* +** qdecd_pat_mul3_u64: +** uqdecd z0\.d, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_mul3_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_MUL3, 16), + z0 = svqdecd_pat (z0, SV_MUL3, 16)) + +/* +** qdecd_pat_all_u64: +** uqdecd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_pat_all_u64, svuint64_t, + z0 = svqdecd_pat_u64 (z0, SV_ALL, 16), + z0 = svqdecd_pat (z0, SV_ALL, 16)) + +/* +** qdecd_pat_n_1_u64_tied: +** uqdecd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_u64_tied, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqdecd_pat (x0, SV_POW2, 1)) + +/* +** qdecd_pat_n_1_u64_untied: +** mov x0, x1 +** uqdecd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_1_u64_untied, uint64_t, + x0 = svqdecd_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqdecd_pat (x1, SV_POW2, 1)) + +/* +** qdecd_pat_n_2_u64: +** uqdecd x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_2_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqdecd_pat (x0, SV_POW2, 2)) + +/* +** qdecd_pat_n_7_u64: +** uqdecd x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_7_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqdecd_pat (x0, SV_POW2, 7)) + +/* +** qdecd_pat_n_15_u64: +** uqdecd x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_15_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqdecd_pat (x0, SV_POW2, 15)) + +/* +** qdecd_pat_n_16_u64: +** uqdecd x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_16_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqdecd_pat (x0, SV_POW2, 16)) + +/* +** qdecd_pat_n_vl1_u64: +** uqdecd x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl1_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqdecd_pat (x0, SV_VL1, 16)) + +/* +** qdecd_pat_n_vl2_u64: +** uqdecd x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl2_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqdecd_pat (x0, SV_VL2, 16)) + +/* +** qdecd_pat_n_vl3_u64: +** uqdecd x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl3_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqdecd_pat (x0, SV_VL3, 16)) + +/* +** qdecd_pat_n_vl4_u64: +** uqdecd x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl4_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqdecd_pat (x0, SV_VL4, 16)) + +/* +** qdecd_pat_n_vl5_u64: +** uqdecd x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl5_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqdecd_pat (x0, SV_VL5, 16)) + +/* +** qdecd_pat_n_vl6_u64: +** uqdecd x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl6_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqdecd_pat (x0, SV_VL6, 16)) + +/* +** qdecd_pat_n_vl7_u64: +** uqdecd x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl7_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqdecd_pat (x0, SV_VL7, 16)) + +/* +** qdecd_pat_n_vl8_u64: +** uqdecd x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl8_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqdecd_pat (x0, SV_VL8, 16)) + +/* +** qdecd_pat_n_vl16_u64: +** uqdecd x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl16_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqdecd_pat (x0, SV_VL16, 16)) + +/* +** qdecd_pat_n_vl32_u64: +** uqdecd x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl32_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqdecd_pat (x0, SV_VL32, 16)) + +/* +** qdecd_pat_n_vl64_u64: +** uqdecd x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl64_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqdecd_pat (x0, SV_VL64, 16)) + +/* +** qdecd_pat_n_vl128_u64: +** uqdecd x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl128_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqdecd_pat (x0, SV_VL128, 16)) + +/* +** qdecd_pat_n_vl256_u64: +** uqdecd x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_vl256_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqdecd_pat (x0, SV_VL256, 16)) + +/* +** qdecd_pat_n_mul4_u64: +** uqdecd x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul4_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqdecd_pat (x0, SV_MUL4, 16)) + +/* +** qdecd_pat_n_mul3_u64: +** uqdecd x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_mul3_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqdecd_pat (x0, SV_MUL3, 16)) + +/* +** qdecd_pat_n_all_u64: +** uqdecd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_pat_n_all_u64, uint64_t, + x0 = svqdecd_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqdecd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s32.c new file mode 100644 index 00000000000..1912ed53f1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_n_1_s32_tied: +** sqdecd x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_s32_tied, int32_t, + x0 = svqdecd_n_s32 (x0, 1), + x0 = svqdecd (x0, 1)) + +/* +** qdecd_n_1_s32_untied: +** mov w0, w1 +** sqdecd x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_s32_untied, int32_t, + x0 = svqdecd_n_s32 (x1, 1), + x0 = svqdecd (x1, 1)) + +/* +** qdecd_n_2_s32: +** sqdecd x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_2_s32, int32_t, + x0 = svqdecd_n_s32 (x0, 2), + x0 = svqdecd (x0, 2)) + +/* +** qdecd_n_7_s32: +** sqdecd x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_7_s32, int32_t, + x0 = svqdecd_n_s32 (x0, 7), + x0 = svqdecd (x0, 7)) + +/* +** qdecd_n_15_s32: +** sqdecd x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_15_s32, int32_t, + x0 = svqdecd_n_s32 (x0, 15), + x0 = svqdecd (x0, 15)) + +/* +** qdecd_n_16_s32: +** sqdecd x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_16_s32, int32_t, + x0 = svqdecd_n_s32 (x0, 16), + x0 = svqdecd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s64.c new file mode 100644 index 00000000000..bd113fc66c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_s64.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_1_s64_tied: +** sqdecd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qdecd_1_s64_tied, svint64_t, + z0 = svqdecd_s64 (z0, 1), + z0 = svqdecd (z0, 1)) + +/* +** qdecd_1_s64_untied: +** movprfx z0, z1 +** sqdecd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qdecd_1_s64_untied, svint64_t, + z0 = svqdecd_s64 (z1, 1), + z0 = svqdecd (z1, 1)) + +/* +** qdecd_2_s64: +** sqdecd z0\.d, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_2_s64, svint64_t, + z0 = svqdecd_s64 (z0, 2), + z0 = svqdecd (z0, 2)) + +/* +** qdecd_7_s64: +** sqdecd z0\.d, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecd_7_s64, svint64_t, + z0 = svqdecd_s64 (z0, 7), + z0 = svqdecd (z0, 7)) + +/* +** qdecd_15_s64: +** sqdecd z0\.d, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecd_15_s64, svint64_t, + z0 = svqdecd_s64 (z0, 15), + z0 = svqdecd (z0, 15)) + +/* +** qdecd_16_s64: +** sqdecd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_16_s64, svint64_t, + z0 = svqdecd_s64 (z0, 16), + z0 = svqdecd (z0, 16)) + +/* +** qdecd_n_1_s64_tied: +** sqdecd x0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_s64_tied, int64_t, + x0 = svqdecd_n_s64 (x0, 1), + x0 = svqdecd (x0, 1)) + +/* +** qdecd_n_1_s64_untied: +** mov x0, x1 +** sqdecd x0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_s64_untied, int64_t, + x0 = svqdecd_n_s64 (x1, 1), + x0 = svqdecd (x1, 1)) + +/* +** qdecd_n_2_s64: +** sqdecd x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_2_s64, int64_t, + x0 = svqdecd_n_s64 (x0, 2), + x0 = svqdecd (x0, 2)) + +/* +** qdecd_n_7_s64: +** sqdecd x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_7_s64, int64_t, + x0 = svqdecd_n_s64 (x0, 7), + x0 = svqdecd (x0, 7)) + +/* +** qdecd_n_15_s64: +** sqdecd x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_15_s64, int64_t, + x0 = svqdecd_n_s64 (x0, 15), + x0 = svqdecd (x0, 15)) + +/* +** qdecd_n_16_s64: +** sqdecd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_16_s64, int64_t, + x0 = svqdecd_n_s64 (x0, 16), + x0 = svqdecd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u32.c new file mode 100644 index 00000000000..a672dc2156e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_n_1_u32_tied: +** uqdecd w0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_u32_tied, uint32_t, + x0 = svqdecd_n_u32 (x0, 1), + x0 = svqdecd (x0, 1)) + +/* +** qdecd_n_1_u32_untied: +** mov w0, w1 +** uqdecd w0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_u32_untied, uint32_t, + x0 = svqdecd_n_u32 (x1, 1), + x0 = svqdecd (x1, 1)) + +/* +** qdecd_n_2_u32: +** uqdecd w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_2_u32, uint32_t, + x0 = svqdecd_n_u32 (x0, 2), + x0 = svqdecd (x0, 2)) + +/* +** qdecd_n_7_u32: +** uqdecd w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_7_u32, uint32_t, + x0 = svqdecd_n_u32 (x0, 7), + x0 = svqdecd (x0, 7)) + +/* +** qdecd_n_15_u32: +** uqdecd w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_15_u32, uint32_t, + x0 = svqdecd_n_u32 (x0, 15), + x0 = svqdecd (x0, 15)) + +/* +** qdecd_n_16_u32: +** uqdecd w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_16_u32, uint32_t, + x0 = svqdecd_n_u32 (x0, 16), + x0 = svqdecd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u64.c new file mode 100644 index 00000000000..fca8868f33a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecd_u64.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecd_1_u64_tied: +** uqdecd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qdecd_1_u64_tied, svuint64_t, + z0 = svqdecd_u64 (z0, 1), + z0 = svqdecd (z0, 1)) + +/* +** qdecd_1_u64_untied: +** movprfx z0, z1 +** uqdecd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qdecd_1_u64_untied, svuint64_t, + z0 = svqdecd_u64 (z1, 1), + z0 = svqdecd (z1, 1)) + +/* +** qdecd_2_u64: +** uqdecd z0\.d, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecd_2_u64, svuint64_t, + z0 = svqdecd_u64 (z0, 2), + z0 = svqdecd (z0, 2)) + +/* +** qdecd_7_u64: +** uqdecd z0\.d, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecd_7_u64, svuint64_t, + z0 = svqdecd_u64 (z0, 7), + z0 = svqdecd (z0, 7)) + +/* +** qdecd_15_u64: +** uqdecd z0\.d, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecd_15_u64, svuint64_t, + z0 = svqdecd_u64 (z0, 15), + z0 = svqdecd (z0, 15)) + +/* +** qdecd_16_u64: +** uqdecd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecd_16_u64, svuint64_t, + z0 = svqdecd_u64 (z0, 16), + z0 = svqdecd (z0, 16)) + +/* +** qdecd_n_1_u64_tied: +** uqdecd x0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_u64_tied, uint64_t, + x0 = svqdecd_n_u64 (x0, 1), + x0 = svqdecd (x0, 1)) + +/* +** qdecd_n_1_u64_untied: +** mov x0, x1 +** uqdecd x0 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_1_u64_untied, uint64_t, + x0 = svqdecd_n_u64 (x1, 1), + x0 = svqdecd (x1, 1)) + +/* +** qdecd_n_2_u64: +** uqdecd x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_2_u64, uint64_t, + x0 = svqdecd_n_u64 (x0, 2), + x0 = svqdecd (x0, 2)) + +/* +** qdecd_n_7_u64: +** uqdecd x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_7_u64, uint64_t, + x0 = svqdecd_n_u64 (x0, 7), + x0 = svqdecd (x0, 7)) + +/* +** qdecd_n_15_u64: +** uqdecd x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_15_u64, uint64_t, + x0 = svqdecd_n_u64 (x0, 15), + x0 = svqdecd (x0, 15)) + +/* +** qdecd_n_16_u64: +** uqdecd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecd_n_16_u64, uint64_t, + x0 = svqdecd_n_u64 (x0, 16), + x0 = svqdecd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s16.c new file mode 100644 index 00000000000..c084043f189 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s16.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_1_s16_tied: +** sqdech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_1_s16_tied, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_POW2, 1), + z0 = svqdech_pat (z0, SV_POW2, 1)) + +/* +** qdech_pat_1_s16_untied: +** movprfx z0, z1 +** sqdech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_1_s16_untied, svint16_t, + z0 = svqdech_pat_s16 (z1, SV_POW2, 1), + z0 = svqdech_pat (z1, SV_POW2, 1)) + +/* +** qdech_pat_2_s16: +** sqdech z0\.h, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_2_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_POW2, 2), + z0 = svqdech_pat (z0, SV_POW2, 2)) + +/* +** qdech_pat_7_s16: +** sqdech z0\.h, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_7_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_POW2, 7), + z0 = svqdech_pat (z0, SV_POW2, 7)) + +/* +** qdech_pat_15_s16: +** sqdech z0\.h, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_15_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_POW2, 15), + z0 = svqdech_pat (z0, SV_POW2, 15)) + +/* +** qdech_pat_16_s16: +** sqdech z0\.h, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_16_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_POW2, 16), + z0 = svqdech_pat (z0, SV_POW2, 16)) + +/* +** qdech_pat_vl1_s16: +** sqdech z0\.h, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl1_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL1, 16), + z0 = svqdech_pat (z0, SV_VL1, 16)) + +/* +** qdech_pat_vl2_s16: +** sqdech z0\.h, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl2_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL2, 16), + z0 = svqdech_pat (z0, SV_VL2, 16)) + +/* +** qdech_pat_vl3_s16: +** sqdech z0\.h, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl3_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL3, 16), + z0 = svqdech_pat (z0, SV_VL3, 16)) + +/* +** qdech_pat_vl4_s16: +** sqdech z0\.h, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl4_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL4, 16), + z0 = svqdech_pat (z0, SV_VL4, 16)) + +/* +** qdech_pat_vl5_s16: +** sqdech z0\.h, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl5_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL5, 16), + z0 = svqdech_pat (z0, SV_VL5, 16)) + +/* +** qdech_pat_vl6_s16: +** sqdech z0\.h, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl6_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL6, 16), + z0 = svqdech_pat (z0, SV_VL6, 16)) + +/* +** qdech_pat_vl7_s16: +** sqdech z0\.h, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl7_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL7, 16), + z0 = svqdech_pat (z0, SV_VL7, 16)) + +/* +** qdech_pat_vl8_s16: +** sqdech z0\.h, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl8_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL8, 16), + z0 = svqdech_pat (z0, SV_VL8, 16)) + +/* +** qdech_pat_vl16_s16: +** sqdech z0\.h, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl16_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL16, 16), + z0 = svqdech_pat (z0, SV_VL16, 16)) + +/* +** qdech_pat_vl32_s16: +** sqdech z0\.h, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl32_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL32, 16), + z0 = svqdech_pat (z0, SV_VL32, 16)) + +/* +** qdech_pat_vl64_s16: +** sqdech z0\.h, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl64_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL64, 16), + z0 = svqdech_pat (z0, SV_VL64, 16)) + +/* +** qdech_pat_vl128_s16: +** sqdech z0\.h, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl128_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL128, 16), + z0 = svqdech_pat (z0, SV_VL128, 16)) + +/* +** qdech_pat_vl256_s16: +** sqdech z0\.h, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl256_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_VL256, 16), + z0 = svqdech_pat (z0, SV_VL256, 16)) + +/* +** qdech_pat_mul4_s16: +** sqdech z0\.h, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_mul4_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_MUL4, 16), + z0 = svqdech_pat (z0, SV_MUL4, 16)) + +/* +** qdech_pat_mul3_s16: +** sqdech z0\.h, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_mul3_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_MUL3, 16), + z0 = svqdech_pat (z0, SV_MUL3, 16)) + +/* +** qdech_pat_all_s16: +** sqdech z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_all_s16, svint16_t, + z0 = svqdech_pat_s16 (z0, SV_ALL, 16), + z0 = svqdech_pat (z0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s32.c new file mode 100644 index 00000000000..b56306db734 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_n_1_s32_tied: +** sqdech x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_s32_tied, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqdech_pat (x0, SV_POW2, 1)) + +/* +** qdech_pat_n_1_s32_untied: +** mov w0, w1 +** sqdech x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_s32_untied, int32_t, + x0 = svqdech_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqdech_pat (x1, SV_POW2, 1)) + +/* +** qdech_pat_n_2_s32: +** sqdech x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_2_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqdech_pat (x0, SV_POW2, 2)) + +/* +** qdech_pat_n_7_s32: +** sqdech x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_7_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqdech_pat (x0, SV_POW2, 7)) + +/* +** qdech_pat_n_15_s32: +** sqdech x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_15_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqdech_pat (x0, SV_POW2, 15)) + +/* +** qdech_pat_n_16_s32: +** sqdech x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_16_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqdech_pat (x0, SV_POW2, 16)) + +/* +** qdech_pat_n_vl1_s32: +** sqdech x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl1_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqdech_pat (x0, SV_VL1, 16)) + +/* +** qdech_pat_n_vl2_s32: +** sqdech x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl2_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqdech_pat (x0, SV_VL2, 16)) + +/* +** qdech_pat_n_vl3_s32: +** sqdech x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl3_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqdech_pat (x0, SV_VL3, 16)) + +/* +** qdech_pat_n_vl4_s32: +** sqdech x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl4_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqdech_pat (x0, SV_VL4, 16)) + +/* +** qdech_pat_n_vl5_s32: +** sqdech x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl5_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqdech_pat (x0, SV_VL5, 16)) + +/* +** qdech_pat_n_vl6_s32: +** sqdech x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl6_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqdech_pat (x0, SV_VL6, 16)) + +/* +** qdech_pat_n_vl7_s32: +** sqdech x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl7_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqdech_pat (x0, SV_VL7, 16)) + +/* +** qdech_pat_n_vl8_s32: +** sqdech x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl8_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqdech_pat (x0, SV_VL8, 16)) + +/* +** qdech_pat_n_vl16_s32: +** sqdech x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl16_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqdech_pat (x0, SV_VL16, 16)) + +/* +** qdech_pat_n_vl32_s32: +** sqdech x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl32_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqdech_pat (x0, SV_VL32, 16)) + +/* +** qdech_pat_n_vl64_s32: +** sqdech x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl64_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqdech_pat (x0, SV_VL64, 16)) + +/* +** qdech_pat_n_vl128_s32: +** sqdech x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl128_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqdech_pat (x0, SV_VL128, 16)) + +/* +** qdech_pat_n_vl256_s32: +** sqdech x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl256_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqdech_pat (x0, SV_VL256, 16)) + +/* +** qdech_pat_n_mul4_s32: +** sqdech x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul4_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqdech_pat (x0, SV_MUL4, 16)) + +/* +** qdech_pat_n_mul3_s32: +** sqdech x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul3_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqdech_pat (x0, SV_MUL3, 16)) + +/* +** qdech_pat_n_all_s32: +** sqdech x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_all_s32, int32_t, + x0 = svqdech_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqdech_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s64.c new file mode 100644 index 00000000000..591658f5452 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_n_1_s64_tied: +** sqdech x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_s64_tied, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqdech_pat (x0, SV_POW2, 1)) + +/* +** qdech_pat_n_1_s64_untied: +** mov x0, x1 +** sqdech x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_s64_untied, int64_t, + x0 = svqdech_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqdech_pat (x1, SV_POW2, 1)) + +/* +** qdech_pat_n_2_s64: +** sqdech x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_2_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqdech_pat (x0, SV_POW2, 2)) + +/* +** qdech_pat_n_7_s64: +** sqdech x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_7_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqdech_pat (x0, SV_POW2, 7)) + +/* +** qdech_pat_n_15_s64: +** sqdech x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_15_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqdech_pat (x0, SV_POW2, 15)) + +/* +** qdech_pat_n_16_s64: +** sqdech x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_16_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqdech_pat (x0, SV_POW2, 16)) + +/* +** qdech_pat_n_vl1_s64: +** sqdech x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl1_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqdech_pat (x0, SV_VL1, 16)) + +/* +** qdech_pat_n_vl2_s64: +** sqdech x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl2_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqdech_pat (x0, SV_VL2, 16)) + +/* +** qdech_pat_n_vl3_s64: +** sqdech x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl3_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqdech_pat (x0, SV_VL3, 16)) + +/* +** qdech_pat_n_vl4_s64: +** sqdech x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl4_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqdech_pat (x0, SV_VL4, 16)) + +/* +** qdech_pat_n_vl5_s64: +** sqdech x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl5_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqdech_pat (x0, SV_VL5, 16)) + +/* +** qdech_pat_n_vl6_s64: +** sqdech x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl6_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqdech_pat (x0, SV_VL6, 16)) + +/* +** qdech_pat_n_vl7_s64: +** sqdech x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl7_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqdech_pat (x0, SV_VL7, 16)) + +/* +** qdech_pat_n_vl8_s64: +** sqdech x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl8_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqdech_pat (x0, SV_VL8, 16)) + +/* +** qdech_pat_n_vl16_s64: +** sqdech x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl16_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqdech_pat (x0, SV_VL16, 16)) + +/* +** qdech_pat_n_vl32_s64: +** sqdech x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl32_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqdech_pat (x0, SV_VL32, 16)) + +/* +** qdech_pat_n_vl64_s64: +** sqdech x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl64_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqdech_pat (x0, SV_VL64, 16)) + +/* +** qdech_pat_n_vl128_s64: +** sqdech x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl128_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqdech_pat (x0, SV_VL128, 16)) + +/* +** qdech_pat_n_vl256_s64: +** sqdech x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl256_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqdech_pat (x0, SV_VL256, 16)) + +/* +** qdech_pat_n_mul4_s64: +** sqdech x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul4_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqdech_pat (x0, SV_MUL4, 16)) + +/* +** qdech_pat_n_mul3_s64: +** sqdech x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul3_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqdech_pat (x0, SV_MUL3, 16)) + +/* +** qdech_pat_n_all_s64: +** sqdech x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_all_s64, int64_t, + x0 = svqdech_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqdech_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u16.c new file mode 100644 index 00000000000..ce0b5f3e8dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u16.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_1_u16_tied: +** uqdech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_1_u16_tied, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_POW2, 1), + z0 = svqdech_pat (z0, SV_POW2, 1)) + +/* +** qdech_pat_1_u16_untied: +** movprfx z0, z1 +** uqdech z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_1_u16_untied, svuint16_t, + z0 = svqdech_pat_u16 (z1, SV_POW2, 1), + z0 = svqdech_pat (z1, SV_POW2, 1)) + +/* +** qdech_pat_2_u16: +** uqdech z0\.h, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_2_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_POW2, 2), + z0 = svqdech_pat (z0, SV_POW2, 2)) + +/* +** qdech_pat_7_u16: +** uqdech z0\.h, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_7_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_POW2, 7), + z0 = svqdech_pat (z0, SV_POW2, 7)) + +/* +** qdech_pat_15_u16: +** uqdech z0\.h, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_15_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_POW2, 15), + z0 = svqdech_pat (z0, SV_POW2, 15)) + +/* +** qdech_pat_16_u16: +** uqdech z0\.h, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_16_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_POW2, 16), + z0 = svqdech_pat (z0, SV_POW2, 16)) + +/* +** qdech_pat_vl1_u16: +** uqdech z0\.h, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl1_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL1, 16), + z0 = svqdech_pat (z0, SV_VL1, 16)) + +/* +** qdech_pat_vl2_u16: +** uqdech z0\.h, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl2_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL2, 16), + z0 = svqdech_pat (z0, SV_VL2, 16)) + +/* +** qdech_pat_vl3_u16: +** uqdech z0\.h, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl3_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL3, 16), + z0 = svqdech_pat (z0, SV_VL3, 16)) + +/* +** qdech_pat_vl4_u16: +** uqdech z0\.h, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl4_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL4, 16), + z0 = svqdech_pat (z0, SV_VL4, 16)) + +/* +** qdech_pat_vl5_u16: +** uqdech z0\.h, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl5_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL5, 16), + z0 = svqdech_pat (z0, SV_VL5, 16)) + +/* +** qdech_pat_vl6_u16: +** uqdech z0\.h, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl6_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL6, 16), + z0 = svqdech_pat (z0, SV_VL6, 16)) + +/* +** qdech_pat_vl7_u16: +** uqdech z0\.h, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl7_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL7, 16), + z0 = svqdech_pat (z0, SV_VL7, 16)) + +/* +** qdech_pat_vl8_u16: +** uqdech z0\.h, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl8_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL8, 16), + z0 = svqdech_pat (z0, SV_VL8, 16)) + +/* +** qdech_pat_vl16_u16: +** uqdech z0\.h, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl16_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL16, 16), + z0 = svqdech_pat (z0, SV_VL16, 16)) + +/* +** qdech_pat_vl32_u16: +** uqdech z0\.h, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl32_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL32, 16), + z0 = svqdech_pat (z0, SV_VL32, 16)) + +/* +** qdech_pat_vl64_u16: +** uqdech z0\.h, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl64_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL64, 16), + z0 = svqdech_pat (z0, SV_VL64, 16)) + +/* +** qdech_pat_vl128_u16: +** uqdech z0\.h, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl128_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL128, 16), + z0 = svqdech_pat (z0, SV_VL128, 16)) + +/* +** qdech_pat_vl256_u16: +** uqdech z0\.h, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_vl256_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_VL256, 16), + z0 = svqdech_pat (z0, SV_VL256, 16)) + +/* +** qdech_pat_mul4_u16: +** uqdech z0\.h, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_mul4_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_MUL4, 16), + z0 = svqdech_pat (z0, SV_MUL4, 16)) + +/* +** qdech_pat_mul3_u16: +** uqdech z0\.h, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_mul3_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_MUL3, 16), + z0 = svqdech_pat (z0, SV_MUL3, 16)) + +/* +** qdech_pat_all_u16: +** uqdech z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_pat_all_u16, svuint16_t, + z0 = svqdech_pat_u16 (z0, SV_ALL, 16), + z0 = svqdech_pat (z0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u32.c new file mode 100644 index 00000000000..177f32ec754 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_n_1_u32_tied: +** uqdech w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_u32_tied, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqdech_pat (x0, SV_POW2, 1)) + +/* +** qdech_pat_n_1_u32_untied: +** mov w0, w1 +** uqdech w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_u32_untied, uint32_t, + x0 = svqdech_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqdech_pat (x1, SV_POW2, 1)) + +/* +** qdech_pat_n_2_u32: +** uqdech w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_2_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqdech_pat (x0, SV_POW2, 2)) + +/* +** qdech_pat_n_7_u32: +** uqdech w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_7_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqdech_pat (x0, SV_POW2, 7)) + +/* +** qdech_pat_n_15_u32: +** uqdech w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_15_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqdech_pat (x0, SV_POW2, 15)) + +/* +** qdech_pat_n_16_u32: +** uqdech w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_16_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqdech_pat (x0, SV_POW2, 16)) + +/* +** qdech_pat_n_vl1_u32: +** uqdech w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl1_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqdech_pat (x0, SV_VL1, 16)) + +/* +** qdech_pat_n_vl2_u32: +** uqdech w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl2_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqdech_pat (x0, SV_VL2, 16)) + +/* +** qdech_pat_n_vl3_u32: +** uqdech w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl3_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqdech_pat (x0, SV_VL3, 16)) + +/* +** qdech_pat_n_vl4_u32: +** uqdech w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl4_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqdech_pat (x0, SV_VL4, 16)) + +/* +** qdech_pat_n_vl5_u32: +** uqdech w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl5_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqdech_pat (x0, SV_VL5, 16)) + +/* +** qdech_pat_n_vl6_u32: +** uqdech w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl6_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqdech_pat (x0, SV_VL6, 16)) + +/* +** qdech_pat_n_vl7_u32: +** uqdech w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl7_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqdech_pat (x0, SV_VL7, 16)) + +/* +** qdech_pat_n_vl8_u32: +** uqdech w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl8_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqdech_pat (x0, SV_VL8, 16)) + +/* +** qdech_pat_n_vl16_u32: +** uqdech w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl16_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqdech_pat (x0, SV_VL16, 16)) + +/* +** qdech_pat_n_vl32_u32: +** uqdech w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl32_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqdech_pat (x0, SV_VL32, 16)) + +/* +** qdech_pat_n_vl64_u32: +** uqdech w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl64_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqdech_pat (x0, SV_VL64, 16)) + +/* +** qdech_pat_n_vl128_u32: +** uqdech w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl128_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqdech_pat (x0, SV_VL128, 16)) + +/* +** qdech_pat_n_vl256_u32: +** uqdech w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl256_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqdech_pat (x0, SV_VL256, 16)) + +/* +** qdech_pat_n_mul4_u32: +** uqdech w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul4_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqdech_pat (x0, SV_MUL4, 16)) + +/* +** qdech_pat_n_mul3_u32: +** uqdech w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul3_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqdech_pat (x0, SV_MUL3, 16)) + +/* +** qdech_pat_n_all_u32: +** uqdech w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_all_u32, uint32_t, + x0 = svqdech_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqdech_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u64.c new file mode 100644 index 00000000000..7092127f272 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_pat_n_1_u64_tied: +** uqdech x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_u64_tied, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqdech_pat (x0, SV_POW2, 1)) + +/* +** qdech_pat_n_1_u64_untied: +** mov x0, x1 +** uqdech x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_1_u64_untied, uint64_t, + x0 = svqdech_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqdech_pat (x1, SV_POW2, 1)) + +/* +** qdech_pat_n_2_u64: +** uqdech x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_2_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqdech_pat (x0, SV_POW2, 2)) + +/* +** qdech_pat_n_7_u64: +** uqdech x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_7_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqdech_pat (x0, SV_POW2, 7)) + +/* +** qdech_pat_n_15_u64: +** uqdech x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_15_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqdech_pat (x0, SV_POW2, 15)) + +/* +** qdech_pat_n_16_u64: +** uqdech x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_16_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqdech_pat (x0, SV_POW2, 16)) + +/* +** qdech_pat_n_vl1_u64: +** uqdech x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl1_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqdech_pat (x0, SV_VL1, 16)) + +/* +** qdech_pat_n_vl2_u64: +** uqdech x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl2_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqdech_pat (x0, SV_VL2, 16)) + +/* +** qdech_pat_n_vl3_u64: +** uqdech x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl3_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqdech_pat (x0, SV_VL3, 16)) + +/* +** qdech_pat_n_vl4_u64: +** uqdech x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl4_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqdech_pat (x0, SV_VL4, 16)) + +/* +** qdech_pat_n_vl5_u64: +** uqdech x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl5_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqdech_pat (x0, SV_VL5, 16)) + +/* +** qdech_pat_n_vl6_u64: +** uqdech x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl6_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqdech_pat (x0, SV_VL6, 16)) + +/* +** qdech_pat_n_vl7_u64: +** uqdech x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl7_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqdech_pat (x0, SV_VL7, 16)) + +/* +** qdech_pat_n_vl8_u64: +** uqdech x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl8_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqdech_pat (x0, SV_VL8, 16)) + +/* +** qdech_pat_n_vl16_u64: +** uqdech x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl16_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqdech_pat (x0, SV_VL16, 16)) + +/* +** qdech_pat_n_vl32_u64: +** uqdech x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl32_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqdech_pat (x0, SV_VL32, 16)) + +/* +** qdech_pat_n_vl64_u64: +** uqdech x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl64_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqdech_pat (x0, SV_VL64, 16)) + +/* +** qdech_pat_n_vl128_u64: +** uqdech x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl128_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqdech_pat (x0, SV_VL128, 16)) + +/* +** qdech_pat_n_vl256_u64: +** uqdech x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_vl256_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqdech_pat (x0, SV_VL256, 16)) + +/* +** qdech_pat_n_mul4_u64: +** uqdech x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul4_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqdech_pat (x0, SV_MUL4, 16)) + +/* +** qdech_pat_n_mul3_u64: +** uqdech x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_mul3_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqdech_pat (x0, SV_MUL3, 16)) + +/* +** qdech_pat_n_all_u64: +** uqdech x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_pat_n_all_u64, uint64_t, + x0 = svqdech_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqdech_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s16.c new file mode 100644 index 00000000000..2a7a8f7a6f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s16.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_1_s16_tied: +** sqdech z0\.h +** ret +*/ +TEST_UNIFORM_Z (qdech_1_s16_tied, svint16_t, + z0 = svqdech_s16 (z0, 1), + z0 = svqdech (z0, 1)) + +/* +** qdech_1_s16_untied: +** movprfx z0, z1 +** sqdech z0\.h +** ret +*/ +TEST_UNIFORM_Z (qdech_1_s16_untied, svint16_t, + z0 = svqdech_s16 (z1, 1), + z0 = svqdech (z1, 1)) + +/* +** qdech_2_s16: +** sqdech z0\.h, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdech_2_s16, svint16_t, + z0 = svqdech_s16 (z0, 2), + z0 = svqdech (z0, 2)) + +/* +** qdech_7_s16: +** sqdech z0\.h, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdech_7_s16, svint16_t, + z0 = svqdech_s16 (z0, 7), + z0 = svqdech (z0, 7)) + +/* +** qdech_15_s16: +** sqdech z0\.h, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdech_15_s16, svint16_t, + z0 = svqdech_s16 (z0, 15), + z0 = svqdech (z0, 15)) + +/* +** qdech_16_s16: +** sqdech z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_16_s16, svint16_t, + z0 = svqdech_s16 (z0, 16), + z0 = svqdech (z0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s32.c new file mode 100644 index 00000000000..7fd57d85a1d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_n_1_s32_tied: +** sqdech x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_s32_tied, int32_t, + x0 = svqdech_n_s32 (x0, 1), + x0 = svqdech (x0, 1)) + +/* +** qdech_n_1_s32_untied: +** mov w0, w1 +** sqdech x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_s32_untied, int32_t, + x0 = svqdech_n_s32 (x1, 1), + x0 = svqdech (x1, 1)) + +/* +** qdech_n_2_s32: +** sqdech x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_n_2_s32, int32_t, + x0 = svqdech_n_s32 (x0, 2), + x0 = svqdech (x0, 2)) + +/* +** qdech_n_7_s32: +** sqdech x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_n_7_s32, int32_t, + x0 = svqdech_n_s32 (x0, 7), + x0 = svqdech (x0, 7)) + +/* +** qdech_n_15_s32: +** sqdech x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_n_15_s32, int32_t, + x0 = svqdech_n_s32 (x0, 15), + x0 = svqdech (x0, 15)) + +/* +** qdech_n_16_s32: +** sqdech x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_n_16_s32, int32_t, + x0 = svqdech_n_s32 (x0, 16), + x0 = svqdech (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s64.c new file mode 100644 index 00000000000..61989f8d607 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_n_1_s64_tied: +** sqdech x0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_s64_tied, int64_t, + x0 = svqdech_n_s64 (x0, 1), + x0 = svqdech (x0, 1)) + +/* +** qdech_n_1_s64_untied: +** mov x0, x1 +** sqdech x0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_s64_untied, int64_t, + x0 = svqdech_n_s64 (x1, 1), + x0 = svqdech (x1, 1)) + +/* +** qdech_n_2_s64: +** sqdech x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_n_2_s64, int64_t, + x0 = svqdech_n_s64 (x0, 2), + x0 = svqdech (x0, 2)) + +/* +** qdech_n_7_s64: +** sqdech x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_n_7_s64, int64_t, + x0 = svqdech_n_s64 (x0, 7), + x0 = svqdech (x0, 7)) + +/* +** qdech_n_15_s64: +** sqdech x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_n_15_s64, int64_t, + x0 = svqdech_n_s64 (x0, 15), + x0 = svqdech (x0, 15)) + +/* +** qdech_n_16_s64: +** sqdech x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_n_16_s64, int64_t, + x0 = svqdech_n_s64 (x0, 16), + x0 = svqdech (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u16.c new file mode 100644 index 00000000000..0d6587851c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u16.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_1_u16_tied: +** uqdech z0\.h +** ret +*/ +TEST_UNIFORM_Z (qdech_1_u16_tied, svuint16_t, + z0 = svqdech_u16 (z0, 1), + z0 = svqdech (z0, 1)) + +/* +** qdech_1_u16_untied: +** movprfx z0, z1 +** uqdech z0\.h +** ret +*/ +TEST_UNIFORM_Z (qdech_1_u16_untied, svuint16_t, + z0 = svqdech_u16 (z1, 1), + z0 = svqdech (z1, 1)) + +/* +** qdech_2_u16: +** uqdech z0\.h, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdech_2_u16, svuint16_t, + z0 = svqdech_u16 (z0, 2), + z0 = svqdech (z0, 2)) + +/* +** qdech_7_u16: +** uqdech z0\.h, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdech_7_u16, svuint16_t, + z0 = svqdech_u16 (z0, 7), + z0 = svqdech (z0, 7)) + +/* +** qdech_15_u16: +** uqdech z0\.h, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdech_15_u16, svuint16_t, + z0 = svqdech_u16 (z0, 15), + z0 = svqdech (z0, 15)) + +/* +** qdech_16_u16: +** uqdech z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdech_16_u16, svuint16_t, + z0 = svqdech_u16 (z0, 16), + z0 = svqdech (z0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u32.c new file mode 100644 index 00000000000..179d6795322 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_n_1_u32_tied: +** uqdech w0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_u32_tied, uint32_t, + x0 = svqdech_n_u32 (x0, 1), + x0 = svqdech (x0, 1)) + +/* +** qdech_n_1_u32_untied: +** mov w0, w1 +** uqdech w0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_u32_untied, uint32_t, + x0 = svqdech_n_u32 (x1, 1), + x0 = svqdech (x1, 1)) + +/* +** qdech_n_2_u32: +** uqdech w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_n_2_u32, uint32_t, + x0 = svqdech_n_u32 (x0, 2), + x0 = svqdech (x0, 2)) + +/* +** qdech_n_7_u32: +** uqdech w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_n_7_u32, uint32_t, + x0 = svqdech_n_u32 (x0, 7), + x0 = svqdech (x0, 7)) + +/* +** qdech_n_15_u32: +** uqdech w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_n_15_u32, uint32_t, + x0 = svqdech_n_u32 (x0, 15), + x0 = svqdech (x0, 15)) + +/* +** qdech_n_16_u32: +** uqdech w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_n_16_u32, uint32_t, + x0 = svqdech_n_u32 (x0, 16), + x0 = svqdech (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u64.c new file mode 100644 index 00000000000..da2f051af6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdech_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdech_n_1_u64_tied: +** uqdech x0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_u64_tied, uint64_t, + x0 = svqdech_n_u64 (x0, 1), + x0 = svqdech (x0, 1)) + +/* +** qdech_n_1_u64_untied: +** mov x0, x1 +** uqdech x0 +** ret +*/ +TEST_UNIFORM_S (qdech_n_1_u64_untied, uint64_t, + x0 = svqdech_n_u64 (x1, 1), + x0 = svqdech (x1, 1)) + +/* +** qdech_n_2_u64: +** uqdech x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdech_n_2_u64, uint64_t, + x0 = svqdech_n_u64 (x0, 2), + x0 = svqdech (x0, 2)) + +/* +** qdech_n_7_u64: +** uqdech x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdech_n_7_u64, uint64_t, + x0 = svqdech_n_u64 (x0, 7), + x0 = svqdech (x0, 7)) + +/* +** qdech_n_15_u64: +** uqdech x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdech_n_15_u64, uint64_t, + x0 = svqdech_n_u64 (x0, 15), + x0 = svqdech (x0, 15)) + +/* +** qdech_n_16_u64: +** uqdech x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdech_n_16_u64, uint64_t, + x0 = svqdech_n_u64 (x0, 16), + x0 = svqdech (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s16.c new file mode 100644 index 00000000000..71b40c15240 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_s16_tied: +** sqdecp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s16_tied, svint16_t, + z0 = svqdecp_s16 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_s16_untied: +** movprfx z0, z1 +** sqdecp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s16_untied, svint16_t, + z0 = svqdecp_s16 (z1, p0), + z0 = svqdecp (z1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s32.c new file mode 100644 index 00000000000..55e4067d164 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s32.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_s32_tied: +** sqdecp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s32_tied, svint32_t, + z0 = svqdecp_s32 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_s32_untied: +** movprfx z0, z1 +** sqdecp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s32_untied, svint32_t, + z0 = svqdecp_s32 (z1, p0), + z0 = svqdecp (z1, p0)) + +/* +** qdecp_n_s32_b8_tied: +** sqdecp x0, p0\.b, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b8_tied, int32_t, + x0 = svqdecp_n_s32_b8 (x0, p0), + x0 = svqdecp_b8 (x0, p0)) + +/* +** qdecp_n_s32_b8_untied: +** mov w0, w1 +** sqdecp x0, p0\.b, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b8_untied, int32_t, + x0 = svqdecp_n_s32_b8 (x1, p0), + x0 = svqdecp_b8 (x1, p0)) + +/* +** qdecp_n_s32_b16_tied: +** sqdecp x0, p0\.h, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b16_tied, int32_t, + x0 = svqdecp_n_s32_b16 (x0, p0), + x0 = svqdecp_b16 (x0, p0)) + +/* +** qdecp_n_s32_b16_untied: +** mov w0, w1 +** sqdecp x0, p0\.h, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b16_untied, int32_t, + x0 = svqdecp_n_s32_b16 (x1, p0), + x0 = svqdecp_b16 (x1, p0)) + +/* +** qdecp_n_s32_b32_tied: +** sqdecp x0, p0\.s, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b32_tied, int32_t, + x0 = svqdecp_n_s32_b32 (x0, p0), + x0 = svqdecp_b32 (x0, p0)) + +/* +** qdecp_n_s32_b32_untied: +** mov w0, w1 +** sqdecp x0, p0\.s, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b32_untied, int32_t, + x0 = svqdecp_n_s32_b32 (x1, p0), + x0 = svqdecp_b32 (x1, p0)) + +/* +** qdecp_n_s32_b64_tied: +** sqdecp x0, p0\.d, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b64_tied, int32_t, + x0 = svqdecp_n_s32_b64 (x0, p0), + x0 = svqdecp_b64 (x0, p0)) + +/* +** qdecp_n_s32_b64_untied: +** mov w0, w1 +** sqdecp x0, p0\.d, w0 +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s32_b64_untied, int32_t, + x0 = svqdecp_n_s32_b64 (x1, p0), + x0 = svqdecp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s64.c new file mode 100644 index 00000000000..9527999c88e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_s64.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_s64_tied: +** sqdecp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s64_tied, svint64_t, + z0 = svqdecp_s64 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_s64_untied: +** movprfx z0, z1 +** sqdecp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_s64_untied, svint64_t, + z0 = svqdecp_s64 (z1, p0), + z0 = svqdecp (z1, p0)) + +/* +** qdecp_n_s64_b8_tied: +** sqdecp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b8_tied, int64_t, + x0 = svqdecp_n_s64_b8 (x0, p0), + x0 = svqdecp_b8 (x0, p0)) + +/* +** qdecp_n_s64_b8_untied: +** mov x0, x1 +** sqdecp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b8_untied, int64_t, + x0 = svqdecp_n_s64_b8 (x1, p0), + x0 = svqdecp_b8 (x1, p0)) + +/* +** qdecp_n_s64_b16_tied: +** sqdecp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b16_tied, int64_t, + x0 = svqdecp_n_s64_b16 (x0, p0), + x0 = svqdecp_b16 (x0, p0)) + +/* +** qdecp_n_s64_b16_untied: +** mov x0, x1 +** sqdecp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b16_untied, int64_t, + x0 = svqdecp_n_s64_b16 (x1, p0), + x0 = svqdecp_b16 (x1, p0)) + +/* +** qdecp_n_s64_b32_tied: +** sqdecp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b32_tied, int64_t, + x0 = svqdecp_n_s64_b32 (x0, p0), + x0 = svqdecp_b32 (x0, p0)) + +/* +** qdecp_n_s64_b32_untied: +** mov x0, x1 +** sqdecp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b32_untied, int64_t, + x0 = svqdecp_n_s64_b32 (x1, p0), + x0 = svqdecp_b32 (x1, p0)) + +/* +** qdecp_n_s64_b64_tied: +** sqdecp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b64_tied, int64_t, + x0 = svqdecp_n_s64_b64 (x0, p0), + x0 = svqdecp_b64 (x0, p0)) + +/* +** qdecp_n_s64_b64_untied: +** mov x0, x1 +** sqdecp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_s64_b64_untied, int64_t, + x0 = svqdecp_n_s64_b64 (x1, p0), + x0 = svqdecp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u16.c new file mode 100644 index 00000000000..33357ada49f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_u16_tied: +** uqdecp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u16_tied, svuint16_t, + z0 = svqdecp_u16 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_u16_untied: +** movprfx z0, z1 +** uqdecp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u16_untied, svuint16_t, + z0 = svqdecp_u16 (z1, p0), + z0 = svqdecp (z1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u32.c new file mode 100644 index 00000000000..58e9a642e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u32.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_u32_tied: +** uqdecp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u32_tied, svuint32_t, + z0 = svqdecp_u32 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_u32_untied: +** movprfx z0, z1 +** uqdecp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u32_untied, svuint32_t, + z0 = svqdecp_u32 (z1, p0), + z0 = svqdecp (z1, p0)) + +/* +** qdecp_n_u32_b8_tied: +** uqdecp w0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b8_tied, uint32_t, + x0 = svqdecp_n_u32_b8 (x0, p0), + x0 = svqdecp_b8 (x0, p0)) + +/* +** qdecp_n_u32_b8_untied: +** mov w0, w1 +** uqdecp w0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b8_untied, uint32_t, + x0 = svqdecp_n_u32_b8 (x1, p0), + x0 = svqdecp_b8 (x1, p0)) + +/* +** qdecp_n_u32_b16_tied: +** uqdecp w0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b16_tied, uint32_t, + x0 = svqdecp_n_u32_b16 (x0, p0), + x0 = svqdecp_b16 (x0, p0)) + +/* +** qdecp_n_u32_b16_untied: +** mov w0, w1 +** uqdecp w0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b16_untied, uint32_t, + x0 = svqdecp_n_u32_b16 (x1, p0), + x0 = svqdecp_b16 (x1, p0)) + +/* +** qdecp_n_u32_b32_tied: +** uqdecp w0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b32_tied, uint32_t, + x0 = svqdecp_n_u32_b32 (x0, p0), + x0 = svqdecp_b32 (x0, p0)) + +/* +** qdecp_n_u32_b32_untied: +** mov w0, w1 +** uqdecp w0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b32_untied, uint32_t, + x0 = svqdecp_n_u32_b32 (x1, p0), + x0 = svqdecp_b32 (x1, p0)) + +/* +** qdecp_n_u32_b64_tied: +** uqdecp w0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b64_tied, uint32_t, + x0 = svqdecp_n_u32_b64 (x0, p0), + x0 = svqdecp_b64 (x0, p0)) + +/* +** qdecp_n_u32_b64_untied: +** mov w0, w1 +** uqdecp w0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u32_b64_untied, uint32_t, + x0 = svqdecp_n_u32_b64 (x1, p0), + x0 = svqdecp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u64.c new file mode 100644 index 00000000000..e2091d8ae7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecp_u64.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecp_u64_tied: +** uqdecp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u64_tied, svuint64_t, + z0 = svqdecp_u64 (z0, p0), + z0 = svqdecp (z0, p0)) + +/* +** qdecp_u64_untied: +** movprfx z0, z1 +** uqdecp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qdecp_u64_untied, svuint64_t, + z0 = svqdecp_u64 (z1, p0), + z0 = svqdecp (z1, p0)) + +/* +** qdecp_n_u64_b8_tied: +** uqdecp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b8_tied, uint64_t, + x0 = svqdecp_n_u64_b8 (x0, p0), + x0 = svqdecp_b8 (x0, p0)) + +/* +** qdecp_n_u64_b8_untied: +** mov x0, x1 +** uqdecp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b8_untied, uint64_t, + x0 = svqdecp_n_u64_b8 (x1, p0), + x0 = svqdecp_b8 (x1, p0)) + +/* +** qdecp_n_u64_b16_tied: +** uqdecp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b16_tied, uint64_t, + x0 = svqdecp_n_u64_b16 (x0, p0), + x0 = svqdecp_b16 (x0, p0)) + +/* +** qdecp_n_u64_b16_untied: +** mov x0, x1 +** uqdecp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b16_untied, uint64_t, + x0 = svqdecp_n_u64_b16 (x1, p0), + x0 = svqdecp_b16 (x1, p0)) + +/* +** qdecp_n_u64_b32_tied: +** uqdecp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b32_tied, uint64_t, + x0 = svqdecp_n_u64_b32 (x0, p0), + x0 = svqdecp_b32 (x0, p0)) + +/* +** qdecp_n_u64_b32_untied: +** mov x0, x1 +** uqdecp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b32_untied, uint64_t, + x0 = svqdecp_n_u64_b32 (x1, p0), + x0 = svqdecp_b32 (x1, p0)) + +/* +** qdecp_n_u64_b64_tied: +** uqdecp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b64_tied, uint64_t, + x0 = svqdecp_n_u64_b64 (x0, p0), + x0 = svqdecp_b64 (x0, p0)) + +/* +** qdecp_n_u64_b64_untied: +** mov x0, x1 +** uqdecp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qdecp_n_u64_b64_untied, uint64_t, + x0 = svqdecp_n_u64_b64 (x1, p0), + x0 = svqdecp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s32.c new file mode 100644 index 00000000000..d80f7be4d2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s32.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_pat_1_s32_tied: +** sqdecw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_1_s32_tied, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_POW2, 1), + z0 = svqdecw_pat (z0, SV_POW2, 1)) + +/* +** qdecw_pat_1_s32_untied: +** movprfx z0, z1 +** sqdecw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_1_s32_untied, svint32_t, + z0 = svqdecw_pat_s32 (z1, SV_POW2, 1), + z0 = svqdecw_pat (z1, SV_POW2, 1)) + +/* +** qdecw_pat_2_s32: +** sqdecw z0\.s, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_2_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_POW2, 2), + z0 = svqdecw_pat (z0, SV_POW2, 2)) + +/* +** qdecw_pat_7_s32: +** sqdecw z0\.s, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_7_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_POW2, 7), + z0 = svqdecw_pat (z0, SV_POW2, 7)) + +/* +** qdecw_pat_15_s32: +** sqdecw z0\.s, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_15_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_POW2, 15), + z0 = svqdecw_pat (z0, SV_POW2, 15)) + +/* +** qdecw_pat_16_s32: +** sqdecw z0\.s, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_16_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_POW2, 16), + z0 = svqdecw_pat (z0, SV_POW2, 16)) + +/* +** qdecw_pat_vl1_s32: +** sqdecw z0\.s, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl1_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL1, 16), + z0 = svqdecw_pat (z0, SV_VL1, 16)) + +/* +** qdecw_pat_vl2_s32: +** sqdecw z0\.s, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl2_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL2, 16), + z0 = svqdecw_pat (z0, SV_VL2, 16)) + +/* +** qdecw_pat_vl3_s32: +** sqdecw z0\.s, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl3_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL3, 16), + z0 = svqdecw_pat (z0, SV_VL3, 16)) + +/* +** qdecw_pat_vl4_s32: +** sqdecw z0\.s, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl4_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL4, 16), + z0 = svqdecw_pat (z0, SV_VL4, 16)) + +/* +** qdecw_pat_vl5_s32: +** sqdecw z0\.s, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl5_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL5, 16), + z0 = svqdecw_pat (z0, SV_VL5, 16)) + +/* +** qdecw_pat_vl6_s32: +** sqdecw z0\.s, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl6_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL6, 16), + z0 = svqdecw_pat (z0, SV_VL6, 16)) + +/* +** qdecw_pat_vl7_s32: +** sqdecw z0\.s, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl7_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL7, 16), + z0 = svqdecw_pat (z0, SV_VL7, 16)) + +/* +** qdecw_pat_vl8_s32: +** sqdecw z0\.s, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl8_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL8, 16), + z0 = svqdecw_pat (z0, SV_VL8, 16)) + +/* +** qdecw_pat_vl16_s32: +** sqdecw z0\.s, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl16_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL16, 16), + z0 = svqdecw_pat (z0, SV_VL16, 16)) + +/* +** qdecw_pat_vl32_s32: +** sqdecw z0\.s, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl32_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL32, 16), + z0 = svqdecw_pat (z0, SV_VL32, 16)) + +/* +** qdecw_pat_vl64_s32: +** sqdecw z0\.s, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl64_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL64, 16), + z0 = svqdecw_pat (z0, SV_VL64, 16)) + +/* +** qdecw_pat_vl128_s32: +** sqdecw z0\.s, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl128_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL128, 16), + z0 = svqdecw_pat (z0, SV_VL128, 16)) + +/* +** qdecw_pat_vl256_s32: +** sqdecw z0\.s, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl256_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_VL256, 16), + z0 = svqdecw_pat (z0, SV_VL256, 16)) + +/* +** qdecw_pat_mul4_s32: +** sqdecw z0\.s, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_mul4_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_MUL4, 16), + z0 = svqdecw_pat (z0, SV_MUL4, 16)) + +/* +** qdecw_pat_mul3_s32: +** sqdecw z0\.s, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_mul3_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_MUL3, 16), + z0 = svqdecw_pat (z0, SV_MUL3, 16)) + +/* +** qdecw_pat_all_s32: +** sqdecw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_all_s32, svint32_t, + z0 = svqdecw_pat_s32 (z0, SV_ALL, 16), + z0 = svqdecw_pat (z0, SV_ALL, 16)) + +/* +** qdecw_pat_n_1_s32_tied: +** sqdecw x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_s32_tied, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqdecw_pat (x0, SV_POW2, 1)) + +/* +** qdecw_pat_n_1_s32_untied: +** mov w0, w1 +** sqdecw x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_s32_untied, int32_t, + x0 = svqdecw_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqdecw_pat (x1, SV_POW2, 1)) + +/* +** qdecw_pat_n_2_s32: +** sqdecw x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_2_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqdecw_pat (x0, SV_POW2, 2)) + +/* +** qdecw_pat_n_7_s32: +** sqdecw x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_7_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqdecw_pat (x0, SV_POW2, 7)) + +/* +** qdecw_pat_n_15_s32: +** sqdecw x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_15_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqdecw_pat (x0, SV_POW2, 15)) + +/* +** qdecw_pat_n_16_s32: +** sqdecw x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_16_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqdecw_pat (x0, SV_POW2, 16)) + +/* +** qdecw_pat_n_vl1_s32: +** sqdecw x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl1_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqdecw_pat (x0, SV_VL1, 16)) + +/* +** qdecw_pat_n_vl2_s32: +** sqdecw x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl2_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqdecw_pat (x0, SV_VL2, 16)) + +/* +** qdecw_pat_n_vl3_s32: +** sqdecw x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl3_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqdecw_pat (x0, SV_VL3, 16)) + +/* +** qdecw_pat_n_vl4_s32: +** sqdecw x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl4_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqdecw_pat (x0, SV_VL4, 16)) + +/* +** qdecw_pat_n_vl5_s32: +** sqdecw x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl5_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqdecw_pat (x0, SV_VL5, 16)) + +/* +** qdecw_pat_n_vl6_s32: +** sqdecw x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl6_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqdecw_pat (x0, SV_VL6, 16)) + +/* +** qdecw_pat_n_vl7_s32: +** sqdecw x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl7_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqdecw_pat (x0, SV_VL7, 16)) + +/* +** qdecw_pat_n_vl8_s32: +** sqdecw x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl8_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqdecw_pat (x0, SV_VL8, 16)) + +/* +** qdecw_pat_n_vl16_s32: +** sqdecw x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl16_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqdecw_pat (x0, SV_VL16, 16)) + +/* +** qdecw_pat_n_vl32_s32: +** sqdecw x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl32_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqdecw_pat (x0, SV_VL32, 16)) + +/* +** qdecw_pat_n_vl64_s32: +** sqdecw x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl64_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqdecw_pat (x0, SV_VL64, 16)) + +/* +** qdecw_pat_n_vl128_s32: +** sqdecw x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl128_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqdecw_pat (x0, SV_VL128, 16)) + +/* +** qdecw_pat_n_vl256_s32: +** sqdecw x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl256_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqdecw_pat (x0, SV_VL256, 16)) + +/* +** qdecw_pat_n_mul4_s32: +** sqdecw x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul4_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqdecw_pat (x0, SV_MUL4, 16)) + +/* +** qdecw_pat_n_mul3_s32: +** sqdecw x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul3_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqdecw_pat (x0, SV_MUL3, 16)) + +/* +** qdecw_pat_n_all_s32: +** sqdecw x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_all_s32, int32_t, + x0 = svqdecw_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqdecw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s64.c new file mode 100644 index 00000000000..9c684a7c7c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_pat_n_1_s64_tied: +** sqdecw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_s64_tied, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqdecw_pat (x0, SV_POW2, 1)) + +/* +** qdecw_pat_n_1_s64_untied: +** mov x0, x1 +** sqdecw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_s64_untied, int64_t, + x0 = svqdecw_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqdecw_pat (x1, SV_POW2, 1)) + +/* +** qdecw_pat_n_2_s64: +** sqdecw x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_2_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqdecw_pat (x0, SV_POW2, 2)) + +/* +** qdecw_pat_n_7_s64: +** sqdecw x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_7_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqdecw_pat (x0, SV_POW2, 7)) + +/* +** qdecw_pat_n_15_s64: +** sqdecw x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_15_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqdecw_pat (x0, SV_POW2, 15)) + +/* +** qdecw_pat_n_16_s64: +** sqdecw x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_16_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqdecw_pat (x0, SV_POW2, 16)) + +/* +** qdecw_pat_n_vl1_s64: +** sqdecw x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl1_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqdecw_pat (x0, SV_VL1, 16)) + +/* +** qdecw_pat_n_vl2_s64: +** sqdecw x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl2_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqdecw_pat (x0, SV_VL2, 16)) + +/* +** qdecw_pat_n_vl3_s64: +** sqdecw x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl3_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqdecw_pat (x0, SV_VL3, 16)) + +/* +** qdecw_pat_n_vl4_s64: +** sqdecw x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl4_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqdecw_pat (x0, SV_VL4, 16)) + +/* +** qdecw_pat_n_vl5_s64: +** sqdecw x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl5_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqdecw_pat (x0, SV_VL5, 16)) + +/* +** qdecw_pat_n_vl6_s64: +** sqdecw x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl6_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqdecw_pat (x0, SV_VL6, 16)) + +/* +** qdecw_pat_n_vl7_s64: +** sqdecw x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl7_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqdecw_pat (x0, SV_VL7, 16)) + +/* +** qdecw_pat_n_vl8_s64: +** sqdecw x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl8_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqdecw_pat (x0, SV_VL8, 16)) + +/* +** qdecw_pat_n_vl16_s64: +** sqdecw x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl16_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqdecw_pat (x0, SV_VL16, 16)) + +/* +** qdecw_pat_n_vl32_s64: +** sqdecw x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl32_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqdecw_pat (x0, SV_VL32, 16)) + +/* +** qdecw_pat_n_vl64_s64: +** sqdecw x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl64_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqdecw_pat (x0, SV_VL64, 16)) + +/* +** qdecw_pat_n_vl128_s64: +** sqdecw x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl128_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqdecw_pat (x0, SV_VL128, 16)) + +/* +** qdecw_pat_n_vl256_s64: +** sqdecw x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl256_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqdecw_pat (x0, SV_VL256, 16)) + +/* +** qdecw_pat_n_mul4_s64: +** sqdecw x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul4_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqdecw_pat (x0, SV_MUL4, 16)) + +/* +** qdecw_pat_n_mul3_s64: +** sqdecw x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul3_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqdecw_pat (x0, SV_MUL3, 16)) + +/* +** qdecw_pat_n_all_s64: +** sqdecw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_all_s64, int64_t, + x0 = svqdecw_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqdecw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u32.c new file mode 100644 index 00000000000..8d3fcb47329 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u32.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_pat_1_u32_tied: +** uqdecw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_1_u32_tied, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_POW2, 1), + z0 = svqdecw_pat (z0, SV_POW2, 1)) + +/* +** qdecw_pat_1_u32_untied: +** movprfx z0, z1 +** uqdecw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_1_u32_untied, svuint32_t, + z0 = svqdecw_pat_u32 (z1, SV_POW2, 1), + z0 = svqdecw_pat (z1, SV_POW2, 1)) + +/* +** qdecw_pat_2_u32: +** uqdecw z0\.s, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_2_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_POW2, 2), + z0 = svqdecw_pat (z0, SV_POW2, 2)) + +/* +** qdecw_pat_7_u32: +** uqdecw z0\.s, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_7_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_POW2, 7), + z0 = svqdecw_pat (z0, SV_POW2, 7)) + +/* +** qdecw_pat_15_u32: +** uqdecw z0\.s, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_15_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_POW2, 15), + z0 = svqdecw_pat (z0, SV_POW2, 15)) + +/* +** qdecw_pat_16_u32: +** uqdecw z0\.s, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_16_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_POW2, 16), + z0 = svqdecw_pat (z0, SV_POW2, 16)) + +/* +** qdecw_pat_vl1_u32: +** uqdecw z0\.s, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl1_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL1, 16), + z0 = svqdecw_pat (z0, SV_VL1, 16)) + +/* +** qdecw_pat_vl2_u32: +** uqdecw z0\.s, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl2_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL2, 16), + z0 = svqdecw_pat (z0, SV_VL2, 16)) + +/* +** qdecw_pat_vl3_u32: +** uqdecw z0\.s, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl3_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL3, 16), + z0 = svqdecw_pat (z0, SV_VL3, 16)) + +/* +** qdecw_pat_vl4_u32: +** uqdecw z0\.s, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl4_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL4, 16), + z0 = svqdecw_pat (z0, SV_VL4, 16)) + +/* +** qdecw_pat_vl5_u32: +** uqdecw z0\.s, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl5_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL5, 16), + z0 = svqdecw_pat (z0, SV_VL5, 16)) + +/* +** qdecw_pat_vl6_u32: +** uqdecw z0\.s, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl6_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL6, 16), + z0 = svqdecw_pat (z0, SV_VL6, 16)) + +/* +** qdecw_pat_vl7_u32: +** uqdecw z0\.s, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl7_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL7, 16), + z0 = svqdecw_pat (z0, SV_VL7, 16)) + +/* +** qdecw_pat_vl8_u32: +** uqdecw z0\.s, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl8_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL8, 16), + z0 = svqdecw_pat (z0, SV_VL8, 16)) + +/* +** qdecw_pat_vl16_u32: +** uqdecw z0\.s, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl16_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL16, 16), + z0 = svqdecw_pat (z0, SV_VL16, 16)) + +/* +** qdecw_pat_vl32_u32: +** uqdecw z0\.s, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl32_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL32, 16), + z0 = svqdecw_pat (z0, SV_VL32, 16)) + +/* +** qdecw_pat_vl64_u32: +** uqdecw z0\.s, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl64_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL64, 16), + z0 = svqdecw_pat (z0, SV_VL64, 16)) + +/* +** qdecw_pat_vl128_u32: +** uqdecw z0\.s, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl128_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL128, 16), + z0 = svqdecw_pat (z0, SV_VL128, 16)) + +/* +** qdecw_pat_vl256_u32: +** uqdecw z0\.s, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_vl256_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_VL256, 16), + z0 = svqdecw_pat (z0, SV_VL256, 16)) + +/* +** qdecw_pat_mul4_u32: +** uqdecw z0\.s, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_mul4_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_MUL4, 16), + z0 = svqdecw_pat (z0, SV_MUL4, 16)) + +/* +** qdecw_pat_mul3_u32: +** uqdecw z0\.s, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_mul3_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_MUL3, 16), + z0 = svqdecw_pat (z0, SV_MUL3, 16)) + +/* +** qdecw_pat_all_u32: +** uqdecw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_pat_all_u32, svuint32_t, + z0 = svqdecw_pat_u32 (z0, SV_ALL, 16), + z0 = svqdecw_pat (z0, SV_ALL, 16)) + +/* +** qdecw_pat_n_1_u32_tied: +** uqdecw w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_u32_tied, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqdecw_pat (x0, SV_POW2, 1)) + +/* +** qdecw_pat_n_1_u32_untied: +** mov w0, w1 +** uqdecw w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_u32_untied, uint32_t, + x0 = svqdecw_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqdecw_pat (x1, SV_POW2, 1)) + +/* +** qdecw_pat_n_2_u32: +** uqdecw w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_2_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqdecw_pat (x0, SV_POW2, 2)) + +/* +** qdecw_pat_n_7_u32: +** uqdecw w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_7_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqdecw_pat (x0, SV_POW2, 7)) + +/* +** qdecw_pat_n_15_u32: +** uqdecw w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_15_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqdecw_pat (x0, SV_POW2, 15)) + +/* +** qdecw_pat_n_16_u32: +** uqdecw w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_16_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqdecw_pat (x0, SV_POW2, 16)) + +/* +** qdecw_pat_n_vl1_u32: +** uqdecw w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl1_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqdecw_pat (x0, SV_VL1, 16)) + +/* +** qdecw_pat_n_vl2_u32: +** uqdecw w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl2_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqdecw_pat (x0, SV_VL2, 16)) + +/* +** qdecw_pat_n_vl3_u32: +** uqdecw w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl3_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqdecw_pat (x0, SV_VL3, 16)) + +/* +** qdecw_pat_n_vl4_u32: +** uqdecw w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl4_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqdecw_pat (x0, SV_VL4, 16)) + +/* +** qdecw_pat_n_vl5_u32: +** uqdecw w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl5_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqdecw_pat (x0, SV_VL5, 16)) + +/* +** qdecw_pat_n_vl6_u32: +** uqdecw w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl6_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqdecw_pat (x0, SV_VL6, 16)) + +/* +** qdecw_pat_n_vl7_u32: +** uqdecw w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl7_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqdecw_pat (x0, SV_VL7, 16)) + +/* +** qdecw_pat_n_vl8_u32: +** uqdecw w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl8_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqdecw_pat (x0, SV_VL8, 16)) + +/* +** qdecw_pat_n_vl16_u32: +** uqdecw w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl16_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqdecw_pat (x0, SV_VL16, 16)) + +/* +** qdecw_pat_n_vl32_u32: +** uqdecw w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl32_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqdecw_pat (x0, SV_VL32, 16)) + +/* +** qdecw_pat_n_vl64_u32: +** uqdecw w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl64_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqdecw_pat (x0, SV_VL64, 16)) + +/* +** qdecw_pat_n_vl128_u32: +** uqdecw w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl128_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqdecw_pat (x0, SV_VL128, 16)) + +/* +** qdecw_pat_n_vl256_u32: +** uqdecw w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl256_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqdecw_pat (x0, SV_VL256, 16)) + +/* +** qdecw_pat_n_mul4_u32: +** uqdecw w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul4_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqdecw_pat (x0, SV_MUL4, 16)) + +/* +** qdecw_pat_n_mul3_u32: +** uqdecw w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul3_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqdecw_pat (x0, SV_MUL3, 16)) + +/* +** qdecw_pat_n_all_u32: +** uqdecw w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_all_u32, uint32_t, + x0 = svqdecw_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqdecw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u64.c new file mode 100644 index 00000000000..015775b17ce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_pat_n_1_u64_tied: +** uqdecw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_u64_tied, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqdecw_pat (x0, SV_POW2, 1)) + +/* +** qdecw_pat_n_1_u64_untied: +** mov x0, x1 +** uqdecw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_1_u64_untied, uint64_t, + x0 = svqdecw_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqdecw_pat (x1, SV_POW2, 1)) + +/* +** qdecw_pat_n_2_u64: +** uqdecw x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_2_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqdecw_pat (x0, SV_POW2, 2)) + +/* +** qdecw_pat_n_7_u64: +** uqdecw x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_7_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqdecw_pat (x0, SV_POW2, 7)) + +/* +** qdecw_pat_n_15_u64: +** uqdecw x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_15_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqdecw_pat (x0, SV_POW2, 15)) + +/* +** qdecw_pat_n_16_u64: +** uqdecw x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_16_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqdecw_pat (x0, SV_POW2, 16)) + +/* +** qdecw_pat_n_vl1_u64: +** uqdecw x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl1_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqdecw_pat (x0, SV_VL1, 16)) + +/* +** qdecw_pat_n_vl2_u64: +** uqdecw x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl2_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqdecw_pat (x0, SV_VL2, 16)) + +/* +** qdecw_pat_n_vl3_u64: +** uqdecw x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl3_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqdecw_pat (x0, SV_VL3, 16)) + +/* +** qdecw_pat_n_vl4_u64: +** uqdecw x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl4_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqdecw_pat (x0, SV_VL4, 16)) + +/* +** qdecw_pat_n_vl5_u64: +** uqdecw x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl5_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqdecw_pat (x0, SV_VL5, 16)) + +/* +** qdecw_pat_n_vl6_u64: +** uqdecw x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl6_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqdecw_pat (x0, SV_VL6, 16)) + +/* +** qdecw_pat_n_vl7_u64: +** uqdecw x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl7_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqdecw_pat (x0, SV_VL7, 16)) + +/* +** qdecw_pat_n_vl8_u64: +** uqdecw x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl8_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqdecw_pat (x0, SV_VL8, 16)) + +/* +** qdecw_pat_n_vl16_u64: +** uqdecw x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl16_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqdecw_pat (x0, SV_VL16, 16)) + +/* +** qdecw_pat_n_vl32_u64: +** uqdecw x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl32_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqdecw_pat (x0, SV_VL32, 16)) + +/* +** qdecw_pat_n_vl64_u64: +** uqdecw x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl64_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqdecw_pat (x0, SV_VL64, 16)) + +/* +** qdecw_pat_n_vl128_u64: +** uqdecw x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl128_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqdecw_pat (x0, SV_VL128, 16)) + +/* +** qdecw_pat_n_vl256_u64: +** uqdecw x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_vl256_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqdecw_pat (x0, SV_VL256, 16)) + +/* +** qdecw_pat_n_mul4_u64: +** uqdecw x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul4_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqdecw_pat (x0, SV_MUL4, 16)) + +/* +** qdecw_pat_n_mul3_u64: +** uqdecw x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_mul3_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqdecw_pat (x0, SV_MUL3, 16)) + +/* +** qdecw_pat_n_all_u64: +** uqdecw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_pat_n_all_u64, uint64_t, + x0 = svqdecw_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqdecw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s32.c new file mode 100644 index 00000000000..8dfe8a177a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s32.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_1_s32_tied: +** sqdecw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qdecw_1_s32_tied, svint32_t, + z0 = svqdecw_s32 (z0, 1), + z0 = svqdecw (z0, 1)) + +/* +** qdecw_1_s32_untied: +** movprfx z0, z1 +** sqdecw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qdecw_1_s32_untied, svint32_t, + z0 = svqdecw_s32 (z1, 1), + z0 = svqdecw (z1, 1)) + +/* +** qdecw_2_s32: +** sqdecw z0\.s, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_2_s32, svint32_t, + z0 = svqdecw_s32 (z0, 2), + z0 = svqdecw (z0, 2)) + +/* +** qdecw_7_s32: +** sqdecw z0\.s, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecw_7_s32, svint32_t, + z0 = svqdecw_s32 (z0, 7), + z0 = svqdecw (z0, 7)) + +/* +** qdecw_15_s32: +** sqdecw z0\.s, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecw_15_s32, svint32_t, + z0 = svqdecw_s32 (z0, 15), + z0 = svqdecw (z0, 15)) + +/* +** qdecw_16_s32: +** sqdecw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_16_s32, svint32_t, + z0 = svqdecw_s32 (z0, 16), + z0 = svqdecw (z0, 16)) + +/* +** qdecw_n_1_s32_tied: +** sqdecw x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_s32_tied, int32_t, + x0 = svqdecw_n_s32 (x0, 1), + x0 = svqdecw (x0, 1)) + +/* +** qdecw_n_1_s32_untied: +** mov w0, w1 +** sqdecw x0, w0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_s32_untied, int32_t, + x0 = svqdecw_n_s32 (x1, 1), + x0 = svqdecw (x1, 1)) + +/* +** qdecw_n_2_s32: +** sqdecw x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_2_s32, int32_t, + x0 = svqdecw_n_s32 (x0, 2), + x0 = svqdecw (x0, 2)) + +/* +** qdecw_n_7_s32: +** sqdecw x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_7_s32, int32_t, + x0 = svqdecw_n_s32 (x0, 7), + x0 = svqdecw (x0, 7)) + +/* +** qdecw_n_15_s32: +** sqdecw x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_15_s32, int32_t, + x0 = svqdecw_n_s32 (x0, 15), + x0 = svqdecw (x0, 15)) + +/* +** qdecw_n_16_s32: +** sqdecw x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_16_s32, int32_t, + x0 = svqdecw_n_s32 (x0, 16), + x0 = svqdecw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s64.c new file mode 100644 index 00000000000..b0841a8b24e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_n_1_s64_tied: +** sqdecw x0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_s64_tied, int64_t, + x0 = svqdecw_n_s64 (x0, 1), + x0 = svqdecw (x0, 1)) + +/* +** qdecw_n_1_s64_untied: +** mov x0, x1 +** sqdecw x0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_s64_untied, int64_t, + x0 = svqdecw_n_s64 (x1, 1), + x0 = svqdecw (x1, 1)) + +/* +** qdecw_n_2_s64: +** sqdecw x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_2_s64, int64_t, + x0 = svqdecw_n_s64 (x0, 2), + x0 = svqdecw (x0, 2)) + +/* +** qdecw_n_7_s64: +** sqdecw x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_7_s64, int64_t, + x0 = svqdecw_n_s64 (x0, 7), + x0 = svqdecw (x0, 7)) + +/* +** qdecw_n_15_s64: +** sqdecw x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_15_s64, int64_t, + x0 = svqdecw_n_s64 (x0, 15), + x0 = svqdecw (x0, 15)) + +/* +** qdecw_n_16_s64: +** sqdecw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_16_s64, int64_t, + x0 = svqdecw_n_s64 (x0, 16), + x0 = svqdecw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u32.c new file mode 100644 index 00000000000..22e8a8d6949 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u32.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_1_u32_tied: +** uqdecw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qdecw_1_u32_tied, svuint32_t, + z0 = svqdecw_u32 (z0, 1), + z0 = svqdecw (z0, 1)) + +/* +** qdecw_1_u32_untied: +** movprfx z0, z1 +** uqdecw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qdecw_1_u32_untied, svuint32_t, + z0 = svqdecw_u32 (z1, 1), + z0 = svqdecw (z1, 1)) + +/* +** qdecw_2_u32: +** uqdecw z0\.s, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qdecw_2_u32, svuint32_t, + z0 = svqdecw_u32 (z0, 2), + z0 = svqdecw (z0, 2)) + +/* +** qdecw_7_u32: +** uqdecw z0\.s, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qdecw_7_u32, svuint32_t, + z0 = svqdecw_u32 (z0, 7), + z0 = svqdecw (z0, 7)) + +/* +** qdecw_15_u32: +** uqdecw z0\.s, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qdecw_15_u32, svuint32_t, + z0 = svqdecw_u32 (z0, 15), + z0 = svqdecw (z0, 15)) + +/* +** qdecw_16_u32: +** uqdecw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qdecw_16_u32, svuint32_t, + z0 = svqdecw_u32 (z0, 16), + z0 = svqdecw (z0, 16)) + +/* +** qdecw_n_1_u32_tied: +** uqdecw w0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_u32_tied, uint32_t, + x0 = svqdecw_n_u32 (x0, 1), + x0 = svqdecw (x0, 1)) + +/* +** qdecw_n_1_u32_untied: +** mov w0, w1 +** uqdecw w0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_u32_untied, uint32_t, + x0 = svqdecw_n_u32 (x1, 1), + x0 = svqdecw (x1, 1)) + +/* +** qdecw_n_2_u32: +** uqdecw w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_2_u32, uint32_t, + x0 = svqdecw_n_u32 (x0, 2), + x0 = svqdecw (x0, 2)) + +/* +** qdecw_n_7_u32: +** uqdecw w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_7_u32, uint32_t, + x0 = svqdecw_n_u32 (x0, 7), + x0 = svqdecw (x0, 7)) + +/* +** qdecw_n_15_u32: +** uqdecw w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_15_u32, uint32_t, + x0 = svqdecw_n_u32 (x0, 15), + x0 = svqdecw (x0, 15)) + +/* +** qdecw_n_16_u32: +** uqdecw w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_16_u32, uint32_t, + x0 = svqdecw_n_u32 (x0, 16), + x0 = svqdecw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u64.c new file mode 100644 index 00000000000..88c484e8b41 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qdecw_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qdecw_n_1_u64_tied: +** uqdecw x0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_u64_tied, uint64_t, + x0 = svqdecw_n_u64 (x0, 1), + x0 = svqdecw (x0, 1)) + +/* +** qdecw_n_1_u64_untied: +** mov x0, x1 +** uqdecw x0 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_1_u64_untied, uint64_t, + x0 = svqdecw_n_u64 (x1, 1), + x0 = svqdecw (x1, 1)) + +/* +** qdecw_n_2_u64: +** uqdecw x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_2_u64, uint64_t, + x0 = svqdecw_n_u64 (x0, 2), + x0 = svqdecw (x0, 2)) + +/* +** qdecw_n_7_u64: +** uqdecw x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_7_u64, uint64_t, + x0 = svqdecw_n_u64 (x0, 7), + x0 = svqdecw (x0, 7)) + +/* +** qdecw_n_15_u64: +** uqdecw x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_15_u64, uint64_t, + x0 = svqdecw_n_u64 (x0, 15), + x0 = svqdecw (x0, 15)) + +/* +** qdecw_n_16_u64: +** uqdecw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qdecw_n_16_u64, uint64_t, + x0 = svqdecw_n_u64 (x0, 16), + x0 = svqdecw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s32.c new file mode 100644 index 00000000000..16a8d8e9a1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_pat_n_1_s32_tied: +** sqincb x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_s32_tied, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqincb_pat (x0, SV_POW2, 1)) + +/* +** qincb_pat_n_1_s32_untied: +** mov w0, w1 +** sqincb x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_s32_untied, int32_t, + x0 = svqincb_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqincb_pat (x1, SV_POW2, 1)) + +/* +** qincb_pat_n_2_s32: +** sqincb x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_2_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqincb_pat (x0, SV_POW2, 2)) + +/* +** qincb_pat_n_7_s32: +** sqincb x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_7_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqincb_pat (x0, SV_POW2, 7)) + +/* +** qincb_pat_n_15_s32: +** sqincb x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_15_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqincb_pat (x0, SV_POW2, 15)) + +/* +** qincb_pat_n_16_s32: +** sqincb x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_16_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqincb_pat (x0, SV_POW2, 16)) + +/* +** qincb_pat_n_vl1_s32: +** sqincb x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl1_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqincb_pat (x0, SV_VL1, 16)) + +/* +** qincb_pat_n_vl2_s32: +** sqincb x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl2_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqincb_pat (x0, SV_VL2, 16)) + +/* +** qincb_pat_n_vl3_s32: +** sqincb x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl3_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqincb_pat (x0, SV_VL3, 16)) + +/* +** qincb_pat_n_vl4_s32: +** sqincb x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl4_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqincb_pat (x0, SV_VL4, 16)) + +/* +** qincb_pat_n_vl5_s32: +** sqincb x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl5_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqincb_pat (x0, SV_VL5, 16)) + +/* +** qincb_pat_n_vl6_s32: +** sqincb x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl6_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqincb_pat (x0, SV_VL6, 16)) + +/* +** qincb_pat_n_vl7_s32: +** sqincb x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl7_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqincb_pat (x0, SV_VL7, 16)) + +/* +** qincb_pat_n_vl8_s32: +** sqincb x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl8_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqincb_pat (x0, SV_VL8, 16)) + +/* +** qincb_pat_n_vl16_s32: +** sqincb x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl16_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqincb_pat (x0, SV_VL16, 16)) + +/* +** qincb_pat_n_vl32_s32: +** sqincb x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl32_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqincb_pat (x0, SV_VL32, 16)) + +/* +** qincb_pat_n_vl64_s32: +** sqincb x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl64_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqincb_pat (x0, SV_VL64, 16)) + +/* +** qincb_pat_n_vl128_s32: +** sqincb x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl128_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqincb_pat (x0, SV_VL128, 16)) + +/* +** qincb_pat_n_vl256_s32: +** sqincb x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl256_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqincb_pat (x0, SV_VL256, 16)) + +/* +** qincb_pat_n_mul4_s32: +** sqincb x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul4_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqincb_pat (x0, SV_MUL4, 16)) + +/* +** qincb_pat_n_mul3_s32: +** sqincb x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul3_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqincb_pat (x0, SV_MUL3, 16)) + +/* +** qincb_pat_n_all_s32: +** sqincb x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_all_s32, int32_t, + x0 = svqincb_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqincb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s64.c new file mode 100644 index 00000000000..79ed73ba784 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_pat_n_1_s64_tied: +** sqincb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_s64_tied, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqincb_pat (x0, SV_POW2, 1)) + +/* +** qincb_pat_n_1_s64_untied: +** mov x0, x1 +** sqincb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_s64_untied, int64_t, + x0 = svqincb_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqincb_pat (x1, SV_POW2, 1)) + +/* +** qincb_pat_n_2_s64: +** sqincb x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_2_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqincb_pat (x0, SV_POW2, 2)) + +/* +** qincb_pat_n_7_s64: +** sqincb x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_7_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqincb_pat (x0, SV_POW2, 7)) + +/* +** qincb_pat_n_15_s64: +** sqincb x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_15_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqincb_pat (x0, SV_POW2, 15)) + +/* +** qincb_pat_n_16_s64: +** sqincb x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_16_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqincb_pat (x0, SV_POW2, 16)) + +/* +** qincb_pat_n_vl1_s64: +** sqincb x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl1_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqincb_pat (x0, SV_VL1, 16)) + +/* +** qincb_pat_n_vl2_s64: +** sqincb x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl2_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqincb_pat (x0, SV_VL2, 16)) + +/* +** qincb_pat_n_vl3_s64: +** sqincb x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl3_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqincb_pat (x0, SV_VL3, 16)) + +/* +** qincb_pat_n_vl4_s64: +** sqincb x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl4_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqincb_pat (x0, SV_VL4, 16)) + +/* +** qincb_pat_n_vl5_s64: +** sqincb x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl5_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqincb_pat (x0, SV_VL5, 16)) + +/* +** qincb_pat_n_vl6_s64: +** sqincb x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl6_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqincb_pat (x0, SV_VL6, 16)) + +/* +** qincb_pat_n_vl7_s64: +** sqincb x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl7_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqincb_pat (x0, SV_VL7, 16)) + +/* +** qincb_pat_n_vl8_s64: +** sqincb x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl8_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqincb_pat (x0, SV_VL8, 16)) + +/* +** qincb_pat_n_vl16_s64: +** sqincb x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl16_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqincb_pat (x0, SV_VL16, 16)) + +/* +** qincb_pat_n_vl32_s64: +** sqincb x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl32_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqincb_pat (x0, SV_VL32, 16)) + +/* +** qincb_pat_n_vl64_s64: +** sqincb x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl64_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqincb_pat (x0, SV_VL64, 16)) + +/* +** qincb_pat_n_vl128_s64: +** sqincb x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl128_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqincb_pat (x0, SV_VL128, 16)) + +/* +** qincb_pat_n_vl256_s64: +** sqincb x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl256_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqincb_pat (x0, SV_VL256, 16)) + +/* +** qincb_pat_n_mul4_s64: +** sqincb x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul4_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqincb_pat (x0, SV_MUL4, 16)) + +/* +** qincb_pat_n_mul3_s64: +** sqincb x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul3_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqincb_pat (x0, SV_MUL3, 16)) + +/* +** qincb_pat_n_all_s64: +** sqincb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_all_s64, int64_t, + x0 = svqincb_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqincb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u32.c new file mode 100644 index 00000000000..30e5f28eee7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_pat_n_1_u32_tied: +** uqincb w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_u32_tied, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqincb_pat (x0, SV_POW2, 1)) + +/* +** qincb_pat_n_1_u32_untied: +** mov w0, w1 +** uqincb w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_u32_untied, uint32_t, + x0 = svqincb_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqincb_pat (x1, SV_POW2, 1)) + +/* +** qincb_pat_n_2_u32: +** uqincb w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_2_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqincb_pat (x0, SV_POW2, 2)) + +/* +** qincb_pat_n_7_u32: +** uqincb w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_7_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqincb_pat (x0, SV_POW2, 7)) + +/* +** qincb_pat_n_15_u32: +** uqincb w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_15_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqincb_pat (x0, SV_POW2, 15)) + +/* +** qincb_pat_n_16_u32: +** uqincb w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_16_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqincb_pat (x0, SV_POW2, 16)) + +/* +** qincb_pat_n_vl1_u32: +** uqincb w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl1_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqincb_pat (x0, SV_VL1, 16)) + +/* +** qincb_pat_n_vl2_u32: +** uqincb w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl2_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqincb_pat (x0, SV_VL2, 16)) + +/* +** qincb_pat_n_vl3_u32: +** uqincb w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl3_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqincb_pat (x0, SV_VL3, 16)) + +/* +** qincb_pat_n_vl4_u32: +** uqincb w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl4_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqincb_pat (x0, SV_VL4, 16)) + +/* +** qincb_pat_n_vl5_u32: +** uqincb w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl5_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqincb_pat (x0, SV_VL5, 16)) + +/* +** qincb_pat_n_vl6_u32: +** uqincb w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl6_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqincb_pat (x0, SV_VL6, 16)) + +/* +** qincb_pat_n_vl7_u32: +** uqincb w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl7_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqincb_pat (x0, SV_VL7, 16)) + +/* +** qincb_pat_n_vl8_u32: +** uqincb w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl8_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqincb_pat (x0, SV_VL8, 16)) + +/* +** qincb_pat_n_vl16_u32: +** uqincb w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl16_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqincb_pat (x0, SV_VL16, 16)) + +/* +** qincb_pat_n_vl32_u32: +** uqincb w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl32_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqincb_pat (x0, SV_VL32, 16)) + +/* +** qincb_pat_n_vl64_u32: +** uqincb w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl64_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqincb_pat (x0, SV_VL64, 16)) + +/* +** qincb_pat_n_vl128_u32: +** uqincb w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl128_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqincb_pat (x0, SV_VL128, 16)) + +/* +** qincb_pat_n_vl256_u32: +** uqincb w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl256_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqincb_pat (x0, SV_VL256, 16)) + +/* +** qincb_pat_n_mul4_u32: +** uqincb w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul4_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqincb_pat (x0, SV_MUL4, 16)) + +/* +** qincb_pat_n_mul3_u32: +** uqincb w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul3_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqincb_pat (x0, SV_MUL3, 16)) + +/* +** qincb_pat_n_all_u32: +** uqincb w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_all_u32, uint32_t, + x0 = svqincb_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqincb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u64.c new file mode 100644 index 00000000000..038b1edb6f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_pat_n_1_u64_tied: +** uqincb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_u64_tied, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqincb_pat (x0, SV_POW2, 1)) + +/* +** qincb_pat_n_1_u64_untied: +** mov x0, x1 +** uqincb x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_1_u64_untied, uint64_t, + x0 = svqincb_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqincb_pat (x1, SV_POW2, 1)) + +/* +** qincb_pat_n_2_u64: +** uqincb x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_2_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqincb_pat (x0, SV_POW2, 2)) + +/* +** qincb_pat_n_7_u64: +** uqincb x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_7_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqincb_pat (x0, SV_POW2, 7)) + +/* +** qincb_pat_n_15_u64: +** uqincb x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_15_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqincb_pat (x0, SV_POW2, 15)) + +/* +** qincb_pat_n_16_u64: +** uqincb x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_16_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqincb_pat (x0, SV_POW2, 16)) + +/* +** qincb_pat_n_vl1_u64: +** uqincb x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl1_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqincb_pat (x0, SV_VL1, 16)) + +/* +** qincb_pat_n_vl2_u64: +** uqincb x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl2_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqincb_pat (x0, SV_VL2, 16)) + +/* +** qincb_pat_n_vl3_u64: +** uqincb x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl3_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqincb_pat (x0, SV_VL3, 16)) + +/* +** qincb_pat_n_vl4_u64: +** uqincb x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl4_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqincb_pat (x0, SV_VL4, 16)) + +/* +** qincb_pat_n_vl5_u64: +** uqincb x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl5_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqincb_pat (x0, SV_VL5, 16)) + +/* +** qincb_pat_n_vl6_u64: +** uqincb x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl6_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqincb_pat (x0, SV_VL6, 16)) + +/* +** qincb_pat_n_vl7_u64: +** uqincb x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl7_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqincb_pat (x0, SV_VL7, 16)) + +/* +** qincb_pat_n_vl8_u64: +** uqincb x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl8_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqincb_pat (x0, SV_VL8, 16)) + +/* +** qincb_pat_n_vl16_u64: +** uqincb x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl16_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqincb_pat (x0, SV_VL16, 16)) + +/* +** qincb_pat_n_vl32_u64: +** uqincb x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl32_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqincb_pat (x0, SV_VL32, 16)) + +/* +** qincb_pat_n_vl64_u64: +** uqincb x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl64_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqincb_pat (x0, SV_VL64, 16)) + +/* +** qincb_pat_n_vl128_u64: +** uqincb x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl128_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqincb_pat (x0, SV_VL128, 16)) + +/* +** qincb_pat_n_vl256_u64: +** uqincb x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_vl256_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqincb_pat (x0, SV_VL256, 16)) + +/* +** qincb_pat_n_mul4_u64: +** uqincb x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul4_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqincb_pat (x0, SV_MUL4, 16)) + +/* +** qincb_pat_n_mul3_u64: +** uqincb x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_mul3_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqincb_pat (x0, SV_MUL3, 16)) + +/* +** qincb_pat_n_all_u64: +** uqincb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_pat_n_all_u64, uint64_t, + x0 = svqincb_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqincb_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s32.c new file mode 100644 index 00000000000..8e74073de87 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_n_1_s32_tied: +** sqincb x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_s32_tied, int32_t, + x0 = svqincb_n_s32 (x0, 1), + x0 = svqincb (x0, 1)) + +/* +** qincb_n_1_s32_untied: +** mov w0, w1 +** sqincb x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_s32_untied, int32_t, + x0 = svqincb_n_s32 (x1, 1), + x0 = svqincb (x1, 1)) + +/* +** qincb_n_2_s32: +** sqincb x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_n_2_s32, int32_t, + x0 = svqincb_n_s32 (x0, 2), + x0 = svqincb (x0, 2)) + +/* +** qincb_n_7_s32: +** sqincb x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_n_7_s32, int32_t, + x0 = svqincb_n_s32 (x0, 7), + x0 = svqincb (x0, 7)) + +/* +** qincb_n_15_s32: +** sqincb x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_n_15_s32, int32_t, + x0 = svqincb_n_s32 (x0, 15), + x0 = svqincb (x0, 15)) + +/* +** qincb_n_16_s32: +** sqincb x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_n_16_s32, int32_t, + x0 = svqincb_n_s32 (x0, 16), + x0 = svqincb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s64.c new file mode 100644 index 00000000000..b064c1264b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_n_1_s64_tied: +** sqincb x0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_s64_tied, int64_t, + x0 = svqincb_n_s64 (x0, 1), + x0 = svqincb (x0, 1)) + +/* +** qincb_n_1_s64_untied: +** mov x0, x1 +** sqincb x0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_s64_untied, int64_t, + x0 = svqincb_n_s64 (x1, 1), + x0 = svqincb (x1, 1)) + +/* +** qincb_n_2_s64: +** sqincb x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_n_2_s64, int64_t, + x0 = svqincb_n_s64 (x0, 2), + x0 = svqincb (x0, 2)) + +/* +** qincb_n_7_s64: +** sqincb x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_n_7_s64, int64_t, + x0 = svqincb_n_s64 (x0, 7), + x0 = svqincb (x0, 7)) + +/* +** qincb_n_15_s64: +** sqincb x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_n_15_s64, int64_t, + x0 = svqincb_n_s64 (x0, 15), + x0 = svqincb (x0, 15)) + +/* +** qincb_n_16_s64: +** sqincb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_n_16_s64, int64_t, + x0 = svqincb_n_s64 (x0, 16), + x0 = svqincb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u32.c new file mode 100644 index 00000000000..df3add73e6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_n_1_u32_tied: +** uqincb w0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_u32_tied, uint32_t, + x0 = svqincb_n_u32 (x0, 1), + x0 = svqincb (x0, 1)) + +/* +** qincb_n_1_u32_untied: +** mov w0, w1 +** uqincb w0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_u32_untied, uint32_t, + x0 = svqincb_n_u32 (x1, 1), + x0 = svqincb (x1, 1)) + +/* +** qincb_n_2_u32: +** uqincb w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_n_2_u32, uint32_t, + x0 = svqincb_n_u32 (x0, 2), + x0 = svqincb (x0, 2)) + +/* +** qincb_n_7_u32: +** uqincb w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_n_7_u32, uint32_t, + x0 = svqincb_n_u32 (x0, 7), + x0 = svqincb (x0, 7)) + +/* +** qincb_n_15_u32: +** uqincb w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_n_15_u32, uint32_t, + x0 = svqincb_n_u32 (x0, 15), + x0 = svqincb (x0, 15)) + +/* +** qincb_n_16_u32: +** uqincb w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_n_16_u32, uint32_t, + x0 = svqincb_n_u32 (x0, 16), + x0 = svqincb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u64.c new file mode 100644 index 00000000000..d9a08c86556 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincb_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincb_n_1_u64_tied: +** uqincb x0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_u64_tied, uint64_t, + x0 = svqincb_n_u64 (x0, 1), + x0 = svqincb (x0, 1)) + +/* +** qincb_n_1_u64_untied: +** mov x0, x1 +** uqincb x0 +** ret +*/ +TEST_UNIFORM_S (qincb_n_1_u64_untied, uint64_t, + x0 = svqincb_n_u64 (x1, 1), + x0 = svqincb (x1, 1)) + +/* +** qincb_n_2_u64: +** uqincb x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincb_n_2_u64, uint64_t, + x0 = svqincb_n_u64 (x0, 2), + x0 = svqincb (x0, 2)) + +/* +** qincb_n_7_u64: +** uqincb x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincb_n_7_u64, uint64_t, + x0 = svqincb_n_u64 (x0, 7), + x0 = svqincb (x0, 7)) + +/* +** qincb_n_15_u64: +** uqincb x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincb_n_15_u64, uint64_t, + x0 = svqincb_n_u64 (x0, 15), + x0 = svqincb (x0, 15)) + +/* +** qincb_n_16_u64: +** uqincb x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincb_n_16_u64, uint64_t, + x0 = svqincb_n_u64 (x0, 16), + x0 = svqincb (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s32.c new file mode 100644 index 00000000000..061f88314df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_pat_n_1_s32_tied: +** sqincd x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_s32_tied, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqincd_pat (x0, SV_POW2, 1)) + +/* +** qincd_pat_n_1_s32_untied: +** mov w0, w1 +** sqincd x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_s32_untied, int32_t, + x0 = svqincd_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqincd_pat (x1, SV_POW2, 1)) + +/* +** qincd_pat_n_2_s32: +** sqincd x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_2_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqincd_pat (x0, SV_POW2, 2)) + +/* +** qincd_pat_n_7_s32: +** sqincd x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_7_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqincd_pat (x0, SV_POW2, 7)) + +/* +** qincd_pat_n_15_s32: +** sqincd x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_15_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqincd_pat (x0, SV_POW2, 15)) + +/* +** qincd_pat_n_16_s32: +** sqincd x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_16_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqincd_pat (x0, SV_POW2, 16)) + +/* +** qincd_pat_n_vl1_s32: +** sqincd x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl1_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqincd_pat (x0, SV_VL1, 16)) + +/* +** qincd_pat_n_vl2_s32: +** sqincd x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl2_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqincd_pat (x0, SV_VL2, 16)) + +/* +** qincd_pat_n_vl3_s32: +** sqincd x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl3_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqincd_pat (x0, SV_VL3, 16)) + +/* +** qincd_pat_n_vl4_s32: +** sqincd x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl4_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqincd_pat (x0, SV_VL4, 16)) + +/* +** qincd_pat_n_vl5_s32: +** sqincd x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl5_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqincd_pat (x0, SV_VL5, 16)) + +/* +** qincd_pat_n_vl6_s32: +** sqincd x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl6_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqincd_pat (x0, SV_VL6, 16)) + +/* +** qincd_pat_n_vl7_s32: +** sqincd x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl7_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqincd_pat (x0, SV_VL7, 16)) + +/* +** qincd_pat_n_vl8_s32: +** sqincd x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl8_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqincd_pat (x0, SV_VL8, 16)) + +/* +** qincd_pat_n_vl16_s32: +** sqincd x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl16_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqincd_pat (x0, SV_VL16, 16)) + +/* +** qincd_pat_n_vl32_s32: +** sqincd x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl32_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqincd_pat (x0, SV_VL32, 16)) + +/* +** qincd_pat_n_vl64_s32: +** sqincd x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl64_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqincd_pat (x0, SV_VL64, 16)) + +/* +** qincd_pat_n_vl128_s32: +** sqincd x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl128_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqincd_pat (x0, SV_VL128, 16)) + +/* +** qincd_pat_n_vl256_s32: +** sqincd x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl256_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqincd_pat (x0, SV_VL256, 16)) + +/* +** qincd_pat_n_mul4_s32: +** sqincd x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul4_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqincd_pat (x0, SV_MUL4, 16)) + +/* +** qincd_pat_n_mul3_s32: +** sqincd x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul3_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqincd_pat (x0, SV_MUL3, 16)) + +/* +** qincd_pat_n_all_s32: +** sqincd x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_all_s32, int32_t, + x0 = svqincd_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqincd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s64.c new file mode 100644 index 00000000000..02b53e1bcdb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_s64.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_pat_1_s64_tied: +** sqincd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_1_s64_tied, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_POW2, 1), + z0 = svqincd_pat (z0, SV_POW2, 1)) + +/* +** qincd_pat_1_s64_untied: +** movprfx z0, z1 +** sqincd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_1_s64_untied, svint64_t, + z0 = svqincd_pat_s64 (z1, SV_POW2, 1), + z0 = svqincd_pat (z1, SV_POW2, 1)) + +/* +** qincd_pat_2_s64: +** sqincd z0\.d, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_2_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_POW2, 2), + z0 = svqincd_pat (z0, SV_POW2, 2)) + +/* +** qincd_pat_7_s64: +** sqincd z0\.d, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_7_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_POW2, 7), + z0 = svqincd_pat (z0, SV_POW2, 7)) + +/* +** qincd_pat_15_s64: +** sqincd z0\.d, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_15_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_POW2, 15), + z0 = svqincd_pat (z0, SV_POW2, 15)) + +/* +** qincd_pat_16_s64: +** sqincd z0\.d, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_16_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_POW2, 16), + z0 = svqincd_pat (z0, SV_POW2, 16)) + +/* +** qincd_pat_vl1_s64: +** sqincd z0\.d, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl1_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL1, 16), + z0 = svqincd_pat (z0, SV_VL1, 16)) + +/* +** qincd_pat_vl2_s64: +** sqincd z0\.d, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl2_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL2, 16), + z0 = svqincd_pat (z0, SV_VL2, 16)) + +/* +** qincd_pat_vl3_s64: +** sqincd z0\.d, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl3_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL3, 16), + z0 = svqincd_pat (z0, SV_VL3, 16)) + +/* +** qincd_pat_vl4_s64: +** sqincd z0\.d, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl4_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL4, 16), + z0 = svqincd_pat (z0, SV_VL4, 16)) + +/* +** qincd_pat_vl5_s64: +** sqincd z0\.d, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl5_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL5, 16), + z0 = svqincd_pat (z0, SV_VL5, 16)) + +/* +** qincd_pat_vl6_s64: +** sqincd z0\.d, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl6_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL6, 16), + z0 = svqincd_pat (z0, SV_VL6, 16)) + +/* +** qincd_pat_vl7_s64: +** sqincd z0\.d, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl7_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL7, 16), + z0 = svqincd_pat (z0, SV_VL7, 16)) + +/* +** qincd_pat_vl8_s64: +** sqincd z0\.d, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl8_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL8, 16), + z0 = svqincd_pat (z0, SV_VL8, 16)) + +/* +** qincd_pat_vl16_s64: +** sqincd z0\.d, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl16_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL16, 16), + z0 = svqincd_pat (z0, SV_VL16, 16)) + +/* +** qincd_pat_vl32_s64: +** sqincd z0\.d, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl32_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL32, 16), + z0 = svqincd_pat (z0, SV_VL32, 16)) + +/* +** qincd_pat_vl64_s64: +** sqincd z0\.d, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl64_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL64, 16), + z0 = svqincd_pat (z0, SV_VL64, 16)) + +/* +** qincd_pat_vl128_s64: +** sqincd z0\.d, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl128_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL128, 16), + z0 = svqincd_pat (z0, SV_VL128, 16)) + +/* +** qincd_pat_vl256_s64: +** sqincd z0\.d, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl256_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_VL256, 16), + z0 = svqincd_pat (z0, SV_VL256, 16)) + +/* +** qincd_pat_mul4_s64: +** sqincd z0\.d, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_mul4_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_MUL4, 16), + z0 = svqincd_pat (z0, SV_MUL4, 16)) + +/* +** qincd_pat_mul3_s64: +** sqincd z0\.d, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_mul3_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_MUL3, 16), + z0 = svqincd_pat (z0, SV_MUL3, 16)) + +/* +** qincd_pat_all_s64: +** sqincd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_all_s64, svint64_t, + z0 = svqincd_pat_s64 (z0, SV_ALL, 16), + z0 = svqincd_pat (z0, SV_ALL, 16)) + +/* +** qincd_pat_n_1_s64_tied: +** sqincd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_s64_tied, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqincd_pat (x0, SV_POW2, 1)) + +/* +** qincd_pat_n_1_s64_untied: +** mov x0, x1 +** sqincd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_s64_untied, int64_t, + x0 = svqincd_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqincd_pat (x1, SV_POW2, 1)) + +/* +** qincd_pat_n_2_s64: +** sqincd x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_2_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqincd_pat (x0, SV_POW2, 2)) + +/* +** qincd_pat_n_7_s64: +** sqincd x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_7_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqincd_pat (x0, SV_POW2, 7)) + +/* +** qincd_pat_n_15_s64: +** sqincd x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_15_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqincd_pat (x0, SV_POW2, 15)) + +/* +** qincd_pat_n_16_s64: +** sqincd x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_16_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqincd_pat (x0, SV_POW2, 16)) + +/* +** qincd_pat_n_vl1_s64: +** sqincd x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl1_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqincd_pat (x0, SV_VL1, 16)) + +/* +** qincd_pat_n_vl2_s64: +** sqincd x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl2_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqincd_pat (x0, SV_VL2, 16)) + +/* +** qincd_pat_n_vl3_s64: +** sqincd x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl3_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqincd_pat (x0, SV_VL3, 16)) + +/* +** qincd_pat_n_vl4_s64: +** sqincd x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl4_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqincd_pat (x0, SV_VL4, 16)) + +/* +** qincd_pat_n_vl5_s64: +** sqincd x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl5_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqincd_pat (x0, SV_VL5, 16)) + +/* +** qincd_pat_n_vl6_s64: +** sqincd x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl6_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqincd_pat (x0, SV_VL6, 16)) + +/* +** qincd_pat_n_vl7_s64: +** sqincd x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl7_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqincd_pat (x0, SV_VL7, 16)) + +/* +** qincd_pat_n_vl8_s64: +** sqincd x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl8_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqincd_pat (x0, SV_VL8, 16)) + +/* +** qincd_pat_n_vl16_s64: +** sqincd x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl16_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqincd_pat (x0, SV_VL16, 16)) + +/* +** qincd_pat_n_vl32_s64: +** sqincd x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl32_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqincd_pat (x0, SV_VL32, 16)) + +/* +** qincd_pat_n_vl64_s64: +** sqincd x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl64_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqincd_pat (x0, SV_VL64, 16)) + +/* +** qincd_pat_n_vl128_s64: +** sqincd x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl128_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqincd_pat (x0, SV_VL128, 16)) + +/* +** qincd_pat_n_vl256_s64: +** sqincd x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl256_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqincd_pat (x0, SV_VL256, 16)) + +/* +** qincd_pat_n_mul4_s64: +** sqincd x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul4_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqincd_pat (x0, SV_MUL4, 16)) + +/* +** qincd_pat_n_mul3_s64: +** sqincd x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul3_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqincd_pat (x0, SV_MUL3, 16)) + +/* +** qincd_pat_n_all_s64: +** sqincd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_all_s64, int64_t, + x0 = svqincd_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqincd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u32.c new file mode 100644 index 00000000000..0e3cbdb5444 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_pat_n_1_u32_tied: +** uqincd w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_u32_tied, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqincd_pat (x0, SV_POW2, 1)) + +/* +** qincd_pat_n_1_u32_untied: +** mov w0, w1 +** uqincd w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_u32_untied, uint32_t, + x0 = svqincd_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqincd_pat (x1, SV_POW2, 1)) + +/* +** qincd_pat_n_2_u32: +** uqincd w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_2_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqincd_pat (x0, SV_POW2, 2)) + +/* +** qincd_pat_n_7_u32: +** uqincd w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_7_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqincd_pat (x0, SV_POW2, 7)) + +/* +** qincd_pat_n_15_u32: +** uqincd w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_15_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqincd_pat (x0, SV_POW2, 15)) + +/* +** qincd_pat_n_16_u32: +** uqincd w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_16_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqincd_pat (x0, SV_POW2, 16)) + +/* +** qincd_pat_n_vl1_u32: +** uqincd w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl1_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqincd_pat (x0, SV_VL1, 16)) + +/* +** qincd_pat_n_vl2_u32: +** uqincd w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl2_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqincd_pat (x0, SV_VL2, 16)) + +/* +** qincd_pat_n_vl3_u32: +** uqincd w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl3_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqincd_pat (x0, SV_VL3, 16)) + +/* +** qincd_pat_n_vl4_u32: +** uqincd w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl4_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqincd_pat (x0, SV_VL4, 16)) + +/* +** qincd_pat_n_vl5_u32: +** uqincd w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl5_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqincd_pat (x0, SV_VL5, 16)) + +/* +** qincd_pat_n_vl6_u32: +** uqincd w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl6_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqincd_pat (x0, SV_VL6, 16)) + +/* +** qincd_pat_n_vl7_u32: +** uqincd w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl7_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqincd_pat (x0, SV_VL7, 16)) + +/* +** qincd_pat_n_vl8_u32: +** uqincd w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl8_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqincd_pat (x0, SV_VL8, 16)) + +/* +** qincd_pat_n_vl16_u32: +** uqincd w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl16_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqincd_pat (x0, SV_VL16, 16)) + +/* +** qincd_pat_n_vl32_u32: +** uqincd w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl32_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqincd_pat (x0, SV_VL32, 16)) + +/* +** qincd_pat_n_vl64_u32: +** uqincd w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl64_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqincd_pat (x0, SV_VL64, 16)) + +/* +** qincd_pat_n_vl128_u32: +** uqincd w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl128_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqincd_pat (x0, SV_VL128, 16)) + +/* +** qincd_pat_n_vl256_u32: +** uqincd w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl256_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqincd_pat (x0, SV_VL256, 16)) + +/* +** qincd_pat_n_mul4_u32: +** uqincd w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul4_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqincd_pat (x0, SV_MUL4, 16)) + +/* +** qincd_pat_n_mul3_u32: +** uqincd w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul3_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqincd_pat (x0, SV_MUL3, 16)) + +/* +** qincd_pat_n_all_u32: +** uqincd w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_all_u32, uint32_t, + x0 = svqincd_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqincd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u64.c new file mode 100644 index 00000000000..49dc350df70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_pat_u64.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_pat_1_u64_tied: +** uqincd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_1_u64_tied, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_POW2, 1), + z0 = svqincd_pat (z0, SV_POW2, 1)) + +/* +** qincd_pat_1_u64_untied: +** movprfx z0, z1 +** uqincd z0\.d, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_1_u64_untied, svuint64_t, + z0 = svqincd_pat_u64 (z1, SV_POW2, 1), + z0 = svqincd_pat (z1, SV_POW2, 1)) + +/* +** qincd_pat_2_u64: +** uqincd z0\.d, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_2_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_POW2, 2), + z0 = svqincd_pat (z0, SV_POW2, 2)) + +/* +** qincd_pat_7_u64: +** uqincd z0\.d, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_7_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_POW2, 7), + z0 = svqincd_pat (z0, SV_POW2, 7)) + +/* +** qincd_pat_15_u64: +** uqincd z0\.d, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_15_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_POW2, 15), + z0 = svqincd_pat (z0, SV_POW2, 15)) + +/* +** qincd_pat_16_u64: +** uqincd z0\.d, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_16_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_POW2, 16), + z0 = svqincd_pat (z0, SV_POW2, 16)) + +/* +** qincd_pat_vl1_u64: +** uqincd z0\.d, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl1_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL1, 16), + z0 = svqincd_pat (z0, SV_VL1, 16)) + +/* +** qincd_pat_vl2_u64: +** uqincd z0\.d, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl2_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL2, 16), + z0 = svqincd_pat (z0, SV_VL2, 16)) + +/* +** qincd_pat_vl3_u64: +** uqincd z0\.d, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl3_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL3, 16), + z0 = svqincd_pat (z0, SV_VL3, 16)) + +/* +** qincd_pat_vl4_u64: +** uqincd z0\.d, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl4_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL4, 16), + z0 = svqincd_pat (z0, SV_VL4, 16)) + +/* +** qincd_pat_vl5_u64: +** uqincd z0\.d, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl5_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL5, 16), + z0 = svqincd_pat (z0, SV_VL5, 16)) + +/* +** qincd_pat_vl6_u64: +** uqincd z0\.d, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl6_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL6, 16), + z0 = svqincd_pat (z0, SV_VL6, 16)) + +/* +** qincd_pat_vl7_u64: +** uqincd z0\.d, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl7_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL7, 16), + z0 = svqincd_pat (z0, SV_VL7, 16)) + +/* +** qincd_pat_vl8_u64: +** uqincd z0\.d, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl8_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL8, 16), + z0 = svqincd_pat (z0, SV_VL8, 16)) + +/* +** qincd_pat_vl16_u64: +** uqincd z0\.d, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl16_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL16, 16), + z0 = svqincd_pat (z0, SV_VL16, 16)) + +/* +** qincd_pat_vl32_u64: +** uqincd z0\.d, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl32_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL32, 16), + z0 = svqincd_pat (z0, SV_VL32, 16)) + +/* +** qincd_pat_vl64_u64: +** uqincd z0\.d, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl64_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL64, 16), + z0 = svqincd_pat (z0, SV_VL64, 16)) + +/* +** qincd_pat_vl128_u64: +** uqincd z0\.d, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl128_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL128, 16), + z0 = svqincd_pat (z0, SV_VL128, 16)) + +/* +** qincd_pat_vl256_u64: +** uqincd z0\.d, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_vl256_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_VL256, 16), + z0 = svqincd_pat (z0, SV_VL256, 16)) + +/* +** qincd_pat_mul4_u64: +** uqincd z0\.d, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_mul4_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_MUL4, 16), + z0 = svqincd_pat (z0, SV_MUL4, 16)) + +/* +** qincd_pat_mul3_u64: +** uqincd z0\.d, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_mul3_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_MUL3, 16), + z0 = svqincd_pat (z0, SV_MUL3, 16)) + +/* +** qincd_pat_all_u64: +** uqincd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_pat_all_u64, svuint64_t, + z0 = svqincd_pat_u64 (z0, SV_ALL, 16), + z0 = svqincd_pat (z0, SV_ALL, 16)) + +/* +** qincd_pat_n_1_u64_tied: +** uqincd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_u64_tied, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqincd_pat (x0, SV_POW2, 1)) + +/* +** qincd_pat_n_1_u64_untied: +** mov x0, x1 +** uqincd x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_1_u64_untied, uint64_t, + x0 = svqincd_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqincd_pat (x1, SV_POW2, 1)) + +/* +** qincd_pat_n_2_u64: +** uqincd x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_2_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqincd_pat (x0, SV_POW2, 2)) + +/* +** qincd_pat_n_7_u64: +** uqincd x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_7_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqincd_pat (x0, SV_POW2, 7)) + +/* +** qincd_pat_n_15_u64: +** uqincd x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_15_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqincd_pat (x0, SV_POW2, 15)) + +/* +** qincd_pat_n_16_u64: +** uqincd x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_16_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqincd_pat (x0, SV_POW2, 16)) + +/* +** qincd_pat_n_vl1_u64: +** uqincd x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl1_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqincd_pat (x0, SV_VL1, 16)) + +/* +** qincd_pat_n_vl2_u64: +** uqincd x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl2_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqincd_pat (x0, SV_VL2, 16)) + +/* +** qincd_pat_n_vl3_u64: +** uqincd x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl3_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqincd_pat (x0, SV_VL3, 16)) + +/* +** qincd_pat_n_vl4_u64: +** uqincd x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl4_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqincd_pat (x0, SV_VL4, 16)) + +/* +** qincd_pat_n_vl5_u64: +** uqincd x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl5_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqincd_pat (x0, SV_VL5, 16)) + +/* +** qincd_pat_n_vl6_u64: +** uqincd x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl6_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqincd_pat (x0, SV_VL6, 16)) + +/* +** qincd_pat_n_vl7_u64: +** uqincd x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl7_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqincd_pat (x0, SV_VL7, 16)) + +/* +** qincd_pat_n_vl8_u64: +** uqincd x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl8_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqincd_pat (x0, SV_VL8, 16)) + +/* +** qincd_pat_n_vl16_u64: +** uqincd x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl16_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqincd_pat (x0, SV_VL16, 16)) + +/* +** qincd_pat_n_vl32_u64: +** uqincd x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl32_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqincd_pat (x0, SV_VL32, 16)) + +/* +** qincd_pat_n_vl64_u64: +** uqincd x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl64_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqincd_pat (x0, SV_VL64, 16)) + +/* +** qincd_pat_n_vl128_u64: +** uqincd x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl128_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqincd_pat (x0, SV_VL128, 16)) + +/* +** qincd_pat_n_vl256_u64: +** uqincd x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_vl256_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqincd_pat (x0, SV_VL256, 16)) + +/* +** qincd_pat_n_mul4_u64: +** uqincd x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul4_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqincd_pat (x0, SV_MUL4, 16)) + +/* +** qincd_pat_n_mul3_u64: +** uqincd x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_mul3_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqincd_pat (x0, SV_MUL3, 16)) + +/* +** qincd_pat_n_all_u64: +** uqincd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_pat_n_all_u64, uint64_t, + x0 = svqincd_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqincd_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s32.c new file mode 100644 index 00000000000..2fa0438a32a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_n_1_s32_tied: +** sqincd x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_s32_tied, int32_t, + x0 = svqincd_n_s32 (x0, 1), + x0 = svqincd (x0, 1)) + +/* +** qincd_n_1_s32_untied: +** mov w0, w1 +** sqincd x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_s32_untied, int32_t, + x0 = svqincd_n_s32 (x1, 1), + x0 = svqincd (x1, 1)) + +/* +** qincd_n_2_s32: +** sqincd x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_n_2_s32, int32_t, + x0 = svqincd_n_s32 (x0, 2), + x0 = svqincd (x0, 2)) + +/* +** qincd_n_7_s32: +** sqincd x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_n_7_s32, int32_t, + x0 = svqincd_n_s32 (x0, 7), + x0 = svqincd (x0, 7)) + +/* +** qincd_n_15_s32: +** sqincd x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_n_15_s32, int32_t, + x0 = svqincd_n_s32 (x0, 15), + x0 = svqincd (x0, 15)) + +/* +** qincd_n_16_s32: +** sqincd x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_n_16_s32, int32_t, + x0 = svqincd_n_s32 (x0, 16), + x0 = svqincd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s64.c new file mode 100644 index 00000000000..0920ac2ec6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_s64.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_1_s64_tied: +** sqincd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qincd_1_s64_tied, svint64_t, + z0 = svqincd_s64 (z0, 1), + z0 = svqincd (z0, 1)) + +/* +** qincd_1_s64_untied: +** movprfx z0, z1 +** sqincd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qincd_1_s64_untied, svint64_t, + z0 = svqincd_s64 (z1, 1), + z0 = svqincd (z1, 1)) + +/* +** qincd_2_s64: +** sqincd z0\.d, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincd_2_s64, svint64_t, + z0 = svqincd_s64 (z0, 2), + z0 = svqincd (z0, 2)) + +/* +** qincd_7_s64: +** sqincd z0\.d, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincd_7_s64, svint64_t, + z0 = svqincd_s64 (z0, 7), + z0 = svqincd (z0, 7)) + +/* +** qincd_15_s64: +** sqincd z0\.d, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincd_15_s64, svint64_t, + z0 = svqincd_s64 (z0, 15), + z0 = svqincd (z0, 15)) + +/* +** qincd_16_s64: +** sqincd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_16_s64, svint64_t, + z0 = svqincd_s64 (z0, 16), + z0 = svqincd (z0, 16)) + +/* +** qincd_n_1_s64_tied: +** sqincd x0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_s64_tied, int64_t, + x0 = svqincd_n_s64 (x0, 1), + x0 = svqincd (x0, 1)) + +/* +** qincd_n_1_s64_untied: +** mov x0, x1 +** sqincd x0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_s64_untied, int64_t, + x0 = svqincd_n_s64 (x1, 1), + x0 = svqincd (x1, 1)) + +/* +** qincd_n_2_s64: +** sqincd x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_n_2_s64, int64_t, + x0 = svqincd_n_s64 (x0, 2), + x0 = svqincd (x0, 2)) + +/* +** qincd_n_7_s64: +** sqincd x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_n_7_s64, int64_t, + x0 = svqincd_n_s64 (x0, 7), + x0 = svqincd (x0, 7)) + +/* +** qincd_n_15_s64: +** sqincd x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_n_15_s64, int64_t, + x0 = svqincd_n_s64 (x0, 15), + x0 = svqincd (x0, 15)) + +/* +** qincd_n_16_s64: +** sqincd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_n_16_s64, int64_t, + x0 = svqincd_n_s64 (x0, 16), + x0 = svqincd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u32.c new file mode 100644 index 00000000000..33dc12cb1fd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_n_1_u32_tied: +** uqincd w0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_u32_tied, uint32_t, + x0 = svqincd_n_u32 (x0, 1), + x0 = svqincd (x0, 1)) + +/* +** qincd_n_1_u32_untied: +** mov w0, w1 +** uqincd w0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_u32_untied, uint32_t, + x0 = svqincd_n_u32 (x1, 1), + x0 = svqincd (x1, 1)) + +/* +** qincd_n_2_u32: +** uqincd w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_n_2_u32, uint32_t, + x0 = svqincd_n_u32 (x0, 2), + x0 = svqincd (x0, 2)) + +/* +** qincd_n_7_u32: +** uqincd w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_n_7_u32, uint32_t, + x0 = svqincd_n_u32 (x0, 7), + x0 = svqincd (x0, 7)) + +/* +** qincd_n_15_u32: +** uqincd w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_n_15_u32, uint32_t, + x0 = svqincd_n_u32 (x0, 15), + x0 = svqincd (x0, 15)) + +/* +** qincd_n_16_u32: +** uqincd w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_n_16_u32, uint32_t, + x0 = svqincd_n_u32 (x0, 16), + x0 = svqincd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u64.c new file mode 100644 index 00000000000..28c611a8ffc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincd_u64.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincd_1_u64_tied: +** uqincd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qincd_1_u64_tied, svuint64_t, + z0 = svqincd_u64 (z0, 1), + z0 = svqincd (z0, 1)) + +/* +** qincd_1_u64_untied: +** movprfx z0, z1 +** uqincd z0\.d +** ret +*/ +TEST_UNIFORM_Z (qincd_1_u64_untied, svuint64_t, + z0 = svqincd_u64 (z1, 1), + z0 = svqincd (z1, 1)) + +/* +** qincd_2_u64: +** uqincd z0\.d, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincd_2_u64, svuint64_t, + z0 = svqincd_u64 (z0, 2), + z0 = svqincd (z0, 2)) + +/* +** qincd_7_u64: +** uqincd z0\.d, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincd_7_u64, svuint64_t, + z0 = svqincd_u64 (z0, 7), + z0 = svqincd (z0, 7)) + +/* +** qincd_15_u64: +** uqincd z0\.d, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincd_15_u64, svuint64_t, + z0 = svqincd_u64 (z0, 15), + z0 = svqincd (z0, 15)) + +/* +** qincd_16_u64: +** uqincd z0\.d, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincd_16_u64, svuint64_t, + z0 = svqincd_u64 (z0, 16), + z0 = svqincd (z0, 16)) + +/* +** qincd_n_1_u64_tied: +** uqincd x0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_u64_tied, uint64_t, + x0 = svqincd_n_u64 (x0, 1), + x0 = svqincd (x0, 1)) + +/* +** qincd_n_1_u64_untied: +** mov x0, x1 +** uqincd x0 +** ret +*/ +TEST_UNIFORM_S (qincd_n_1_u64_untied, uint64_t, + x0 = svqincd_n_u64 (x1, 1), + x0 = svqincd (x1, 1)) + +/* +** qincd_n_2_u64: +** uqincd x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincd_n_2_u64, uint64_t, + x0 = svqincd_n_u64 (x0, 2), + x0 = svqincd (x0, 2)) + +/* +** qincd_n_7_u64: +** uqincd x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincd_n_7_u64, uint64_t, + x0 = svqincd_n_u64 (x0, 7), + x0 = svqincd (x0, 7)) + +/* +** qincd_n_15_u64: +** uqincd x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincd_n_15_u64, uint64_t, + x0 = svqincd_n_u64 (x0, 15), + x0 = svqincd (x0, 15)) + +/* +** qincd_n_16_u64: +** uqincd x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincd_n_16_u64, uint64_t, + x0 = svqincd_n_u64 (x0, 16), + x0 = svqincd (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s16.c new file mode 100644 index 00000000000..708d635c5ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s16.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_1_s16_tied: +** sqinch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_1_s16_tied, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_POW2, 1), + z0 = svqinch_pat (z0, SV_POW2, 1)) + +/* +** qinch_pat_1_s16_untied: +** movprfx z0, z1 +** sqinch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_1_s16_untied, svint16_t, + z0 = svqinch_pat_s16 (z1, SV_POW2, 1), + z0 = svqinch_pat (z1, SV_POW2, 1)) + +/* +** qinch_pat_2_s16: +** sqinch z0\.h, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_2_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_POW2, 2), + z0 = svqinch_pat (z0, SV_POW2, 2)) + +/* +** qinch_pat_7_s16: +** sqinch z0\.h, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_7_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_POW2, 7), + z0 = svqinch_pat (z0, SV_POW2, 7)) + +/* +** qinch_pat_15_s16: +** sqinch z0\.h, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_15_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_POW2, 15), + z0 = svqinch_pat (z0, SV_POW2, 15)) + +/* +** qinch_pat_16_s16: +** sqinch z0\.h, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_16_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_POW2, 16), + z0 = svqinch_pat (z0, SV_POW2, 16)) + +/* +** qinch_pat_vl1_s16: +** sqinch z0\.h, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl1_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL1, 16), + z0 = svqinch_pat (z0, SV_VL1, 16)) + +/* +** qinch_pat_vl2_s16: +** sqinch z0\.h, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl2_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL2, 16), + z0 = svqinch_pat (z0, SV_VL2, 16)) + +/* +** qinch_pat_vl3_s16: +** sqinch z0\.h, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl3_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL3, 16), + z0 = svqinch_pat (z0, SV_VL3, 16)) + +/* +** qinch_pat_vl4_s16: +** sqinch z0\.h, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl4_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL4, 16), + z0 = svqinch_pat (z0, SV_VL4, 16)) + +/* +** qinch_pat_vl5_s16: +** sqinch z0\.h, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl5_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL5, 16), + z0 = svqinch_pat (z0, SV_VL5, 16)) + +/* +** qinch_pat_vl6_s16: +** sqinch z0\.h, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl6_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL6, 16), + z0 = svqinch_pat (z0, SV_VL6, 16)) + +/* +** qinch_pat_vl7_s16: +** sqinch z0\.h, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl7_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL7, 16), + z0 = svqinch_pat (z0, SV_VL7, 16)) + +/* +** qinch_pat_vl8_s16: +** sqinch z0\.h, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl8_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL8, 16), + z0 = svqinch_pat (z0, SV_VL8, 16)) + +/* +** qinch_pat_vl16_s16: +** sqinch z0\.h, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl16_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL16, 16), + z0 = svqinch_pat (z0, SV_VL16, 16)) + +/* +** qinch_pat_vl32_s16: +** sqinch z0\.h, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl32_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL32, 16), + z0 = svqinch_pat (z0, SV_VL32, 16)) + +/* +** qinch_pat_vl64_s16: +** sqinch z0\.h, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl64_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL64, 16), + z0 = svqinch_pat (z0, SV_VL64, 16)) + +/* +** qinch_pat_vl128_s16: +** sqinch z0\.h, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl128_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL128, 16), + z0 = svqinch_pat (z0, SV_VL128, 16)) + +/* +** qinch_pat_vl256_s16: +** sqinch z0\.h, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl256_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_VL256, 16), + z0 = svqinch_pat (z0, SV_VL256, 16)) + +/* +** qinch_pat_mul4_s16: +** sqinch z0\.h, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_mul4_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_MUL4, 16), + z0 = svqinch_pat (z0, SV_MUL4, 16)) + +/* +** qinch_pat_mul3_s16: +** sqinch z0\.h, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_mul3_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_MUL3, 16), + z0 = svqinch_pat (z0, SV_MUL3, 16)) + +/* +** qinch_pat_all_s16: +** sqinch z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_all_s16, svint16_t, + z0 = svqinch_pat_s16 (z0, SV_ALL, 16), + z0 = svqinch_pat (z0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s32.c new file mode 100644 index 00000000000..7c91c6202e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_n_1_s32_tied: +** sqinch x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_s32_tied, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqinch_pat (x0, SV_POW2, 1)) + +/* +** qinch_pat_n_1_s32_untied: +** mov w0, w1 +** sqinch x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_s32_untied, int32_t, + x0 = svqinch_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqinch_pat (x1, SV_POW2, 1)) + +/* +** qinch_pat_n_2_s32: +** sqinch x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_2_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqinch_pat (x0, SV_POW2, 2)) + +/* +** qinch_pat_n_7_s32: +** sqinch x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_7_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqinch_pat (x0, SV_POW2, 7)) + +/* +** qinch_pat_n_15_s32: +** sqinch x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_15_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqinch_pat (x0, SV_POW2, 15)) + +/* +** qinch_pat_n_16_s32: +** sqinch x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_16_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqinch_pat (x0, SV_POW2, 16)) + +/* +** qinch_pat_n_vl1_s32: +** sqinch x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl1_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqinch_pat (x0, SV_VL1, 16)) + +/* +** qinch_pat_n_vl2_s32: +** sqinch x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl2_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqinch_pat (x0, SV_VL2, 16)) + +/* +** qinch_pat_n_vl3_s32: +** sqinch x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl3_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqinch_pat (x0, SV_VL3, 16)) + +/* +** qinch_pat_n_vl4_s32: +** sqinch x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl4_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqinch_pat (x0, SV_VL4, 16)) + +/* +** qinch_pat_n_vl5_s32: +** sqinch x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl5_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqinch_pat (x0, SV_VL5, 16)) + +/* +** qinch_pat_n_vl6_s32: +** sqinch x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl6_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqinch_pat (x0, SV_VL6, 16)) + +/* +** qinch_pat_n_vl7_s32: +** sqinch x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl7_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqinch_pat (x0, SV_VL7, 16)) + +/* +** qinch_pat_n_vl8_s32: +** sqinch x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl8_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqinch_pat (x0, SV_VL8, 16)) + +/* +** qinch_pat_n_vl16_s32: +** sqinch x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl16_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqinch_pat (x0, SV_VL16, 16)) + +/* +** qinch_pat_n_vl32_s32: +** sqinch x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl32_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqinch_pat (x0, SV_VL32, 16)) + +/* +** qinch_pat_n_vl64_s32: +** sqinch x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl64_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqinch_pat (x0, SV_VL64, 16)) + +/* +** qinch_pat_n_vl128_s32: +** sqinch x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl128_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqinch_pat (x0, SV_VL128, 16)) + +/* +** qinch_pat_n_vl256_s32: +** sqinch x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl256_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqinch_pat (x0, SV_VL256, 16)) + +/* +** qinch_pat_n_mul4_s32: +** sqinch x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul4_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqinch_pat (x0, SV_MUL4, 16)) + +/* +** qinch_pat_n_mul3_s32: +** sqinch x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul3_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqinch_pat (x0, SV_MUL3, 16)) + +/* +** qinch_pat_n_all_s32: +** sqinch x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_all_s32, int32_t, + x0 = svqinch_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqinch_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s64.c new file mode 100644 index 00000000000..2cde6482fd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_n_1_s64_tied: +** sqinch x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_s64_tied, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqinch_pat (x0, SV_POW2, 1)) + +/* +** qinch_pat_n_1_s64_untied: +** mov x0, x1 +** sqinch x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_s64_untied, int64_t, + x0 = svqinch_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqinch_pat (x1, SV_POW2, 1)) + +/* +** qinch_pat_n_2_s64: +** sqinch x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_2_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqinch_pat (x0, SV_POW2, 2)) + +/* +** qinch_pat_n_7_s64: +** sqinch x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_7_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqinch_pat (x0, SV_POW2, 7)) + +/* +** qinch_pat_n_15_s64: +** sqinch x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_15_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqinch_pat (x0, SV_POW2, 15)) + +/* +** qinch_pat_n_16_s64: +** sqinch x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_16_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqinch_pat (x0, SV_POW2, 16)) + +/* +** qinch_pat_n_vl1_s64: +** sqinch x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl1_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqinch_pat (x0, SV_VL1, 16)) + +/* +** qinch_pat_n_vl2_s64: +** sqinch x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl2_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqinch_pat (x0, SV_VL2, 16)) + +/* +** qinch_pat_n_vl3_s64: +** sqinch x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl3_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqinch_pat (x0, SV_VL3, 16)) + +/* +** qinch_pat_n_vl4_s64: +** sqinch x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl4_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqinch_pat (x0, SV_VL4, 16)) + +/* +** qinch_pat_n_vl5_s64: +** sqinch x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl5_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqinch_pat (x0, SV_VL5, 16)) + +/* +** qinch_pat_n_vl6_s64: +** sqinch x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl6_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqinch_pat (x0, SV_VL6, 16)) + +/* +** qinch_pat_n_vl7_s64: +** sqinch x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl7_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqinch_pat (x0, SV_VL7, 16)) + +/* +** qinch_pat_n_vl8_s64: +** sqinch x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl8_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqinch_pat (x0, SV_VL8, 16)) + +/* +** qinch_pat_n_vl16_s64: +** sqinch x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl16_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqinch_pat (x0, SV_VL16, 16)) + +/* +** qinch_pat_n_vl32_s64: +** sqinch x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl32_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqinch_pat (x0, SV_VL32, 16)) + +/* +** qinch_pat_n_vl64_s64: +** sqinch x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl64_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqinch_pat (x0, SV_VL64, 16)) + +/* +** qinch_pat_n_vl128_s64: +** sqinch x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl128_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqinch_pat (x0, SV_VL128, 16)) + +/* +** qinch_pat_n_vl256_s64: +** sqinch x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl256_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqinch_pat (x0, SV_VL256, 16)) + +/* +** qinch_pat_n_mul4_s64: +** sqinch x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul4_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqinch_pat (x0, SV_MUL4, 16)) + +/* +** qinch_pat_n_mul3_s64: +** sqinch x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul3_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqinch_pat (x0, SV_MUL3, 16)) + +/* +** qinch_pat_n_all_s64: +** sqinch x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_all_s64, int64_t, + x0 = svqinch_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqinch_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u16.c new file mode 100644 index 00000000000..5a1a846a0ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u16.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_1_u16_tied: +** uqinch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_1_u16_tied, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_POW2, 1), + z0 = svqinch_pat (z0, SV_POW2, 1)) + +/* +** qinch_pat_1_u16_untied: +** movprfx z0, z1 +** uqinch z0\.h, pow2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_1_u16_untied, svuint16_t, + z0 = svqinch_pat_u16 (z1, SV_POW2, 1), + z0 = svqinch_pat (z1, SV_POW2, 1)) + +/* +** qinch_pat_2_u16: +** uqinch z0\.h, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_2_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_POW2, 2), + z0 = svqinch_pat (z0, SV_POW2, 2)) + +/* +** qinch_pat_7_u16: +** uqinch z0\.h, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_7_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_POW2, 7), + z0 = svqinch_pat (z0, SV_POW2, 7)) + +/* +** qinch_pat_15_u16: +** uqinch z0\.h, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_15_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_POW2, 15), + z0 = svqinch_pat (z0, SV_POW2, 15)) + +/* +** qinch_pat_16_u16: +** uqinch z0\.h, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_16_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_POW2, 16), + z0 = svqinch_pat (z0, SV_POW2, 16)) + +/* +** qinch_pat_vl1_u16: +** uqinch z0\.h, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl1_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL1, 16), + z0 = svqinch_pat (z0, SV_VL1, 16)) + +/* +** qinch_pat_vl2_u16: +** uqinch z0\.h, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl2_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL2, 16), + z0 = svqinch_pat (z0, SV_VL2, 16)) + +/* +** qinch_pat_vl3_u16: +** uqinch z0\.h, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl3_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL3, 16), + z0 = svqinch_pat (z0, SV_VL3, 16)) + +/* +** qinch_pat_vl4_u16: +** uqinch z0\.h, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl4_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL4, 16), + z0 = svqinch_pat (z0, SV_VL4, 16)) + +/* +** qinch_pat_vl5_u16: +** uqinch z0\.h, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl5_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL5, 16), + z0 = svqinch_pat (z0, SV_VL5, 16)) + +/* +** qinch_pat_vl6_u16: +** uqinch z0\.h, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl6_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL6, 16), + z0 = svqinch_pat (z0, SV_VL6, 16)) + +/* +** qinch_pat_vl7_u16: +** uqinch z0\.h, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl7_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL7, 16), + z0 = svqinch_pat (z0, SV_VL7, 16)) + +/* +** qinch_pat_vl8_u16: +** uqinch z0\.h, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl8_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL8, 16), + z0 = svqinch_pat (z0, SV_VL8, 16)) + +/* +** qinch_pat_vl16_u16: +** uqinch z0\.h, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl16_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL16, 16), + z0 = svqinch_pat (z0, SV_VL16, 16)) + +/* +** qinch_pat_vl32_u16: +** uqinch z0\.h, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl32_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL32, 16), + z0 = svqinch_pat (z0, SV_VL32, 16)) + +/* +** qinch_pat_vl64_u16: +** uqinch z0\.h, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl64_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL64, 16), + z0 = svqinch_pat (z0, SV_VL64, 16)) + +/* +** qinch_pat_vl128_u16: +** uqinch z0\.h, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl128_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL128, 16), + z0 = svqinch_pat (z0, SV_VL128, 16)) + +/* +** qinch_pat_vl256_u16: +** uqinch z0\.h, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_vl256_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_VL256, 16), + z0 = svqinch_pat (z0, SV_VL256, 16)) + +/* +** qinch_pat_mul4_u16: +** uqinch z0\.h, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_mul4_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_MUL4, 16), + z0 = svqinch_pat (z0, SV_MUL4, 16)) + +/* +** qinch_pat_mul3_u16: +** uqinch z0\.h, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_mul3_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_MUL3, 16), + z0 = svqinch_pat (z0, SV_MUL3, 16)) + +/* +** qinch_pat_all_u16: +** uqinch z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_pat_all_u16, svuint16_t, + z0 = svqinch_pat_u16 (z0, SV_ALL, 16), + z0 = svqinch_pat (z0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u32.c new file mode 100644 index 00000000000..8398c56892c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u32.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_n_1_u32_tied: +** uqinch w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_u32_tied, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqinch_pat (x0, SV_POW2, 1)) + +/* +** qinch_pat_n_1_u32_untied: +** mov w0, w1 +** uqinch w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_u32_untied, uint32_t, + x0 = svqinch_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqinch_pat (x1, SV_POW2, 1)) + +/* +** qinch_pat_n_2_u32: +** uqinch w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_2_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqinch_pat (x0, SV_POW2, 2)) + +/* +** qinch_pat_n_7_u32: +** uqinch w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_7_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqinch_pat (x0, SV_POW2, 7)) + +/* +** qinch_pat_n_15_u32: +** uqinch w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_15_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqinch_pat (x0, SV_POW2, 15)) + +/* +** qinch_pat_n_16_u32: +** uqinch w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_16_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqinch_pat (x0, SV_POW2, 16)) + +/* +** qinch_pat_n_vl1_u32: +** uqinch w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl1_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqinch_pat (x0, SV_VL1, 16)) + +/* +** qinch_pat_n_vl2_u32: +** uqinch w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl2_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqinch_pat (x0, SV_VL2, 16)) + +/* +** qinch_pat_n_vl3_u32: +** uqinch w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl3_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqinch_pat (x0, SV_VL3, 16)) + +/* +** qinch_pat_n_vl4_u32: +** uqinch w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl4_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqinch_pat (x0, SV_VL4, 16)) + +/* +** qinch_pat_n_vl5_u32: +** uqinch w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl5_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqinch_pat (x0, SV_VL5, 16)) + +/* +** qinch_pat_n_vl6_u32: +** uqinch w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl6_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqinch_pat (x0, SV_VL6, 16)) + +/* +** qinch_pat_n_vl7_u32: +** uqinch w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl7_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqinch_pat (x0, SV_VL7, 16)) + +/* +** qinch_pat_n_vl8_u32: +** uqinch w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl8_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqinch_pat (x0, SV_VL8, 16)) + +/* +** qinch_pat_n_vl16_u32: +** uqinch w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl16_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqinch_pat (x0, SV_VL16, 16)) + +/* +** qinch_pat_n_vl32_u32: +** uqinch w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl32_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqinch_pat (x0, SV_VL32, 16)) + +/* +** qinch_pat_n_vl64_u32: +** uqinch w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl64_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqinch_pat (x0, SV_VL64, 16)) + +/* +** qinch_pat_n_vl128_u32: +** uqinch w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl128_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqinch_pat (x0, SV_VL128, 16)) + +/* +** qinch_pat_n_vl256_u32: +** uqinch w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl256_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqinch_pat (x0, SV_VL256, 16)) + +/* +** qinch_pat_n_mul4_u32: +** uqinch w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul4_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqinch_pat (x0, SV_MUL4, 16)) + +/* +** qinch_pat_n_mul3_u32: +** uqinch w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul3_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqinch_pat (x0, SV_MUL3, 16)) + +/* +** qinch_pat_n_all_u32: +** uqinch w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_all_u32, uint32_t, + x0 = svqinch_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqinch_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u64.c new file mode 100644 index 00000000000..51722646d1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_pat_n_1_u64_tied: +** uqinch x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_u64_tied, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqinch_pat (x0, SV_POW2, 1)) + +/* +** qinch_pat_n_1_u64_untied: +** mov x0, x1 +** uqinch x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_1_u64_untied, uint64_t, + x0 = svqinch_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqinch_pat (x1, SV_POW2, 1)) + +/* +** qinch_pat_n_2_u64: +** uqinch x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_2_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqinch_pat (x0, SV_POW2, 2)) + +/* +** qinch_pat_n_7_u64: +** uqinch x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_7_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqinch_pat (x0, SV_POW2, 7)) + +/* +** qinch_pat_n_15_u64: +** uqinch x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_15_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqinch_pat (x0, SV_POW2, 15)) + +/* +** qinch_pat_n_16_u64: +** uqinch x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_16_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqinch_pat (x0, SV_POW2, 16)) + +/* +** qinch_pat_n_vl1_u64: +** uqinch x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl1_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqinch_pat (x0, SV_VL1, 16)) + +/* +** qinch_pat_n_vl2_u64: +** uqinch x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl2_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqinch_pat (x0, SV_VL2, 16)) + +/* +** qinch_pat_n_vl3_u64: +** uqinch x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl3_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqinch_pat (x0, SV_VL3, 16)) + +/* +** qinch_pat_n_vl4_u64: +** uqinch x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl4_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqinch_pat (x0, SV_VL4, 16)) + +/* +** qinch_pat_n_vl5_u64: +** uqinch x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl5_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqinch_pat (x0, SV_VL5, 16)) + +/* +** qinch_pat_n_vl6_u64: +** uqinch x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl6_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqinch_pat (x0, SV_VL6, 16)) + +/* +** qinch_pat_n_vl7_u64: +** uqinch x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl7_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqinch_pat (x0, SV_VL7, 16)) + +/* +** qinch_pat_n_vl8_u64: +** uqinch x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl8_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqinch_pat (x0, SV_VL8, 16)) + +/* +** qinch_pat_n_vl16_u64: +** uqinch x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl16_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqinch_pat (x0, SV_VL16, 16)) + +/* +** qinch_pat_n_vl32_u64: +** uqinch x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl32_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqinch_pat (x0, SV_VL32, 16)) + +/* +** qinch_pat_n_vl64_u64: +** uqinch x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl64_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqinch_pat (x0, SV_VL64, 16)) + +/* +** qinch_pat_n_vl128_u64: +** uqinch x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl128_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqinch_pat (x0, SV_VL128, 16)) + +/* +** qinch_pat_n_vl256_u64: +** uqinch x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_vl256_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqinch_pat (x0, SV_VL256, 16)) + +/* +** qinch_pat_n_mul4_u64: +** uqinch x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul4_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqinch_pat (x0, SV_MUL4, 16)) + +/* +** qinch_pat_n_mul3_u64: +** uqinch x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_mul3_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqinch_pat (x0, SV_MUL3, 16)) + +/* +** qinch_pat_n_all_u64: +** uqinch x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_pat_n_all_u64, uint64_t, + x0 = svqinch_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqinch_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s16.c new file mode 100644 index 00000000000..1f460db8e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s16.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_1_s16_tied: +** sqinch z0\.h +** ret +*/ +TEST_UNIFORM_Z (qinch_1_s16_tied, svint16_t, + z0 = svqinch_s16 (z0, 1), + z0 = svqinch (z0, 1)) + +/* +** qinch_1_s16_untied: +** movprfx z0, z1 +** sqinch z0\.h +** ret +*/ +TEST_UNIFORM_Z (qinch_1_s16_untied, svint16_t, + z0 = svqinch_s16 (z1, 1), + z0 = svqinch (z1, 1)) + +/* +** qinch_2_s16: +** sqinch z0\.h, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qinch_2_s16, svint16_t, + z0 = svqinch_s16 (z0, 2), + z0 = svqinch (z0, 2)) + +/* +** qinch_7_s16: +** sqinch z0\.h, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qinch_7_s16, svint16_t, + z0 = svqinch_s16 (z0, 7), + z0 = svqinch (z0, 7)) + +/* +** qinch_15_s16: +** sqinch z0\.h, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qinch_15_s16, svint16_t, + z0 = svqinch_s16 (z0, 15), + z0 = svqinch (z0, 15)) + +/* +** qinch_16_s16: +** sqinch z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_16_s16, svint16_t, + z0 = svqinch_s16 (z0, 16), + z0 = svqinch (z0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s32.c new file mode 100644 index 00000000000..a7b1aac8005 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_n_1_s32_tied: +** sqinch x0, w0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_s32_tied, int32_t, + x0 = svqinch_n_s32 (x0, 1), + x0 = svqinch (x0, 1)) + +/* +** qinch_n_1_s32_untied: +** mov w0, w1 +** sqinch x0, w0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_s32_untied, int32_t, + x0 = svqinch_n_s32 (x1, 1), + x0 = svqinch (x1, 1)) + +/* +** qinch_n_2_s32: +** sqinch x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_n_2_s32, int32_t, + x0 = svqinch_n_s32 (x0, 2), + x0 = svqinch (x0, 2)) + +/* +** qinch_n_7_s32: +** sqinch x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_n_7_s32, int32_t, + x0 = svqinch_n_s32 (x0, 7), + x0 = svqinch (x0, 7)) + +/* +** qinch_n_15_s32: +** sqinch x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_n_15_s32, int32_t, + x0 = svqinch_n_s32 (x0, 15), + x0 = svqinch (x0, 15)) + +/* +** qinch_n_16_s32: +** sqinch x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_n_16_s32, int32_t, + x0 = svqinch_n_s32 (x0, 16), + x0 = svqinch (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s64.c new file mode 100644 index 00000000000..74ac6a3dfcc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_n_1_s64_tied: +** sqinch x0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_s64_tied, int64_t, + x0 = svqinch_n_s64 (x0, 1), + x0 = svqinch (x0, 1)) + +/* +** qinch_n_1_s64_untied: +** mov x0, x1 +** sqinch x0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_s64_untied, int64_t, + x0 = svqinch_n_s64 (x1, 1), + x0 = svqinch (x1, 1)) + +/* +** qinch_n_2_s64: +** sqinch x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_n_2_s64, int64_t, + x0 = svqinch_n_s64 (x0, 2), + x0 = svqinch (x0, 2)) + +/* +** qinch_n_7_s64: +** sqinch x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_n_7_s64, int64_t, + x0 = svqinch_n_s64 (x0, 7), + x0 = svqinch (x0, 7)) + +/* +** qinch_n_15_s64: +** sqinch x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_n_15_s64, int64_t, + x0 = svqinch_n_s64 (x0, 15), + x0 = svqinch (x0, 15)) + +/* +** qinch_n_16_s64: +** sqinch x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_n_16_s64, int64_t, + x0 = svqinch_n_s64 (x0, 16), + x0 = svqinch (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u16.c new file mode 100644 index 00000000000..aa99058975f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u16.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_1_u16_tied: +** uqinch z0\.h +** ret +*/ +TEST_UNIFORM_Z (qinch_1_u16_tied, svuint16_t, + z0 = svqinch_u16 (z0, 1), + z0 = svqinch (z0, 1)) + +/* +** qinch_1_u16_untied: +** movprfx z0, z1 +** uqinch z0\.h +** ret +*/ +TEST_UNIFORM_Z (qinch_1_u16_untied, svuint16_t, + z0 = svqinch_u16 (z1, 1), + z0 = svqinch (z1, 1)) + +/* +** qinch_2_u16: +** uqinch z0\.h, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qinch_2_u16, svuint16_t, + z0 = svqinch_u16 (z0, 2), + z0 = svqinch (z0, 2)) + +/* +** qinch_7_u16: +** uqinch z0\.h, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qinch_7_u16, svuint16_t, + z0 = svqinch_u16 (z0, 7), + z0 = svqinch (z0, 7)) + +/* +** qinch_15_u16: +** uqinch z0\.h, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qinch_15_u16, svuint16_t, + z0 = svqinch_u16 (z0, 15), + z0 = svqinch (z0, 15)) + +/* +** qinch_16_u16: +** uqinch z0\.h, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qinch_16_u16, svuint16_t, + z0 = svqinch_u16 (z0, 16), + z0 = svqinch (z0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u32.c new file mode 100644 index 00000000000..396f95b2aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u32.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_n_1_u32_tied: +** uqinch w0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_u32_tied, uint32_t, + x0 = svqinch_n_u32 (x0, 1), + x0 = svqinch (x0, 1)) + +/* +** qinch_n_1_u32_untied: +** mov w0, w1 +** uqinch w0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_u32_untied, uint32_t, + x0 = svqinch_n_u32 (x1, 1), + x0 = svqinch (x1, 1)) + +/* +** qinch_n_2_u32: +** uqinch w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_n_2_u32, uint32_t, + x0 = svqinch_n_u32 (x0, 2), + x0 = svqinch (x0, 2)) + +/* +** qinch_n_7_u32: +** uqinch w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_n_7_u32, uint32_t, + x0 = svqinch_n_u32 (x0, 7), + x0 = svqinch (x0, 7)) + +/* +** qinch_n_15_u32: +** uqinch w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_n_15_u32, uint32_t, + x0 = svqinch_n_u32 (x0, 15), + x0 = svqinch (x0, 15)) + +/* +** qinch_n_16_u32: +** uqinch w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_n_16_u32, uint32_t, + x0 = svqinch_n_u32 (x0, 16), + x0 = svqinch (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u64.c new file mode 100644 index 00000000000..5a9231722e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qinch_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qinch_n_1_u64_tied: +** uqinch x0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_u64_tied, uint64_t, + x0 = svqinch_n_u64 (x0, 1), + x0 = svqinch (x0, 1)) + +/* +** qinch_n_1_u64_untied: +** mov x0, x1 +** uqinch x0 +** ret +*/ +TEST_UNIFORM_S (qinch_n_1_u64_untied, uint64_t, + x0 = svqinch_n_u64 (x1, 1), + x0 = svqinch (x1, 1)) + +/* +** qinch_n_2_u64: +** uqinch x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qinch_n_2_u64, uint64_t, + x0 = svqinch_n_u64 (x0, 2), + x0 = svqinch (x0, 2)) + +/* +** qinch_n_7_u64: +** uqinch x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qinch_n_7_u64, uint64_t, + x0 = svqinch_n_u64 (x0, 7), + x0 = svqinch (x0, 7)) + +/* +** qinch_n_15_u64: +** uqinch x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qinch_n_15_u64, uint64_t, + x0 = svqinch_n_u64 (x0, 15), + x0 = svqinch (x0, 15)) + +/* +** qinch_n_16_u64: +** uqinch x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qinch_n_16_u64, uint64_t, + x0 = svqinch_n_u64 (x0, 16), + x0 = svqinch (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s16.c new file mode 100644 index 00000000000..979b57476ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_s16_tied: +** sqincp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s16_tied, svint16_t, + z0 = svqincp_s16 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_s16_untied: +** movprfx z0, z1 +** sqincp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s16_untied, svint16_t, + z0 = svqincp_s16 (z1, p0), + z0 = svqincp (z1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s32.c new file mode 100644 index 00000000000..46ad51b018e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s32.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_s32_tied: +** sqincp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s32_tied, svint32_t, + z0 = svqincp_s32 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_s32_untied: +** movprfx z0, z1 +** sqincp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s32_untied, svint32_t, + z0 = svqincp_s32 (z1, p0), + z0 = svqincp (z1, p0)) + +/* +** qincp_n_s32_b8_tied: +** sqincp x0, p0\.b, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b8_tied, int32_t, + x0 = svqincp_n_s32_b8 (x0, p0), + x0 = svqincp_b8 (x0, p0)) + +/* +** qincp_n_s32_b8_untied: +** mov w0, w1 +** sqincp x0, p0\.b, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b8_untied, int32_t, + x0 = svqincp_n_s32_b8 (x1, p0), + x0 = svqincp_b8 (x1, p0)) + +/* +** qincp_n_s32_b16_tied: +** sqincp x0, p0\.h, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b16_tied, int32_t, + x0 = svqincp_n_s32_b16 (x0, p0), + x0 = svqincp_b16 (x0, p0)) + +/* +** qincp_n_s32_b16_untied: +** mov w0, w1 +** sqincp x0, p0\.h, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b16_untied, int32_t, + x0 = svqincp_n_s32_b16 (x1, p0), + x0 = svqincp_b16 (x1, p0)) + +/* +** qincp_n_s32_b32_tied: +** sqincp x0, p0\.s, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b32_tied, int32_t, + x0 = svqincp_n_s32_b32 (x0, p0), + x0 = svqincp_b32 (x0, p0)) + +/* +** qincp_n_s32_b32_untied: +** mov w0, w1 +** sqincp x0, p0\.s, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b32_untied, int32_t, + x0 = svqincp_n_s32_b32 (x1, p0), + x0 = svqincp_b32 (x1, p0)) + +/* +** qincp_n_s32_b64_tied: +** sqincp x0, p0\.d, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b64_tied, int32_t, + x0 = svqincp_n_s32_b64 (x0, p0), + x0 = svqincp_b64 (x0, p0)) + +/* +** qincp_n_s32_b64_untied: +** mov w0, w1 +** sqincp x0, p0\.d, w0 +** ret +*/ +TEST_UNIFORM_S (qincp_n_s32_b64_untied, int32_t, + x0 = svqincp_n_s32_b64 (x1, p0), + x0 = svqincp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s64.c new file mode 100644 index 00000000000..226502328e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_s64.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_s64_tied: +** sqincp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s64_tied, svint64_t, + z0 = svqincp_s64 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_s64_untied: +** movprfx z0, z1 +** sqincp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_s64_untied, svint64_t, + z0 = svqincp_s64 (z1, p0), + z0 = svqincp (z1, p0)) + +/* +** qincp_n_s64_b8_tied: +** sqincp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b8_tied, int64_t, + x0 = svqincp_n_s64_b8 (x0, p0), + x0 = svqincp_b8 (x0, p0)) + +/* +** qincp_n_s64_b8_untied: +** mov x0, x1 +** sqincp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b8_untied, int64_t, + x0 = svqincp_n_s64_b8 (x1, p0), + x0 = svqincp_b8 (x1, p0)) + +/* +** qincp_n_s64_b16_tied: +** sqincp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b16_tied, int64_t, + x0 = svqincp_n_s64_b16 (x0, p0), + x0 = svqincp_b16 (x0, p0)) + +/* +** qincp_n_s64_b16_untied: +** mov x0, x1 +** sqincp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b16_untied, int64_t, + x0 = svqincp_n_s64_b16 (x1, p0), + x0 = svqincp_b16 (x1, p0)) + +/* +** qincp_n_s64_b32_tied: +** sqincp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b32_tied, int64_t, + x0 = svqincp_n_s64_b32 (x0, p0), + x0 = svqincp_b32 (x0, p0)) + +/* +** qincp_n_s64_b32_untied: +** mov x0, x1 +** sqincp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b32_untied, int64_t, + x0 = svqincp_n_s64_b32 (x1, p0), + x0 = svqincp_b32 (x1, p0)) + +/* +** qincp_n_s64_b64_tied: +** sqincp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b64_tied, int64_t, + x0 = svqincp_n_s64_b64 (x0, p0), + x0 = svqincp_b64 (x0, p0)) + +/* +** qincp_n_s64_b64_untied: +** mov x0, x1 +** sqincp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_s64_b64_untied, int64_t, + x0 = svqincp_n_s64_b64 (x1, p0), + x0 = svqincp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u16.c new file mode 100644 index 00000000000..ecd84470c7a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u16.c @@ -0,0 +1,22 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_u16_tied: +** uqincp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u16_tied, svuint16_t, + z0 = svqincp_u16 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_u16_untied: +** movprfx z0, z1 +** uqincp z0\.h, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u16_untied, svuint16_t, + z0 = svqincp_u16 (z1, p0), + z0 = svqincp (z1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u32.c new file mode 100644 index 00000000000..011a2625359 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u32.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_u32_tied: +** uqincp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u32_tied, svuint32_t, + z0 = svqincp_u32 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_u32_untied: +** movprfx z0, z1 +** uqincp z0\.s, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u32_untied, svuint32_t, + z0 = svqincp_u32 (z1, p0), + z0 = svqincp (z1, p0)) + +/* +** qincp_n_u32_b8_tied: +** uqincp w0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b8_tied, uint32_t, + x0 = svqincp_n_u32_b8 (x0, p0), + x0 = svqincp_b8 (x0, p0)) + +/* +** qincp_n_u32_b8_untied: +** mov w0, w1 +** uqincp w0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b8_untied, uint32_t, + x0 = svqincp_n_u32_b8 (x1, p0), + x0 = svqincp_b8 (x1, p0)) + +/* +** qincp_n_u32_b16_tied: +** uqincp w0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b16_tied, uint32_t, + x0 = svqincp_n_u32_b16 (x0, p0), + x0 = svqincp_b16 (x0, p0)) + +/* +** qincp_n_u32_b16_untied: +** mov w0, w1 +** uqincp w0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b16_untied, uint32_t, + x0 = svqincp_n_u32_b16 (x1, p0), + x0 = svqincp_b16 (x1, p0)) + +/* +** qincp_n_u32_b32_tied: +** uqincp w0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b32_tied, uint32_t, + x0 = svqincp_n_u32_b32 (x0, p0), + x0 = svqincp_b32 (x0, p0)) + +/* +** qincp_n_u32_b32_untied: +** mov w0, w1 +** uqincp w0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b32_untied, uint32_t, + x0 = svqincp_n_u32_b32 (x1, p0), + x0 = svqincp_b32 (x1, p0)) + +/* +** qincp_n_u32_b64_tied: +** uqincp w0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b64_tied, uint32_t, + x0 = svqincp_n_u32_b64 (x0, p0), + x0 = svqincp_b64 (x0, p0)) + +/* +** qincp_n_u32_b64_untied: +** mov w0, w1 +** uqincp w0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_u32_b64_untied, uint32_t, + x0 = svqincp_n_u32_b64 (x1, p0), + x0 = svqincp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u64.c new file mode 100644 index 00000000000..761ac553a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincp_u64.c @@ -0,0 +1,98 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincp_u64_tied: +** uqincp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u64_tied, svuint64_t, + z0 = svqincp_u64 (z0, p0), + z0 = svqincp (z0, p0)) + +/* +** qincp_u64_untied: +** movprfx z0, z1 +** uqincp z0\.d, p0 +** ret +*/ +TEST_UNIFORM_Z (qincp_u64_untied, svuint64_t, + z0 = svqincp_u64 (z1, p0), + z0 = svqincp (z1, p0)) + +/* +** qincp_n_u64_b8_tied: +** uqincp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b8_tied, uint64_t, + x0 = svqincp_n_u64_b8 (x0, p0), + x0 = svqincp_b8 (x0, p0)) + +/* +** qincp_n_u64_b8_untied: +** mov x0, x1 +** uqincp x0, p0\.b +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b8_untied, uint64_t, + x0 = svqincp_n_u64_b8 (x1, p0), + x0 = svqincp_b8 (x1, p0)) + +/* +** qincp_n_u64_b16_tied: +** uqincp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b16_tied, uint64_t, + x0 = svqincp_n_u64_b16 (x0, p0), + x0 = svqincp_b16 (x0, p0)) + +/* +** qincp_n_u64_b16_untied: +** mov x0, x1 +** uqincp x0, p0\.h +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b16_untied, uint64_t, + x0 = svqincp_n_u64_b16 (x1, p0), + x0 = svqincp_b16 (x1, p0)) + +/* +** qincp_n_u64_b32_tied: +** uqincp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b32_tied, uint64_t, + x0 = svqincp_n_u64_b32 (x0, p0), + x0 = svqincp_b32 (x0, p0)) + +/* +** qincp_n_u64_b32_untied: +** mov x0, x1 +** uqincp x0, p0\.s +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b32_untied, uint64_t, + x0 = svqincp_n_u64_b32 (x1, p0), + x0 = svqincp_b32 (x1, p0)) + +/* +** qincp_n_u64_b64_tied: +** uqincp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b64_tied, uint64_t, + x0 = svqincp_n_u64_b64 (x0, p0), + x0 = svqincp_b64 (x0, p0)) + +/* +** qincp_n_u64_b64_untied: +** mov x0, x1 +** uqincp x0, p0\.d +** ret +*/ +TEST_UNIFORM_S (qincp_n_u64_b64_untied, uint64_t, + x0 = svqincp_n_u64_b64 (x1, p0), + x0 = svqincp_b64 (x1, p0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s32.c new file mode 100644 index 00000000000..6ceb003ab9e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s32.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_pat_1_s32_tied: +** sqincw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_1_s32_tied, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_POW2, 1), + z0 = svqincw_pat (z0, SV_POW2, 1)) + +/* +** qincw_pat_1_s32_untied: +** movprfx z0, z1 +** sqincw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_1_s32_untied, svint32_t, + z0 = svqincw_pat_s32 (z1, SV_POW2, 1), + z0 = svqincw_pat (z1, SV_POW2, 1)) + +/* +** qincw_pat_2_s32: +** sqincw z0\.s, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_2_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_POW2, 2), + z0 = svqincw_pat (z0, SV_POW2, 2)) + +/* +** qincw_pat_7_s32: +** sqincw z0\.s, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_7_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_POW2, 7), + z0 = svqincw_pat (z0, SV_POW2, 7)) + +/* +** qincw_pat_15_s32: +** sqincw z0\.s, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_15_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_POW2, 15), + z0 = svqincw_pat (z0, SV_POW2, 15)) + +/* +** qincw_pat_16_s32: +** sqincw z0\.s, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_16_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_POW2, 16), + z0 = svqincw_pat (z0, SV_POW2, 16)) + +/* +** qincw_pat_vl1_s32: +** sqincw z0\.s, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl1_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL1, 16), + z0 = svqincw_pat (z0, SV_VL1, 16)) + +/* +** qincw_pat_vl2_s32: +** sqincw z0\.s, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl2_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL2, 16), + z0 = svqincw_pat (z0, SV_VL2, 16)) + +/* +** qincw_pat_vl3_s32: +** sqincw z0\.s, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl3_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL3, 16), + z0 = svqincw_pat (z0, SV_VL3, 16)) + +/* +** qincw_pat_vl4_s32: +** sqincw z0\.s, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl4_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL4, 16), + z0 = svqincw_pat (z0, SV_VL4, 16)) + +/* +** qincw_pat_vl5_s32: +** sqincw z0\.s, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl5_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL5, 16), + z0 = svqincw_pat (z0, SV_VL5, 16)) + +/* +** qincw_pat_vl6_s32: +** sqincw z0\.s, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl6_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL6, 16), + z0 = svqincw_pat (z0, SV_VL6, 16)) + +/* +** qincw_pat_vl7_s32: +** sqincw z0\.s, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl7_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL7, 16), + z0 = svqincw_pat (z0, SV_VL7, 16)) + +/* +** qincw_pat_vl8_s32: +** sqincw z0\.s, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl8_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL8, 16), + z0 = svqincw_pat (z0, SV_VL8, 16)) + +/* +** qincw_pat_vl16_s32: +** sqincw z0\.s, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl16_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL16, 16), + z0 = svqincw_pat (z0, SV_VL16, 16)) + +/* +** qincw_pat_vl32_s32: +** sqincw z0\.s, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl32_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL32, 16), + z0 = svqincw_pat (z0, SV_VL32, 16)) + +/* +** qincw_pat_vl64_s32: +** sqincw z0\.s, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl64_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL64, 16), + z0 = svqincw_pat (z0, SV_VL64, 16)) + +/* +** qincw_pat_vl128_s32: +** sqincw z0\.s, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl128_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL128, 16), + z0 = svqincw_pat (z0, SV_VL128, 16)) + +/* +** qincw_pat_vl256_s32: +** sqincw z0\.s, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl256_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_VL256, 16), + z0 = svqincw_pat (z0, SV_VL256, 16)) + +/* +** qincw_pat_mul4_s32: +** sqincw z0\.s, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_mul4_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_MUL4, 16), + z0 = svqincw_pat (z0, SV_MUL4, 16)) + +/* +** qincw_pat_mul3_s32: +** sqincw z0\.s, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_mul3_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_MUL3, 16), + z0 = svqincw_pat (z0, SV_MUL3, 16)) + +/* +** qincw_pat_all_s32: +** sqincw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_all_s32, svint32_t, + z0 = svqincw_pat_s32 (z0, SV_ALL, 16), + z0 = svqincw_pat (z0, SV_ALL, 16)) + +/* +** qincw_pat_n_1_s32_tied: +** sqincw x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_s32_tied, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_POW2, 1), + x0 = svqincw_pat (x0, SV_POW2, 1)) + +/* +** qincw_pat_n_1_s32_untied: +** mov w0, w1 +** sqincw x0, w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_s32_untied, int32_t, + x0 = svqincw_pat_n_s32 (x1, SV_POW2, 1), + x0 = svqincw_pat (x1, SV_POW2, 1)) + +/* +** qincw_pat_n_2_s32: +** sqincw x0, w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_2_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_POW2, 2), + x0 = svqincw_pat (x0, SV_POW2, 2)) + +/* +** qincw_pat_n_7_s32: +** sqincw x0, w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_7_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_POW2, 7), + x0 = svqincw_pat (x0, SV_POW2, 7)) + +/* +** qincw_pat_n_15_s32: +** sqincw x0, w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_15_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_POW2, 15), + x0 = svqincw_pat (x0, SV_POW2, 15)) + +/* +** qincw_pat_n_16_s32: +** sqincw x0, w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_16_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_POW2, 16), + x0 = svqincw_pat (x0, SV_POW2, 16)) + +/* +** qincw_pat_n_vl1_s32: +** sqincw x0, w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl1_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL1, 16), + x0 = svqincw_pat (x0, SV_VL1, 16)) + +/* +** qincw_pat_n_vl2_s32: +** sqincw x0, w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl2_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL2, 16), + x0 = svqincw_pat (x0, SV_VL2, 16)) + +/* +** qincw_pat_n_vl3_s32: +** sqincw x0, w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl3_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL3, 16), + x0 = svqincw_pat (x0, SV_VL3, 16)) + +/* +** qincw_pat_n_vl4_s32: +** sqincw x0, w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl4_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL4, 16), + x0 = svqincw_pat (x0, SV_VL4, 16)) + +/* +** qincw_pat_n_vl5_s32: +** sqincw x0, w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl5_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL5, 16), + x0 = svqincw_pat (x0, SV_VL5, 16)) + +/* +** qincw_pat_n_vl6_s32: +** sqincw x0, w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl6_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL6, 16), + x0 = svqincw_pat (x0, SV_VL6, 16)) + +/* +** qincw_pat_n_vl7_s32: +** sqincw x0, w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl7_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL7, 16), + x0 = svqincw_pat (x0, SV_VL7, 16)) + +/* +** qincw_pat_n_vl8_s32: +** sqincw x0, w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl8_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL8, 16), + x0 = svqincw_pat (x0, SV_VL8, 16)) + +/* +** qincw_pat_n_vl16_s32: +** sqincw x0, w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl16_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL16, 16), + x0 = svqincw_pat (x0, SV_VL16, 16)) + +/* +** qincw_pat_n_vl32_s32: +** sqincw x0, w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl32_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL32, 16), + x0 = svqincw_pat (x0, SV_VL32, 16)) + +/* +** qincw_pat_n_vl64_s32: +** sqincw x0, w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl64_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL64, 16), + x0 = svqincw_pat (x0, SV_VL64, 16)) + +/* +** qincw_pat_n_vl128_s32: +** sqincw x0, w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl128_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL128, 16), + x0 = svqincw_pat (x0, SV_VL128, 16)) + +/* +** qincw_pat_n_vl256_s32: +** sqincw x0, w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl256_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_VL256, 16), + x0 = svqincw_pat (x0, SV_VL256, 16)) + +/* +** qincw_pat_n_mul4_s32: +** sqincw x0, w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul4_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_MUL4, 16), + x0 = svqincw_pat (x0, SV_MUL4, 16)) + +/* +** qincw_pat_n_mul3_s32: +** sqincw x0, w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul3_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_MUL3, 16), + x0 = svqincw_pat (x0, SV_MUL3, 16)) + +/* +** qincw_pat_n_all_s32: +** sqincw x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_all_s32, int32_t, + x0 = svqincw_pat_n_s32 (x0, SV_ALL, 16), + x0 = svqincw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s64.c new file mode 100644 index 00000000000..feebc25cc3c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_s64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_pat_n_1_s64_tied: +** sqincw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_s64_tied, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_POW2, 1), + x0 = svqincw_pat (x0, SV_POW2, 1)) + +/* +** qincw_pat_n_1_s64_untied: +** mov x0, x1 +** sqincw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_s64_untied, int64_t, + x0 = svqincw_pat_n_s64 (x1, SV_POW2, 1), + x0 = svqincw_pat (x1, SV_POW2, 1)) + +/* +** qincw_pat_n_2_s64: +** sqincw x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_2_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_POW2, 2), + x0 = svqincw_pat (x0, SV_POW2, 2)) + +/* +** qincw_pat_n_7_s64: +** sqincw x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_7_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_POW2, 7), + x0 = svqincw_pat (x0, SV_POW2, 7)) + +/* +** qincw_pat_n_15_s64: +** sqincw x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_15_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_POW2, 15), + x0 = svqincw_pat (x0, SV_POW2, 15)) + +/* +** qincw_pat_n_16_s64: +** sqincw x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_16_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_POW2, 16), + x0 = svqincw_pat (x0, SV_POW2, 16)) + +/* +** qincw_pat_n_vl1_s64: +** sqincw x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl1_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL1, 16), + x0 = svqincw_pat (x0, SV_VL1, 16)) + +/* +** qincw_pat_n_vl2_s64: +** sqincw x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl2_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL2, 16), + x0 = svqincw_pat (x0, SV_VL2, 16)) + +/* +** qincw_pat_n_vl3_s64: +** sqincw x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl3_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL3, 16), + x0 = svqincw_pat (x0, SV_VL3, 16)) + +/* +** qincw_pat_n_vl4_s64: +** sqincw x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl4_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL4, 16), + x0 = svqincw_pat (x0, SV_VL4, 16)) + +/* +** qincw_pat_n_vl5_s64: +** sqincw x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl5_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL5, 16), + x0 = svqincw_pat (x0, SV_VL5, 16)) + +/* +** qincw_pat_n_vl6_s64: +** sqincw x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl6_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL6, 16), + x0 = svqincw_pat (x0, SV_VL6, 16)) + +/* +** qincw_pat_n_vl7_s64: +** sqincw x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl7_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL7, 16), + x0 = svqincw_pat (x0, SV_VL7, 16)) + +/* +** qincw_pat_n_vl8_s64: +** sqincw x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl8_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL8, 16), + x0 = svqincw_pat (x0, SV_VL8, 16)) + +/* +** qincw_pat_n_vl16_s64: +** sqincw x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl16_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL16, 16), + x0 = svqincw_pat (x0, SV_VL16, 16)) + +/* +** qincw_pat_n_vl32_s64: +** sqincw x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl32_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL32, 16), + x0 = svqincw_pat (x0, SV_VL32, 16)) + +/* +** qincw_pat_n_vl64_s64: +** sqincw x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl64_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL64, 16), + x0 = svqincw_pat (x0, SV_VL64, 16)) + +/* +** qincw_pat_n_vl128_s64: +** sqincw x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl128_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL128, 16), + x0 = svqincw_pat (x0, SV_VL128, 16)) + +/* +** qincw_pat_n_vl256_s64: +** sqincw x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl256_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_VL256, 16), + x0 = svqincw_pat (x0, SV_VL256, 16)) + +/* +** qincw_pat_n_mul4_s64: +** sqincw x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul4_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_MUL4, 16), + x0 = svqincw_pat (x0, SV_MUL4, 16)) + +/* +** qincw_pat_n_mul3_s64: +** sqincw x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul3_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_MUL3, 16), + x0 = svqincw_pat (x0, SV_MUL3, 16)) + +/* +** qincw_pat_n_all_s64: +** sqincw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_all_s64, int64_t, + x0 = svqincw_pat_n_s64 (x0, SV_ALL, 16), + x0 = svqincw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u32.c new file mode 100644 index 00000000000..e08e91d0981 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u32.c @@ -0,0 +1,401 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_pat_1_u32_tied: +** uqincw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_1_u32_tied, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_POW2, 1), + z0 = svqincw_pat (z0, SV_POW2, 1)) + +/* +** qincw_pat_1_u32_untied: +** movprfx z0, z1 +** uqincw z0\.s, pow2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_1_u32_untied, svuint32_t, + z0 = svqincw_pat_u32 (z1, SV_POW2, 1), + z0 = svqincw_pat (z1, SV_POW2, 1)) + +/* +** qincw_pat_2_u32: +** uqincw z0\.s, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_2_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_POW2, 2), + z0 = svqincw_pat (z0, SV_POW2, 2)) + +/* +** qincw_pat_7_u32: +** uqincw z0\.s, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_7_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_POW2, 7), + z0 = svqincw_pat (z0, SV_POW2, 7)) + +/* +** qincw_pat_15_u32: +** uqincw z0\.s, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_15_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_POW2, 15), + z0 = svqincw_pat (z0, SV_POW2, 15)) + +/* +** qincw_pat_16_u32: +** uqincw z0\.s, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_16_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_POW2, 16), + z0 = svqincw_pat (z0, SV_POW2, 16)) + +/* +** qincw_pat_vl1_u32: +** uqincw z0\.s, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl1_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL1, 16), + z0 = svqincw_pat (z0, SV_VL1, 16)) + +/* +** qincw_pat_vl2_u32: +** uqincw z0\.s, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl2_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL2, 16), + z0 = svqincw_pat (z0, SV_VL2, 16)) + +/* +** qincw_pat_vl3_u32: +** uqincw z0\.s, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl3_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL3, 16), + z0 = svqincw_pat (z0, SV_VL3, 16)) + +/* +** qincw_pat_vl4_u32: +** uqincw z0\.s, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl4_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL4, 16), + z0 = svqincw_pat (z0, SV_VL4, 16)) + +/* +** qincw_pat_vl5_u32: +** uqincw z0\.s, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl5_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL5, 16), + z0 = svqincw_pat (z0, SV_VL5, 16)) + +/* +** qincw_pat_vl6_u32: +** uqincw z0\.s, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl6_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL6, 16), + z0 = svqincw_pat (z0, SV_VL6, 16)) + +/* +** qincw_pat_vl7_u32: +** uqincw z0\.s, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl7_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL7, 16), + z0 = svqincw_pat (z0, SV_VL7, 16)) + +/* +** qincw_pat_vl8_u32: +** uqincw z0\.s, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl8_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL8, 16), + z0 = svqincw_pat (z0, SV_VL8, 16)) + +/* +** qincw_pat_vl16_u32: +** uqincw z0\.s, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl16_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL16, 16), + z0 = svqincw_pat (z0, SV_VL16, 16)) + +/* +** qincw_pat_vl32_u32: +** uqincw z0\.s, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl32_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL32, 16), + z0 = svqincw_pat (z0, SV_VL32, 16)) + +/* +** qincw_pat_vl64_u32: +** uqincw z0\.s, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl64_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL64, 16), + z0 = svqincw_pat (z0, SV_VL64, 16)) + +/* +** qincw_pat_vl128_u32: +** uqincw z0\.s, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl128_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL128, 16), + z0 = svqincw_pat (z0, SV_VL128, 16)) + +/* +** qincw_pat_vl256_u32: +** uqincw z0\.s, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_vl256_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_VL256, 16), + z0 = svqincw_pat (z0, SV_VL256, 16)) + +/* +** qincw_pat_mul4_u32: +** uqincw z0\.s, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_mul4_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_MUL4, 16), + z0 = svqincw_pat (z0, SV_MUL4, 16)) + +/* +** qincw_pat_mul3_u32: +** uqincw z0\.s, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_mul3_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_MUL3, 16), + z0 = svqincw_pat (z0, SV_MUL3, 16)) + +/* +** qincw_pat_all_u32: +** uqincw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_pat_all_u32, svuint32_t, + z0 = svqincw_pat_u32 (z0, SV_ALL, 16), + z0 = svqincw_pat (z0, SV_ALL, 16)) + +/* +** qincw_pat_n_1_u32_tied: +** uqincw w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_u32_tied, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_POW2, 1), + x0 = svqincw_pat (x0, SV_POW2, 1)) + +/* +** qincw_pat_n_1_u32_untied: +** mov w0, w1 +** uqincw w0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_u32_untied, uint32_t, + x0 = svqincw_pat_n_u32 (x1, SV_POW2, 1), + x0 = svqincw_pat (x1, SV_POW2, 1)) + +/* +** qincw_pat_n_2_u32: +** uqincw w0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_2_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_POW2, 2), + x0 = svqincw_pat (x0, SV_POW2, 2)) + +/* +** qincw_pat_n_7_u32: +** uqincw w0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_7_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_POW2, 7), + x0 = svqincw_pat (x0, SV_POW2, 7)) + +/* +** qincw_pat_n_15_u32: +** uqincw w0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_15_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_POW2, 15), + x0 = svqincw_pat (x0, SV_POW2, 15)) + +/* +** qincw_pat_n_16_u32: +** uqincw w0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_16_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_POW2, 16), + x0 = svqincw_pat (x0, SV_POW2, 16)) + +/* +** qincw_pat_n_vl1_u32: +** uqincw w0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl1_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL1, 16), + x0 = svqincw_pat (x0, SV_VL1, 16)) + +/* +** qincw_pat_n_vl2_u32: +** uqincw w0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl2_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL2, 16), + x0 = svqincw_pat (x0, SV_VL2, 16)) + +/* +** qincw_pat_n_vl3_u32: +** uqincw w0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl3_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL3, 16), + x0 = svqincw_pat (x0, SV_VL3, 16)) + +/* +** qincw_pat_n_vl4_u32: +** uqincw w0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl4_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL4, 16), + x0 = svqincw_pat (x0, SV_VL4, 16)) + +/* +** qincw_pat_n_vl5_u32: +** uqincw w0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl5_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL5, 16), + x0 = svqincw_pat (x0, SV_VL5, 16)) + +/* +** qincw_pat_n_vl6_u32: +** uqincw w0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl6_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL6, 16), + x0 = svqincw_pat (x0, SV_VL6, 16)) + +/* +** qincw_pat_n_vl7_u32: +** uqincw w0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl7_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL7, 16), + x0 = svqincw_pat (x0, SV_VL7, 16)) + +/* +** qincw_pat_n_vl8_u32: +** uqincw w0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl8_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL8, 16), + x0 = svqincw_pat (x0, SV_VL8, 16)) + +/* +** qincw_pat_n_vl16_u32: +** uqincw w0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl16_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL16, 16), + x0 = svqincw_pat (x0, SV_VL16, 16)) + +/* +** qincw_pat_n_vl32_u32: +** uqincw w0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl32_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL32, 16), + x0 = svqincw_pat (x0, SV_VL32, 16)) + +/* +** qincw_pat_n_vl64_u32: +** uqincw w0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl64_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL64, 16), + x0 = svqincw_pat (x0, SV_VL64, 16)) + +/* +** qincw_pat_n_vl128_u32: +** uqincw w0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl128_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL128, 16), + x0 = svqincw_pat (x0, SV_VL128, 16)) + +/* +** qincw_pat_n_vl256_u32: +** uqincw w0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl256_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_VL256, 16), + x0 = svqincw_pat (x0, SV_VL256, 16)) + +/* +** qincw_pat_n_mul4_u32: +** uqincw w0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul4_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_MUL4, 16), + x0 = svqincw_pat (x0, SV_MUL4, 16)) + +/* +** qincw_pat_n_mul3_u32: +** uqincw w0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul3_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_MUL3, 16), + x0 = svqincw_pat (x0, SV_MUL3, 16)) + +/* +** qincw_pat_n_all_u32: +** uqincw w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_all_u32, uint32_t, + x0 = svqincw_pat_n_u32 (x0, SV_ALL, 16), + x0 = svqincw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u64.c new file mode 100644 index 00000000000..a2ac9ee7252 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_pat_u64.c @@ -0,0 +1,202 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_pat_n_1_u64_tied: +** uqincw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_u64_tied, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_POW2, 1), + x0 = svqincw_pat (x0, SV_POW2, 1)) + +/* +** qincw_pat_n_1_u64_untied: +** mov x0, x1 +** uqincw x0, pow2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_1_u64_untied, uint64_t, + x0 = svqincw_pat_n_u64 (x1, SV_POW2, 1), + x0 = svqincw_pat (x1, SV_POW2, 1)) + +/* +** qincw_pat_n_2_u64: +** uqincw x0, pow2, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_2_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_POW2, 2), + x0 = svqincw_pat (x0, SV_POW2, 2)) + +/* +** qincw_pat_n_7_u64: +** uqincw x0, pow2, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_7_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_POW2, 7), + x0 = svqincw_pat (x0, SV_POW2, 7)) + +/* +** qincw_pat_n_15_u64: +** uqincw x0, pow2, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_15_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_POW2, 15), + x0 = svqincw_pat (x0, SV_POW2, 15)) + +/* +** qincw_pat_n_16_u64: +** uqincw x0, pow2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_16_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_POW2, 16), + x0 = svqincw_pat (x0, SV_POW2, 16)) + +/* +** qincw_pat_n_vl1_u64: +** uqincw x0, vl1, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl1_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL1, 16), + x0 = svqincw_pat (x0, SV_VL1, 16)) + +/* +** qincw_pat_n_vl2_u64: +** uqincw x0, vl2, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl2_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL2, 16), + x0 = svqincw_pat (x0, SV_VL2, 16)) + +/* +** qincw_pat_n_vl3_u64: +** uqincw x0, vl3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl3_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL3, 16), + x0 = svqincw_pat (x0, SV_VL3, 16)) + +/* +** qincw_pat_n_vl4_u64: +** uqincw x0, vl4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl4_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL4, 16), + x0 = svqincw_pat (x0, SV_VL4, 16)) + +/* +** qincw_pat_n_vl5_u64: +** uqincw x0, vl5, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl5_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL5, 16), + x0 = svqincw_pat (x0, SV_VL5, 16)) + +/* +** qincw_pat_n_vl6_u64: +** uqincw x0, vl6, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl6_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL6, 16), + x0 = svqincw_pat (x0, SV_VL6, 16)) + +/* +** qincw_pat_n_vl7_u64: +** uqincw x0, vl7, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl7_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL7, 16), + x0 = svqincw_pat (x0, SV_VL7, 16)) + +/* +** qincw_pat_n_vl8_u64: +** uqincw x0, vl8, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl8_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL8, 16), + x0 = svqincw_pat (x0, SV_VL8, 16)) + +/* +** qincw_pat_n_vl16_u64: +** uqincw x0, vl16, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl16_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL16, 16), + x0 = svqincw_pat (x0, SV_VL16, 16)) + +/* +** qincw_pat_n_vl32_u64: +** uqincw x0, vl32, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl32_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL32, 16), + x0 = svqincw_pat (x0, SV_VL32, 16)) + +/* +** qincw_pat_n_vl64_u64: +** uqincw x0, vl64, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl64_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL64, 16), + x0 = svqincw_pat (x0, SV_VL64, 16)) + +/* +** qincw_pat_n_vl128_u64: +** uqincw x0, vl128, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl128_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL128, 16), + x0 = svqincw_pat (x0, SV_VL128, 16)) + +/* +** qincw_pat_n_vl256_u64: +** uqincw x0, vl256, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_vl256_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_VL256, 16), + x0 = svqincw_pat (x0, SV_VL256, 16)) + +/* +** qincw_pat_n_mul4_u64: +** uqincw x0, mul4, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul4_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_MUL4, 16), + x0 = svqincw_pat (x0, SV_MUL4, 16)) + +/* +** qincw_pat_n_mul3_u64: +** uqincw x0, mul3, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_mul3_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_MUL3, 16), + x0 = svqincw_pat (x0, SV_MUL3, 16)) + +/* +** qincw_pat_n_all_u64: +** uqincw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_pat_n_all_u64, uint64_t, + x0 = svqincw_pat_n_u64 (x0, SV_ALL, 16), + x0 = svqincw_pat (x0, SV_ALL, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s32.c new file mode 100644 index 00000000000..031824acfe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s32.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_1_s32_tied: +** sqincw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qincw_1_s32_tied, svint32_t, + z0 = svqincw_s32 (z0, 1), + z0 = svqincw (z0, 1)) + +/* +** qincw_1_s32_untied: +** movprfx z0, z1 +** sqincw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qincw_1_s32_untied, svint32_t, + z0 = svqincw_s32 (z1, 1), + z0 = svqincw (z1, 1)) + +/* +** qincw_2_s32: +** sqincw z0\.s, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincw_2_s32, svint32_t, + z0 = svqincw_s32 (z0, 2), + z0 = svqincw (z0, 2)) + +/* +** qincw_7_s32: +** sqincw z0\.s, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincw_7_s32, svint32_t, + z0 = svqincw_s32 (z0, 7), + z0 = svqincw (z0, 7)) + +/* +** qincw_15_s32: +** sqincw z0\.s, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincw_15_s32, svint32_t, + z0 = svqincw_s32 (z0, 15), + z0 = svqincw (z0, 15)) + +/* +** qincw_16_s32: +** sqincw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_16_s32, svint32_t, + z0 = svqincw_s32 (z0, 16), + z0 = svqincw (z0, 16)) + +/* +** qincw_n_1_s32_tied: +** sqincw x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_s32_tied, int32_t, + x0 = svqincw_n_s32 (x0, 1), + x0 = svqincw (x0, 1)) + +/* +** qincw_n_1_s32_untied: +** mov w0, w1 +** sqincw x0, w0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_s32_untied, int32_t, + x0 = svqincw_n_s32 (x1, 1), + x0 = svqincw (x1, 1)) + +/* +** qincw_n_2_s32: +** sqincw x0, w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_n_2_s32, int32_t, + x0 = svqincw_n_s32 (x0, 2), + x0 = svqincw (x0, 2)) + +/* +** qincw_n_7_s32: +** sqincw x0, w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_n_7_s32, int32_t, + x0 = svqincw_n_s32 (x0, 7), + x0 = svqincw (x0, 7)) + +/* +** qincw_n_15_s32: +** sqincw x0, w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_n_15_s32, int32_t, + x0 = svqincw_n_s32 (x0, 15), + x0 = svqincw (x0, 15)) + +/* +** qincw_n_16_s32: +** sqincw x0, w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_n_16_s32, int32_t, + x0 = svqincw_n_s32 (x0, 16), + x0 = svqincw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s64.c new file mode 100644 index 00000000000..df61f909fcc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_s64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_n_1_s64_tied: +** sqincw x0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_s64_tied, int64_t, + x0 = svqincw_n_s64 (x0, 1), + x0 = svqincw (x0, 1)) + +/* +** qincw_n_1_s64_untied: +** mov x0, x1 +** sqincw x0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_s64_untied, int64_t, + x0 = svqincw_n_s64 (x1, 1), + x0 = svqincw (x1, 1)) + +/* +** qincw_n_2_s64: +** sqincw x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_n_2_s64, int64_t, + x0 = svqincw_n_s64 (x0, 2), + x0 = svqincw (x0, 2)) + +/* +** qincw_n_7_s64: +** sqincw x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_n_7_s64, int64_t, + x0 = svqincw_n_s64 (x0, 7), + x0 = svqincw (x0, 7)) + +/* +** qincw_n_15_s64: +** sqincw x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_n_15_s64, int64_t, + x0 = svqincw_n_s64 (x0, 15), + x0 = svqincw (x0, 15)) + +/* +** qincw_n_16_s64: +** sqincw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_n_16_s64, int64_t, + x0 = svqincw_n_s64 (x0, 16), + x0 = svqincw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u32.c new file mode 100644 index 00000000000..65a446ab6c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u32.c @@ -0,0 +1,113 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_1_u32_tied: +** uqincw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qincw_1_u32_tied, svuint32_t, + z0 = svqincw_u32 (z0, 1), + z0 = svqincw (z0, 1)) + +/* +** qincw_1_u32_untied: +** movprfx z0, z1 +** uqincw z0\.s +** ret +*/ +TEST_UNIFORM_Z (qincw_1_u32_untied, svuint32_t, + z0 = svqincw_u32 (z1, 1), + z0 = svqincw (z1, 1)) + +/* +** qincw_2_u32: +** uqincw z0\.s, all, mul #2 +** ret +*/ +TEST_UNIFORM_Z (qincw_2_u32, svuint32_t, + z0 = svqincw_u32 (z0, 2), + z0 = svqincw (z0, 2)) + +/* +** qincw_7_u32: +** uqincw z0\.s, all, mul #7 +** ret +*/ +TEST_UNIFORM_Z (qincw_7_u32, svuint32_t, + z0 = svqincw_u32 (z0, 7), + z0 = svqincw (z0, 7)) + +/* +** qincw_15_u32: +** uqincw z0\.s, all, mul #15 +** ret +*/ +TEST_UNIFORM_Z (qincw_15_u32, svuint32_t, + z0 = svqincw_u32 (z0, 15), + z0 = svqincw (z0, 15)) + +/* +** qincw_16_u32: +** uqincw z0\.s, all, mul #16 +** ret +*/ +TEST_UNIFORM_Z (qincw_16_u32, svuint32_t, + z0 = svqincw_u32 (z0, 16), + z0 = svqincw (z0, 16)) + +/* +** qincw_n_1_u32_tied: +** uqincw w0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_u32_tied, uint32_t, + x0 = svqincw_n_u32 (x0, 1), + x0 = svqincw (x0, 1)) + +/* +** qincw_n_1_u32_untied: +** mov w0, w1 +** uqincw w0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_u32_untied, uint32_t, + x0 = svqincw_n_u32 (x1, 1), + x0 = svqincw (x1, 1)) + +/* +** qincw_n_2_u32: +** uqincw w0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_n_2_u32, uint32_t, + x0 = svqincw_n_u32 (x0, 2), + x0 = svqincw (x0, 2)) + +/* +** qincw_n_7_u32: +** uqincw w0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_n_7_u32, uint32_t, + x0 = svqincw_n_u32 (x0, 7), + x0 = svqincw (x0, 7)) + +/* +** qincw_n_15_u32: +** uqincw w0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_n_15_u32, uint32_t, + x0 = svqincw_n_u32 (x0, 15), + x0 = svqincw (x0, 15)) + +/* +** qincw_n_16_u32: +** uqincw w0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_n_16_u32, uint32_t, + x0 = svqincw_n_u32 (x0, 16), + x0 = svqincw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u64.c new file mode 100644 index 00000000000..806a79945e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qincw_u64.c @@ -0,0 +1,58 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qincw_n_1_u64_tied: +** uqincw x0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_u64_tied, uint64_t, + x0 = svqincw_n_u64 (x0, 1), + x0 = svqincw (x0, 1)) + +/* +** qincw_n_1_u64_untied: +** mov x0, x1 +** uqincw x0 +** ret +*/ +TEST_UNIFORM_S (qincw_n_1_u64_untied, uint64_t, + x0 = svqincw_n_u64 (x1, 1), + x0 = svqincw (x1, 1)) + +/* +** qincw_n_2_u64: +** uqincw x0, all, mul #2 +** ret +*/ +TEST_UNIFORM_S (qincw_n_2_u64, uint64_t, + x0 = svqincw_n_u64 (x0, 2), + x0 = svqincw (x0, 2)) + +/* +** qincw_n_7_u64: +** uqincw x0, all, mul #7 +** ret +*/ +TEST_UNIFORM_S (qincw_n_7_u64, uint64_t, + x0 = svqincw_n_u64 (x0, 7), + x0 = svqincw (x0, 7)) + +/* +** qincw_n_15_u64: +** uqincw x0, all, mul #15 +** ret +*/ +TEST_UNIFORM_S (qincw_n_15_u64, uint64_t, + x0 = svqincw_n_u64 (x0, 15), + x0 = svqincw (x0, 15)) + +/* +** qincw_n_16_u64: +** uqincw x0, all, mul #16 +** ret +*/ +TEST_UNIFORM_S (qincw_n_16_u64, uint64_t, + x0 = svqincw_n_u64 (x0, 16), + x0 = svqincw (x0, 16)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s16.c new file mode 100644 index 00000000000..8dd8381dc15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s16.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_s16_tied1: +** sqsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_s16_tied1, svint16_t, + z0 = svqsub_s16 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_s16_tied2: +** sqsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_s16_tied2, svint16_t, + z0 = svqsub_s16 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_s16_untied: +** sqsub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_s16_untied, svint16_t, + z0 = svqsub_s16 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_s16_tied1: +** mov (z[0-9]+\.h), w0 +** sqsub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s16_tied1, svint16_t, int16_t, + z0 = svqsub_n_s16 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_s16_untied: +** mov (z[0-9]+\.h), w0 +** sqsub z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s16_untied, svint16_t, int16_t, + z0 = svqsub_n_s16 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_s16_tied1: +** sqsub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s16_tied1, svint16_t, + z0 = svqsub_n_s16 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_s16_untied: +** movprfx z0, z1 +** sqsub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s16_untied, svint16_t, + z0 = svqsub_n_s16 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_s16: +** sqsub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_s16, svint16_t, + z0 = svqsub_n_s16 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_s16: +** sqsub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_s16, svint16_t, + z0 = svqsub_n_s16 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_s16: +** sqsub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_s16, svint16_t, + z0 = svqsub_n_s16 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_s16: +** sqadd z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_s16, svint16_t, + z0 = svqsub_n_s16 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_s16: +** sqadd z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_s16, svint16_t, + z0 = svqsub_n_s16 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_s16: +** sqadd z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_s16, svint16_t, + z0 = svqsub_n_s16 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s32.c new file mode 100644 index 00000000000..920736aecdf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s32.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_s32_tied1: +** sqsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_s32_tied1, svint32_t, + z0 = svqsub_s32 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_s32_tied2: +** sqsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_s32_tied2, svint32_t, + z0 = svqsub_s32 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_s32_untied: +** sqsub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_s32_untied, svint32_t, + z0 = svqsub_s32 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_s32_tied1: +** mov (z[0-9]+\.s), w0 +** sqsub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s32_tied1, svint32_t, int32_t, + z0 = svqsub_n_s32 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_s32_untied: +** mov (z[0-9]+\.s), w0 +** sqsub z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s32_untied, svint32_t, int32_t, + z0 = svqsub_n_s32 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_s32_tied1: +** sqsub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s32_tied1, svint32_t, + z0 = svqsub_n_s32 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_s32_untied: +** movprfx z0, z1 +** sqsub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s32_untied, svint32_t, + z0 = svqsub_n_s32 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_s32: +** sqsub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_s32, svint32_t, + z0 = svqsub_n_s32 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_s32: +** sqsub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_s32, svint32_t, + z0 = svqsub_n_s32 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_s32: +** sqsub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_s32, svint32_t, + z0 = svqsub_n_s32 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_s32: +** sqadd z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_s32, svint32_t, + z0 = svqsub_n_s32 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_s32: +** sqadd z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_s32, svint32_t, + z0 = svqsub_n_s32 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_s32: +** sqadd z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_s32, svint32_t, + z0 = svqsub_n_s32 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s64.c new file mode 100644 index 00000000000..3d0fc2bccf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s64.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_s64_tied1: +** sqsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_s64_tied1, svint64_t, + z0 = svqsub_s64 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_s64_tied2: +** sqsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_s64_tied2, svint64_t, + z0 = svqsub_s64 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_s64_untied: +** sqsub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_s64_untied, svint64_t, + z0 = svqsub_s64 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_x0_s64_tied1: +** mov (z[0-9]+\.d), x0 +** sqsub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_x0_s64_tied1, svint64_t, int64_t, + z0 = svqsub_n_s64 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_x0_s64_untied: +** mov (z[0-9]+\.d), x0 +** sqsub z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_x0_s64_untied, svint64_t, int64_t, + z0 = svqsub_n_s64 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_s64_tied1: +** sqsub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s64_tied1, svint64_t, + z0 = svqsub_n_s64 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_s64_untied: +** movprfx z0, z1 +** sqsub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s64_untied, svint64_t, + z0 = svqsub_n_s64 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_s64: +** sqsub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_s64, svint64_t, + z0 = svqsub_n_s64 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_s64: +** sqsub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_s64, svint64_t, + z0 = svqsub_n_s64 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_s64: +** sqsub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_s64, svint64_t, + z0 = svqsub_n_s64 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_s64: +** sqadd z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_s64, svint64_t, + z0 = svqsub_n_s64 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_s64: +** sqadd z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_s64, svint64_t, + z0 = svqsub_n_s64 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_s64: +** sqadd z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_s64, svint64_t, + z0 = svqsub_n_s64 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s8.c new file mode 100644 index 00000000000..3e7e84c77cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_s8.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_s8_tied1: +** sqsub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_s8_tied1, svint8_t, + z0 = svqsub_s8 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_s8_tied2: +** sqsub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_s8_tied2, svint8_t, + z0 = svqsub_s8 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_s8_untied: +** sqsub z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_s8_untied, svint8_t, + z0 = svqsub_s8 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_s8_tied1: +** mov (z[0-9]+\.b), w0 +** sqsub z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s8_tied1, svint8_t, int8_t, + z0 = svqsub_n_s8 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_s8_untied: +** mov (z[0-9]+\.b), w0 +** sqsub z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_s8_untied, svint8_t, int8_t, + z0 = svqsub_n_s8 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_s8_tied1: +** sqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s8_tied1, svint8_t, + z0 = svqsub_n_s8 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_s8_untied: +** movprfx z0, z1 +** sqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_s8_untied, svint8_t, + z0 = svqsub_n_s8 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_s8: +** sqsub z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_s8, svint8_t, + z0 = svqsub_n_s8 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_s8: +** sqadd z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_s8, svint8_t, + z0 = svqsub_n_s8 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_s8: +** sqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_s8, svint8_t, + z0 = svqsub_n_s8 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_s8: +** sqadd z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_s8, svint8_t, + z0 = svqsub_n_s8 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_s8: +** sqadd z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_s8, svint8_t, + z0 = svqsub_n_s8 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_s8: +** sqadd z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_s8, svint8_t, + z0 = svqsub_n_s8 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u16.c new file mode 100644 index 00000000000..6d4d68e207e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u16.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_u16_tied1: +** uqsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_u16_tied1, svuint16_t, + z0 = svqsub_u16 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_u16_tied2: +** uqsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_u16_tied2, svuint16_t, + z0 = svqsub_u16 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_u16_untied: +** uqsub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_u16_untied, svuint16_t, + z0 = svqsub_u16 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** uqsub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svqsub_n_u16 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** uqsub z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u16_untied, svuint16_t, uint16_t, + z0 = svqsub_n_u16 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_u16_tied1: +** uqsub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u16_tied1, svuint16_t, + z0 = svqsub_n_u16 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_u16_untied: +** movprfx z0, z1 +** uqsub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u16_untied, svuint16_t, + z0 = svqsub_n_u16 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_u16: +** uqsub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_u16: +** uqsub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_u16: +** uqsub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_u16: +** mov (z[0-9]+)\.b, #-1 +** uqsub z0\.h, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_u16: +** mov (z[0-9]+\.h), #-127 +** uqsub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_u16: +** mov (z[0-9]+\.h), #-128 +** uqsub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_u16, svuint16_t, + z0 = svqsub_n_u16 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u32.c new file mode 100644 index 00000000000..9c93cfc453b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u32.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_u32_tied1: +** uqsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_u32_tied1, svuint32_t, + z0 = svqsub_u32 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_u32_tied2: +** uqsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_u32_tied2, svuint32_t, + z0 = svqsub_u32 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_u32_untied: +** uqsub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_u32_untied, svuint32_t, + z0 = svqsub_u32 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** uqsub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svqsub_n_u32 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** uqsub z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u32_untied, svuint32_t, uint32_t, + z0 = svqsub_n_u32 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_u32_tied1: +** uqsub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u32_tied1, svuint32_t, + z0 = svqsub_n_u32 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_u32_untied: +** movprfx z0, z1 +** uqsub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u32_untied, svuint32_t, + z0 = svqsub_n_u32 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_u32: +** uqsub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_u32: +** uqsub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_u32: +** uqsub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_u32: +** mov (z[0-9]+)\.b, #-1 +** uqsub z0\.s, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_u32: +** mov (z[0-9]+\.s), #-127 +** uqsub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_u32: +** mov (z[0-9]+\.s), #-128 +** uqsub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_u32, svuint32_t, + z0 = svqsub_n_u32 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u64.c new file mode 100644 index 00000000000..6109b5f29de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u64.c @@ -0,0 +1,126 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_u64_tied1: +** uqsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_u64_tied1, svuint64_t, + z0 = svqsub_u64 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_u64_tied2: +** uqsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_u64_tied2, svuint64_t, + z0 = svqsub_u64 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_u64_untied: +** uqsub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_u64_untied, svuint64_t, + z0 = svqsub_u64 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** uqsub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svqsub_n_u64 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** uqsub z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_x0_u64_untied, svuint64_t, uint64_t, + z0 = svqsub_n_u64 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_u64_tied1: +** uqsub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u64_tied1, svuint64_t, + z0 = svqsub_n_u64 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_u64_untied: +** movprfx z0, z1 +** uqsub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u64_untied, svuint64_t, + z0 = svqsub_n_u64 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_u64: +** uqsub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_u64: +** uqsub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_u64: +** uqsub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_u64: +** mov (z[0-9]+)\.b, #-1 +** uqsub z0\.d, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_u64: +** mov (z[0-9]+\.d), #-127 +** uqsub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_u64: +** mov (z[0-9]+\.d), #-128 +** uqsub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_u64, svuint64_t, + z0 = svqsub_n_u64 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u8.c new file mode 100644 index 00000000000..40aa74e8d97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/qsub_u8.c @@ -0,0 +1,123 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** qsub_u8_tied1: +** uqsub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_u8_tied1, svuint8_t, + z0 = svqsub_u8 (z0, z1), + z0 = svqsub (z0, z1)) + +/* +** qsub_u8_tied2: +** uqsub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_u8_tied2, svuint8_t, + z0 = svqsub_u8 (z1, z0), + z0 = svqsub (z1, z0)) + +/* +** qsub_u8_untied: +** uqsub z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (qsub_u8_untied, svuint8_t, + z0 = svqsub_u8 (z1, z2), + z0 = svqsub (z1, z2)) + +/* +** qsub_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** uqsub z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svqsub_n_u8 (z0, x0), + z0 = svqsub (z0, x0)) + +/* +** qsub_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** uqsub z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (qsub_w0_u8_untied, svuint8_t, uint8_t, + z0 = svqsub_n_u8 (z1, x0), + z0 = svqsub (z1, x0)) + +/* +** qsub_1_u8_tied1: +** uqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u8_tied1, svuint8_t, + z0 = svqsub_n_u8 (z0, 1), + z0 = svqsub (z0, 1)) + +/* +** qsub_1_u8_untied: +** movprfx z0, z1 +** uqsub z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (qsub_1_u8_untied, svuint8_t, + z0 = svqsub_n_u8 (z1, 1), + z0 = svqsub (z1, 1)) + +/* +** qsub_127_u8: +** uqsub z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (qsub_127_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, 127), + z0 = svqsub (z0, 127)) + +/* +** qsub_128_u8: +** uqsub z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_128_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, 128), + z0 = svqsub (z0, 128)) + +/* +** qsub_255_u8: +** uqsub z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_255_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, 255), + z0 = svqsub (z0, 255)) + +/* +** qsub_m1_u8: +** uqsub z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (qsub_m1_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, -1), + z0 = svqsub (z0, -1)) + +/* +** qsub_m127_u8: +** uqsub z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (qsub_m127_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, -127), + z0 = svqsub (z0, -127)) + +/* +** qsub_m128_u8: +** uqsub z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (qsub_m128_u8, svuint8_t, + z0 = svqsub_n_u8 (z0, -128), + z0 = svqsub (z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c new file mode 100644 index 00000000000..4f794f60074 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_s16_m_tied12: +** rbit z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_m_tied12, svint16_t, + z0 = svrbit_s16_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_s16_m_tied1: +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_m_tied1, svint16_t, + z0 = svrbit_s16_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_m_tied2, svint16_t, + z0 = svrbit_s16_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_s16_m_untied: +** movprfx z0, z2 +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_m_untied, svint16_t, + z0 = svrbit_s16_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** rbit z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_z_tied1, svint16_t, + z0 = svrbit_s16_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_z_untied, svint16_t, + z0 = svrbit_s16_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_s16_x_tied1: +** rbit z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_x_tied1, svint16_t, + z0 = svrbit_s16_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_s16_x_untied: +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_s16_x_untied, svint16_t, + z0 = svrbit_s16_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c new file mode 100644 index 00000000000..8b5e1a463a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_s32_m_tied12: +** rbit z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_m_tied12, svint32_t, + z0 = svrbit_s32_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_s32_m_tied1: +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_m_tied1, svint32_t, + z0 = svrbit_s32_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_m_tied2, svint32_t, + z0 = svrbit_s32_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_s32_m_untied: +** movprfx z0, z2 +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_m_untied, svint32_t, + z0 = svrbit_s32_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** rbit z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_z_tied1, svint32_t, + z0 = svrbit_s32_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_z_untied, svint32_t, + z0 = svrbit_s32_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_s32_x_tied1: +** rbit z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_x_tied1, svint32_t, + z0 = svrbit_s32_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_s32_x_untied: +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_s32_x_untied, svint32_t, + z0 = svrbit_s32_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c new file mode 100644 index 00000000000..cec27a42182 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_s64_m_tied12: +** rbit z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_m_tied12, svint64_t, + z0 = svrbit_s64_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_s64_m_tied1: +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_m_tied1, svint64_t, + z0 = svrbit_s64_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** rbit z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_m_tied2, svint64_t, + z0 = svrbit_s64_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_s64_m_untied: +** movprfx z0, z2 +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_m_untied, svint64_t, + z0 = svrbit_s64_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** rbit z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_z_tied1, svint64_t, + z0 = svrbit_s64_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_z_untied, svint64_t, + z0 = svrbit_s64_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_s64_x_tied1: +** rbit z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_x_tied1, svint64_t, + z0 = svrbit_s64_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_s64_x_untied: +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_s64_x_untied, svint64_t, + z0 = svrbit_s64_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c new file mode 100644 index 00000000000..9c152116acf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_s8_m_tied12: +** rbit z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_m_tied12, svint8_t, + z0 = svrbit_s8_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_s8_m_tied1: +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_m_tied1, svint8_t, + z0 = svrbit_s8_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_m_tied2, svint8_t, + z0 = svrbit_s8_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_s8_m_untied: +** movprfx z0, z2 +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_m_untied, svint8_t, + z0 = svrbit_s8_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_s8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** rbit z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_z_tied1, svint8_t, + z0 = svrbit_s8_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_s8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_z_untied, svint8_t, + z0 = svrbit_s8_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_s8_x_tied1: +** rbit z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_x_tied1, svint8_t, + z0 = svrbit_s8_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_s8_x_untied: +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_s8_x_untied, svint8_t, + z0 = svrbit_s8_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c new file mode 100644 index 00000000000..001ef2bf075 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_u16_m_tied12: +** rbit z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_m_tied12, svuint16_t, + z0 = svrbit_u16_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_u16_m_tied1: +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_m_tied1, svuint16_t, + z0 = svrbit_u16_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_m_tied2, svuint16_t, + z0 = svrbit_u16_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_u16_m_untied: +** movprfx z0, z2 +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_m_untied, svuint16_t, + z0 = svrbit_u16_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** rbit z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_z_tied1, svuint16_t, + z0 = svrbit_u16_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_z_untied, svuint16_t, + z0 = svrbit_u16_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_u16_x_tied1: +** rbit z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_x_tied1, svuint16_t, + z0 = svrbit_u16_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_u16_x_untied: +** rbit z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rbit_u16_x_untied, svuint16_t, + z0 = svrbit_u16_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c new file mode 100644 index 00000000000..4d91e954d7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_u32_m_tied12: +** rbit z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_m_tied12, svuint32_t, + z0 = svrbit_u32_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_u32_m_tied1: +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_m_tied1, svuint32_t, + z0 = svrbit_u32_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_m_tied2, svuint32_t, + z0 = svrbit_u32_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_u32_m_untied: +** movprfx z0, z2 +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_m_untied, svuint32_t, + z0 = svrbit_u32_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** rbit z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_z_tied1, svuint32_t, + z0 = svrbit_u32_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_z_untied, svuint32_t, + z0 = svrbit_u32_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_u32_x_tied1: +** rbit z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_x_tied1, svuint32_t, + z0 = svrbit_u32_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_u32_x_untied: +** rbit z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rbit_u32_x_untied, svuint32_t, + z0 = svrbit_u32_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c new file mode 100644 index 00000000000..77f88d116a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_u64_m_tied12: +** rbit z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_m_tied12, svuint64_t, + z0 = svrbit_u64_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_u64_m_tied1: +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_m_tied1, svuint64_t, + z0 = svrbit_u64_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** rbit z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_m_tied2, svuint64_t, + z0 = svrbit_u64_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_u64_m_untied: +** movprfx z0, z2 +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_m_untied, svuint64_t, + z0 = svrbit_u64_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** rbit z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_z_tied1, svuint64_t, + z0 = svrbit_u64_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_z_untied, svuint64_t, + z0 = svrbit_u64_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_u64_x_tied1: +** rbit z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_x_tied1, svuint64_t, + z0 = svrbit_u64_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_u64_x_untied: +** rbit z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rbit_u64_x_untied, svuint64_t, + z0 = svrbit_u64_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c new file mode 100644 index 00000000000..fa347e4c7e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rbit_u8_m_tied12: +** rbit z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_m_tied12, svuint8_t, + z0 = svrbit_u8_m (z0, p0, z0), + z0 = svrbit_m (z0, p0, z0)) + +/* +** rbit_u8_m_tied1: +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_m_tied1, svuint8_t, + z0 = svrbit_u8_m (z0, p0, z1), + z0 = svrbit_m (z0, p0, z1)) + +/* +** rbit_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** rbit z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_m_tied2, svuint8_t, + z0 = svrbit_u8_m (z1, p0, z0), + z0 = svrbit_m (z1, p0, z0)) + +/* +** rbit_u8_m_untied: +** movprfx z0, z2 +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_m_untied, svuint8_t, + z0 = svrbit_u8_m (z2, p0, z1), + z0 = svrbit_m (z2, p0, z1)) + +/* +** rbit_u8_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.b, p0/z, \1\.b +** rbit z0\.b, p0/m, \1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_z_tied1, svuint8_t, + z0 = svrbit_u8_z (p0, z0), + z0 = svrbit_z (p0, z0)) + +/* +** rbit_u8_z_untied: +** movprfx z0\.b, p0/z, z1\.b +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_z_untied, svuint8_t, + z0 = svrbit_u8_z (p0, z1), + z0 = svrbit_z (p0, z1)) + +/* +** rbit_u8_x_tied1: +** rbit z0\.b, p0/m, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_x_tied1, svuint8_t, + z0 = svrbit_u8_x (p0, z0), + z0 = svrbit_x (p0, z0)) + +/* +** rbit_u8_x_untied: +** rbit z0\.b, p0/m, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rbit_u8_x_untied, svuint8_t, + z0 = svrbit_u8_x (p0, z1), + z0 = svrbit_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rdffr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rdffr_1.c new file mode 100644 index 00000000000..5564e967fcf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rdffr_1.c @@ -0,0 +1,59 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** setffr_rdffr_1: +** ptrue p0\.b, all +** ret +*/ +TEST_UNIFORM_P_SINGLE (setffr_rdffr_1, + svsetffr (); + p0 = svrdffr ()); + +/* +** setffr_rdffr_2: +** ret +*/ +TEST_UNIFORM_P_SINGLE (setffr_rdffr_2, + svsetffr (); + svrdffr ()); + +/* +** setffr_rdffr_3: +** ptrue p0\.b, all +** ret +*/ +TEST_UNIFORM_P_SINGLE (setffr_rdffr_3, + svsetffr (); + svsetffr (); + svrdffr (); + p0 = svrdffr ()); + +/* +** wrffr_rdffr_1: +** mov p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P_SINGLE (wrffr_rdffr_1, + svwrffr (p1); + p0 = svrdffr ()); + +/* +** wrffr_rdffr_2: +** ret +*/ +TEST_UNIFORM_P_SINGLE (wrffr_rdffr_2, + svwrffr (p1); + svrdffr ()); + +/* +** wrffr_rdffr_3: +** mov p0\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P_SINGLE (wrffr_rdffr_3, + svwrffr (p1); + svwrffr (p2); + svrdffr (); + p0 = svrdffr ()); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f16.c new file mode 100644 index 00000000000..d0cd8281a8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpe_f16_tied1: +** frecpe z0\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (recpe_f16_tied1, svfloat16_t, + z0 = svrecpe_f16 (z0), + z0 = svrecpe (z0)) + +/* +** recpe_f16_untied: +** frecpe z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpe_f16_untied, svfloat16_t, + z0 = svrecpe_f16 (z1), + z0 = svrecpe (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f32.c new file mode 100644 index 00000000000..013ed8c4328 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpe_f32_tied1: +** frecpe z0\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (recpe_f32_tied1, svfloat32_t, + z0 = svrecpe_f32 (z0), + z0 = svrecpe (z0)) + +/* +** recpe_f32_untied: +** frecpe z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpe_f32_untied, svfloat32_t, + z0 = svrecpe_f32 (z1), + z0 = svrecpe (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f64.c new file mode 100644 index 00000000000..40b3df29248 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpe_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpe_f64_tied1: +** frecpe z0\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (recpe_f64_tied1, svfloat64_t, + z0 = svrecpe_f64 (z0), + z0 = svrecpe (z0)) + +/* +** recpe_f64_untied: +** frecpe z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpe_f64_untied, svfloat64_t, + z0 = svrecpe_f64 (z1), + z0 = svrecpe (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f16.c new file mode 100644 index 00000000000..e35c5c545ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recps_f16_tied1: +** frecps z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recps_f16_tied1, svfloat16_t, + z0 = svrecps_f16 (z0, z1), + z0 = svrecps (z0, z1)) + +/* +** recps_f16_tied2: +** frecps z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (recps_f16_tied2, svfloat16_t, + z0 = svrecps_f16 (z1, z0), + z0 = svrecps (z1, z0)) + +/* +** recps_f16_untied: +** frecps z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (recps_f16_untied, svfloat16_t, + z0 = svrecps_f16 (z1, z2), + z0 = svrecps (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f32.c new file mode 100644 index 00000000000..3f3aa203e83 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recps_f32_tied1: +** frecps z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recps_f32_tied1, svfloat32_t, + z0 = svrecps_f32 (z0, z1), + z0 = svrecps (z0, z1)) + +/* +** recps_f32_tied2: +** frecps z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (recps_f32_tied2, svfloat32_t, + z0 = svrecps_f32 (z1, z0), + z0 = svrecps (z1, z0)) + +/* +** recps_f32_untied: +** frecps z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (recps_f32_untied, svfloat32_t, + z0 = svrecps_f32 (z1, z2), + z0 = svrecps (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f64.c new file mode 100644 index 00000000000..eca421d5e1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recps_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recps_f64_tied1: +** frecps z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recps_f64_tied1, svfloat64_t, + z0 = svrecps_f64 (z0, z1), + z0 = svrecps (z0, z1)) + +/* +** recps_f64_tied2: +** frecps z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (recps_f64_tied2, svfloat64_t, + z0 = svrecps_f64 (z1, z0), + z0 = svrecps (z1, z0)) + +/* +** recps_f64_untied: +** frecps z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (recps_f64_untied, svfloat64_t, + z0 = svrecps_f64 (z1, z2), + z0 = svrecps (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c new file mode 100644 index 00000000000..2dd7ada2c21 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpx_f16_m_tied12: +** frecpx z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_m_tied12, svfloat16_t, + z0 = svrecpx_f16_m (z0, p0, z0), + z0 = svrecpx_m (z0, p0, z0)) + +/* +** recpx_f16_m_tied1: +** frecpx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_m_tied1, svfloat16_t, + z0 = svrecpx_f16_m (z0, p0, z1), + z0 = svrecpx_m (z0, p0, z1)) + +/* +** recpx_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frecpx z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_m_tied2, svfloat16_t, + z0 = svrecpx_f16_m (z1, p0, z0), + z0 = svrecpx_m (z1, p0, z0)) + +/* +** recpx_f16_m_untied: +** movprfx z0, z2 +** frecpx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_m_untied, svfloat16_t, + z0 = svrecpx_f16_m (z2, p0, z1), + z0 = svrecpx_m (z2, p0, z1)) + +/* +** recpx_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frecpx z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_z_tied1, svfloat16_t, + z0 = svrecpx_f16_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frecpx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_z_untied, svfloat16_t, + z0 = svrecpx_f16_z (p0, z1), + z0 = svrecpx_z (p0, z1)) + +/* +** recpx_f16_x_tied1: +** frecpx z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_x_tied1, svfloat16_t, + z0 = svrecpx_f16_x (p0, z0), + z0 = svrecpx_x (p0, z0)) + +/* +** recpx_f16_x_untied: +** frecpx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (recpx_f16_x_untied, svfloat16_t, + z0 = svrecpx_f16_x (p0, z1), + z0 = svrecpx_x (p0, z1)) + +/* +** ptrue_recpx_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f16_x_tied1, svfloat16_t, + z0 = svrecpx_f16_x (svptrue_b16 (), z0), + z0 = svrecpx_x (svptrue_b16 (), z0)) + +/* +** ptrue_recpx_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f16_x_untied, svfloat16_t, + z0 = svrecpx_f16_x (svptrue_b16 (), z1), + z0 = svrecpx_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c new file mode 100644 index 00000000000..6364fb83ba3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpx_f32_m_tied12: +** frecpx z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_m_tied12, svfloat32_t, + z0 = svrecpx_f32_m (z0, p0, z0), + z0 = svrecpx_m (z0, p0, z0)) + +/* +** recpx_f32_m_tied1: +** frecpx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_m_tied1, svfloat32_t, + z0 = svrecpx_f32_m (z0, p0, z1), + z0 = svrecpx_m (z0, p0, z1)) + +/* +** recpx_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frecpx z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_m_tied2, svfloat32_t, + z0 = svrecpx_f32_m (z1, p0, z0), + z0 = svrecpx_m (z1, p0, z0)) + +/* +** recpx_f32_m_untied: +** movprfx z0, z2 +** frecpx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_m_untied, svfloat32_t, + z0 = svrecpx_f32_m (z2, p0, z1), + z0 = svrecpx_m (z2, p0, z1)) + +/* +** recpx_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frecpx z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_z_tied1, svfloat32_t, + z0 = svrecpx_f32_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frecpx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_z_untied, svfloat32_t, + z0 = svrecpx_f32_z (p0, z1), + z0 = svrecpx_z (p0, z1)) + +/* +** recpx_f32_x_tied1: +** frecpx z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_x_tied1, svfloat32_t, + z0 = svrecpx_f32_x (p0, z0), + z0 = svrecpx_x (p0, z0)) + +/* +** recpx_f32_x_untied: +** frecpx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (recpx_f32_x_untied, svfloat32_t, + z0 = svrecpx_f32_x (p0, z1), + z0 = svrecpx_x (p0, z1)) + +/* +** ptrue_recpx_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f32_x_tied1, svfloat32_t, + z0 = svrecpx_f32_x (svptrue_b32 (), z0), + z0 = svrecpx_x (svptrue_b32 (), z0)) + +/* +** ptrue_recpx_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f32_x_untied, svfloat32_t, + z0 = svrecpx_f32_x (svptrue_b32 (), z1), + z0 = svrecpx_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c new file mode 100644 index 00000000000..ca5232331db --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** recpx_f64_m_tied12: +** frecpx z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_m_tied12, svfloat64_t, + z0 = svrecpx_f64_m (z0, p0, z0), + z0 = svrecpx_m (z0, p0, z0)) + +/* +** recpx_f64_m_tied1: +** frecpx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_m_tied1, svfloat64_t, + z0 = svrecpx_f64_m (z0, p0, z1), + z0 = svrecpx_m (z0, p0, z1)) + +/* +** recpx_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frecpx z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_m_tied2, svfloat64_t, + z0 = svrecpx_f64_m (z1, p0, z0), + z0 = svrecpx_m (z1, p0, z0)) + +/* +** recpx_f64_m_untied: +** movprfx z0, z2 +** frecpx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_m_untied, svfloat64_t, + z0 = svrecpx_f64_m (z2, p0, z1), + z0 = svrecpx_m (z2, p0, z1)) + +/* +** recpx_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frecpx z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_z_tied1, svfloat64_t, + z0 = svrecpx_f64_z (p0, z0), + z0 = svrecpx_z (p0, z0)) + +/* +** recpx_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frecpx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_z_untied, svfloat64_t, + z0 = svrecpx_f64_z (p0, z1), + z0 = svrecpx_z (p0, z1)) + +/* +** recpx_f64_x_tied1: +** frecpx z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_x_tied1, svfloat64_t, + z0 = svrecpx_f64_x (p0, z0), + z0 = svrecpx_x (p0, z0)) + +/* +** recpx_f64_x_untied: +** frecpx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (recpx_f64_x_untied, svfloat64_t, + z0 = svrecpx_f64_x (p0, z1), + z0 = svrecpx_x (p0, z1)) + +/* +** ptrue_recpx_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f64_x_tied1, svfloat64_t, + z0 = svrecpx_f64_x (svptrue_b64 (), z0), + z0 = svrecpx_x (svptrue_b64 (), z0)) + +/* +** ptrue_recpx_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_recpx_f64_x_untied, svfloat64_t, + z0 = svrecpx_f64_x (svptrue_b64 (), z1), + z0 = svrecpx_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f16.c new file mode 100644 index 00000000000..0890700dd75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f16.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_f16_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_f16_tied1, svfloat16_t, svfloat16_t, + z0_res = svreinterpret_f16_f16 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_f16_untied, svfloat16_t, svfloat16_t, + z0 = svreinterpret_f16_f16 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_f32_tied1, svfloat16_t, svfloat32_t, + z0_res = svreinterpret_f16_f32 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_f32_untied, svfloat16_t, svfloat32_t, + z0 = svreinterpret_f16_f32 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_f64_tied1, svfloat16_t, svfloat64_t, + z0_res = svreinterpret_f16_f64 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_f64_untied, svfloat16_t, svfloat64_t, + z0 = svreinterpret_f16_f64 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_s8_tied1, svfloat16_t, svint8_t, + z0_res = svreinterpret_f16_s8 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_s8_untied, svfloat16_t, svint8_t, + z0 = svreinterpret_f16_s8 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_s16_tied1, svfloat16_t, svint16_t, + z0_res = svreinterpret_f16_s16 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_s16_untied, svfloat16_t, svint16_t, + z0 = svreinterpret_f16_s16 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_s32_tied1, svfloat16_t, svint32_t, + z0_res = svreinterpret_f16_s32 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_s32_untied, svfloat16_t, svint32_t, + z0 = svreinterpret_f16_s32 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_s64_tied1, svfloat16_t, svint64_t, + z0_res = svreinterpret_f16_s64 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_s64_untied, svfloat16_t, svint64_t, + z0 = svreinterpret_f16_s64 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_u8_tied1, svfloat16_t, svuint8_t, + z0_res = svreinterpret_f16_u8 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_u8_untied, svfloat16_t, svuint8_t, + z0 = svreinterpret_f16_u8 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_u16_tied1, svfloat16_t, svuint16_t, + z0_res = svreinterpret_f16_u16 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_u16_untied, svfloat16_t, svuint16_t, + z0 = svreinterpret_f16_u16 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_u32_tied1, svfloat16_t, svuint32_t, + z0_res = svreinterpret_f16_u32 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_u32_untied, svfloat16_t, svuint32_t, + z0 = svreinterpret_f16_u32 (z4), + z0 = svreinterpret_f16 (z4)) + +/* +** reinterpret_f16_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f16_u64_tied1, svfloat16_t, svuint64_t, + z0_res = svreinterpret_f16_u64 (z0), + z0_res = svreinterpret_f16 (z0)) + +/* +** reinterpret_f16_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f16_u64_untied, svfloat16_t, svuint64_t, + z0 = svreinterpret_f16_u64 (z4), + z0 = svreinterpret_f16 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f32.c new file mode 100644 index 00000000000..aed31c8ec93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f32.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_f32_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_f16_tied1, svfloat32_t, svfloat16_t, + z0_res = svreinterpret_f32_f16 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_f16_untied, svfloat32_t, svfloat16_t, + z0 = svreinterpret_f32_f16 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_f32_tied1, svfloat32_t, svfloat32_t, + z0_res = svreinterpret_f32_f32 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_f32_untied, svfloat32_t, svfloat32_t, + z0 = svreinterpret_f32_f32 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_f64_tied1, svfloat32_t, svfloat64_t, + z0_res = svreinterpret_f32_f64 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_f64_untied, svfloat32_t, svfloat64_t, + z0 = svreinterpret_f32_f64 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_s8_tied1, svfloat32_t, svint8_t, + z0_res = svreinterpret_f32_s8 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_s8_untied, svfloat32_t, svint8_t, + z0 = svreinterpret_f32_s8 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_s16_tied1, svfloat32_t, svint16_t, + z0_res = svreinterpret_f32_s16 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_s16_untied, svfloat32_t, svint16_t, + z0 = svreinterpret_f32_s16 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_s32_tied1, svfloat32_t, svint32_t, + z0_res = svreinterpret_f32_s32 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_s32_untied, svfloat32_t, svint32_t, + z0 = svreinterpret_f32_s32 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_s64_tied1, svfloat32_t, svint64_t, + z0_res = svreinterpret_f32_s64 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_s64_untied, svfloat32_t, svint64_t, + z0 = svreinterpret_f32_s64 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_u8_tied1, svfloat32_t, svuint8_t, + z0_res = svreinterpret_f32_u8 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_u8_untied, svfloat32_t, svuint8_t, + z0 = svreinterpret_f32_u8 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_u16_tied1, svfloat32_t, svuint16_t, + z0_res = svreinterpret_f32_u16 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_u16_untied, svfloat32_t, svuint16_t, + z0 = svreinterpret_f32_u16 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_u32_tied1, svfloat32_t, svuint32_t, + z0_res = svreinterpret_f32_u32 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_u32_untied, svfloat32_t, svuint32_t, + z0 = svreinterpret_f32_u32 (z4), + z0 = svreinterpret_f32 (z4)) + +/* +** reinterpret_f32_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f32_u64_tied1, svfloat32_t, svuint64_t, + z0_res = svreinterpret_f32_u64 (z0), + z0_res = svreinterpret_f32 (z0)) + +/* +** reinterpret_f32_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f32_u64_untied, svfloat32_t, svuint64_t, + z0 = svreinterpret_f32_u64 (z4), + z0 = svreinterpret_f32 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f64.c new file mode 100644 index 00000000000..92c68eeeb54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_f64.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_f64_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_f16_tied1, svfloat64_t, svfloat16_t, + z0_res = svreinterpret_f64_f16 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_f16_untied, svfloat64_t, svfloat16_t, + z0 = svreinterpret_f64_f16 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_f32_tied1, svfloat64_t, svfloat32_t, + z0_res = svreinterpret_f64_f32 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_f32_untied, svfloat64_t, svfloat32_t, + z0 = svreinterpret_f64_f32 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_f64_tied1, svfloat64_t, svfloat64_t, + z0_res = svreinterpret_f64_f64 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_f64_untied, svfloat64_t, svfloat64_t, + z0 = svreinterpret_f64_f64 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_s8_tied1, svfloat64_t, svint8_t, + z0_res = svreinterpret_f64_s8 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_s8_untied, svfloat64_t, svint8_t, + z0 = svreinterpret_f64_s8 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_s16_tied1, svfloat64_t, svint16_t, + z0_res = svreinterpret_f64_s16 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_s16_untied, svfloat64_t, svint16_t, + z0 = svreinterpret_f64_s16 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_s32_tied1, svfloat64_t, svint32_t, + z0_res = svreinterpret_f64_s32 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_s32_untied, svfloat64_t, svint32_t, + z0 = svreinterpret_f64_s32 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_s64_tied1, svfloat64_t, svint64_t, + z0_res = svreinterpret_f64_s64 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_s64_untied, svfloat64_t, svint64_t, + z0 = svreinterpret_f64_s64 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_u8_tied1, svfloat64_t, svuint8_t, + z0_res = svreinterpret_f64_u8 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_u8_untied, svfloat64_t, svuint8_t, + z0 = svreinterpret_f64_u8 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_u16_tied1, svfloat64_t, svuint16_t, + z0_res = svreinterpret_f64_u16 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_u16_untied, svfloat64_t, svuint16_t, + z0 = svreinterpret_f64_u16 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_u32_tied1, svfloat64_t, svuint32_t, + z0_res = svreinterpret_f64_u32 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_u32_untied, svfloat64_t, svuint32_t, + z0 = svreinterpret_f64_u32 (z4), + z0 = svreinterpret_f64 (z4)) + +/* +** reinterpret_f64_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_f64_u64_tied1, svfloat64_t, svuint64_t, + z0_res = svreinterpret_f64_u64 (z0), + z0_res = svreinterpret_f64 (z0)) + +/* +** reinterpret_f64_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_f64_u64_untied, svfloat64_t, svuint64_t, + z0 = svreinterpret_f64_u64 (z4), + z0 = svreinterpret_f64 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s16.c new file mode 100644 index 00000000000..e5d9178ba62 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s16.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_s16_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_f16_tied1, svint16_t, svfloat16_t, + z0_res = svreinterpret_s16_f16 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_f16_untied, svint16_t, svfloat16_t, + z0 = svreinterpret_s16_f16 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_f32_tied1, svint16_t, svfloat32_t, + z0_res = svreinterpret_s16_f32 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_f32_untied, svint16_t, svfloat32_t, + z0 = svreinterpret_s16_f32 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_f64_tied1, svint16_t, svfloat64_t, + z0_res = svreinterpret_s16_f64 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_f64_untied, svint16_t, svfloat64_t, + z0 = svreinterpret_s16_f64 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_s8_tied1, svint16_t, svint8_t, + z0_res = svreinterpret_s16_s8 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_s8_untied, svint16_t, svint8_t, + z0 = svreinterpret_s16_s8 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_s16_tied1, svint16_t, svint16_t, + z0_res = svreinterpret_s16_s16 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_s16_untied, svint16_t, svint16_t, + z0 = svreinterpret_s16_s16 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_s32_tied1, svint16_t, svint32_t, + z0_res = svreinterpret_s16_s32 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_s32_untied, svint16_t, svint32_t, + z0 = svreinterpret_s16_s32 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_s64_tied1, svint16_t, svint64_t, + z0_res = svreinterpret_s16_s64 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_s64_untied, svint16_t, svint64_t, + z0 = svreinterpret_s16_s64 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_u8_tied1, svint16_t, svuint8_t, + z0_res = svreinterpret_s16_u8 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_u8_untied, svint16_t, svuint8_t, + z0 = svreinterpret_s16_u8 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_u16_tied1, svint16_t, svuint16_t, + z0_res = svreinterpret_s16_u16 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_u16_untied, svint16_t, svuint16_t, + z0 = svreinterpret_s16_u16 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_u32_tied1, svint16_t, svuint32_t, + z0_res = svreinterpret_s16_u32 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_u32_untied, svint16_t, svuint32_t, + z0 = svreinterpret_s16_u32 (z4), + z0 = svreinterpret_s16 (z4)) + +/* +** reinterpret_s16_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s16_u64_tied1, svint16_t, svuint64_t, + z0_res = svreinterpret_s16_u64 (z0), + z0_res = svreinterpret_s16 (z0)) + +/* +** reinterpret_s16_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s16_u64_untied, svint16_t, svuint64_t, + z0 = svreinterpret_s16_u64 (z4), + z0 = svreinterpret_s16 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s32.c new file mode 100644 index 00000000000..f188104e5e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s32.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_s32_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_f16_tied1, svint32_t, svfloat16_t, + z0_res = svreinterpret_s32_f16 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_f16_untied, svint32_t, svfloat16_t, + z0 = svreinterpret_s32_f16 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_f32_tied1, svint32_t, svfloat32_t, + z0_res = svreinterpret_s32_f32 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_f32_untied, svint32_t, svfloat32_t, + z0 = svreinterpret_s32_f32 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_f64_tied1, svint32_t, svfloat64_t, + z0_res = svreinterpret_s32_f64 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_f64_untied, svint32_t, svfloat64_t, + z0 = svreinterpret_s32_f64 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_s8_tied1, svint32_t, svint8_t, + z0_res = svreinterpret_s32_s8 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_s8_untied, svint32_t, svint8_t, + z0 = svreinterpret_s32_s8 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_s16_tied1, svint32_t, svint16_t, + z0_res = svreinterpret_s32_s16 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_s16_untied, svint32_t, svint16_t, + z0 = svreinterpret_s32_s16 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_s32_tied1, svint32_t, svint32_t, + z0_res = svreinterpret_s32_s32 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_s32_untied, svint32_t, svint32_t, + z0 = svreinterpret_s32_s32 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_s64_tied1, svint32_t, svint64_t, + z0_res = svreinterpret_s32_s64 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_s64_untied, svint32_t, svint64_t, + z0 = svreinterpret_s32_s64 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_u8_tied1, svint32_t, svuint8_t, + z0_res = svreinterpret_s32_u8 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_u8_untied, svint32_t, svuint8_t, + z0 = svreinterpret_s32_u8 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_u16_tied1, svint32_t, svuint16_t, + z0_res = svreinterpret_s32_u16 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_u16_untied, svint32_t, svuint16_t, + z0 = svreinterpret_s32_u16 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_u32_tied1, svint32_t, svuint32_t, + z0_res = svreinterpret_s32_u32 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_u32_untied, svint32_t, svuint32_t, + z0 = svreinterpret_s32_u32 (z4), + z0 = svreinterpret_s32 (z4)) + +/* +** reinterpret_s32_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s32_u64_tied1, svint32_t, svuint64_t, + z0_res = svreinterpret_s32_u64 (z0), + z0_res = svreinterpret_s32 (z0)) + +/* +** reinterpret_s32_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s32_u64_untied, svint32_t, svuint64_t, + z0 = svreinterpret_s32_u64 (z4), + z0 = svreinterpret_s32 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s64.c new file mode 100644 index 00000000000..f8fbb33d68a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s64.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_s64_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_f16_tied1, svint64_t, svfloat16_t, + z0_res = svreinterpret_s64_f16 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_f16_untied, svint64_t, svfloat16_t, + z0 = svreinterpret_s64_f16 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_f32_tied1, svint64_t, svfloat32_t, + z0_res = svreinterpret_s64_f32 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_f32_untied, svint64_t, svfloat32_t, + z0 = svreinterpret_s64_f32 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_f64_tied1, svint64_t, svfloat64_t, + z0_res = svreinterpret_s64_f64 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_f64_untied, svint64_t, svfloat64_t, + z0 = svreinterpret_s64_f64 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_s8_tied1, svint64_t, svint8_t, + z0_res = svreinterpret_s64_s8 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_s8_untied, svint64_t, svint8_t, + z0 = svreinterpret_s64_s8 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_s16_tied1, svint64_t, svint16_t, + z0_res = svreinterpret_s64_s16 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_s16_untied, svint64_t, svint16_t, + z0 = svreinterpret_s64_s16 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_s32_tied1, svint64_t, svint32_t, + z0_res = svreinterpret_s64_s32 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_s32_untied, svint64_t, svint32_t, + z0 = svreinterpret_s64_s32 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_s64_tied1, svint64_t, svint64_t, + z0_res = svreinterpret_s64_s64 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_s64_untied, svint64_t, svint64_t, + z0 = svreinterpret_s64_s64 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_u8_tied1, svint64_t, svuint8_t, + z0_res = svreinterpret_s64_u8 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_u8_untied, svint64_t, svuint8_t, + z0 = svreinterpret_s64_u8 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_u16_tied1, svint64_t, svuint16_t, + z0_res = svreinterpret_s64_u16 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_u16_untied, svint64_t, svuint16_t, + z0 = svreinterpret_s64_u16 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_u32_tied1, svint64_t, svuint32_t, + z0_res = svreinterpret_s64_u32 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_u32_untied, svint64_t, svuint32_t, + z0 = svreinterpret_s64_u32 (z4), + z0 = svreinterpret_s64 (z4)) + +/* +** reinterpret_s64_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s64_u64_tied1, svint64_t, svuint64_t, + z0_res = svreinterpret_s64_u64 (z0), + z0_res = svreinterpret_s64 (z0)) + +/* +** reinterpret_s64_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s64_u64_untied, svint64_t, svuint64_t, + z0 = svreinterpret_s64_u64 (z4), + z0 = svreinterpret_s64 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s8.c new file mode 100644 index 00000000000..cfa591cae33 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_s8.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_s8_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_f16_tied1, svint8_t, svfloat16_t, + z0_res = svreinterpret_s8_f16 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_f16_untied, svint8_t, svfloat16_t, + z0 = svreinterpret_s8_f16 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_f32_tied1, svint8_t, svfloat32_t, + z0_res = svreinterpret_s8_f32 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_f32_untied, svint8_t, svfloat32_t, + z0 = svreinterpret_s8_f32 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_f64_tied1, svint8_t, svfloat64_t, + z0_res = svreinterpret_s8_f64 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_f64_untied, svint8_t, svfloat64_t, + z0 = svreinterpret_s8_f64 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_s8_tied1, svint8_t, svint8_t, + z0_res = svreinterpret_s8_s8 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_s8_untied, svint8_t, svint8_t, + z0 = svreinterpret_s8_s8 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_s16_tied1, svint8_t, svint16_t, + z0_res = svreinterpret_s8_s16 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_s16_untied, svint8_t, svint16_t, + z0 = svreinterpret_s8_s16 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_s32_tied1, svint8_t, svint32_t, + z0_res = svreinterpret_s8_s32 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_s32_untied, svint8_t, svint32_t, + z0 = svreinterpret_s8_s32 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_s64_tied1, svint8_t, svint64_t, + z0_res = svreinterpret_s8_s64 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_s64_untied, svint8_t, svint64_t, + z0 = svreinterpret_s8_s64 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_u8_tied1, svint8_t, svuint8_t, + z0_res = svreinterpret_s8_u8 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_u8_untied, svint8_t, svuint8_t, + z0 = svreinterpret_s8_u8 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_u16_tied1, svint8_t, svuint16_t, + z0_res = svreinterpret_s8_u16 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_u16_untied, svint8_t, svuint16_t, + z0 = svreinterpret_s8_u16 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_u32_tied1, svint8_t, svuint32_t, + z0_res = svreinterpret_s8_u32 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_u32_untied, svint8_t, svuint32_t, + z0 = svreinterpret_s8_u32 (z4), + z0 = svreinterpret_s8 (z4)) + +/* +** reinterpret_s8_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_s8_u64_tied1, svint8_t, svuint64_t, + z0_res = svreinterpret_s8_u64 (z0), + z0_res = svreinterpret_s8 (z0)) + +/* +** reinterpret_s8_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_s8_u64_untied, svint8_t, svuint64_t, + z0 = svreinterpret_s8_u64 (z4), + z0 = svreinterpret_s8 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u16.c new file mode 100644 index 00000000000..0980e73fab8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u16.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_u16_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_f16_tied1, svuint16_t, svfloat16_t, + z0_res = svreinterpret_u16_f16 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_f16_untied, svuint16_t, svfloat16_t, + z0 = svreinterpret_u16_f16 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_f32_tied1, svuint16_t, svfloat32_t, + z0_res = svreinterpret_u16_f32 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_f32_untied, svuint16_t, svfloat32_t, + z0 = svreinterpret_u16_f32 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_f64_tied1, svuint16_t, svfloat64_t, + z0_res = svreinterpret_u16_f64 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_f64_untied, svuint16_t, svfloat64_t, + z0 = svreinterpret_u16_f64 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_s8_tied1, svuint16_t, svint8_t, + z0_res = svreinterpret_u16_s8 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_s8_untied, svuint16_t, svint8_t, + z0 = svreinterpret_u16_s8 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_s16_tied1, svuint16_t, svint16_t, + z0_res = svreinterpret_u16_s16 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_s16_untied, svuint16_t, svint16_t, + z0 = svreinterpret_u16_s16 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_s32_tied1, svuint16_t, svint32_t, + z0_res = svreinterpret_u16_s32 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_s32_untied, svuint16_t, svint32_t, + z0 = svreinterpret_u16_s32 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_s64_tied1, svuint16_t, svint64_t, + z0_res = svreinterpret_u16_s64 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_s64_untied, svuint16_t, svint64_t, + z0 = svreinterpret_u16_s64 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_u8_tied1, svuint16_t, svuint8_t, + z0_res = svreinterpret_u16_u8 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_u8_untied, svuint16_t, svuint8_t, + z0 = svreinterpret_u16_u8 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_u16_tied1, svuint16_t, svuint16_t, + z0_res = svreinterpret_u16_u16 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_u16_untied, svuint16_t, svuint16_t, + z0 = svreinterpret_u16_u16 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_u32_tied1, svuint16_t, svuint32_t, + z0_res = svreinterpret_u16_u32 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_u32_untied, svuint16_t, svuint32_t, + z0 = svreinterpret_u16_u32 (z4), + z0 = svreinterpret_u16 (z4)) + +/* +** reinterpret_u16_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u16_u64_tied1, svuint16_t, svuint64_t, + z0_res = svreinterpret_u16_u64 (z0), + z0_res = svreinterpret_u16 (z0)) + +/* +** reinterpret_u16_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u16_u64_untied, svuint16_t, svuint64_t, + z0 = svreinterpret_u16_u64 (z4), + z0 = svreinterpret_u16 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u32.c new file mode 100644 index 00000000000..92e3f5b0ee5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u32.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_u32_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_f16_tied1, svuint32_t, svfloat16_t, + z0_res = svreinterpret_u32_f16 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_f16_untied, svuint32_t, svfloat16_t, + z0 = svreinterpret_u32_f16 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_f32_tied1, svuint32_t, svfloat32_t, + z0_res = svreinterpret_u32_f32 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_f32_untied, svuint32_t, svfloat32_t, + z0 = svreinterpret_u32_f32 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_f64_tied1, svuint32_t, svfloat64_t, + z0_res = svreinterpret_u32_f64 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_f64_untied, svuint32_t, svfloat64_t, + z0 = svreinterpret_u32_f64 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_s8_tied1, svuint32_t, svint8_t, + z0_res = svreinterpret_u32_s8 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_s8_untied, svuint32_t, svint8_t, + z0 = svreinterpret_u32_s8 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_s16_tied1, svuint32_t, svint16_t, + z0_res = svreinterpret_u32_s16 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_s16_untied, svuint32_t, svint16_t, + z0 = svreinterpret_u32_s16 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_s32_tied1, svuint32_t, svint32_t, + z0_res = svreinterpret_u32_s32 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_s32_untied, svuint32_t, svint32_t, + z0 = svreinterpret_u32_s32 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_s64_tied1, svuint32_t, svint64_t, + z0_res = svreinterpret_u32_s64 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_s64_untied, svuint32_t, svint64_t, + z0 = svreinterpret_u32_s64 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_u8_tied1, svuint32_t, svuint8_t, + z0_res = svreinterpret_u32_u8 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_u8_untied, svuint32_t, svuint8_t, + z0 = svreinterpret_u32_u8 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_u16_tied1, svuint32_t, svuint16_t, + z0_res = svreinterpret_u32_u16 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_u16_untied, svuint32_t, svuint16_t, + z0 = svreinterpret_u32_u16 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_u32_tied1, svuint32_t, svuint32_t, + z0_res = svreinterpret_u32_u32 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_u32_untied, svuint32_t, svuint32_t, + z0 = svreinterpret_u32_u32 (z4), + z0 = svreinterpret_u32 (z4)) + +/* +** reinterpret_u32_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u32_u64_tied1, svuint32_t, svuint64_t, + z0_res = svreinterpret_u32_u64 (z0), + z0_res = svreinterpret_u32 (z0)) + +/* +** reinterpret_u32_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u32_u64_untied, svuint32_t, svuint64_t, + z0 = svreinterpret_u32_u64 (z4), + z0 = svreinterpret_u32 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u64.c new file mode 100644 index 00000000000..bcfa3363b9f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u64.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_u64_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_f16_tied1, svuint64_t, svfloat16_t, + z0_res = svreinterpret_u64_f16 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_f16_untied, svuint64_t, svfloat16_t, + z0 = svreinterpret_u64_f16 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_f32_tied1, svuint64_t, svfloat32_t, + z0_res = svreinterpret_u64_f32 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_f32_untied, svuint64_t, svfloat32_t, + z0 = svreinterpret_u64_f32 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_f64_tied1, svuint64_t, svfloat64_t, + z0_res = svreinterpret_u64_f64 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_f64_untied, svuint64_t, svfloat64_t, + z0 = svreinterpret_u64_f64 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_s8_tied1, svuint64_t, svint8_t, + z0_res = svreinterpret_u64_s8 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_s8_untied, svuint64_t, svint8_t, + z0 = svreinterpret_u64_s8 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_s16_tied1, svuint64_t, svint16_t, + z0_res = svreinterpret_u64_s16 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_s16_untied, svuint64_t, svint16_t, + z0 = svreinterpret_u64_s16 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_s32_tied1, svuint64_t, svint32_t, + z0_res = svreinterpret_u64_s32 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_s32_untied, svuint64_t, svint32_t, + z0 = svreinterpret_u64_s32 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_s64_tied1, svuint64_t, svint64_t, + z0_res = svreinterpret_u64_s64 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_s64_untied, svuint64_t, svint64_t, + z0 = svreinterpret_u64_s64 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_u8_tied1, svuint64_t, svuint8_t, + z0_res = svreinterpret_u64_u8 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_u8_untied, svuint64_t, svuint8_t, + z0 = svreinterpret_u64_u8 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_u16_tied1, svuint64_t, svuint16_t, + z0_res = svreinterpret_u64_u16 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_u16_untied, svuint64_t, svuint16_t, + z0 = svreinterpret_u64_u16 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_u32_tied1, svuint64_t, svuint32_t, + z0_res = svreinterpret_u64_u32 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_u32_untied, svuint64_t, svuint32_t, + z0 = svreinterpret_u64_u32 (z4), + z0 = svreinterpret_u64 (z4)) + +/* +** reinterpret_u64_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u64_u64_tied1, svuint64_t, svuint64_t, + z0_res = svreinterpret_u64_u64 (z0), + z0_res = svreinterpret_u64 (z0)) + +/* +** reinterpret_u64_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u64_u64_untied, svuint64_t, svuint64_t, + z0 = svreinterpret_u64_u64 (z4), + z0 = svreinterpret_u64 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u8.c new file mode 100644 index 00000000000..dd1286b972d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/reinterpret_u8.c @@ -0,0 +1,190 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** reinterpret_u8_f16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_f16_tied1, svuint8_t, svfloat16_t, + z0_res = svreinterpret_u8_f16 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_f16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_f16_untied, svuint8_t, svfloat16_t, + z0 = svreinterpret_u8_f16 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_f32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_f32_tied1, svuint8_t, svfloat32_t, + z0_res = svreinterpret_u8_f32 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_f32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_f32_untied, svuint8_t, svfloat32_t, + z0 = svreinterpret_u8_f32 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_f64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_f64_tied1, svuint8_t, svfloat64_t, + z0_res = svreinterpret_u8_f64 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_f64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_f64_untied, svuint8_t, svfloat64_t, + z0 = svreinterpret_u8_f64 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_s8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_s8_tied1, svuint8_t, svint8_t, + z0_res = svreinterpret_u8_s8 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_s8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_s8_untied, svuint8_t, svint8_t, + z0 = svreinterpret_u8_s8 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_s16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_s16_tied1, svuint8_t, svint16_t, + z0_res = svreinterpret_u8_s16 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_s16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_s16_untied, svuint8_t, svint16_t, + z0 = svreinterpret_u8_s16 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_s32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_s32_tied1, svuint8_t, svint32_t, + z0_res = svreinterpret_u8_s32 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_s32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_s32_untied, svuint8_t, svint32_t, + z0 = svreinterpret_u8_s32 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_s64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_s64_tied1, svuint8_t, svint64_t, + z0_res = svreinterpret_u8_s64 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_s64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_s64_untied, svuint8_t, svint64_t, + z0 = svreinterpret_u8_s64 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_u8_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_u8_tied1, svuint8_t, svuint8_t, + z0_res = svreinterpret_u8_u8 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_u8_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_u8_untied, svuint8_t, svuint8_t, + z0 = svreinterpret_u8_u8 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_u16_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_u16_tied1, svuint8_t, svuint16_t, + z0_res = svreinterpret_u8_u16 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_u16_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_u16_untied, svuint8_t, svuint16_t, + z0 = svreinterpret_u8_u16 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_u32_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_u32_tied1, svuint8_t, svuint32_t, + z0_res = svreinterpret_u8_u32 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_u32_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_u32_untied, svuint8_t, svuint32_t, + z0 = svreinterpret_u8_u32 (z4), + z0 = svreinterpret_u8 (z4)) + +/* +** reinterpret_u8_u64_tied1: +** ret +*/ +TEST_DUAL_Z_REV (reinterpret_u8_u64_tied1, svuint8_t, svuint64_t, + z0_res = svreinterpret_u8_u64 (z0), + z0_res = svreinterpret_u8 (z0)) + +/* +** reinterpret_u8_u64_untied: +** mov z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (reinterpret_u8_u64_untied, svuint8_t, svuint64_t, + z0 = svreinterpret_u8_u64 (z4), + z0 = svreinterpret_u8 (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b16.c new file mode 100644 index 00000000000..7d5c67d5c97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_b16_tied1: +** rev p0\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (rev_b16_tied1, + p0 = svrev_b16 (p0), + p0 = svrev_b16 (p0)) + +/* +** rev_b16_untied: +** rev p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (rev_b16_untied, + p0 = svrev_b16 (p1), + p0 = svrev_b16 (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b32.c new file mode 100644 index 00000000000..3f8c810c011 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_b32_tied1: +** rev p0\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (rev_b32_tied1, + p0 = svrev_b32 (p0), + p0 = svrev_b32 (p0)) + +/* +** rev_b32_untied: +** rev p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (rev_b32_untied, + p0 = svrev_b32 (p1), + p0 = svrev_b32 (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b64.c new file mode 100644 index 00000000000..fe937ecc69b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_b64_tied1: +** rev p0\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (rev_b64_tied1, + p0 = svrev_b64 (p0), + p0 = svrev_b64 (p0)) + +/* +** rev_b64_untied: +** rev p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (rev_b64_untied, + p0 = svrev_b64 (p1), + p0 = svrev_b64 (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b8.c new file mode 100644 index 00000000000..d23e504071a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_b8.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_b8_tied1: +** rev p0\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (rev_b8_tied1, + p0 = svrev_b8 (p0), + p0 = svrev_b8 (p0)) + +/* +** rev_b8_untied: +** rev p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (rev_b8_untied, + p0 = svrev_b8 (p1), + p0 = svrev_b8 (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f16.c new file mode 100644 index 00000000000..321e2f90050 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_f16_tied1: +** rev z0\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rev_f16_tied1, svfloat16_t, + z0 = svrev_f16 (z0), + z0 = svrev (z0)) + +/* +** rev_f16_untied: +** rev z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rev_f16_untied, svfloat16_t, + z0 = svrev_f16 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f32.c new file mode 100644 index 00000000000..6f31928b56e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_f32_tied1: +** rev z0\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rev_f32_tied1, svfloat32_t, + z0 = svrev_f32 (z0), + z0 = svrev (z0)) + +/* +** rev_f32_untied: +** rev z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rev_f32_untied, svfloat32_t, + z0 = svrev_f32 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f64.c new file mode 100644 index 00000000000..6f14078a7be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_f64_tied1: +** rev z0\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rev_f64_tied1, svfloat64_t, + z0 = svrev_f64 (z0), + z0 = svrev (z0)) + +/* +** rev_f64_untied: +** rev z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rev_f64_untied, svfloat64_t, + z0 = svrev_f64 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s16.c new file mode 100644 index 00000000000..63f6ea73c24 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_s16_tied1: +** rev z0\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rev_s16_tied1, svint16_t, + z0 = svrev_s16 (z0), + z0 = svrev (z0)) + +/* +** rev_s16_untied: +** rev z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rev_s16_untied, svint16_t, + z0 = svrev_s16 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s32.c new file mode 100644 index 00000000000..38240b7ec67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_s32_tied1: +** rev z0\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rev_s32_tied1, svint32_t, + z0 = svrev_s32 (z0), + z0 = svrev (z0)) + +/* +** rev_s32_untied: +** rev z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rev_s32_untied, svint32_t, + z0 = svrev_s32 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s64.c new file mode 100644 index 00000000000..0004e458625 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_s64_tied1: +** rev z0\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rev_s64_tied1, svint64_t, + z0 = svrev_s64 (z0), + z0 = svrev (z0)) + +/* +** rev_s64_untied: +** rev z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rev_s64_untied, svint64_t, + z0 = svrev_s64 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s8.c new file mode 100644 index 00000000000..44b874c928d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_s8.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_s8_tied1: +** rev z0\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rev_s8_tied1, svint8_t, + z0 = svrev_s8 (z0), + z0 = svrev (z0)) + +/* +** rev_s8_untied: +** rev z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rev_s8_untied, svint8_t, + z0 = svrev_s8 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u16.c new file mode 100644 index 00000000000..2b4c8885434 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_u16_tied1: +** rev z0\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rev_u16_tied1, svuint16_t, + z0 = svrev_u16 (z0), + z0 = svrev (z0)) + +/* +** rev_u16_untied: +** rev z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rev_u16_untied, svuint16_t, + z0 = svrev_u16 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u32.c new file mode 100644 index 00000000000..e14351f3015 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_u32_tied1: +** rev z0\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rev_u32_tied1, svuint32_t, + z0 = svrev_u32 (z0), + z0 = svrev (z0)) + +/* +** rev_u32_untied: +** rev z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rev_u32_untied, svuint32_t, + z0 = svrev_u32 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u64.c new file mode 100644 index 00000000000..5fc9874751d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_u64_tied1: +** rev z0\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rev_u64_tied1, svuint64_t, + z0 = svrev_u64 (z0), + z0 = svrev (z0)) + +/* +** rev_u64_untied: +** rev z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rev_u64_untied, svuint64_t, + z0 = svrev_u64 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u8.c new file mode 100644 index 00000000000..9dd4f440b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rev_u8.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rev_u8_tied1: +** rev z0\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (rev_u8_tied1, svuint8_t, + z0 = svrev_u8 (z0), + z0 = svrev (z0)) + +/* +** rev_u8_untied: +** rev z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (rev_u8_untied, svuint8_t, + z0 = svrev_u8 (z1), + z0 = svrev (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c new file mode 100644 index 00000000000..ecfabe668ee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_s16_m_tied12: +** revb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_m_tied12, svint16_t, + z0 = svrevb_s16_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_s16_m_tied1: +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_m_tied1, svint16_t, + z0 = svrevb_s16_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_m_tied2, svint16_t, + z0 = svrevb_s16_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_s16_m_untied: +** movprfx z0, z2 +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_m_untied, svint16_t, + z0 = svrevb_s16_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_s16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** revb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_z_tied1, svint16_t, + z0 = svrevb_s16_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_z_untied, svint16_t, + z0 = svrevb_s16_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_s16_x_tied1: +** revb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_x_tied1, svint16_t, + z0 = svrevb_s16_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_s16_x_untied: +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_s16_x_untied, svint16_t, + z0 = svrevb_s16_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c new file mode 100644 index 00000000000..a46a819737a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_s32_m_tied12: +** revb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_m_tied12, svint32_t, + z0 = svrevb_s32_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_s32_m_tied1: +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_m_tied1, svint32_t, + z0 = svrevb_s32_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_m_tied2, svint32_t, + z0 = svrevb_s32_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_s32_m_untied: +** movprfx z0, z2 +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_m_untied, svint32_t, + z0 = svrevb_s32_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** revb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_z_tied1, svint32_t, + z0 = svrevb_s32_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_z_untied, svint32_t, + z0 = svrevb_s32_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_s32_x_tied1: +** revb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_x_tied1, svint32_t, + z0 = svrevb_s32_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_s32_x_untied: +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_s32_x_untied, svint32_t, + z0 = svrevb_s32_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c new file mode 100644 index 00000000000..21547238c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_s64_m_tied12: +** revb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_m_tied12, svint64_t, + z0 = svrevb_s64_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_s64_m_tied1: +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_m_tied1, svint64_t, + z0 = svrevb_s64_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revb_s64_m_tied2, svint64_t, + z0 = svrevb_s64_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_s64_m_untied: +** movprfx z0, z2 +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_m_untied, svint64_t, + z0 = svrevb_s64_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revb_s64_z_tied1, svint64_t, + z0 = svrevb_s64_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_z_untied, svint64_t, + z0 = svrevb_s64_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_s64_x_tied1: +** revb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_x_tied1, svint64_t, + z0 = svrevb_s64_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_s64_x_untied: +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_s64_x_untied, svint64_t, + z0 = svrevb_s64_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c new file mode 100644 index 00000000000..d58bd3d7409 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_u16_m_tied12: +** revb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_m_tied12, svuint16_t, + z0 = svrevb_u16_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_u16_m_tied1: +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_m_tied1, svuint16_t, + z0 = svrevb_u16_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_m_tied2, svuint16_t, + z0 = svrevb_u16_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_u16_m_untied: +** movprfx z0, z2 +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_m_untied, svuint16_t, + z0 = svrevb_u16_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_u16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** revb z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_z_tied1, svuint16_t, + z0 = svrevb_u16_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_z_untied, svuint16_t, + z0 = svrevb_u16_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_u16_x_tied1: +** revb z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_x_tied1, svuint16_t, + z0 = svrevb_u16_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_u16_x_untied: +** revb z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (revb_u16_x_untied, svuint16_t, + z0 = svrevb_u16_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c new file mode 100644 index 00000000000..33df990d55f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_u32_m_tied12: +** revb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_m_tied12, svuint32_t, + z0 = svrevb_u32_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_u32_m_tied1: +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_m_tied1, svuint32_t, + z0 = svrevb_u32_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_m_tied2, svuint32_t, + z0 = svrevb_u32_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_u32_m_untied: +** movprfx z0, z2 +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_m_untied, svuint32_t, + z0 = svrevb_u32_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** revb z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_z_tied1, svuint32_t, + z0 = svrevb_u32_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_z_untied, svuint32_t, + z0 = svrevb_u32_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_u32_x_tied1: +** revb z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_x_tied1, svuint32_t, + z0 = svrevb_u32_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_u32_x_untied: +** revb z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revb_u32_x_untied, svuint32_t, + z0 = svrevb_u32_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c new file mode 100644 index 00000000000..50ad618cc1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revb_u64_m_tied12: +** revb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_m_tied12, svuint64_t, + z0 = svrevb_u64_m (z0, p0, z0), + z0 = svrevb_m (z0, p0, z0)) + +/* +** revb_u64_m_tied1: +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_m_tied1, svuint64_t, + z0 = svrevb_u64_m (z0, p0, z1), + z0 = svrevb_m (z0, p0, z1)) + +/* +** revb_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revb_u64_m_tied2, svuint64_t, + z0 = svrevb_u64_m (z1, p0, z0), + z0 = svrevb_m (z1, p0, z0)) + +/* +** revb_u64_m_untied: +** movprfx z0, z2 +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_m_untied, svuint64_t, + z0 = svrevb_u64_m (z2, p0, z1), + z0 = svrevb_m (z2, p0, z1)) + +/* +** revb_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revb z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revb_u64_z_tied1, svuint64_t, + z0 = svrevb_u64_z (p0, z0), + z0 = svrevb_z (p0, z0)) + +/* +** revb_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_z_untied, svuint64_t, + z0 = svrevb_u64_z (p0, z1), + z0 = svrevb_z (p0, z1)) + +/* +** revb_u64_x_tied1: +** revb z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_x_tied1, svuint64_t, + z0 = svrevb_u64_x (p0, z0), + z0 = svrevb_x (p0, z0)) + +/* +** revb_u64_x_untied: +** revb z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revb_u64_x_untied, svuint64_t, + z0 = svrevb_u64_x (p0, z1), + z0 = svrevb_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c new file mode 100644 index 00000000000..07d512ddb75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revh_s32_m_tied12: +** revh z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_m_tied12, svint32_t, + z0 = svrevh_s32_m (z0, p0, z0), + z0 = svrevh_m (z0, p0, z0)) + +/* +** revh_s32_m_tied1: +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_m_tied1, svint32_t, + z0 = svrevh_s32_m (z0, p0, z1), + z0 = svrevh_m (z0, p0, z1)) + +/* +** revh_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revh z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_m_tied2, svint32_t, + z0 = svrevh_s32_m (z1, p0, z0), + z0 = svrevh_m (z1, p0, z0)) + +/* +** revh_s32_m_untied: +** movprfx z0, z2 +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_m_untied, svint32_t, + z0 = svrevh_s32_m (z2, p0, z1), + z0 = svrevh_m (z2, p0, z1)) + +/* +** revh_s32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** revh z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_z_tied1, svint32_t, + z0 = svrevh_s32_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_s32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_z_untied, svint32_t, + z0 = svrevh_s32_z (p0, z1), + z0 = svrevh_z (p0, z1)) + +/* +** revh_s32_x_tied1: +** revh z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_x_tied1, svint32_t, + z0 = svrevh_s32_x (p0, z0), + z0 = svrevh_x (p0, z0)) + +/* +** revh_s32_x_untied: +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_s32_x_untied, svint32_t, + z0 = svrevh_s32_x (p0, z1), + z0 = svrevh_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c new file mode 100644 index 00000000000..b1446347c0f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revh_s64_m_tied12: +** revh z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_m_tied12, svint64_t, + z0 = svrevh_s64_m (z0, p0, z0), + z0 = svrevh_m (z0, p0, z0)) + +/* +** revh_s64_m_tied1: +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_m_tied1, svint64_t, + z0 = svrevh_s64_m (z0, p0, z1), + z0 = svrevh_m (z0, p0, z1)) + +/* +** revh_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revh z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revh_s64_m_tied2, svint64_t, + z0 = svrevh_s64_m (z1, p0, z0), + z0 = svrevh_m (z1, p0, z0)) + +/* +** revh_s64_m_untied: +** movprfx z0, z2 +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_m_untied, svint64_t, + z0 = svrevh_s64_m (z2, p0, z1), + z0 = svrevh_m (z2, p0, z1)) + +/* +** revh_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revh z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revh_s64_z_tied1, svint64_t, + z0 = svrevh_s64_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_z_untied, svint64_t, + z0 = svrevh_s64_z (p0, z1), + z0 = svrevh_z (p0, z1)) + +/* +** revh_s64_x_tied1: +** revh z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_x_tied1, svint64_t, + z0 = svrevh_s64_x (p0, z0), + z0 = svrevh_x (p0, z0)) + +/* +** revh_s64_x_untied: +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_s64_x_untied, svint64_t, + z0 = svrevh_s64_x (p0, z1), + z0 = svrevh_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c new file mode 100644 index 00000000000..9ea51884d1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revh_u32_m_tied12: +** revh z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_m_tied12, svuint32_t, + z0 = svrevh_u32_m (z0, p0, z0), + z0 = svrevh_m (z0, p0, z0)) + +/* +** revh_u32_m_tied1: +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_m_tied1, svuint32_t, + z0 = svrevh_u32_m (z0, p0, z1), + z0 = svrevh_m (z0, p0, z1)) + +/* +** revh_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** revh z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_m_tied2, svuint32_t, + z0 = svrevh_u32_m (z1, p0, z0), + z0 = svrevh_m (z1, p0, z0)) + +/* +** revh_u32_m_untied: +** movprfx z0, z2 +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_m_untied, svuint32_t, + z0 = svrevh_u32_m (z2, p0, z1), + z0 = svrevh_m (z2, p0, z1)) + +/* +** revh_u32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** revh z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_z_tied1, svuint32_t, + z0 = svrevh_u32_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_u32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_z_untied, svuint32_t, + z0 = svrevh_u32_z (p0, z1), + z0 = svrevh_z (p0, z1)) + +/* +** revh_u32_x_tied1: +** revh z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_x_tied1, svuint32_t, + z0 = svrevh_u32_x (p0, z0), + z0 = svrevh_x (p0, z0)) + +/* +** revh_u32_x_untied: +** revh z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (revh_u32_x_untied, svuint32_t, + z0 = svrevh_u32_x (p0, z1), + z0 = svrevh_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c new file mode 100644 index 00000000000..7b2da2701c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revh_u64_m_tied12: +** revh z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_m_tied12, svuint64_t, + z0 = svrevh_u64_m (z0, p0, z0), + z0 = svrevh_m (z0, p0, z0)) + +/* +** revh_u64_m_tied1: +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_m_tied1, svuint64_t, + z0 = svrevh_u64_m (z0, p0, z1), + z0 = svrevh_m (z0, p0, z1)) + +/* +** revh_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revh z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revh_u64_m_tied2, svuint64_t, + z0 = svrevh_u64_m (z1, p0, z0), + z0 = svrevh_m (z1, p0, z0)) + +/* +** revh_u64_m_untied: +** movprfx z0, z2 +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_m_untied, svuint64_t, + z0 = svrevh_u64_m (z2, p0, z1), + z0 = svrevh_m (z2, p0, z1)) + +/* +** revh_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revh z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revh_u64_z_tied1, svuint64_t, + z0 = svrevh_u64_z (p0, z0), + z0 = svrevh_z (p0, z0)) + +/* +** revh_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_z_untied, svuint64_t, + z0 = svrevh_u64_z (p0, z1), + z0 = svrevh_z (p0, z1)) + +/* +** revh_u64_x_tied1: +** revh z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_x_tied1, svuint64_t, + z0 = svrevh_u64_x (p0, z0), + z0 = svrevh_x (p0, z0)) + +/* +** revh_u64_x_untied: +** revh z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revh_u64_x_untied, svuint64_t, + z0 = svrevh_u64_x (p0, z1), + z0 = svrevh_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c new file mode 100644 index 00000000000..26ca0f0bd52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revw_s64_m_tied12: +** revw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_m_tied12, svint64_t, + z0 = svrevw_s64_m (z0, p0, z0), + z0 = svrevw_m (z0, p0, z0)) + +/* +** revw_s64_m_tied1: +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_m_tied1, svint64_t, + z0 = svrevw_s64_m (z0, p0, z1), + z0 = svrevw_m (z0, p0, z1)) + +/* +** revw_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revw_s64_m_tied2, svint64_t, + z0 = svrevw_s64_m (z1, p0, z0), + z0 = svrevw_m (z1, p0, z0)) + +/* +** revw_s64_m_untied: +** movprfx z0, z2 +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_m_untied, svint64_t, + z0 = svrevw_s64_m (z2, p0, z1), + z0 = svrevw_m (z2, p0, z1)) + +/* +** revw_s64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revw_s64_z_tied1, svint64_t, + z0 = svrevw_s64_z (p0, z0), + z0 = svrevw_z (p0, z0)) + +/* +** revw_s64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_z_untied, svint64_t, + z0 = svrevw_s64_z (p0, z1), + z0 = svrevw_z (p0, z1)) + +/* +** revw_s64_x_tied1: +** revw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_x_tied1, svint64_t, + z0 = svrevw_s64_x (p0, z0), + z0 = svrevw_x (p0, z0)) + +/* +** revw_s64_x_untied: +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_s64_x_untied, svint64_t, + z0 = svrevw_s64_x (p0, z1), + z0 = svrevw_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c new file mode 100644 index 00000000000..c70cdb428ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c @@ -0,0 +1,81 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** revw_u64_m_tied12: +** revw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_m_tied12, svuint64_t, + z0 = svrevw_u64_m (z0, p0, z0), + z0 = svrevw_m (z0, p0, z0)) + +/* +** revw_u64_m_tied1: +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_m_tied1, svuint64_t, + z0 = svrevw_u64_m (z0, p0, z1), + z0 = svrevw_m (z0, p0, z1)) + +/* +** revw_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** revw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revw_u64_m_tied2, svuint64_t, + z0 = svrevw_u64_m (z1, p0, z0), + z0 = svrevw_m (z1, p0, z0)) + +/* +** revw_u64_m_untied: +** movprfx z0, z2 +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_m_untied, svuint64_t, + z0 = svrevw_u64_m (z2, p0, z1), + z0 = svrevw_m (z2, p0, z1)) + +/* +** revw_u64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** revw z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (revw_u64_z_tied1, svuint64_t, + z0 = svrevw_u64_z (p0, z0), + z0 = svrevw_z (p0, z0)) + +/* +** revw_u64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_z_untied, svuint64_t, + z0 = svrevw_u64_z (p0, z1), + z0 = svrevw_z (p0, z1)) + +/* +** revw_u64_x_tied1: +** revw z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_x_tied1, svuint64_t, + z0 = svrevw_u64_x (p0, z0), + z0 = svrevw_x (p0, z0)) + +/* +** revw_u64_x_untied: +** revw z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (revw_u64_x_untied, svuint64_t, + z0 = svrevw_u64_x (p0, z1), + z0 = svrevw_x (p0, z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c new file mode 100644 index 00000000000..99a60420942 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinta_f16_m_tied12: +** frinta z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_m_tied12, svfloat16_t, + z0 = svrinta_f16_m (z0, p0, z0), + z0 = svrinta_m (z0, p0, z0)) + +/* +** rinta_f16_m_tied1: +** frinta z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_m_tied1, svfloat16_t, + z0 = svrinta_f16_m (z0, p0, z1), + z0 = svrinta_m (z0, p0, z1)) + +/* +** rinta_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frinta z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_m_tied2, svfloat16_t, + z0 = svrinta_f16_m (z1, p0, z0), + z0 = svrinta_m (z1, p0, z0)) + +/* +** rinta_f16_m_untied: +** movprfx z0, z2 +** frinta z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_m_untied, svfloat16_t, + z0 = svrinta_f16_m (z2, p0, z1), + z0 = svrinta_m (z2, p0, z1)) + +/* +** rinta_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frinta z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_z_tied1, svfloat16_t, + z0 = svrinta_f16_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frinta z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_z_untied, svfloat16_t, + z0 = svrinta_f16_z (p0, z1), + z0 = svrinta_z (p0, z1)) + +/* +** rinta_f16_x_tied1: +** frinta z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_x_tied1, svfloat16_t, + z0 = svrinta_f16_x (p0, z0), + z0 = svrinta_x (p0, z0)) + +/* +** rinta_f16_x_untied: +** frinta z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinta_f16_x_untied, svfloat16_t, + z0 = svrinta_f16_x (p0, z1), + z0 = svrinta_x (p0, z1)) + +/* +** ptrue_rinta_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f16_x_tied1, svfloat16_t, + z0 = svrinta_f16_x (svptrue_b16 (), z0), + z0 = svrinta_x (svptrue_b16 (), z0)) + +/* +** ptrue_rinta_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f16_x_untied, svfloat16_t, + z0 = svrinta_f16_x (svptrue_b16 (), z1), + z0 = svrinta_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c new file mode 100644 index 00000000000..b4e3714bc4e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinta_f32_m_tied12: +** frinta z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_m_tied12, svfloat32_t, + z0 = svrinta_f32_m (z0, p0, z0), + z0 = svrinta_m (z0, p0, z0)) + +/* +** rinta_f32_m_tied1: +** frinta z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_m_tied1, svfloat32_t, + z0 = svrinta_f32_m (z0, p0, z1), + z0 = svrinta_m (z0, p0, z1)) + +/* +** rinta_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frinta z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_m_tied2, svfloat32_t, + z0 = svrinta_f32_m (z1, p0, z0), + z0 = svrinta_m (z1, p0, z0)) + +/* +** rinta_f32_m_untied: +** movprfx z0, z2 +** frinta z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_m_untied, svfloat32_t, + z0 = svrinta_f32_m (z2, p0, z1), + z0 = svrinta_m (z2, p0, z1)) + +/* +** rinta_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frinta z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_z_tied1, svfloat32_t, + z0 = svrinta_f32_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frinta z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_z_untied, svfloat32_t, + z0 = svrinta_f32_z (p0, z1), + z0 = svrinta_z (p0, z1)) + +/* +** rinta_f32_x_tied1: +** frinta z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_x_tied1, svfloat32_t, + z0 = svrinta_f32_x (p0, z0), + z0 = svrinta_x (p0, z0)) + +/* +** rinta_f32_x_untied: +** frinta z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinta_f32_x_untied, svfloat32_t, + z0 = svrinta_f32_x (p0, z1), + z0 = svrinta_x (p0, z1)) + +/* +** ptrue_rinta_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f32_x_tied1, svfloat32_t, + z0 = svrinta_f32_x (svptrue_b32 (), z0), + z0 = svrinta_x (svptrue_b32 (), z0)) + +/* +** ptrue_rinta_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f32_x_untied, svfloat32_t, + z0 = svrinta_f32_x (svptrue_b32 (), z1), + z0 = svrinta_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c new file mode 100644 index 00000000000..24d6b7dc8b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinta_f64_m_tied12: +** frinta z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_m_tied12, svfloat64_t, + z0 = svrinta_f64_m (z0, p0, z0), + z0 = svrinta_m (z0, p0, z0)) + +/* +** rinta_f64_m_tied1: +** frinta z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_m_tied1, svfloat64_t, + z0 = svrinta_f64_m (z0, p0, z1), + z0 = svrinta_m (z0, p0, z1)) + +/* +** rinta_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frinta z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_m_tied2, svfloat64_t, + z0 = svrinta_f64_m (z1, p0, z0), + z0 = svrinta_m (z1, p0, z0)) + +/* +** rinta_f64_m_untied: +** movprfx z0, z2 +** frinta z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_m_untied, svfloat64_t, + z0 = svrinta_f64_m (z2, p0, z1), + z0 = svrinta_m (z2, p0, z1)) + +/* +** rinta_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frinta z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_z_tied1, svfloat64_t, + z0 = svrinta_f64_z (p0, z0), + z0 = svrinta_z (p0, z0)) + +/* +** rinta_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frinta z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_z_untied, svfloat64_t, + z0 = svrinta_f64_z (p0, z1), + z0 = svrinta_z (p0, z1)) + +/* +** rinta_f64_x_tied1: +** frinta z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_x_tied1, svfloat64_t, + z0 = svrinta_f64_x (p0, z0), + z0 = svrinta_x (p0, z0)) + +/* +** rinta_f64_x_untied: +** frinta z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinta_f64_x_untied, svfloat64_t, + z0 = svrinta_f64_x (p0, z1), + z0 = svrinta_x (p0, z1)) + +/* +** ptrue_rinta_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f64_x_tied1, svfloat64_t, + z0 = svrinta_f64_x (svptrue_b64 (), z0), + z0 = svrinta_x (svptrue_b64 (), z0)) + +/* +** ptrue_rinta_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinta_f64_x_untied, svfloat64_t, + z0 = svrinta_f64_x (svptrue_b64 (), z1), + z0 = svrinta_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c new file mode 100644 index 00000000000..1f0ac85e33a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinti_f16_m_tied12: +** frinti z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_m_tied12, svfloat16_t, + z0 = svrinti_f16_m (z0, p0, z0), + z0 = svrinti_m (z0, p0, z0)) + +/* +** rinti_f16_m_tied1: +** frinti z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_m_tied1, svfloat16_t, + z0 = svrinti_f16_m (z0, p0, z1), + z0 = svrinti_m (z0, p0, z1)) + +/* +** rinti_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frinti z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_m_tied2, svfloat16_t, + z0 = svrinti_f16_m (z1, p0, z0), + z0 = svrinti_m (z1, p0, z0)) + +/* +** rinti_f16_m_untied: +** movprfx z0, z2 +** frinti z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_m_untied, svfloat16_t, + z0 = svrinti_f16_m (z2, p0, z1), + z0 = svrinti_m (z2, p0, z1)) + +/* +** rinti_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frinti z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_z_tied1, svfloat16_t, + z0 = svrinti_f16_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frinti z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_z_untied, svfloat16_t, + z0 = svrinti_f16_z (p0, z1), + z0 = svrinti_z (p0, z1)) + +/* +** rinti_f16_x_tied1: +** frinti z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_x_tied1, svfloat16_t, + z0 = svrinti_f16_x (p0, z0), + z0 = svrinti_x (p0, z0)) + +/* +** rinti_f16_x_untied: +** frinti z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rinti_f16_x_untied, svfloat16_t, + z0 = svrinti_f16_x (p0, z1), + z0 = svrinti_x (p0, z1)) + +/* +** ptrue_rinti_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f16_x_tied1, svfloat16_t, + z0 = svrinti_f16_x (svptrue_b16 (), z0), + z0 = svrinti_x (svptrue_b16 (), z0)) + +/* +** ptrue_rinti_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f16_x_untied, svfloat16_t, + z0 = svrinti_f16_x (svptrue_b16 (), z1), + z0 = svrinti_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c new file mode 100644 index 00000000000..cf54fde5c36 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinti_f32_m_tied12: +** frinti z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_m_tied12, svfloat32_t, + z0 = svrinti_f32_m (z0, p0, z0), + z0 = svrinti_m (z0, p0, z0)) + +/* +** rinti_f32_m_tied1: +** frinti z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_m_tied1, svfloat32_t, + z0 = svrinti_f32_m (z0, p0, z1), + z0 = svrinti_m (z0, p0, z1)) + +/* +** rinti_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frinti z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_m_tied2, svfloat32_t, + z0 = svrinti_f32_m (z1, p0, z0), + z0 = svrinti_m (z1, p0, z0)) + +/* +** rinti_f32_m_untied: +** movprfx z0, z2 +** frinti z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_m_untied, svfloat32_t, + z0 = svrinti_f32_m (z2, p0, z1), + z0 = svrinti_m (z2, p0, z1)) + +/* +** rinti_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frinti z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_z_tied1, svfloat32_t, + z0 = svrinti_f32_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frinti z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_z_untied, svfloat32_t, + z0 = svrinti_f32_z (p0, z1), + z0 = svrinti_z (p0, z1)) + +/* +** rinti_f32_x_tied1: +** frinti z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_x_tied1, svfloat32_t, + z0 = svrinti_f32_x (p0, z0), + z0 = svrinti_x (p0, z0)) + +/* +** rinti_f32_x_untied: +** frinti z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rinti_f32_x_untied, svfloat32_t, + z0 = svrinti_f32_x (p0, z1), + z0 = svrinti_x (p0, z1)) + +/* +** ptrue_rinti_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f32_x_tied1, svfloat32_t, + z0 = svrinti_f32_x (svptrue_b32 (), z0), + z0 = svrinti_x (svptrue_b32 (), z0)) + +/* +** ptrue_rinti_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f32_x_untied, svfloat32_t, + z0 = svrinti_f32_x (svptrue_b32 (), z1), + z0 = svrinti_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c new file mode 100644 index 00000000000..08b861caa1e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rinti_f64_m_tied12: +** frinti z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_m_tied12, svfloat64_t, + z0 = svrinti_f64_m (z0, p0, z0), + z0 = svrinti_m (z0, p0, z0)) + +/* +** rinti_f64_m_tied1: +** frinti z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_m_tied1, svfloat64_t, + z0 = svrinti_f64_m (z0, p0, z1), + z0 = svrinti_m (z0, p0, z1)) + +/* +** rinti_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frinti z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_m_tied2, svfloat64_t, + z0 = svrinti_f64_m (z1, p0, z0), + z0 = svrinti_m (z1, p0, z0)) + +/* +** rinti_f64_m_untied: +** movprfx z0, z2 +** frinti z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_m_untied, svfloat64_t, + z0 = svrinti_f64_m (z2, p0, z1), + z0 = svrinti_m (z2, p0, z1)) + +/* +** rinti_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frinti z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_z_tied1, svfloat64_t, + z0 = svrinti_f64_z (p0, z0), + z0 = svrinti_z (p0, z0)) + +/* +** rinti_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frinti z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_z_untied, svfloat64_t, + z0 = svrinti_f64_z (p0, z1), + z0 = svrinti_z (p0, z1)) + +/* +** rinti_f64_x_tied1: +** frinti z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_x_tied1, svfloat64_t, + z0 = svrinti_f64_x (p0, z0), + z0 = svrinti_x (p0, z0)) + +/* +** rinti_f64_x_untied: +** frinti z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rinti_f64_x_untied, svfloat64_t, + z0 = svrinti_f64_x (p0, z1), + z0 = svrinti_x (p0, z1)) + +/* +** ptrue_rinti_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f64_x_tied1, svfloat64_t, + z0 = svrinti_f64_x (svptrue_b64 (), z0), + z0 = svrinti_x (svptrue_b64 (), z0)) + +/* +** ptrue_rinti_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rinti_f64_x_untied, svfloat64_t, + z0 = svrinti_f64_x (svptrue_b64 (), z1), + z0 = svrinti_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c new file mode 100644 index 00000000000..194d01cbd0b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintm_f16_m_tied12: +** frintm z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_m_tied12, svfloat16_t, + z0 = svrintm_f16_m (z0, p0, z0), + z0 = svrintm_m (z0, p0, z0)) + +/* +** rintm_f16_m_tied1: +** frintm z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_m_tied1, svfloat16_t, + z0 = svrintm_f16_m (z0, p0, z1), + z0 = svrintm_m (z0, p0, z1)) + +/* +** rintm_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintm z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_m_tied2, svfloat16_t, + z0 = svrintm_f16_m (z1, p0, z0), + z0 = svrintm_m (z1, p0, z0)) + +/* +** rintm_f16_m_untied: +** movprfx z0, z2 +** frintm z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_m_untied, svfloat16_t, + z0 = svrintm_f16_m (z2, p0, z1), + z0 = svrintm_m (z2, p0, z1)) + +/* +** rintm_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frintm z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_z_tied1, svfloat16_t, + z0 = svrintm_f16_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frintm z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_z_untied, svfloat16_t, + z0 = svrintm_f16_z (p0, z1), + z0 = svrintm_z (p0, z1)) + +/* +** rintm_f16_x_tied1: +** frintm z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_x_tied1, svfloat16_t, + z0 = svrintm_f16_x (p0, z0), + z0 = svrintm_x (p0, z0)) + +/* +** rintm_f16_x_untied: +** frintm z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintm_f16_x_untied, svfloat16_t, + z0 = svrintm_f16_x (p0, z1), + z0 = svrintm_x (p0, z1)) + +/* +** ptrue_rintm_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f16_x_tied1, svfloat16_t, + z0 = svrintm_f16_x (svptrue_b16 (), z0), + z0 = svrintm_x (svptrue_b16 (), z0)) + +/* +** ptrue_rintm_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f16_x_untied, svfloat16_t, + z0 = svrintm_f16_x (svptrue_b16 (), z1), + z0 = svrintm_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c new file mode 100644 index 00000000000..6c3297aa1a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintm_f32_m_tied12: +** frintm z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_m_tied12, svfloat32_t, + z0 = svrintm_f32_m (z0, p0, z0), + z0 = svrintm_m (z0, p0, z0)) + +/* +** rintm_f32_m_tied1: +** frintm z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_m_tied1, svfloat32_t, + z0 = svrintm_f32_m (z0, p0, z1), + z0 = svrintm_m (z0, p0, z1)) + +/* +** rintm_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintm z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_m_tied2, svfloat32_t, + z0 = svrintm_f32_m (z1, p0, z0), + z0 = svrintm_m (z1, p0, z0)) + +/* +** rintm_f32_m_untied: +** movprfx z0, z2 +** frintm z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_m_untied, svfloat32_t, + z0 = svrintm_f32_m (z2, p0, z1), + z0 = svrintm_m (z2, p0, z1)) + +/* +** rintm_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frintm z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_z_tied1, svfloat32_t, + z0 = svrintm_f32_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frintm z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_z_untied, svfloat32_t, + z0 = svrintm_f32_z (p0, z1), + z0 = svrintm_z (p0, z1)) + +/* +** rintm_f32_x_tied1: +** frintm z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_x_tied1, svfloat32_t, + z0 = svrintm_f32_x (p0, z0), + z0 = svrintm_x (p0, z0)) + +/* +** rintm_f32_x_untied: +** frintm z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintm_f32_x_untied, svfloat32_t, + z0 = svrintm_f32_x (p0, z1), + z0 = svrintm_x (p0, z1)) + +/* +** ptrue_rintm_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f32_x_tied1, svfloat32_t, + z0 = svrintm_f32_x (svptrue_b32 (), z0), + z0 = svrintm_x (svptrue_b32 (), z0)) + +/* +** ptrue_rintm_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f32_x_untied, svfloat32_t, + z0 = svrintm_f32_x (svptrue_b32 (), z1), + z0 = svrintm_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c new file mode 100644 index 00000000000..ecbb2444766 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintm_f64_m_tied12: +** frintm z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_m_tied12, svfloat64_t, + z0 = svrintm_f64_m (z0, p0, z0), + z0 = svrintm_m (z0, p0, z0)) + +/* +** rintm_f64_m_tied1: +** frintm z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_m_tied1, svfloat64_t, + z0 = svrintm_f64_m (z0, p0, z1), + z0 = svrintm_m (z0, p0, z1)) + +/* +** rintm_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frintm z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_m_tied2, svfloat64_t, + z0 = svrintm_f64_m (z1, p0, z0), + z0 = svrintm_m (z1, p0, z0)) + +/* +** rintm_f64_m_untied: +** movprfx z0, z2 +** frintm z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_m_untied, svfloat64_t, + z0 = svrintm_f64_m (z2, p0, z1), + z0 = svrintm_m (z2, p0, z1)) + +/* +** rintm_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frintm z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_z_tied1, svfloat64_t, + z0 = svrintm_f64_z (p0, z0), + z0 = svrintm_z (p0, z0)) + +/* +** rintm_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frintm z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_z_untied, svfloat64_t, + z0 = svrintm_f64_z (p0, z1), + z0 = svrintm_z (p0, z1)) + +/* +** rintm_f64_x_tied1: +** frintm z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_x_tied1, svfloat64_t, + z0 = svrintm_f64_x (p0, z0), + z0 = svrintm_x (p0, z0)) + +/* +** rintm_f64_x_untied: +** frintm z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintm_f64_x_untied, svfloat64_t, + z0 = svrintm_f64_x (p0, z1), + z0 = svrintm_x (p0, z1)) + +/* +** ptrue_rintm_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f64_x_tied1, svfloat64_t, + z0 = svrintm_f64_x (svptrue_b64 (), z0), + z0 = svrintm_x (svptrue_b64 (), z0)) + +/* +** ptrue_rintm_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintm_f64_x_untied, svfloat64_t, + z0 = svrintm_f64_x (svptrue_b64 (), z1), + z0 = svrintm_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c new file mode 100644 index 00000000000..273307ef134 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintn_f16_m_tied12: +** frintn z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_m_tied12, svfloat16_t, + z0 = svrintn_f16_m (z0, p0, z0), + z0 = svrintn_m (z0, p0, z0)) + +/* +** rintn_f16_m_tied1: +** frintn z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_m_tied1, svfloat16_t, + z0 = svrintn_f16_m (z0, p0, z1), + z0 = svrintn_m (z0, p0, z1)) + +/* +** rintn_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintn z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_m_tied2, svfloat16_t, + z0 = svrintn_f16_m (z1, p0, z0), + z0 = svrintn_m (z1, p0, z0)) + +/* +** rintn_f16_m_untied: +** movprfx z0, z2 +** frintn z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_m_untied, svfloat16_t, + z0 = svrintn_f16_m (z2, p0, z1), + z0 = svrintn_m (z2, p0, z1)) + +/* +** rintn_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frintn z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_z_tied1, svfloat16_t, + z0 = svrintn_f16_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frintn z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_z_untied, svfloat16_t, + z0 = svrintn_f16_z (p0, z1), + z0 = svrintn_z (p0, z1)) + +/* +** rintn_f16_x_tied1: +** frintn z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_x_tied1, svfloat16_t, + z0 = svrintn_f16_x (p0, z0), + z0 = svrintn_x (p0, z0)) + +/* +** rintn_f16_x_untied: +** frintn z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintn_f16_x_untied, svfloat16_t, + z0 = svrintn_f16_x (p0, z1), + z0 = svrintn_x (p0, z1)) + +/* +** ptrue_rintn_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f16_x_tied1, svfloat16_t, + z0 = svrintn_f16_x (svptrue_b16 (), z0), + z0 = svrintn_x (svptrue_b16 (), z0)) + +/* +** ptrue_rintn_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f16_x_untied, svfloat16_t, + z0 = svrintn_f16_x (svptrue_b16 (), z1), + z0 = svrintn_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c new file mode 100644 index 00000000000..bafd43106d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintn_f32_m_tied12: +** frintn z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_m_tied12, svfloat32_t, + z0 = svrintn_f32_m (z0, p0, z0), + z0 = svrintn_m (z0, p0, z0)) + +/* +** rintn_f32_m_tied1: +** frintn z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_m_tied1, svfloat32_t, + z0 = svrintn_f32_m (z0, p0, z1), + z0 = svrintn_m (z0, p0, z1)) + +/* +** rintn_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintn z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_m_tied2, svfloat32_t, + z0 = svrintn_f32_m (z1, p0, z0), + z0 = svrintn_m (z1, p0, z0)) + +/* +** rintn_f32_m_untied: +** movprfx z0, z2 +** frintn z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_m_untied, svfloat32_t, + z0 = svrintn_f32_m (z2, p0, z1), + z0 = svrintn_m (z2, p0, z1)) + +/* +** rintn_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frintn z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_z_tied1, svfloat32_t, + z0 = svrintn_f32_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frintn z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_z_untied, svfloat32_t, + z0 = svrintn_f32_z (p0, z1), + z0 = svrintn_z (p0, z1)) + +/* +** rintn_f32_x_tied1: +** frintn z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_x_tied1, svfloat32_t, + z0 = svrintn_f32_x (p0, z0), + z0 = svrintn_x (p0, z0)) + +/* +** rintn_f32_x_untied: +** frintn z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintn_f32_x_untied, svfloat32_t, + z0 = svrintn_f32_x (p0, z1), + z0 = svrintn_x (p0, z1)) + +/* +** ptrue_rintn_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f32_x_tied1, svfloat32_t, + z0 = svrintn_f32_x (svptrue_b32 (), z0), + z0 = svrintn_x (svptrue_b32 (), z0)) + +/* +** ptrue_rintn_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f32_x_untied, svfloat32_t, + z0 = svrintn_f32_x (svptrue_b32 (), z1), + z0 = svrintn_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c new file mode 100644 index 00000000000..0142315e695 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintn_f64_m_tied12: +** frintn z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_m_tied12, svfloat64_t, + z0 = svrintn_f64_m (z0, p0, z0), + z0 = svrintn_m (z0, p0, z0)) + +/* +** rintn_f64_m_tied1: +** frintn z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_m_tied1, svfloat64_t, + z0 = svrintn_f64_m (z0, p0, z1), + z0 = svrintn_m (z0, p0, z1)) + +/* +** rintn_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frintn z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_m_tied2, svfloat64_t, + z0 = svrintn_f64_m (z1, p0, z0), + z0 = svrintn_m (z1, p0, z0)) + +/* +** rintn_f64_m_untied: +** movprfx z0, z2 +** frintn z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_m_untied, svfloat64_t, + z0 = svrintn_f64_m (z2, p0, z1), + z0 = svrintn_m (z2, p0, z1)) + +/* +** rintn_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frintn z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_z_tied1, svfloat64_t, + z0 = svrintn_f64_z (p0, z0), + z0 = svrintn_z (p0, z0)) + +/* +** rintn_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frintn z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_z_untied, svfloat64_t, + z0 = svrintn_f64_z (p0, z1), + z0 = svrintn_z (p0, z1)) + +/* +** rintn_f64_x_tied1: +** frintn z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_x_tied1, svfloat64_t, + z0 = svrintn_f64_x (p0, z0), + z0 = svrintn_x (p0, z0)) + +/* +** rintn_f64_x_untied: +** frintn z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintn_f64_x_untied, svfloat64_t, + z0 = svrintn_f64_x (p0, z1), + z0 = svrintn_x (p0, z1)) + +/* +** ptrue_rintn_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f64_x_tied1, svfloat64_t, + z0 = svrintn_f64_x (svptrue_b64 (), z0), + z0 = svrintn_x (svptrue_b64 (), z0)) + +/* +** ptrue_rintn_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintn_f64_x_untied, svfloat64_t, + z0 = svrintn_f64_x (svptrue_b64 (), z1), + z0 = svrintn_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c new file mode 100644 index 00000000000..0e85c34481a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintp_f16_m_tied12: +** frintp z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_m_tied12, svfloat16_t, + z0 = svrintp_f16_m (z0, p0, z0), + z0 = svrintp_m (z0, p0, z0)) + +/* +** rintp_f16_m_tied1: +** frintp z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_m_tied1, svfloat16_t, + z0 = svrintp_f16_m (z0, p0, z1), + z0 = svrintp_m (z0, p0, z1)) + +/* +** rintp_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintp z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_m_tied2, svfloat16_t, + z0 = svrintp_f16_m (z1, p0, z0), + z0 = svrintp_m (z1, p0, z0)) + +/* +** rintp_f16_m_untied: +** movprfx z0, z2 +** frintp z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_m_untied, svfloat16_t, + z0 = svrintp_f16_m (z2, p0, z1), + z0 = svrintp_m (z2, p0, z1)) + +/* +** rintp_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frintp z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_z_tied1, svfloat16_t, + z0 = svrintp_f16_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frintp z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_z_untied, svfloat16_t, + z0 = svrintp_f16_z (p0, z1), + z0 = svrintp_z (p0, z1)) + +/* +** rintp_f16_x_tied1: +** frintp z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_x_tied1, svfloat16_t, + z0 = svrintp_f16_x (p0, z0), + z0 = svrintp_x (p0, z0)) + +/* +** rintp_f16_x_untied: +** frintp z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintp_f16_x_untied, svfloat16_t, + z0 = svrintp_f16_x (p0, z1), + z0 = svrintp_x (p0, z1)) + +/* +** ptrue_rintp_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f16_x_tied1, svfloat16_t, + z0 = svrintp_f16_x (svptrue_b16 (), z0), + z0 = svrintp_x (svptrue_b16 (), z0)) + +/* +** ptrue_rintp_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f16_x_untied, svfloat16_t, + z0 = svrintp_f16_x (svptrue_b16 (), z1), + z0 = svrintp_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c new file mode 100644 index 00000000000..cec360d7cce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintp_f32_m_tied12: +** frintp z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_m_tied12, svfloat32_t, + z0 = svrintp_f32_m (z0, p0, z0), + z0 = svrintp_m (z0, p0, z0)) + +/* +** rintp_f32_m_tied1: +** frintp z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_m_tied1, svfloat32_t, + z0 = svrintp_f32_m (z0, p0, z1), + z0 = svrintp_m (z0, p0, z1)) + +/* +** rintp_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintp z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_m_tied2, svfloat32_t, + z0 = svrintp_f32_m (z1, p0, z0), + z0 = svrintp_m (z1, p0, z0)) + +/* +** rintp_f32_m_untied: +** movprfx z0, z2 +** frintp z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_m_untied, svfloat32_t, + z0 = svrintp_f32_m (z2, p0, z1), + z0 = svrintp_m (z2, p0, z1)) + +/* +** rintp_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frintp z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_z_tied1, svfloat32_t, + z0 = svrintp_f32_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frintp z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_z_untied, svfloat32_t, + z0 = svrintp_f32_z (p0, z1), + z0 = svrintp_z (p0, z1)) + +/* +** rintp_f32_x_tied1: +** frintp z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_x_tied1, svfloat32_t, + z0 = svrintp_f32_x (p0, z0), + z0 = svrintp_x (p0, z0)) + +/* +** rintp_f32_x_untied: +** frintp z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintp_f32_x_untied, svfloat32_t, + z0 = svrintp_f32_x (p0, z1), + z0 = svrintp_x (p0, z1)) + +/* +** ptrue_rintp_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f32_x_tied1, svfloat32_t, + z0 = svrintp_f32_x (svptrue_b32 (), z0), + z0 = svrintp_x (svptrue_b32 (), z0)) + +/* +** ptrue_rintp_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f32_x_untied, svfloat32_t, + z0 = svrintp_f32_x (svptrue_b32 (), z1), + z0 = svrintp_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c new file mode 100644 index 00000000000..1305fb6823f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintp_f64_m_tied12: +** frintp z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_m_tied12, svfloat64_t, + z0 = svrintp_f64_m (z0, p0, z0), + z0 = svrintp_m (z0, p0, z0)) + +/* +** rintp_f64_m_tied1: +** frintp z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_m_tied1, svfloat64_t, + z0 = svrintp_f64_m (z0, p0, z1), + z0 = svrintp_m (z0, p0, z1)) + +/* +** rintp_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frintp z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_m_tied2, svfloat64_t, + z0 = svrintp_f64_m (z1, p0, z0), + z0 = svrintp_m (z1, p0, z0)) + +/* +** rintp_f64_m_untied: +** movprfx z0, z2 +** frintp z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_m_untied, svfloat64_t, + z0 = svrintp_f64_m (z2, p0, z1), + z0 = svrintp_m (z2, p0, z1)) + +/* +** rintp_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frintp z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_z_tied1, svfloat64_t, + z0 = svrintp_f64_z (p0, z0), + z0 = svrintp_z (p0, z0)) + +/* +** rintp_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frintp z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_z_untied, svfloat64_t, + z0 = svrintp_f64_z (p0, z1), + z0 = svrintp_z (p0, z1)) + +/* +** rintp_f64_x_tied1: +** frintp z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_x_tied1, svfloat64_t, + z0 = svrintp_f64_x (p0, z0), + z0 = svrintp_x (p0, z0)) + +/* +** rintp_f64_x_untied: +** frintp z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintp_f64_x_untied, svfloat64_t, + z0 = svrintp_f64_x (p0, z1), + z0 = svrintp_x (p0, z1)) + +/* +** ptrue_rintp_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f64_x_tied1, svfloat64_t, + z0 = svrintp_f64_x (svptrue_b64 (), z0), + z0 = svrintp_x (svptrue_b64 (), z0)) + +/* +** ptrue_rintp_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintp_f64_x_untied, svfloat64_t, + z0 = svrintp_f64_x (svptrue_b64 (), z1), + z0 = svrintp_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c new file mode 100644 index 00000000000..96f7f2c7206 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintx_f16_m_tied12: +** frintx z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_m_tied12, svfloat16_t, + z0 = svrintx_f16_m (z0, p0, z0), + z0 = svrintx_m (z0, p0, z0)) + +/* +** rintx_f16_m_tied1: +** frintx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_m_tied1, svfloat16_t, + z0 = svrintx_f16_m (z0, p0, z1), + z0 = svrintx_m (z0, p0, z1)) + +/* +** rintx_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintx z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_m_tied2, svfloat16_t, + z0 = svrintx_f16_m (z1, p0, z0), + z0 = svrintx_m (z1, p0, z0)) + +/* +** rintx_f16_m_untied: +** movprfx z0, z2 +** frintx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_m_untied, svfloat16_t, + z0 = svrintx_f16_m (z2, p0, z1), + z0 = svrintx_m (z2, p0, z1)) + +/* +** rintx_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frintx z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_z_tied1, svfloat16_t, + z0 = svrintx_f16_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frintx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_z_untied, svfloat16_t, + z0 = svrintx_f16_z (p0, z1), + z0 = svrintx_z (p0, z1)) + +/* +** rintx_f16_x_tied1: +** frintx z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_x_tied1, svfloat16_t, + z0 = svrintx_f16_x (p0, z0), + z0 = svrintx_x (p0, z0)) + +/* +** rintx_f16_x_untied: +** frintx z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintx_f16_x_untied, svfloat16_t, + z0 = svrintx_f16_x (p0, z1), + z0 = svrintx_x (p0, z1)) + +/* +** ptrue_rintx_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f16_x_tied1, svfloat16_t, + z0 = svrintx_f16_x (svptrue_b16 (), z0), + z0 = svrintx_x (svptrue_b16 (), z0)) + +/* +** ptrue_rintx_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f16_x_untied, svfloat16_t, + z0 = svrintx_f16_x (svptrue_b16 (), z1), + z0 = svrintx_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c new file mode 100644 index 00000000000..1c42d2a9480 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintx_f32_m_tied12: +** frintx z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_m_tied12, svfloat32_t, + z0 = svrintx_f32_m (z0, p0, z0), + z0 = svrintx_m (z0, p0, z0)) + +/* +** rintx_f32_m_tied1: +** frintx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_m_tied1, svfloat32_t, + z0 = svrintx_f32_m (z0, p0, z1), + z0 = svrintx_m (z0, p0, z1)) + +/* +** rintx_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintx z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_m_tied2, svfloat32_t, + z0 = svrintx_f32_m (z1, p0, z0), + z0 = svrintx_m (z1, p0, z0)) + +/* +** rintx_f32_m_untied: +** movprfx z0, z2 +** frintx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_m_untied, svfloat32_t, + z0 = svrintx_f32_m (z2, p0, z1), + z0 = svrintx_m (z2, p0, z1)) + +/* +** rintx_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frintx z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_z_tied1, svfloat32_t, + z0 = svrintx_f32_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frintx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_z_untied, svfloat32_t, + z0 = svrintx_f32_z (p0, z1), + z0 = svrintx_z (p0, z1)) + +/* +** rintx_f32_x_tied1: +** frintx z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_x_tied1, svfloat32_t, + z0 = svrintx_f32_x (p0, z0), + z0 = svrintx_x (p0, z0)) + +/* +** rintx_f32_x_untied: +** frintx z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintx_f32_x_untied, svfloat32_t, + z0 = svrintx_f32_x (p0, z1), + z0 = svrintx_x (p0, z1)) + +/* +** ptrue_rintx_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f32_x_tied1, svfloat32_t, + z0 = svrintx_f32_x (svptrue_b32 (), z0), + z0 = svrintx_x (svptrue_b32 (), z0)) + +/* +** ptrue_rintx_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f32_x_untied, svfloat32_t, + z0 = svrintx_f32_x (svptrue_b32 (), z1), + z0 = svrintx_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c new file mode 100644 index 00000000000..bee806b3bee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintx_f64_m_tied12: +** frintx z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_m_tied12, svfloat64_t, + z0 = svrintx_f64_m (z0, p0, z0), + z0 = svrintx_m (z0, p0, z0)) + +/* +** rintx_f64_m_tied1: +** frintx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_m_tied1, svfloat64_t, + z0 = svrintx_f64_m (z0, p0, z1), + z0 = svrintx_m (z0, p0, z1)) + +/* +** rintx_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frintx z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_m_tied2, svfloat64_t, + z0 = svrintx_f64_m (z1, p0, z0), + z0 = svrintx_m (z1, p0, z0)) + +/* +** rintx_f64_m_untied: +** movprfx z0, z2 +** frintx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_m_untied, svfloat64_t, + z0 = svrintx_f64_m (z2, p0, z1), + z0 = svrintx_m (z2, p0, z1)) + +/* +** rintx_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frintx z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_z_tied1, svfloat64_t, + z0 = svrintx_f64_z (p0, z0), + z0 = svrintx_z (p0, z0)) + +/* +** rintx_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frintx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_z_untied, svfloat64_t, + z0 = svrintx_f64_z (p0, z1), + z0 = svrintx_z (p0, z1)) + +/* +** rintx_f64_x_tied1: +** frintx z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_x_tied1, svfloat64_t, + z0 = svrintx_f64_x (p0, z0), + z0 = svrintx_x (p0, z0)) + +/* +** rintx_f64_x_untied: +** frintx z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintx_f64_x_untied, svfloat64_t, + z0 = svrintx_f64_x (p0, z1), + z0 = svrintx_x (p0, z1)) + +/* +** ptrue_rintx_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f64_x_tied1, svfloat64_t, + z0 = svrintx_f64_x (svptrue_b64 (), z0), + z0 = svrintx_x (svptrue_b64 (), z0)) + +/* +** ptrue_rintx_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintx_f64_x_untied, svfloat64_t, + z0 = svrintx_f64_x (svptrue_b64 (), z1), + z0 = svrintx_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c new file mode 100644 index 00000000000..be13d82b4a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintz_f16_m_tied12: +** frintz z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_m_tied12, svfloat16_t, + z0 = svrintz_f16_m (z0, p0, z0), + z0 = svrintz_m (z0, p0, z0)) + +/* +** rintz_f16_m_tied1: +** frintz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_m_tied1, svfloat16_t, + z0 = svrintz_f16_m (z0, p0, z1), + z0 = svrintz_m (z0, p0, z1)) + +/* +** rintz_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintz z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_m_tied2, svfloat16_t, + z0 = svrintz_f16_m (z1, p0, z0), + z0 = svrintz_m (z1, p0, z0)) + +/* +** rintz_f16_m_untied: +** movprfx z0, z2 +** frintz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_m_untied, svfloat16_t, + z0 = svrintz_f16_m (z2, p0, z1), + z0 = svrintz_m (z2, p0, z1)) + +/* +** rintz_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** frintz z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_z_tied1, svfloat16_t, + z0 = svrintz_f16_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** frintz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_z_untied, svfloat16_t, + z0 = svrintz_f16_z (p0, z1), + z0 = svrintz_z (p0, z1)) + +/* +** rintz_f16_x_tied1: +** frintz z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_x_tied1, svfloat16_t, + z0 = svrintz_f16_x (p0, z0), + z0 = svrintz_x (p0, z0)) + +/* +** rintz_f16_x_untied: +** frintz z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rintz_f16_x_untied, svfloat16_t, + z0 = svrintz_f16_x (p0, z1), + z0 = svrintz_x (p0, z1)) + +/* +** ptrue_rintz_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f16_x_tied1, svfloat16_t, + z0 = svrintz_f16_x (svptrue_b16 (), z0), + z0 = svrintz_x (svptrue_b16 (), z0)) + +/* +** ptrue_rintz_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f16_x_untied, svfloat16_t, + z0 = svrintz_f16_x (svptrue_b16 (), z1), + z0 = svrintz_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c new file mode 100644 index 00000000000..873c0d468ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintz_f32_m_tied12: +** frintz z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_m_tied12, svfloat32_t, + z0 = svrintz_f32_m (z0, p0, z0), + z0 = svrintz_m (z0, p0, z0)) + +/* +** rintz_f32_m_tied1: +** frintz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_m_tied1, svfloat32_t, + z0 = svrintz_f32_m (z0, p0, z1), + z0 = svrintz_m (z0, p0, z1)) + +/* +** rintz_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** frintz z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_m_tied2, svfloat32_t, + z0 = svrintz_f32_m (z1, p0, z0), + z0 = svrintz_m (z1, p0, z0)) + +/* +** rintz_f32_m_untied: +** movprfx z0, z2 +** frintz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_m_untied, svfloat32_t, + z0 = svrintz_f32_m (z2, p0, z1), + z0 = svrintz_m (z2, p0, z1)) + +/* +** rintz_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** frintz z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_z_tied1, svfloat32_t, + z0 = svrintz_f32_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** frintz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_z_untied, svfloat32_t, + z0 = svrintz_f32_z (p0, z1), + z0 = svrintz_z (p0, z1)) + +/* +** rintz_f32_x_tied1: +** frintz z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_x_tied1, svfloat32_t, + z0 = svrintz_f32_x (p0, z0), + z0 = svrintz_x (p0, z0)) + +/* +** rintz_f32_x_untied: +** frintz z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rintz_f32_x_untied, svfloat32_t, + z0 = svrintz_f32_x (p0, z1), + z0 = svrintz_x (p0, z1)) + +/* +** ptrue_rintz_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f32_x_tied1, svfloat32_t, + z0 = svrintz_f32_x (svptrue_b32 (), z0), + z0 = svrintz_x (svptrue_b32 (), z0)) + +/* +** ptrue_rintz_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f32_x_untied, svfloat32_t, + z0 = svrintz_f32_x (svptrue_b32 (), z1), + z0 = svrintz_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c new file mode 100644 index 00000000000..e6c9d1fc86f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rintz_f64_m_tied12: +** frintz z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_m_tied12, svfloat64_t, + z0 = svrintz_f64_m (z0, p0, z0), + z0 = svrintz_m (z0, p0, z0)) + +/* +** rintz_f64_m_tied1: +** frintz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_m_tied1, svfloat64_t, + z0 = svrintz_f64_m (z0, p0, z1), + z0 = svrintz_m (z0, p0, z1)) + +/* +** rintz_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** frintz z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_m_tied2, svfloat64_t, + z0 = svrintz_f64_m (z1, p0, z0), + z0 = svrintz_m (z1, p0, z0)) + +/* +** rintz_f64_m_untied: +** movprfx z0, z2 +** frintz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_m_untied, svfloat64_t, + z0 = svrintz_f64_m (z2, p0, z1), + z0 = svrintz_m (z2, p0, z1)) + +/* +** rintz_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** frintz z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_z_tied1, svfloat64_t, + z0 = svrintz_f64_z (p0, z0), + z0 = svrintz_z (p0, z0)) + +/* +** rintz_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** frintz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_z_untied, svfloat64_t, + z0 = svrintz_f64_z (p0, z1), + z0 = svrintz_z (p0, z1)) + +/* +** rintz_f64_x_tied1: +** frintz z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_x_tied1, svfloat64_t, + z0 = svrintz_f64_x (p0, z0), + z0 = svrintz_x (p0, z0)) + +/* +** rintz_f64_x_untied: +** frintz z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rintz_f64_x_untied, svfloat64_t, + z0 = svrintz_f64_x (p0, z1), + z0 = svrintz_x (p0, z1)) + +/* +** ptrue_rintz_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f64_x_tied1, svfloat64_t, + z0 = svrintz_f64_x (svptrue_b64 (), z0), + z0 = svrintz_x (svptrue_b64 (), z0)) + +/* +** ptrue_rintz_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_rintz_f64_x_untied, svfloat64_t, + z0 = svrintz_f64_x (svptrue_b64 (), z1), + z0 = svrintz_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f16.c new file mode 100644 index 00000000000..adfdc2b9c54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrte_f16_tied1: +** frsqrte z0\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f16_tied1, svfloat16_t, + z0 = svrsqrte_f16 (z0), + z0 = svrsqrte (z0)) + +/* +** rsqrte_f16_untied: +** frsqrte z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f16_untied, svfloat16_t, + z0 = svrsqrte_f16 (z1), + z0 = svrsqrte (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f32.c new file mode 100644 index 00000000000..fd938ebdf72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrte_f32_tied1: +** frsqrte z0\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f32_tied1, svfloat32_t, + z0 = svrsqrte_f32 (z0), + z0 = svrsqrte (z0)) + +/* +** rsqrte_f32_untied: +** frsqrte z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f32_untied, svfloat32_t, + z0 = svrsqrte_f32 (z1), + z0 = svrsqrte (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f64.c new file mode 100644 index 00000000000..3ac0f40537a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrte_f64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrte_f64_tied1: +** frsqrte z0\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f64_tied1, svfloat64_t, + z0 = svrsqrte_f64 (z0), + z0 = svrsqrte (z0)) + +/* +** rsqrte_f64_untied: +** frsqrte z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rsqrte_f64_untied, svfloat64_t, + z0 = svrsqrte_f64 (z1), + z0 = svrsqrte (z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f16.c new file mode 100644 index 00000000000..2d88be3d6c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrts_f16_tied1: +** frsqrts z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f16_tied1, svfloat16_t, + z0 = svrsqrts_f16 (z0, z1), + z0 = svrsqrts (z0, z1)) + +/* +** rsqrts_f16_tied2: +** frsqrts z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f16_tied2, svfloat16_t, + z0 = svrsqrts_f16 (z1, z0), + z0 = svrsqrts (z1, z0)) + +/* +** rsqrts_f16_untied: +** frsqrts z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f16_untied, svfloat16_t, + z0 = svrsqrts_f16 (z1, z2), + z0 = svrsqrts (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f32.c new file mode 100644 index 00000000000..cd76aef4d87 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrts_f32_tied1: +** frsqrts z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f32_tied1, svfloat32_t, + z0 = svrsqrts_f32 (z0, z1), + z0 = svrsqrts (z0, z1)) + +/* +** rsqrts_f32_tied2: +** frsqrts z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f32_tied2, svfloat32_t, + z0 = svrsqrts_f32 (z1, z0), + z0 = svrsqrts (z1, z0)) + +/* +** rsqrts_f32_untied: +** frsqrts z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f32_untied, svfloat32_t, + z0 = svrsqrts_f32 (z1, z2), + z0 = svrsqrts (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f64.c new file mode 100644 index 00000000000..e72a82fcb7a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rsqrts_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** rsqrts_f64_tied1: +** frsqrts z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f64_tied1, svfloat64_t, + z0 = svrsqrts_f64 (z0, z1), + z0 = svrsqrts (z0, z1)) + +/* +** rsqrts_f64_tied2: +** frsqrts z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f64_tied2, svfloat64_t, + z0 = svrsqrts_f64 (z1, z0), + z0 = svrsqrts (z1, z0)) + +/* +** rsqrts_f64_untied: +** frsqrts z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (rsqrts_f64_untied, svfloat64_t, + z0 = svrsqrts_f64 (z1, z2), + z0 = svrsqrts (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c new file mode 100644 index 00000000000..9c554255b44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c @@ -0,0 +1,330 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** scale_f16_m_tied1: +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_m_tied1, svfloat16_t, svint16_t, + z0 = svscale_f16_m (p0, z0, z4), + z0 = svscale_m (p0, z0, z4)) + +/* +** scale_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fscale z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (scale_f16_m_tied2, svfloat16_t, svint16_t, + z0_res = svscale_f16_m (p0, z4, z0), + z0_res = svscale_m (p0, z4, z0)) + +/* +** scale_f16_m_untied: +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_m_untied, svfloat16_t, svint16_t, + z0 = svscale_f16_m (p0, z1, z4), + z0 = svscale_m (p0, z1, z4)) + +/* +** scale_w0_f16_m_tied1: +** mov (z[0-9]+\.h), w0 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_m_tied1, svfloat16_t, int16_t, + z0 = svscale_n_f16_m (p0, z0, x0), + z0 = svscale_m (p0, z0, x0)) + +/* +** scale_w0_f16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_m_untied, svfloat16_t, int16_t, + z0 = svscale_n_f16_m (p0, z1, x0), + z0 = svscale_m (p0, z1, x0)) + +/* +** scale_3_f16_m_tied1: +** mov (z[0-9]+\.h), #3 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_m_tied1, svfloat16_t, + z0 = svscale_n_f16_m (p0, z0, 3), + z0 = svscale_m (p0, z0, 3)) + +/* +** scale_3_f16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #3 +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_m_untied, svfloat16_t, + z0 = svscale_n_f16_m (p0, z1, 3), + z0 = svscale_m (p0, z1, 3)) + +/* +** scale_m3_f16_m: +** mov (z[0-9]+\.h), #-3 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f16_m, svfloat16_t, + z0 = svscale_n_f16_m (p0, z0, -3), + z0 = svscale_m (p0, z0, -3)) + +/* +** scale_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_z_tied1, svfloat16_t, svint16_t, + z0 = svscale_f16_z (p0, z0, z4), + z0 = svscale_z (p0, z0, z4)) + +/* +** scale_f16_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, z4\.h +** fscale z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (scale_f16_z_tied2, svfloat16_t, svint16_t, + z0_res = svscale_f16_z (p0, z4, z0), + z0_res = svscale_z (p0, z4, z0)) + +/* +** scale_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_z_untied, svfloat16_t, svint16_t, + z0 = svscale_f16_z (p0, z1, z4), + z0 = svscale_z (p0, z1, z4)) + +/* +** scale_w0_f16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_z_tied1, svfloat16_t, int16_t, + z0 = svscale_n_f16_z (p0, z0, x0), + z0 = svscale_z (p0, z0, x0)) + +/* +** scale_w0_f16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z1\.h +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_z_untied, svfloat16_t, int16_t, + z0 = svscale_n_f16_z (p0, z1, x0), + z0 = svscale_z (p0, z1, x0)) + +/* +** scale_3_f16_z_tied1: +** mov (z[0-9]+\.h), #3 +** movprfx z0\.h, p0/z, z0\.h +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_z_tied1, svfloat16_t, + z0 = svscale_n_f16_z (p0, z0, 3), + z0 = svscale_z (p0, z0, 3)) + +/* +** scale_3_f16_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #3 +** movprfx z0\.h, p0/z, z1\.h +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_z_untied, svfloat16_t, + z0 = svscale_n_f16_z (p0, z1, 3), + z0 = svscale_z (p0, z1, 3)) + +/* +** scale_m3_f16_z: +** mov (z[0-9]+\.h), #-3 +** movprfx z0\.h, p0/z, z0\.h +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f16_z, svfloat16_t, + z0 = svscale_n_f16_z (p0, z0, -3), + z0 = svscale_z (p0, z0, -3)) + +/* +** scale_f16_x_tied1: +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_x_tied1, svfloat16_t, svint16_t, + z0 = svscale_f16_x (p0, z0, z4), + z0 = svscale_x (p0, z0, z4)) + +/* +** scale_f16_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fscale z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_DUAL_Z_REV (scale_f16_x_tied2, svfloat16_t, svint16_t, + z0_res = svscale_f16_x (p0, z4, z0), + z0_res = svscale_x (p0, z4, z0)) + +/* +** scale_f16_x_untied: +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (scale_f16_x_untied, svfloat16_t, svint16_t, + z0 = svscale_f16_x (p0, z1, z4), + z0 = svscale_x (p0, z1, z4)) + +/* +** scale_w0_f16_x_tied1: +** mov (z[0-9]+\.h), w0 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_x_tied1, svfloat16_t, int16_t, + z0 = svscale_n_f16_x (p0, z0, x0), + z0 = svscale_x (p0, z0, x0)) + +/* +** scale_w0_f16_x_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f16_x_untied, svfloat16_t, int16_t, + z0 = svscale_n_f16_x (p0, z1, x0), + z0 = svscale_x (p0, z1, x0)) + +/* +** scale_3_f16_x_tied1: +** mov (z[0-9]+\.h), #3 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_x_tied1, svfloat16_t, + z0 = svscale_n_f16_x (p0, z0, 3), + z0 = svscale_x (p0, z0, 3)) + +/* +** scale_3_f16_x_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #3 +** movprfx z0, z1 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f16_x_untied, svfloat16_t, + z0 = svscale_n_f16_x (p0, z1, 3), + z0 = svscale_x (p0, z1, 3)) + +/* +** scale_m3_f16_x: +** mov (z[0-9]+\.h), #-3 +** fscale z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f16_x, svfloat16_t, + z0 = svscale_n_f16_x (p0, z0, -3), + z0 = svscale_x (p0, z0, -3)) + +/* +** ptrue_scale_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f16_x_tied1, svfloat16_t, svint16_t, + z0 = svscale_f16_x (svptrue_b16 (), z0, z4), + z0 = svscale_x (svptrue_b16 (), z0, z4)) + +/* +** ptrue_scale_f16_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_scale_f16_x_tied2, svfloat16_t, svint16_t, + z0_res = svscale_f16_x (svptrue_b16 (), z4, z0), + z0_res = svscale_x (svptrue_b16 (), z4, z0)) + +/* +** ptrue_scale_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f16_x_untied, svfloat16_t, svint16_t, + z0 = svscale_f16_x (svptrue_b16 (), z1, z4), + z0 = svscale_x (svptrue_b16 (), z1, z4)) + +/* +** ptrue_scale_3_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f16_x_tied1, svfloat16_t, + z0 = svscale_n_f16_x (svptrue_b16 (), z0, 3), + z0 = svscale_x (svptrue_b16 (), z0, 3)) + +/* +** ptrue_scale_3_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f16_x_untied, svfloat16_t, + z0 = svscale_n_f16_x (svptrue_b16 (), z1, 3), + z0 = svscale_x (svptrue_b16 (), z1, 3)) + +/* +** ptrue_scale_m3_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f16_x_tied1, svfloat16_t, + z0 = svscale_n_f16_x (svptrue_b16 (), z0, -3), + z0 = svscale_x (svptrue_b16 (), z0, -3)) + +/* +** ptrue_scale_m3_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f16_x_untied, svfloat16_t, + z0 = svscale_n_f16_x (svptrue_b16 (), z1, -3), + z0 = svscale_x (svptrue_b16 (), z1, -3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f32.c new file mode 100644 index 00000000000..747f8a6397b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f32.c @@ -0,0 +1,330 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** scale_f32_m_tied1: +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_m_tied1, svfloat32_t, svint32_t, + z0 = svscale_f32_m (p0, z0, z4), + z0 = svscale_m (p0, z0, z4)) + +/* +** scale_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fscale z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (scale_f32_m_tied2, svfloat32_t, svint32_t, + z0_res = svscale_f32_m (p0, z4, z0), + z0_res = svscale_m (p0, z4, z0)) + +/* +** scale_f32_m_untied: +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_m_untied, svfloat32_t, svint32_t, + z0 = svscale_f32_m (p0, z1, z4), + z0 = svscale_m (p0, z1, z4)) + +/* +** scale_w0_f32_m_tied1: +** mov (z[0-9]+\.s), w0 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_m_tied1, svfloat32_t, int32_t, + z0 = svscale_n_f32_m (p0, z0, x0), + z0 = svscale_m (p0, z0, x0)) + +/* +** scale_w0_f32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_m_untied, svfloat32_t, int32_t, + z0 = svscale_n_f32_m (p0, z1, x0), + z0 = svscale_m (p0, z1, x0)) + +/* +** scale_3_f32_m_tied1: +** mov (z[0-9]+\.s), #3 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_m_tied1, svfloat32_t, + z0 = svscale_n_f32_m (p0, z0, 3), + z0 = svscale_m (p0, z0, 3)) + +/* +** scale_3_f32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #3 +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_m_untied, svfloat32_t, + z0 = svscale_n_f32_m (p0, z1, 3), + z0 = svscale_m (p0, z1, 3)) + +/* +** scale_m3_f32_m: +** mov (z[0-9]+\.s), #-3 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f32_m, svfloat32_t, + z0 = svscale_n_f32_m (p0, z0, -3), + z0 = svscale_m (p0, z0, -3)) + +/* +** scale_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_z_tied1, svfloat32_t, svint32_t, + z0 = svscale_f32_z (p0, z0, z4), + z0 = svscale_z (p0, z0, z4)) + +/* +** scale_f32_z_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, z4\.s +** fscale z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (scale_f32_z_tied2, svfloat32_t, svint32_t, + z0_res = svscale_f32_z (p0, z4, z0), + z0_res = svscale_z (p0, z4, z0)) + +/* +** scale_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_z_untied, svfloat32_t, svint32_t, + z0 = svscale_f32_z (p0, z1, z4), + z0 = svscale_z (p0, z1, z4)) + +/* +** scale_w0_f32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_z_tied1, svfloat32_t, int32_t, + z0 = svscale_n_f32_z (p0, z0, x0), + z0 = svscale_z (p0, z0, x0)) + +/* +** scale_w0_f32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z1\.s +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_z_untied, svfloat32_t, int32_t, + z0 = svscale_n_f32_z (p0, z1, x0), + z0 = svscale_z (p0, z1, x0)) + +/* +** scale_3_f32_z_tied1: +** mov (z[0-9]+\.s), #3 +** movprfx z0\.s, p0/z, z0\.s +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_z_tied1, svfloat32_t, + z0 = svscale_n_f32_z (p0, z0, 3), + z0 = svscale_z (p0, z0, 3)) + +/* +** scale_3_f32_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #3 +** movprfx z0\.s, p0/z, z1\.s +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_z_untied, svfloat32_t, + z0 = svscale_n_f32_z (p0, z1, 3), + z0 = svscale_z (p0, z1, 3)) + +/* +** scale_m3_f32_z: +** mov (z[0-9]+\.s), #-3 +** movprfx z0\.s, p0/z, z0\.s +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f32_z, svfloat32_t, + z0 = svscale_n_f32_z (p0, z0, -3), + z0 = svscale_z (p0, z0, -3)) + +/* +** scale_f32_x_tied1: +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_x_tied1, svfloat32_t, svint32_t, + z0 = svscale_f32_x (p0, z0, z4), + z0 = svscale_x (p0, z0, z4)) + +/* +** scale_f32_x_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z4 +** fscale z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_DUAL_Z_REV (scale_f32_x_tied2, svfloat32_t, svint32_t, + z0_res = svscale_f32_x (p0, z4, z0), + z0_res = svscale_x (p0, z4, z0)) + +/* +** scale_f32_x_untied: +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (scale_f32_x_untied, svfloat32_t, svint32_t, + z0 = svscale_f32_x (p0, z1, z4), + z0 = svscale_x (p0, z1, z4)) + +/* +** scale_w0_f32_x_tied1: +** mov (z[0-9]+\.s), w0 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_x_tied1, svfloat32_t, int32_t, + z0 = svscale_n_f32_x (p0, z0, x0), + z0 = svscale_x (p0, z0, x0)) + +/* +** scale_w0_f32_x_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_w0_f32_x_untied, svfloat32_t, int32_t, + z0 = svscale_n_f32_x (p0, z1, x0), + z0 = svscale_x (p0, z1, x0)) + +/* +** scale_3_f32_x_tied1: +** mov (z[0-9]+\.s), #3 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_x_tied1, svfloat32_t, + z0 = svscale_n_f32_x (p0, z0, 3), + z0 = svscale_x (p0, z0, 3)) + +/* +** scale_3_f32_x_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #3 +** movprfx z0, z1 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f32_x_untied, svfloat32_t, + z0 = svscale_n_f32_x (p0, z1, 3), + z0 = svscale_x (p0, z1, 3)) + +/* +** scale_m3_f32_x: +** mov (z[0-9]+\.s), #-3 +** fscale z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f32_x, svfloat32_t, + z0 = svscale_n_f32_x (p0, z0, -3), + z0 = svscale_x (p0, z0, -3)) + +/* +** ptrue_scale_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f32_x_tied1, svfloat32_t, svint32_t, + z0 = svscale_f32_x (svptrue_b32 (), z0, z4), + z0 = svscale_x (svptrue_b32 (), z0, z4)) + +/* +** ptrue_scale_f32_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_scale_f32_x_tied2, svfloat32_t, svint32_t, + z0_res = svscale_f32_x (svptrue_b32 (), z4, z0), + z0_res = svscale_x (svptrue_b32 (), z4, z0)) + +/* +** ptrue_scale_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f32_x_untied, svfloat32_t, svint32_t, + z0 = svscale_f32_x (svptrue_b32 (), z1, z4), + z0 = svscale_x (svptrue_b32 (), z1, z4)) + +/* +** ptrue_scale_3_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f32_x_tied1, svfloat32_t, + z0 = svscale_n_f32_x (svptrue_b32 (), z0, 3), + z0 = svscale_x (svptrue_b32 (), z0, 3)) + +/* +** ptrue_scale_3_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f32_x_untied, svfloat32_t, + z0 = svscale_n_f32_x (svptrue_b32 (), z1, 3), + z0 = svscale_x (svptrue_b32 (), z1, 3)) + +/* +** ptrue_scale_m3_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f32_x_tied1, svfloat32_t, + z0 = svscale_n_f32_x (svptrue_b32 (), z0, -3), + z0 = svscale_x (svptrue_b32 (), z0, -3)) + +/* +** ptrue_scale_m3_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f32_x_untied, svfloat32_t, + z0 = svscale_n_f32_x (svptrue_b32 (), z1, -3), + z0 = svscale_x (svptrue_b32 (), z1, -3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f64.c new file mode 100644 index 00000000000..004cbfa3eff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f64.c @@ -0,0 +1,330 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** scale_f64_m_tied1: +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_m_tied1, svfloat64_t, svint64_t, + z0 = svscale_f64_m (p0, z0, z4), + z0 = svscale_m (p0, z0, z4)) + +/* +** scale_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_DUAL_Z_REV (scale_f64_m_tied2, svfloat64_t, svint64_t, + z0_res = svscale_f64_m (p0, z4, z0), + z0_res = svscale_m (p0, z4, z0)) + +/* +** scale_f64_m_untied: +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_m_untied, svfloat64_t, svint64_t, + z0 = svscale_f64_m (p0, z1, z4), + z0 = svscale_m (p0, z1, z4)) + +/* +** scale_x0_f64_m_tied1: +** mov (z[0-9]+\.d), x0 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_m_tied1, svfloat64_t, int64_t, + z0 = svscale_n_f64_m (p0, z0, x0), + z0 = svscale_m (p0, z0, x0)) + +/* +** scale_x0_f64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_m_untied, svfloat64_t, int64_t, + z0 = svscale_n_f64_m (p0, z1, x0), + z0 = svscale_m (p0, z1, x0)) + +/* +** scale_3_f64_m_tied1: +** mov (z[0-9]+\.d), #3 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_m_tied1, svfloat64_t, + z0 = svscale_n_f64_m (p0, z0, 3), + z0 = svscale_m (p0, z0, 3)) + +/* +** scale_3_f64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #3 +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_m_untied, svfloat64_t, + z0 = svscale_n_f64_m (p0, z1, 3), + z0 = svscale_m (p0, z1, 3)) + +/* +** scale_m3_f64_m: +** mov (z[0-9]+\.d), #-3 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f64_m, svfloat64_t, + z0 = svscale_n_f64_m (p0, z0, -3), + z0 = svscale_m (p0, z0, -3)) + +/* +** scale_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_z_tied1, svfloat64_t, svint64_t, + z0 = svscale_f64_z (p0, z0, z4), + z0 = svscale_z (p0, z0, z4)) + +/* +** scale_f64_z_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, z4\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_DUAL_Z_REV (scale_f64_z_tied2, svfloat64_t, svint64_t, + z0_res = svscale_f64_z (p0, z4, z0), + z0_res = svscale_z (p0, z4, z0)) + +/* +** scale_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_z_untied, svfloat64_t, svint64_t, + z0 = svscale_f64_z (p0, z1, z4), + z0 = svscale_z (p0, z1, z4)) + +/* +** scale_x0_f64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_z_tied1, svfloat64_t, int64_t, + z0 = svscale_n_f64_z (p0, z0, x0), + z0 = svscale_z (p0, z0, x0)) + +/* +** scale_x0_f64_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z1\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_z_untied, svfloat64_t, int64_t, + z0 = svscale_n_f64_z (p0, z1, x0), + z0 = svscale_z (p0, z1, x0)) + +/* +** scale_3_f64_z_tied1: +** mov (z[0-9]+\.d), #3 +** movprfx z0\.d, p0/z, z0\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_z_tied1, svfloat64_t, + z0 = svscale_n_f64_z (p0, z0, 3), + z0 = svscale_z (p0, z0, 3)) + +/* +** scale_3_f64_z_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #3 +** movprfx z0\.d, p0/z, z1\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_z_untied, svfloat64_t, + z0 = svscale_n_f64_z (p0, z1, 3), + z0 = svscale_z (p0, z1, 3)) + +/* +** scale_m3_f64_z: +** mov (z[0-9]+\.d), #-3 +** movprfx z0\.d, p0/z, z0\.d +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f64_z, svfloat64_t, + z0 = svscale_n_f64_z (p0, z0, -3), + z0 = svscale_z (p0, z0, -3)) + +/* +** scale_f64_x_tied1: +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_x_tied1, svfloat64_t, svint64_t, + z0 = svscale_f64_x (p0, z0, z4), + z0 = svscale_x (p0, z0, z4)) + +/* +** scale_f64_x_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z4 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_DUAL_Z_REV (scale_f64_x_tied2, svfloat64_t, svint64_t, + z0_res = svscale_f64_x (p0, z4, z0), + z0_res = svscale_x (p0, z4, z0)) + +/* +** scale_f64_x_untied: +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (scale_f64_x_untied, svfloat64_t, svint64_t, + z0 = svscale_f64_x (p0, z1, z4), + z0 = svscale_x (p0, z1, z4)) + +/* +** scale_x0_f64_x_tied1: +** mov (z[0-9]+\.d), x0 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_x_tied1, svfloat64_t, int64_t, + z0 = svscale_n_f64_x (p0, z0, x0), + z0 = svscale_x (p0, z0, x0)) + +/* +** scale_x0_f64_x_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (scale_x0_f64_x_untied, svfloat64_t, int64_t, + z0 = svscale_n_f64_x (p0, z1, x0), + z0 = svscale_x (p0, z1, x0)) + +/* +** scale_3_f64_x_tied1: +** mov (z[0-9]+\.d), #3 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_x_tied1, svfloat64_t, + z0 = svscale_n_f64_x (p0, z0, 3), + z0 = svscale_x (p0, z0, 3)) + +/* +** scale_3_f64_x_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #3 +** movprfx z0, z1 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_3_f64_x_untied, svfloat64_t, + z0 = svscale_n_f64_x (p0, z1, 3), + z0 = svscale_x (p0, z1, 3)) + +/* +** scale_m3_f64_x: +** mov (z[0-9]+\.d), #-3 +** fscale z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (scale_m3_f64_x, svfloat64_t, + z0 = svscale_n_f64_x (p0, z0, -3), + z0 = svscale_x (p0, z0, -3)) + +/* +** ptrue_scale_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f64_x_tied1, svfloat64_t, svint64_t, + z0 = svscale_f64_x (svptrue_b64 (), z0, z4), + z0 = svscale_x (svptrue_b64 (), z0, z4)) + +/* +** ptrue_scale_f64_x_tied2: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z_REV (ptrue_scale_f64_x_tied2, svfloat64_t, svint64_t, + z0_res = svscale_f64_x (svptrue_b64 (), z4, z0), + z0_res = svscale_x (svptrue_b64 (), z4, z0)) + +/* +** ptrue_scale_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_DUAL_Z (ptrue_scale_f64_x_untied, svfloat64_t, svint64_t, + z0 = svscale_f64_x (svptrue_b64 (), z1, z4), + z0 = svscale_x (svptrue_b64 (), z1, z4)) + +/* +** ptrue_scale_3_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f64_x_tied1, svfloat64_t, + z0 = svscale_n_f64_x (svptrue_b64 (), z0, 3), + z0 = svscale_x (svptrue_b64 (), z0, 3)) + +/* +** ptrue_scale_3_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_3_f64_x_untied, svfloat64_t, + z0 = svscale_n_f64_x (svptrue_b64 (), z1, 3), + z0 = svscale_x (svptrue_b64 (), z1, 3)) + +/* +** ptrue_scale_m3_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f64_x_tied1, svfloat64_t, + z0 = svscale_n_f64_x (svptrue_b64 (), z0, -3), + z0 = svscale_x (svptrue_b64 (), z0, -3)) + +/* +** ptrue_scale_m3_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_scale_m3_f64_x_untied, svfloat64_t, + z0 = svscale_n_f64_x (svptrue_b64 (), z1, -3), + z0 = svscale_x (svptrue_b64 (), z1, -3)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_b.c new file mode 100644 index 00000000000..a135e9c9912 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_b.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_b_tied1: +** sel p0\.b, p3, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (sel_b_tied1, + p0 = svsel_b (p3, p0, p1), + p0 = svsel (p3, p0, p1)) + +/* +** sel_b_tied2: +** sel p0\.b, p3, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (sel_b_tied2, + p0 = svsel_b (p3, p1, p0), + p0 = svsel (p3, p1, p0)) + +/* +** sel_b_untied: +** sel p0\.b, p3, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (sel_b_untied, + p0 = svsel_b (p3, p1, p2), + p0 = svsel (p3, p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f16.c new file mode 100644 index 00000000000..35750ea816c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_f16_tied1: +** sel z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sel_f16_tied1, svfloat16_t, + z0 = svsel_f16 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_f16_tied2: +** sel z0\.h, p0, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sel_f16_tied2, svfloat16_t, + z0 = svsel_f16 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_f16_untied: +** sel z0\.h, p0, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sel_f16_untied, svfloat16_t, + z0 = svsel_f16 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f32.c new file mode 100644 index 00000000000..639a84724c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_f32_tied1: +** sel z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sel_f32_tied1, svfloat32_t, + z0 = svsel_f32 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_f32_tied2: +** sel z0\.s, p0, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sel_f32_tied2, svfloat32_t, + z0 = svsel_f32 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_f32_untied: +** sel z0\.s, p0, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sel_f32_untied, svfloat32_t, + z0 = svsel_f32 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f64.c new file mode 100644 index 00000000000..048d6e52a52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_f64_tied1: +** sel z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sel_f64_tied1, svfloat64_t, + z0 = svsel_f64 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_f64_tied2: +** sel z0\.d, p0, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sel_f64_tied2, svfloat64_t, + z0 = svsel_f64 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_f64_untied: +** sel z0\.d, p0, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sel_f64_untied, svfloat64_t, + z0 = svsel_f64 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s16.c new file mode 100644 index 00000000000..e162da4990b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_s16_tied1: +** sel z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sel_s16_tied1, svint16_t, + z0 = svsel_s16 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_s16_tied2: +** sel z0\.h, p0, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sel_s16_tied2, svint16_t, + z0 = svsel_s16 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_s16_untied: +** sel z0\.h, p0, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sel_s16_untied, svint16_t, + z0 = svsel_s16 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s32.c new file mode 100644 index 00000000000..80839d8031d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_s32_tied1: +** sel z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sel_s32_tied1, svint32_t, + z0 = svsel_s32 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_s32_tied2: +** sel z0\.s, p0, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sel_s32_tied2, svint32_t, + z0 = svsel_s32 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_s32_untied: +** sel z0\.s, p0, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sel_s32_untied, svint32_t, + z0 = svsel_s32 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s64.c new file mode 100644 index 00000000000..85a77eafb6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_s64_tied1: +** sel z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sel_s64_tied1, svint64_t, + z0 = svsel_s64 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_s64_tied2: +** sel z0\.d, p0, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sel_s64_tied2, svint64_t, + z0 = svsel_s64 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_s64_untied: +** sel z0\.d, p0, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sel_s64_untied, svint64_t, + z0 = svsel_s64 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s8.c new file mode 100644 index 00000000000..28c43f627c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_s8_tied1: +** sel z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sel_s8_tied1, svint8_t, + z0 = svsel_s8 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_s8_tied2: +** sel z0\.b, p0, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (sel_s8_tied2, svint8_t, + z0 = svsel_s8 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_s8_untied: +** sel z0\.b, p0, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sel_s8_untied, svint8_t, + z0 = svsel_s8 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u16.c new file mode 100644 index 00000000000..b85ede80301 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_u16_tied1: +** sel z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sel_u16_tied1, svuint16_t, + z0 = svsel_u16 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_u16_tied2: +** sel z0\.h, p0, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sel_u16_tied2, svuint16_t, + z0 = svsel_u16 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_u16_untied: +** sel z0\.h, p0, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sel_u16_untied, svuint16_t, + z0 = svsel_u16 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u32.c new file mode 100644 index 00000000000..636cf8790a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_u32_tied1: +** sel z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sel_u32_tied1, svuint32_t, + z0 = svsel_u32 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_u32_tied2: +** sel z0\.s, p0, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sel_u32_tied2, svuint32_t, + z0 = svsel_u32 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_u32_untied: +** sel z0\.s, p0, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sel_u32_untied, svuint32_t, + z0 = svsel_u32 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u64.c new file mode 100644 index 00000000000..6325ca56feb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_u64_tied1: +** sel z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sel_u64_tied1, svuint64_t, + z0 = svsel_u64 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_u64_tied2: +** sel z0\.d, p0, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sel_u64_tied2, svuint64_t, + z0 = svsel_u64 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_u64_untied: +** sel z0\.d, p0, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sel_u64_untied, svuint64_t, + z0 = svsel_u64 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u8.c new file mode 100644 index 00000000000..5af53dccde5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sel_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sel_u8_tied1: +** sel z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sel_u8_tied1, svuint8_t, + z0 = svsel_u8 (p0, z0, z1), + z0 = svsel (p0, z0, z1)) + +/* +** sel_u8_tied2: +** sel z0\.b, p0, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (sel_u8_tied2, svuint8_t, + z0 = svsel_u8 (p0, z1, z0), + z0 = svsel (p0, z1, z0)) + +/* +** sel_u8_untied: +** sel z0\.b, p0, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sel_u8_untied, svuint8_t, + z0 = svsel_u8 (p0, z1, z2), + z0 = svsel (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f16.c new file mode 100644 index 00000000000..85960069814 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_f16_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_f16_z24_0, svfloat16x2_t, svfloat16_t, + z24 = svset2_f16 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_f16_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_f16_z24_1, svfloat16x2_t, svfloat16_t, + z24 = svset2_f16 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_f16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_f16_z4_0, svfloat16x2_t, svfloat16_t, + z4 = svset2_f16 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_f16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_f16_z4_1, svfloat16x2_t, svfloat16_t, + z4 = svset2_f16 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f32.c new file mode 100644 index 00000000000..a95ff2fc587 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_f32_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_f32_z24_0, svfloat32x2_t, svfloat32_t, + z24 = svset2_f32 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_f32_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_f32_z24_1, svfloat32x2_t, svfloat32_t, + z24 = svset2_f32 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_f32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_f32_z4_0, svfloat32x2_t, svfloat32_t, + z4 = svset2_f32 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_f32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_f32_z4_1, svfloat32x2_t, svfloat32_t, + z4 = svset2_f32 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f64.c new file mode 100644 index 00000000000..77837b7d8da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_f64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_f64_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_f64_z24_0, svfloat64x2_t, svfloat64_t, + z24 = svset2_f64 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_f64_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_f64_z24_1, svfloat64x2_t, svfloat64_t, + z24 = svset2_f64 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_f64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_f64_z4_0, svfloat64x2_t, svfloat64_t, + z4 = svset2_f64 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_f64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_f64_z4_1, svfloat64x2_t, svfloat64_t, + z4 = svset2_f64 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s16.c new file mode 100644 index 00000000000..aa2e70fd1a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_s16_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_s16_z24_0, svint16x2_t, svint16_t, + z24 = svset2_s16 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_s16_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_s16_z24_1, svint16x2_t, svint16_t, + z24 = svset2_s16 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_s16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_s16_z4_0, svint16x2_t, svint16_t, + z4 = svset2_s16 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_s16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_s16_z4_1, svint16x2_t, svint16_t, + z4 = svset2_s16 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s32.c new file mode 100644 index 00000000000..3a7c289aa5b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_s32_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_s32_z24_0, svint32x2_t, svint32_t, + z24 = svset2_s32 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_s32_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_s32_z24_1, svint32x2_t, svint32_t, + z24 = svset2_s32 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_s32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_s32_z4_0, svint32x2_t, svint32_t, + z4 = svset2_s32 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_s32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_s32_z4_1, svint32x2_t, svint32_t, + z4 = svset2_s32 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s64.c new file mode 100644 index 00000000000..ca6df54d970 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_s64_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_s64_z24_0, svint64x2_t, svint64_t, + z24 = svset2_s64 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_s64_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_s64_z24_1, svint64x2_t, svint64_t, + z24 = svset2_s64 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_s64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_s64_z4_0, svint64x2_t, svint64_t, + z4 = svset2_s64 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_s64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_s64_z4_1, svint64x2_t, svint64_t, + z4 = svset2_s64 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s8.c new file mode 100644 index 00000000000..e143128a42c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_s8.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_s8_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_s8_z24_0, svint8x2_t, svint8_t, + z24 = svset2_s8 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_s8_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_s8_z24_1, svint8x2_t, svint8_t, + z24 = svset2_s8 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_s8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_s8_z4_0, svint8x2_t, svint8_t, + z4 = svset2_s8 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_s8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_s8_z4_1, svint8x2_t, svint8_t, + z4 = svset2_s8 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u16.c new file mode 100644 index 00000000000..53da08398ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u16.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_u16_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_u16_z24_0, svuint16x2_t, svuint16_t, + z24 = svset2_u16 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_u16_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_u16_z24_1, svuint16x2_t, svuint16_t, + z24 = svset2_u16 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_u16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_u16_z4_0, svuint16x2_t, svuint16_t, + z4 = svset2_u16 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_u16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_u16_z4_1, svuint16x2_t, svuint16_t, + z4 = svset2_u16 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u32.c new file mode 100644 index 00000000000..5266a62d84b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u32.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_u32_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_u32_z24_0, svuint32x2_t, svuint32_t, + z24 = svset2_u32 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_u32_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_u32_z24_1, svuint32x2_t, svuint32_t, + z24 = svset2_u32 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_u32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_u32_z4_0, svuint32x2_t, svuint32_t, + z4 = svset2_u32 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_u32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_u32_z4_1, svuint32x2_t, svuint32_t, + z4 = svset2_u32 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u64.c new file mode 100644 index 00000000000..f7d2a180771 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u64.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_u64_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_u64_z24_0, svuint64x2_t, svuint64_t, + z24 = svset2_u64 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_u64_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_u64_z24_1, svuint64x2_t, svuint64_t, + z24 = svset2_u64 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_u64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_u64_z4_0, svuint64x2_t, svuint64_t, + z4 = svset2_u64 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_u64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_u64_z4_1, svuint64x2_t, svuint64_t, + z4 = svset2_u64 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u8.c new file mode 100644 index 00000000000..9494a0e5443 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set2_u8.c @@ -0,0 +1,41 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set2_u8_z24_0: +** mov z25\.d, z5\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set2_u8_z24_0, svuint8x2_t, svuint8_t, + z24 = svset2_u8 (z4, 0, z0), + z24 = svset2 (z4, 0, z0)) + +/* +** set2_u8_z24_1: +** mov z24\.d, z4\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set2_u8_z24_1, svuint8x2_t, svuint8_t, + z24 = svset2_u8 (z4, 1, z0), + z24 = svset2 (z4, 1, z0)) + +/* +** set2_u8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set2_u8_z4_0, svuint8x2_t, svuint8_t, + z4 = svset2_u8 (z4, 0, z0), + z4 = svset2 (z4, 0, z0)) + +/* +** set2_u8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set2_u8_z4_1, svuint8x2_t, svuint8_t, + z4 = svset2_u8 (z4, 1, z0), + z4 = svset2 (z4, 1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f16.c new file mode 100644 index 00000000000..b6bb3a2bff5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f16.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_f16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z24_0, svfloat16x3_t, svfloat16_t, + z24 = svset3_f16 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_f16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z24_1, svfloat16x3_t, svfloat16_t, + z24 = svset3_f16 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_f16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z24_2, svfloat16x3_t, svfloat16_t, + z24 = svset3_f16 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_f16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z4_0, svfloat16x3_t, svfloat16_t, + z4 = svset3_f16 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_f16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z4_1, svfloat16x3_t, svfloat16_t, + z4 = svset3_f16 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_f16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_f16_z4_2, svfloat16x3_t, svfloat16_t, + z4 = svset3_f16 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f32.c new file mode 100644 index 00000000000..659bc713f7d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f32.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_f32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z24_0, svfloat32x3_t, svfloat32_t, + z24 = svset3_f32 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_f32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z24_1, svfloat32x3_t, svfloat32_t, + z24 = svset3_f32 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_f32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z24_2, svfloat32x3_t, svfloat32_t, + z24 = svset3_f32 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_f32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z4_0, svfloat32x3_t, svfloat32_t, + z4 = svset3_f32 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_f32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z4_1, svfloat32x3_t, svfloat32_t, + z4 = svset3_f32 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_f32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_f32_z4_2, svfloat32x3_t, svfloat32_t, + z4 = svset3_f32 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f64.c new file mode 100644 index 00000000000..2cf3b601545 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_f64.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_f64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z24_0, svfloat64x3_t, svfloat64_t, + z24 = svset3_f64 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_f64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z24_1, svfloat64x3_t, svfloat64_t, + z24 = svset3_f64 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_f64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z24_2, svfloat64x3_t, svfloat64_t, + z24 = svset3_f64 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_f64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z4_0, svfloat64x3_t, svfloat64_t, + z4 = svset3_f64 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_f64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z4_1, svfloat64x3_t, svfloat64_t, + z4 = svset3_f64 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_f64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_f64_z4_2, svfloat64x3_t, svfloat64_t, + z4 = svset3_f64 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s16.c new file mode 100644 index 00000000000..907ae9894cd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s16.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_s16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z24_0, svint16x3_t, svint16_t, + z24 = svset3_s16 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_s16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z24_1, svint16x3_t, svint16_t, + z24 = svset3_s16 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_s16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z24_2, svint16x3_t, svint16_t, + z24 = svset3_s16 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_s16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z4_0, svint16x3_t, svint16_t, + z4 = svset3_s16 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_s16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z4_1, svint16x3_t, svint16_t, + z4 = svset3_s16 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_s16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_s16_z4_2, svint16x3_t, svint16_t, + z4 = svset3_s16 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s32.c new file mode 100644 index 00000000000..0baa33c3a12 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s32.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_s32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z24_0, svint32x3_t, svint32_t, + z24 = svset3_s32 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_s32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z24_1, svint32x3_t, svint32_t, + z24 = svset3_s32 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_s32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z24_2, svint32x3_t, svint32_t, + z24 = svset3_s32 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_s32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z4_0, svint32x3_t, svint32_t, + z4 = svset3_s32 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_s32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z4_1, svint32x3_t, svint32_t, + z4 = svset3_s32 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_s32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_s32_z4_2, svint32x3_t, svint32_t, + z4 = svset3_s32 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s64.c new file mode 100644 index 00000000000..d1d142c71f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s64.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_s64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z24_0, svint64x3_t, svint64_t, + z24 = svset3_s64 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_s64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z24_1, svint64x3_t, svint64_t, + z24 = svset3_s64 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_s64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z24_2, svint64x3_t, svint64_t, + z24 = svset3_s64 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_s64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z4_0, svint64x3_t, svint64_t, + z4 = svset3_s64 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_s64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z4_1, svint64x3_t, svint64_t, + z4 = svset3_s64 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_s64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_s64_z4_2, svint64x3_t, svint64_t, + z4 = svset3_s64 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s8.c new file mode 100644 index 00000000000..8badf4b1d67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_s8.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_s8_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z24_0, svint8x3_t, svint8_t, + z24 = svset3_s8 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_s8_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z24_1, svint8x3_t, svint8_t, + z24 = svset3_s8 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_s8_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z24_2, svint8x3_t, svint8_t, + z24 = svset3_s8 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_s8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z4_0, svint8x3_t, svint8_t, + z4 = svset3_s8 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_s8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z4_1, svint8x3_t, svint8_t, + z4 = svset3_s8 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_s8_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_s8_z4_2, svint8x3_t, svint8_t, + z4 = svset3_s8 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u16.c new file mode 100644 index 00000000000..df7ce88d8be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u16.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_u16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z24_0, svuint16x3_t, svuint16_t, + z24 = svset3_u16 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_u16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z24_1, svuint16x3_t, svuint16_t, + z24 = svset3_u16 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_u16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z24_2, svuint16x3_t, svuint16_t, + z24 = svset3_u16 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_u16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z4_0, svuint16x3_t, svuint16_t, + z4 = svset3_u16 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_u16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z4_1, svuint16x3_t, svuint16_t, + z4 = svset3_u16 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_u16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_u16_z4_2, svuint16x3_t, svuint16_t, + z4 = svset3_u16 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u32.c new file mode 100644 index 00000000000..703a68f5cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u32.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_u32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z24_0, svuint32x3_t, svuint32_t, + z24 = svset3_u32 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_u32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z24_1, svuint32x3_t, svuint32_t, + z24 = svset3_u32 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_u32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z24_2, svuint32x3_t, svuint32_t, + z24 = svset3_u32 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_u32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z4_0, svuint32x3_t, svuint32_t, + z4 = svset3_u32 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_u32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z4_1, svuint32x3_t, svuint32_t, + z4 = svset3_u32 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_u32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_u32_z4_2, svuint32x3_t, svuint32_t, + z4 = svset3_u32 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u64.c new file mode 100644 index 00000000000..bff5b3539cd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u64.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_u64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z24_0, svuint64x3_t, svuint64_t, + z24 = svset3_u64 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_u64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z24_1, svuint64x3_t, svuint64_t, + z24 = svset3_u64 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_u64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z24_2, svuint64x3_t, svuint64_t, + z24 = svset3_u64 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_u64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z4_0, svuint64x3_t, svuint64_t, + z4 = svset3_u64 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_u64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z4_1, svuint64x3_t, svuint64_t, + z4 = svset3_u64 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_u64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_u64_z4_2, svuint64x3_t, svuint64_t, + z4 = svset3_u64 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u8.c new file mode 100644 index 00000000000..9f40001c4a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set3_u8.c @@ -0,0 +1,63 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set3_u8_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z24_0, svuint8x3_t, svuint8_t, + z24 = svset3_u8 (z4, 0, z0), + z24 = svset3 (z4, 0, z0)) + +/* +** set3_u8_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z24_1, svuint8x3_t, svuint8_t, + z24 = svset3_u8 (z4, 1, z0), + z24 = svset3 (z4, 1, z0)) + +/* +** set3_u8_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z24_2, svuint8x3_t, svuint8_t, + z24 = svset3_u8 (z4, 2, z0), + z24 = svset3 (z4, 2, z0)) + +/* +** set3_u8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z4_0, svuint8x3_t, svuint8_t, + z4 = svset3_u8 (z4, 0, z0), + z4 = svset3 (z4, 0, z0)) + +/* +** set3_u8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z4_1, svuint8x3_t, svuint8_t, + z4 = svset3_u8 (z4, 1, z0), + z4 = svset3 (z4, 1, z0)) + +/* +** set3_u8_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set3_u8_z4_2, svuint8x3_t, svuint8_t, + z4 = svset3_u8 (z4, 2, z0), + z4 = svset3 (z4, 2, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f16.c new file mode 100644 index 00000000000..a28ff9ca619 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f16.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_f16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z24_0, svfloat16x4_t, svfloat16_t, + z24 = svset4_f16 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_f16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z24_1, svfloat16x4_t, svfloat16_t, + z24 = svset4_f16 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_f16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z24_2, svfloat16x4_t, svfloat16_t, + z24 = svset4_f16 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_f16_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z24_3, svfloat16x4_t, svfloat16_t, + z24 = svset4_f16 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_f16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z4_0, svfloat16x4_t, svfloat16_t, + z4 = svset4_f16 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_f16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z4_1, svfloat16x4_t, svfloat16_t, + z4 = svset4_f16 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_f16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z4_2, svfloat16x4_t, svfloat16_t, + z4 = svset4_f16 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_f16_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_f16_z4_3, svfloat16x4_t, svfloat16_t, + z4 = svset4_f16 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f32.c new file mode 100644 index 00000000000..e6e3f5ebd4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f32.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_f32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z24_0, svfloat32x4_t, svfloat32_t, + z24 = svset4_f32 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_f32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z24_1, svfloat32x4_t, svfloat32_t, + z24 = svset4_f32 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_f32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z24_2, svfloat32x4_t, svfloat32_t, + z24 = svset4_f32 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_f32_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z24_3, svfloat32x4_t, svfloat32_t, + z24 = svset4_f32 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_f32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z4_0, svfloat32x4_t, svfloat32_t, + z4 = svset4_f32 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_f32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z4_1, svfloat32x4_t, svfloat32_t, + z4 = svset4_f32 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_f32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z4_2, svfloat32x4_t, svfloat32_t, + z4 = svset4_f32 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_f32_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_f32_z4_3, svfloat32x4_t, svfloat32_t, + z4 = svset4_f32 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f64.c new file mode 100644 index 00000000000..3ceaa459aa0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_f64.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_f64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z24_0, svfloat64x4_t, svfloat64_t, + z24 = svset4_f64 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_f64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z24_1, svfloat64x4_t, svfloat64_t, + z24 = svset4_f64 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_f64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z24_2, svfloat64x4_t, svfloat64_t, + z24 = svset4_f64 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_f64_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z24_3, svfloat64x4_t, svfloat64_t, + z24 = svset4_f64 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_f64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z4_0, svfloat64x4_t, svfloat64_t, + z4 = svset4_f64 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_f64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z4_1, svfloat64x4_t, svfloat64_t, + z4 = svset4_f64 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_f64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z4_2, svfloat64x4_t, svfloat64_t, + z4 = svset4_f64 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_f64_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_f64_z4_3, svfloat64x4_t, svfloat64_t, + z4 = svset4_f64 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s16.c new file mode 100644 index 00000000000..3cef6ebe8e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s16.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_s16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z24_0, svint16x4_t, svint16_t, + z24 = svset4_s16 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_s16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z24_1, svint16x4_t, svint16_t, + z24 = svset4_s16 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_s16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z24_2, svint16x4_t, svint16_t, + z24 = svset4_s16 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_s16_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z24_3, svint16x4_t, svint16_t, + z24 = svset4_s16 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_s16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z4_0, svint16x4_t, svint16_t, + z4 = svset4_s16 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_s16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z4_1, svint16x4_t, svint16_t, + z4 = svset4_s16 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_s16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z4_2, svint16x4_t, svint16_t, + z4 = svset4_s16 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_s16_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_s16_z4_3, svint16x4_t, svint16_t, + z4 = svset4_s16 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s32.c new file mode 100644 index 00000000000..49f646e8d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s32.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_s32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z24_0, svint32x4_t, svint32_t, + z24 = svset4_s32 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_s32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z24_1, svint32x4_t, svint32_t, + z24 = svset4_s32 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_s32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z24_2, svint32x4_t, svint32_t, + z24 = svset4_s32 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_s32_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z24_3, svint32x4_t, svint32_t, + z24 = svset4_s32 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_s32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z4_0, svint32x4_t, svint32_t, + z4 = svset4_s32 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_s32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z4_1, svint32x4_t, svint32_t, + z4 = svset4_s32 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_s32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z4_2, svint32x4_t, svint32_t, + z4 = svset4_s32 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_s32_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_s32_z4_3, svint32x4_t, svint32_t, + z4 = svset4_s32 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s64.c new file mode 100644 index 00000000000..7544e25a2ea --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s64.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_s64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z24_0, svint64x4_t, svint64_t, + z24 = svset4_s64 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_s64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z24_1, svint64x4_t, svint64_t, + z24 = svset4_s64 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_s64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z24_2, svint64x4_t, svint64_t, + z24 = svset4_s64 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_s64_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z24_3, svint64x4_t, svint64_t, + z24 = svset4_s64 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_s64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z4_0, svint64x4_t, svint64_t, + z4 = svset4_s64 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_s64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z4_1, svint64x4_t, svint64_t, + z4 = svset4_s64 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_s64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z4_2, svint64x4_t, svint64_t, + z4 = svset4_s64 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_s64_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_s64_z4_3, svint64x4_t, svint64_t, + z4 = svset4_s64 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s8.c new file mode 100644 index 00000000000..2ec9ff0598b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_s8.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_s8_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z24_0, svint8x4_t, svint8_t, + z24 = svset4_s8 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_s8_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z24_1, svint8x4_t, svint8_t, + z24 = svset4_s8 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_s8_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z24_2, svint8x4_t, svint8_t, + z24 = svset4_s8 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_s8_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z24_3, svint8x4_t, svint8_t, + z24 = svset4_s8 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_s8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z4_0, svint8x4_t, svint8_t, + z4 = svset4_s8 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_s8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z4_1, svint8x4_t, svint8_t, + z4 = svset4_s8 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_s8_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z4_2, svint8x4_t, svint8_t, + z4 = svset4_s8 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_s8_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_s8_z4_3, svint8x4_t, svint8_t, + z4 = svset4_s8 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u16.c new file mode 100644 index 00000000000..c9499b04487 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u16.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_u16_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z24_0, svuint16x4_t, svuint16_t, + z24 = svset4_u16 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_u16_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z24_1, svuint16x4_t, svuint16_t, + z24 = svset4_u16 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_u16_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z24_2, svuint16x4_t, svuint16_t, + z24 = svset4_u16 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_u16_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z24_3, svuint16x4_t, svuint16_t, + z24 = svset4_u16 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_u16_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z4_0, svuint16x4_t, svuint16_t, + z4 = svset4_u16 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_u16_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z4_1, svuint16x4_t, svuint16_t, + z4 = svset4_u16 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_u16_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z4_2, svuint16x4_t, svuint16_t, + z4 = svset4_u16 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_u16_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_u16_z4_3, svuint16x4_t, svuint16_t, + z4 = svset4_u16 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u32.c new file mode 100644 index 00000000000..00b3dc5131a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u32.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_u32_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z24_0, svuint32x4_t, svuint32_t, + z24 = svset4_u32 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_u32_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z24_1, svuint32x4_t, svuint32_t, + z24 = svset4_u32 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_u32_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z24_2, svuint32x4_t, svuint32_t, + z24 = svset4_u32 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_u32_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z24_3, svuint32x4_t, svuint32_t, + z24 = svset4_u32 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_u32_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z4_0, svuint32x4_t, svuint32_t, + z4 = svset4_u32 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_u32_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z4_1, svuint32x4_t, svuint32_t, + z4 = svset4_u32 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_u32_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z4_2, svuint32x4_t, svuint32_t, + z4 = svset4_u32 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_u32_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_u32_z4_3, svuint32x4_t, svuint32_t, + z4 = svset4_u32 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u64.c new file mode 100644 index 00000000000..d2f048b8207 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u64.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_u64_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z24_0, svuint64x4_t, svuint64_t, + z24 = svset4_u64 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_u64_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z24_1, svuint64x4_t, svuint64_t, + z24 = svset4_u64 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_u64_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z24_2, svuint64x4_t, svuint64_t, + z24 = svset4_u64 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_u64_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z24_3, svuint64x4_t, svuint64_t, + z24 = svset4_u64 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_u64_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z4_0, svuint64x4_t, svuint64_t, + z4 = svset4_u64 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_u64_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z4_1, svuint64x4_t, svuint64_t, + z4 = svset4_u64 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_u64_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z4_2, svuint64x4_t, svuint64_t, + z4 = svset4_u64 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_u64_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_u64_z4_3, svuint64x4_t, svuint64_t, + z4 = svset4_u64 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u8.c new file mode 100644 index 00000000000..b4f27c6f1b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/set4_u8.c @@ -0,0 +1,87 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** set4_u8_z24_0: +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z24\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z24_0, svuint8x4_t, svuint8_t, + z24 = svset4_u8 (z4, 0, z0), + z24 = svset4 (z4, 0, z0)) + +/* +** set4_u8_z24_1: +** mov z24\.d, z4\.d +** mov z26\.d, z6\.d +** mov z27\.d, z7\.d +** mov z25\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z24_1, svuint8x4_t, svuint8_t, + z24 = svset4_u8 (z4, 1, z0), + z24 = svset4 (z4, 1, z0)) + +/* +** set4_u8_z24_2: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z27\.d, z7\.d +** mov z26\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z24_2, svuint8x4_t, svuint8_t, + z24 = svset4_u8 (z4, 2, z0), + z24 = svset4 (z4, 2, z0)) + +/* +** set4_u8_z24_3: +** mov z24\.d, z4\.d +** mov z25\.d, z5\.d +** mov z26\.d, z6\.d +** mov z27\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z24_3, svuint8x4_t, svuint8_t, + z24 = svset4_u8 (z4, 3, z0), + z24 = svset4 (z4, 3, z0)) + +/* +** set4_u8_z4_0: +** mov z4\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z4_0, svuint8x4_t, svuint8_t, + z4 = svset4_u8 (z4, 0, z0), + z4 = svset4 (z4, 0, z0)) + +/* +** set4_u8_z4_1: +** mov z5\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z4_1, svuint8x4_t, svuint8_t, + z4 = svset4_u8 (z4, 1, z0), + z4 = svset4 (z4, 1, z0)) + +/* +** set4_u8_z4_2: +** mov z6\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z4_2, svuint8x4_t, svuint8_t, + z4 = svset4_u8 (z4, 2, z0), + z4 = svset4 (z4, 2, z0)) + +/* +** set4_u8_z4_3: +** mov z7\.d, z0\.d +** ret +*/ +TEST_SET (set4_u8_z4_3, svuint8x4_t, svuint8_t, + z4 = svset4_u8 (z4, 3, z0), + z4 = svset4 (z4, 3, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f16.c new file mode 100644 index 00000000000..b796eaf3d54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f16.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_f16_tied1: +** splice z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_f16_tied1, svfloat16_t, + z0 = svsplice_f16 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_f16_tied2, svfloat16_t, + z0 = svsplice_f16 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_f16_untied: +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (splice_f16_untied, svfloat16_t, + z0 = svsplice_f16 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f32.c new file mode 100644 index 00000000000..1fc552bc31a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f32.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_f32_tied1: +** splice z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_f32_tied1, svfloat32_t, + z0 = svsplice_f32 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_f32_tied2, svfloat32_t, + z0 = svsplice_f32 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_f32_untied: +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (splice_f32_untied, svfloat32_t, + z0 = svsplice_f32 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f64.c new file mode 100644 index 00000000000..26b523520f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_f64.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_f64_tied1: +** splice z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (splice_f64_tied1, svfloat64_t, + z0 = svsplice_f64 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (splice_f64_tied2, svfloat64_t, + z0 = svsplice_f64 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_f64_untied: +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (splice_f64_untied, svfloat64_t, + z0 = svsplice_f64 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s16.c new file mode 100644 index 00000000000..8796c6ecd5d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s16.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_s16_tied1: +** splice z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_s16_tied1, svint16_t, + z0 = svsplice_s16 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_s16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_s16_tied2, svint16_t, + z0 = svsplice_s16 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_s16_untied: +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (splice_s16_untied, svint16_t, + z0 = svsplice_s16 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s32.c new file mode 100644 index 00000000000..5f2798e0612 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s32.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_s32_tied1: +** splice z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_s32_tied1, svint32_t, + z0 = svsplice_s32 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_s32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_s32_tied2, svint32_t, + z0 = svsplice_s32 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_s32_untied: +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (splice_s32_untied, svint32_t, + z0 = svsplice_s32 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s64.c new file mode 100644 index 00000000000..024bfa479df --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s64.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_s64_tied1: +** splice z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (splice_s64_tied1, svint64_t, + z0 = svsplice_s64 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_s64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (splice_s64_tied2, svint64_t, + z0 = svsplice_s64 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_s64_untied: +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (splice_s64_untied, svint64_t, + z0 = svsplice_s64 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s8.c new file mode 100644 index 00000000000..cd91ee2456e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_s8.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_s8_tied1: +** splice z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (splice_s8_tied1, svint8_t, + z0 = svsplice_s8 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_s8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (splice_s8_tied2, svint8_t, + z0 = svsplice_s8 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_s8_untied: +** movprfx z0, z1 +** splice z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (splice_s8_untied, svint8_t, + z0 = svsplice_s8 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u16.c new file mode 100644 index 00000000000..821ebaee689 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u16.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_u16_tied1: +** splice z0\.h, p0, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_u16_tied1, svuint16_t, + z0 = svsplice_u16 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_u16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (splice_u16_tied2, svuint16_t, + z0 = svsplice_u16 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_u16_untied: +** movprfx z0, z1 +** splice z0\.h, p0, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (splice_u16_untied, svuint16_t, + z0 = svsplice_u16 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u32.c new file mode 100644 index 00000000000..200364f20f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u32.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_u32_tied1: +** splice z0\.s, p0, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_u32_tied1, svuint32_t, + z0 = svsplice_u32 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_u32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (splice_u32_tied2, svuint32_t, + z0 = svsplice_u32 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_u32_untied: +** movprfx z0, z1 +** splice z0\.s, p0, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (splice_u32_untied, svuint32_t, + z0 = svsplice_u32 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u64.c new file mode 100644 index 00000000000..352bcdeed29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u64.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_u64_tied1: +** splice z0\.d, p0, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (splice_u64_tied1, svuint64_t, + z0 = svsplice_u64 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_u64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (splice_u64_tied2, svuint64_t, + z0 = svsplice_u64 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_u64_untied: +** movprfx z0, z1 +** splice z0\.d, p0, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (splice_u64_untied, svuint64_t, + z0 = svsplice_u64 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u8.c new file mode 100644 index 00000000000..6c24fe64deb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/splice_u8.c @@ -0,0 +1,33 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** splice_u8_tied1: +** splice z0\.b, p0, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (splice_u8_tied1, svuint8_t, + z0 = svsplice_u8 (p0, z0, z1), + z0 = svsplice (p0, z0, z1)) + +/* +** splice_u8_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** splice z0\.b, p0, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (splice_u8_tied2, svuint8_t, + z0 = svsplice_u8 (p0, z1, z0), + z0 = svsplice (p0, z1, z0)) + +/* +** splice_u8_untied: +** movprfx z0, z1 +** splice z0\.b, p0, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (splice_u8_untied, svuint8_t, + z0 = svsplice_u8 (p0, z1, z2), + z0 = svsplice (p0, z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c new file mode 100644 index 00000000000..6dc5940fb9b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sqrt_f16_m_tied12: +** fsqrt z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_m_tied12, svfloat16_t, + z0 = svsqrt_f16_m (z0, p0, z0), + z0 = svsqrt_m (z0, p0, z0)) + +/* +** sqrt_f16_m_tied1: +** fsqrt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_m_tied1, svfloat16_t, + z0 = svsqrt_f16_m (z0, p0, z1), + z0 = svsqrt_m (z0, p0, z1)) + +/* +** sqrt_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsqrt z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_m_tied2, svfloat16_t, + z0 = svsqrt_f16_m (z1, p0, z0), + z0 = svsqrt_m (z1, p0, z0)) + +/* +** sqrt_f16_m_untied: +** movprfx z0, z2 +** fsqrt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_m_untied, svfloat16_t, + z0 = svsqrt_f16_m (z2, p0, z1), + z0 = svsqrt_m (z2, p0, z1)) + +/* +** sqrt_f16_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.h, p0/z, \1\.h +** fsqrt z0\.h, p0/m, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_z_tied1, svfloat16_t, + z0 = svsqrt_f16_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsqrt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_z_untied, svfloat16_t, + z0 = svsqrt_f16_z (p0, z1), + z0 = svsqrt_z (p0, z1)) + +/* +** sqrt_f16_x_tied1: +** fsqrt z0\.h, p0/m, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_x_tied1, svfloat16_t, + z0 = svsqrt_f16_x (p0, z0), + z0 = svsqrt_x (p0, z0)) + +/* +** sqrt_f16_x_untied: +** fsqrt z0\.h, p0/m, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sqrt_f16_x_untied, svfloat16_t, + z0 = svsqrt_f16_x (p0, z1), + z0 = svsqrt_x (p0, z1)) + +/* +** ptrue_sqrt_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f16_x_tied1, svfloat16_t, + z0 = svsqrt_f16_x (svptrue_b16 (), z0), + z0 = svsqrt_x (svptrue_b16 (), z0)) + +/* +** ptrue_sqrt_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f16_x_untied, svfloat16_t, + z0 = svsqrt_f16_x (svptrue_b16 (), z1), + z0 = svsqrt_x (svptrue_b16 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c new file mode 100644 index 00000000000..71d1f8f74e4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sqrt_f32_m_tied12: +** fsqrt z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_m_tied12, svfloat32_t, + z0 = svsqrt_f32_m (z0, p0, z0), + z0 = svsqrt_m (z0, p0, z0)) + +/* +** sqrt_f32_m_tied1: +** fsqrt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_m_tied1, svfloat32_t, + z0 = svsqrt_f32_m (z0, p0, z1), + z0 = svsqrt_m (z0, p0, z1)) + +/* +** sqrt_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsqrt z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_m_tied2, svfloat32_t, + z0 = svsqrt_f32_m (z1, p0, z0), + z0 = svsqrt_m (z1, p0, z0)) + +/* +** sqrt_f32_m_untied: +** movprfx z0, z2 +** fsqrt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_m_untied, svfloat32_t, + z0 = svsqrt_f32_m (z2, p0, z1), + z0 = svsqrt_m (z2, p0, z1)) + +/* +** sqrt_f32_z_tied1: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0\.s, p0/z, \1\.s +** fsqrt z0\.s, p0/m, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_z_tied1, svfloat32_t, + z0 = svsqrt_f32_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsqrt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_z_untied, svfloat32_t, + z0 = svsqrt_f32_z (p0, z1), + z0 = svsqrt_z (p0, z1)) + +/* +** sqrt_f32_x_tied1: +** fsqrt z0\.s, p0/m, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_x_tied1, svfloat32_t, + z0 = svsqrt_f32_x (p0, z0), + z0 = svsqrt_x (p0, z0)) + +/* +** sqrt_f32_x_untied: +** fsqrt z0\.s, p0/m, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sqrt_f32_x_untied, svfloat32_t, + z0 = svsqrt_f32_x (p0, z1), + z0 = svsqrt_x (p0, z1)) + +/* +** ptrue_sqrt_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f32_x_tied1, svfloat32_t, + z0 = svsqrt_f32_x (svptrue_b32 (), z0), + z0 = svsqrt_x (svptrue_b32 (), z0)) + +/* +** ptrue_sqrt_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f32_x_untied, svfloat32_t, + z0 = svsqrt_f32_x (svptrue_b32 (), z1), + z0 = svsqrt_x (svptrue_b32 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c new file mode 100644 index 00000000000..7771df545db --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c @@ -0,0 +1,103 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sqrt_f64_m_tied12: +** fsqrt z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_m_tied12, svfloat64_t, + z0 = svsqrt_f64_m (z0, p0, z0), + z0 = svsqrt_m (z0, p0, z0)) + +/* +** sqrt_f64_m_tied1: +** fsqrt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_m_tied1, svfloat64_t, + z0 = svsqrt_f64_m (z0, p0, z1), + z0 = svsqrt_m (z0, p0, z1)) + +/* +** sqrt_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fsqrt z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_m_tied2, svfloat64_t, + z0 = svsqrt_f64_m (z1, p0, z0), + z0 = svsqrt_m (z1, p0, z0)) + +/* +** sqrt_f64_m_untied: +** movprfx z0, z2 +** fsqrt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_m_untied, svfloat64_t, + z0 = svsqrt_f64_m (z2, p0, z1), + z0 = svsqrt_m (z2, p0, z1)) + +/* +** sqrt_f64_z_tied1: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0\.d, p0/z, \1 +** fsqrt z0\.d, p0/m, \1 +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_z_tied1, svfloat64_t, + z0 = svsqrt_f64_z (p0, z0), + z0 = svsqrt_z (p0, z0)) + +/* +** sqrt_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsqrt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_z_untied, svfloat64_t, + z0 = svsqrt_f64_z (p0, z1), + z0 = svsqrt_z (p0, z1)) + +/* +** sqrt_f64_x_tied1: +** fsqrt z0\.d, p0/m, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_x_tied1, svfloat64_t, + z0 = svsqrt_f64_x (p0, z0), + z0 = svsqrt_x (p0, z0)) + +/* +** sqrt_f64_x_untied: +** fsqrt z0\.d, p0/m, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sqrt_f64_x_untied, svfloat64_t, + z0 = svsqrt_f64_x (p0, z1), + z0 = svsqrt_x (p0, z1)) + +/* +** ptrue_sqrt_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f64_x_tied1, svfloat64_t, + z0 = svsqrt_f64_x (svptrue_b64 (), z0), + z0 = svsqrt_x (svptrue_b64 (), z0)) + +/* +** ptrue_sqrt_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sqrt_f64_x_untied, svfloat64_t, + z0 = svsqrt_f64_x (svptrue_b64 (), z1), + z0 = svsqrt_x (svptrue_b64 (), z1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f16.c new file mode 100644 index 00000000000..728ed9d12fe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_f16_base: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f16_base, svfloat16_t, float16_t, + svst1_f16 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_f16_index: +** st1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1_f16_index, svfloat16_t, float16_t, + svst1_f16 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_f16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_f16_1, svfloat16_t, float16_t, + svst1_f16 (p0, x0 + svcnth (), z0), + svst1 (p0, x0 + svcnth (), z0)) + +/* +** st1_f16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_f16_7, svfloat16_t, float16_t, + svst1_f16 (p0, x0 + svcnth () * 7, z0), + svst1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f16_8, svfloat16_t, float16_t, + svst1_f16 (p0, x0 + svcnth () * 8, z0), + svst1 (p0, x0 + svcnth () * 8, z0)) + +/* +** st1_f16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_f16_m1, svfloat16_t, float16_t, + svst1_f16 (p0, x0 - svcnth (), z0), + svst1 (p0, x0 - svcnth (), z0)) + +/* +** st1_f16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_f16_m8, svfloat16_t, float16_t, + svst1_f16 (p0, x0 - svcnth () * 8, z0), + svst1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f16_m9, svfloat16_t, float16_t, + svst1_f16 (p0, x0 - svcnth () * 9, z0), + svst1 (p0, x0 - svcnth () * 9, z0)) + +/* +** st1_vnum_f16_0: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f16_0, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_f16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f16_1, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_f16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f16_7, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f16_8, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_f16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f16_m1, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_f16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f16_m8, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f16_m9, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_f16_x1, svfloat16_t, float16_t, + svst1_vnum_f16 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f32.c new file mode 100644 index 00000000000..d4cb8bf2b0d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_f32_base: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f32_base, svfloat32_t, float32_t, + svst1_f32 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_f32_index: +** st1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st1_f32_index, svfloat32_t, float32_t, + svst1_f32 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_f32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_f32_1, svfloat32_t, float32_t, + svst1_f32 (p0, x0 + svcntw (), z0), + svst1 (p0, x0 + svcntw (), z0)) + +/* +** st1_f32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_f32_7, svfloat32_t, float32_t, + svst1_f32 (p0, x0 + svcntw () * 7, z0), + svst1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f32_8, svfloat32_t, float32_t, + svst1_f32 (p0, x0 + svcntw () * 8, z0), + svst1 (p0, x0 + svcntw () * 8, z0)) + +/* +** st1_f32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_f32_m1, svfloat32_t, float32_t, + svst1_f32 (p0, x0 - svcntw (), z0), + svst1 (p0, x0 - svcntw (), z0)) + +/* +** st1_f32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_f32_m8, svfloat32_t, float32_t, + svst1_f32 (p0, x0 - svcntw () * 8, z0), + svst1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f32_m9, svfloat32_t, float32_t, + svst1_f32 (p0, x0 - svcntw () * 9, z0), + svst1 (p0, x0 - svcntw () * 9, z0)) + +/* +** st1_vnum_f32_0: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f32_0, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_f32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f32_1, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_f32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f32_7, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f32_8, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_f32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f32_m1, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_f32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f32_m8, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f32_m9, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_f32_x1, svfloat32_t, float32_t, + svst1_vnum_f32 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f64.c new file mode 100644 index 00000000000..15eca431cd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_f64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_f64_base: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f64_base, svfloat64_t, float64_t, + svst1_f64 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_f64_index: +** st1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st1_f64_index, svfloat64_t, float64_t, + svst1_f64 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_f64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_f64_1, svfloat64_t, float64_t, + svst1_f64 (p0, x0 + svcntd (), z0), + svst1 (p0, x0 + svcntd (), z0)) + +/* +** st1_f64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_f64_7, svfloat64_t, float64_t, + svst1_f64 (p0, x0 + svcntd () * 7, z0), + svst1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f64_8, svfloat64_t, float64_t, + svst1_f64 (p0, x0 + svcntd () * 8, z0), + svst1 (p0, x0 + svcntd () * 8, z0)) + +/* +** st1_f64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_f64_m1, svfloat64_t, float64_t, + svst1_f64 (p0, x0 - svcntd (), z0), + svst1 (p0, x0 - svcntd (), z0)) + +/* +** st1_f64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_f64_m8, svfloat64_t, float64_t, + svst1_f64 (p0, x0 - svcntd () * 8, z0), + svst1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_f64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_f64_m9, svfloat64_t, float64_t, + svst1_f64 (p0, x0 - svcntd () * 9, z0), + svst1 (p0, x0 - svcntd () * 9, z0)) + +/* +** st1_vnum_f64_0: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f64_0, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_f64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f64_1, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_f64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f64_7, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f64_8, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_f64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f64_m1, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_f64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_f64_m8, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_f64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_f64_m9, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_f64_x1, svfloat64_t, float64_t, + svst1_vnum_f64 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s16.c new file mode 100644 index 00000000000..fe20aab8d89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_s16_base: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s16_base, svint16_t, int16_t, + svst1_s16 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_s16_index: +** st1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1_s16_index, svint16_t, int16_t, + svst1_s16 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_s16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_s16_1, svint16_t, int16_t, + svst1_s16 (p0, x0 + svcnth (), z0), + svst1 (p0, x0 + svcnth (), z0)) + +/* +** st1_s16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_s16_7, svint16_t, int16_t, + svst1_s16 (p0, x0 + svcnth () * 7, z0), + svst1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s16_8, svint16_t, int16_t, + svst1_s16 (p0, x0 + svcnth () * 8, z0), + svst1 (p0, x0 + svcnth () * 8, z0)) + +/* +** st1_s16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_s16_m1, svint16_t, int16_t, + svst1_s16 (p0, x0 - svcnth (), z0), + svst1 (p0, x0 - svcnth (), z0)) + +/* +** st1_s16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_s16_m8, svint16_t, int16_t, + svst1_s16 (p0, x0 - svcnth () * 8, z0), + svst1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s16_m9, svint16_t, int16_t, + svst1_s16 (p0, x0 - svcnth () * 9, z0), + svst1 (p0, x0 - svcnth () * 9, z0)) + +/* +** st1_vnum_s16_0: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s16_0, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_s16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s16_1, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_s16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s16_7, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s16_8, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_s16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s16_m1, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_s16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s16_m8, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s16_m9, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_s16_x1, svint16_t, int16_t, + svst1_vnum_s16 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s32.c new file mode 100644 index 00000000000..7f182aed2e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_s32_base: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s32_base, svint32_t, int32_t, + svst1_s32 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_s32_index: +** st1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st1_s32_index, svint32_t, int32_t, + svst1_s32 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_s32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_s32_1, svint32_t, int32_t, + svst1_s32 (p0, x0 + svcntw (), z0), + svst1 (p0, x0 + svcntw (), z0)) + +/* +** st1_s32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_s32_7, svint32_t, int32_t, + svst1_s32 (p0, x0 + svcntw () * 7, z0), + svst1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s32_8, svint32_t, int32_t, + svst1_s32 (p0, x0 + svcntw () * 8, z0), + svst1 (p0, x0 + svcntw () * 8, z0)) + +/* +** st1_s32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_s32_m1, svint32_t, int32_t, + svst1_s32 (p0, x0 - svcntw (), z0), + svst1 (p0, x0 - svcntw (), z0)) + +/* +** st1_s32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_s32_m8, svint32_t, int32_t, + svst1_s32 (p0, x0 - svcntw () * 8, z0), + svst1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s32_m9, svint32_t, int32_t, + svst1_s32 (p0, x0 - svcntw () * 9, z0), + svst1 (p0, x0 - svcntw () * 9, z0)) + +/* +** st1_vnum_s32_0: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s32_0, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_s32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s32_1, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_s32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s32_7, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s32_8, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_s32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s32_m1, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_s32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s32_m8, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s32_m9, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_s32_x1, svint32_t, int32_t, + svst1_vnum_s32 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s64.c new file mode 100644 index 00000000000..cd8a8c042b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_s64_base: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s64_base, svint64_t, int64_t, + svst1_s64 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_s64_index: +** st1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st1_s64_index, svint64_t, int64_t, + svst1_s64 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_s64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_s64_1, svint64_t, int64_t, + svst1_s64 (p0, x0 + svcntd (), z0), + svst1 (p0, x0 + svcntd (), z0)) + +/* +** st1_s64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_s64_7, svint64_t, int64_t, + svst1_s64 (p0, x0 + svcntd () * 7, z0), + svst1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s64_8, svint64_t, int64_t, + svst1_s64 (p0, x0 + svcntd () * 8, z0), + svst1 (p0, x0 + svcntd () * 8, z0)) + +/* +** st1_s64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_s64_m1, svint64_t, int64_t, + svst1_s64 (p0, x0 - svcntd (), z0), + svst1 (p0, x0 - svcntd (), z0)) + +/* +** st1_s64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_s64_m8, svint64_t, int64_t, + svst1_s64 (p0, x0 - svcntd () * 8, z0), + svst1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s64_m9, svint64_t, int64_t, + svst1_s64 (p0, x0 - svcntd () * 9, z0), + svst1 (p0, x0 - svcntd () * 9, z0)) + +/* +** st1_vnum_s64_0: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s64_0, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_s64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s64_1, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_s64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s64_7, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s64_8, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_s64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s64_m1, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_s64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s64_m8, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s64_m9, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_s64_x1, svint64_t, int64_t, + svst1_vnum_s64 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s8.c new file mode 100644 index 00000000000..c8f6b97a29f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_s8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_s8_base: +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s8_base, svint8_t, int8_t, + svst1_s8 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_s8_index: +** st1b z0\.b, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1_s8_index, svint8_t, int8_t, + svst1_s8 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_s8_1: +** st1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_s8_1, svint8_t, int8_t, + svst1_s8 (p0, x0 + svcntb (), z0), + svst1 (p0, x0 + svcntb (), z0)) + +/* +** st1_s8_7: +** st1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_s8_7, svint8_t, int8_t, + svst1_s8 (p0, x0 + svcntb () * 7, z0), + svst1 (p0, x0 + svcntb () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s8_8: +** incb x0, all, mul #8 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s8_8, svint8_t, int8_t, + svst1_s8 (p0, x0 + svcntb () * 8, z0), + svst1 (p0, x0 + svcntb () * 8, z0)) + +/* +** st1_s8_m1: +** st1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_s8_m1, svint8_t, int8_t, + svst1_s8 (p0, x0 - svcntb (), z0), + svst1 (p0, x0 - svcntb (), z0)) + +/* +** st1_s8_m8: +** st1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_s8_m8, svint8_t, int8_t, + svst1_s8 (p0, x0 - svcntb () * 8, z0), + svst1 (p0, x0 - svcntb () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_s8_m9: +** decb x0, all, mul #9 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_s8_m9, svint8_t, int8_t, + svst1_s8 (p0, x0 - svcntb () * 9, z0), + svst1 (p0, x0 - svcntb () * 9, z0)) + +/* +** st1_vnum_s8_0: +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s8_0, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_s8_1: +** st1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s8_1, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_s8_7: +** st1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s8_7, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s8_8: +** incb x0, all, mul #8 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s8_8, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_s8_m1: +** st1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s8_m1, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_s8_m8: +** st1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_s8_m8, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_s8_m9: +** decb x0, all, mul #9 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_s8_m9, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* +** st1_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.b, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.b, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1_vnum_s8_x1, svint8_t, int8_t, + svst1_vnum_s8 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f32.c new file mode 100644 index 00000000000..09f0ad748da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f32.c @@ -0,0 +1,227 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_f32: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_f32, svfloat32_t, svuint32_t, + svst1_scatter_u32base_f32 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_f32_offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m4_f32_offset: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m4_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, -4, z0), + svst1_scatter_offset (p0, z1, -4, z0)) + +/* +** st1_scatter_0_f32_offset: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_5_f32_offset: +** mov (x[0-9]+), #?5 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 5, z0), + svst1_scatter_offset (p0, z1, 5, z0)) + +/* +** st1_scatter_6_f32_offset: +** mov (x[0-9]+), #?6 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_6_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 6, z0), + svst1_scatter_offset (p0, z1, 6, z0)) + +/* +** st1_scatter_7_f32_offset: +** mov (x[0-9]+), #?7 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_7_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 7, z0), + svst1_scatter_offset (p0, z1, 7, z0)) + +/* +** st1_scatter_8_f32_offset: +** st1w z0\.s, p0, \[z1\.s, #8\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_8_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 8, z0), + svst1_scatter_offset (p0, z1, 8, z0)) + +/* +** st1_scatter_124_f32_offset: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_124_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 124, z0), + svst1_scatter_offset (p0, z1, 124, z0)) + +/* +** st1_scatter_128_f32_offset: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_128_f32_offset, svfloat32_t, svuint32_t, + svst1_scatter_u32base_offset_f32 (p0, z1, 128, z0), + svst1_scatter_offset (p0, z1, 128, z0)) + +/* +** st1_scatter_x0_f32_index: +** lsl (x[0-9]+), x0, #?2 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_f32_index: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_f32_index: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_f32_index: +** st1w z0\.s, p0, \[z1\.s, #20\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_f32_index: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_f32_index: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_f32_index, svfloat32_t, svuint32_t, + svst1_scatter_u32base_index_f32 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_f32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f32_s32offset, svfloat32_t, float32_t, svint32_t, + svst1_scatter_s32offset_f32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_f32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f32_s32offset, svfloat32_t, float32_t, svint32_t, + svst1_scatter_s32offset_f32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_f32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + svst1_scatter_u32offset_f32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_f32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f32_u32offset, svfloat32_t, float32_t, svuint32_t, + svst1_scatter_u32offset_f32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_f32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f32_s32index, svfloat32_t, float32_t, svint32_t, + svst1_scatter_s32index_f32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_f32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f32_s32index, svfloat32_t, float32_t, svint32_t, + svst1_scatter_s32index_f32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_f32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f32_u32index, svfloat32_t, float32_t, svuint32_t, + svst1_scatter_u32index_f32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_f32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f32_u32index, svfloat32_t, float32_t, svuint32_t, + svst1_scatter_u32index_f32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f64.c new file mode 100644 index 00000000000..c8418b245a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_f64.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_f64: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_f64, svfloat64_t, svuint64_t, + svst1_scatter_u64base_f64 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_f64_offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m8_f64_offset: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m8_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, -8, z0), + svst1_scatter_offset (p0, z1, -8, z0)) + +/* +** st1_scatter_0_f64_offset: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_9_f64_offset: +** mov (x[0-9]+), #?9 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_9_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 9, z0), + svst1_scatter_offset (p0, z1, 9, z0)) + +/* +** st1_scatter_10_f64_offset: +** mov (x[0-9]+), #?10 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_10_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 10, z0), + svst1_scatter_offset (p0, z1, 10, z0)) + +/* +** st1_scatter_11_f64_offset: +** mov (x[0-9]+), #?11 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_11_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 11, z0), + svst1_scatter_offset (p0, z1, 11, z0)) + +/* +** st1_scatter_12_f64_offset: +** mov (x[0-9]+), #?12 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_12_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 12, z0), + svst1_scatter_offset (p0, z1, 12, z0)) + +/* +** st1_scatter_13_f64_offset: +** mov (x[0-9]+), #?13 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_13_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 13, z0), + svst1_scatter_offset (p0, z1, 13, z0)) + +/* +** st1_scatter_14_f64_offset: +** mov (x[0-9]+), #?14 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_14_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 14, z0), + svst1_scatter_offset (p0, z1, 14, z0)) + +/* +** st1_scatter_15_f64_offset: +** mov (x[0-9]+), #?15 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_15_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 15, z0), + svst1_scatter_offset (p0, z1, 15, z0)) + +/* +** st1_scatter_16_f64_offset: +** st1d z0\.d, p0, \[z1\.d, #16\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_16_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 16, z0), + svst1_scatter_offset (p0, z1, 16, z0)) + +/* +** st1_scatter_248_f64_offset: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_248_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 248, z0), + svst1_scatter_offset (p0, z1, 248, z0)) + +/* +** st1_scatter_256_f64_offset: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_256_f64_offset, svfloat64_t, svuint64_t, + svst1_scatter_u64base_offset_f64 (p0, z1, 256, z0), + svst1_scatter_offset (p0, z1, 256, z0)) + +/* +** st1_scatter_x0_f64_index: +** lsl (x[0-9]+), x0, #?3 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_f64_index: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_f64_index: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_f64_index: +** st1d z0\.d, p0, \[z1\.d, #40\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_f64_index: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_f64_index: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_f64_index, svfloat64_t, svuint64_t, + svst1_scatter_u64base_index_f64 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_f64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f64_s64offset, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64offset_f64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_f64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f64_s64offset, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64offset_f64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_f64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_f64_s64offset, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64offset_f64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_f64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64offset_f64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_f64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64offset_f64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_f64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_f64_u64offset, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64offset_f64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_f64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f64_s64index, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64index_f64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_f64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f64_s64index, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64index_f64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_f64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_f64_s64index, svfloat64_t, float64_t, svint64_t, + svst1_scatter_s64index_f64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_f64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_f64_u64index, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64index_f64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_f64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_f64_u64index, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64index_f64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_f64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_f64_u64index, svfloat64_t, float64_t, svuint64_t, + svst1_scatter_u64index_f64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s32.c new file mode 100644 index 00000000000..ca30b991041 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s32.c @@ -0,0 +1,227 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_s32: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_s32, svint32_t, svuint32_t, + svst1_scatter_u32base_s32 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_s32_offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m4_s32_offset: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m4_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, -4, z0), + svst1_scatter_offset (p0, z1, -4, z0)) + +/* +** st1_scatter_0_s32_offset: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_5_s32_offset: +** mov (x[0-9]+), #?5 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 5, z0), + svst1_scatter_offset (p0, z1, 5, z0)) + +/* +** st1_scatter_6_s32_offset: +** mov (x[0-9]+), #?6 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_6_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 6, z0), + svst1_scatter_offset (p0, z1, 6, z0)) + +/* +** st1_scatter_7_s32_offset: +** mov (x[0-9]+), #?7 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_7_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 7, z0), + svst1_scatter_offset (p0, z1, 7, z0)) + +/* +** st1_scatter_8_s32_offset: +** st1w z0\.s, p0, \[z1\.s, #8\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_8_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 8, z0), + svst1_scatter_offset (p0, z1, 8, z0)) + +/* +** st1_scatter_124_s32_offset: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_124_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 124, z0), + svst1_scatter_offset (p0, z1, 124, z0)) + +/* +** st1_scatter_128_s32_offset: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_128_s32_offset, svint32_t, svuint32_t, + svst1_scatter_u32base_offset_s32 (p0, z1, 128, z0), + svst1_scatter_offset (p0, z1, 128, z0)) + +/* +** st1_scatter_x0_s32_index: +** lsl (x[0-9]+), x0, #?2 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_s32_index: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_s32_index: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_s32_index: +** st1w z0\.s, p0, \[z1\.s, #20\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_s32_index: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_s32_index: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_s32_index, svint32_t, svuint32_t, + svst1_scatter_u32base_index_s32 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_s32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s32_s32offset, svint32_t, int32_t, svint32_t, + svst1_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_s32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s32_s32offset, svint32_t, int32_t, svint32_t, + svst1_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_s32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s32_u32offset, svint32_t, int32_t, svuint32_t, + svst1_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_s32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s32_u32offset, svint32_t, int32_t, svuint32_t, + svst1_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_s32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s32_s32index, svint32_t, int32_t, svint32_t, + svst1_scatter_s32index_s32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_s32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s32_s32index, svint32_t, int32_t, svint32_t, + svst1_scatter_s32index_s32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_s32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s32_u32index, svint32_t, int32_t, svuint32_t, + svst1_scatter_u32index_s32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_s32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s32_u32index, svint32_t, int32_t, svuint32_t, + svst1_scatter_u32index_s32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s64.c new file mode 100644 index 00000000000..fcc6acb609b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_s64.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_s64: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_s64, svint64_t, svuint64_t, + svst1_scatter_u64base_s64 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_s64_offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m8_s64_offset: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m8_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, -8, z0), + svst1_scatter_offset (p0, z1, -8, z0)) + +/* +** st1_scatter_0_s64_offset: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_9_s64_offset: +** mov (x[0-9]+), #?9 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_9_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 9, z0), + svst1_scatter_offset (p0, z1, 9, z0)) + +/* +** st1_scatter_10_s64_offset: +** mov (x[0-9]+), #?10 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_10_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 10, z0), + svst1_scatter_offset (p0, z1, 10, z0)) + +/* +** st1_scatter_11_s64_offset: +** mov (x[0-9]+), #?11 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_11_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 11, z0), + svst1_scatter_offset (p0, z1, 11, z0)) + +/* +** st1_scatter_12_s64_offset: +** mov (x[0-9]+), #?12 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_12_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 12, z0), + svst1_scatter_offset (p0, z1, 12, z0)) + +/* +** st1_scatter_13_s64_offset: +** mov (x[0-9]+), #?13 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_13_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 13, z0), + svst1_scatter_offset (p0, z1, 13, z0)) + +/* +** st1_scatter_14_s64_offset: +** mov (x[0-9]+), #?14 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_14_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 14, z0), + svst1_scatter_offset (p0, z1, 14, z0)) + +/* +** st1_scatter_15_s64_offset: +** mov (x[0-9]+), #?15 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_15_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 15, z0), + svst1_scatter_offset (p0, z1, 15, z0)) + +/* +** st1_scatter_16_s64_offset: +** st1d z0\.d, p0, \[z1\.d, #16\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_16_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 16, z0), + svst1_scatter_offset (p0, z1, 16, z0)) + +/* +** st1_scatter_248_s64_offset: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_248_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 248, z0), + svst1_scatter_offset (p0, z1, 248, z0)) + +/* +** st1_scatter_256_s64_offset: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_256_s64_offset, svint64_t, svuint64_t, + svst1_scatter_u64base_offset_s64 (p0, z1, 256, z0), + svst1_scatter_offset (p0, z1, 256, z0)) + +/* +** st1_scatter_x0_s64_index: +** lsl (x[0-9]+), x0, #?3 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_s64_index: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_s64_index: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_s64_index: +** st1d z0\.d, p0, \[z1\.d, #40\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_s64_index: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_s64_index: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_s64_index, svint64_t, svuint64_t, + svst1_scatter_u64base_index_s64 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_s64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s64_s64offset, svint64_t, int64_t, svint64_t, + svst1_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_s64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s64_s64offset, svint64_t, int64_t, svint64_t, + svst1_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_s64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_s64_s64offset, svint64_t, int64_t, svint64_t, + svst1_scatter_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_s64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s64_u64offset, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_s64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s64_u64offset, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_s64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_s64_u64offset, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_s64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s64_s64index, svint64_t, int64_t, svint64_t, + svst1_scatter_s64index_s64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_s64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s64_s64index, svint64_t, int64_t, svint64_t, + svst1_scatter_s64index_s64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_s64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_s64_s64index, svint64_t, int64_t, svint64_t, + svst1_scatter_s64index_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_s64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_s64_u64index, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64index_s64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_s64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_s64_u64index, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64index_s64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_s64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_s64_u64index, svint64_t, int64_t, svuint64_t, + svst1_scatter_u64index_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u32.c new file mode 100644 index 00000000000..18d636ab364 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u32.c @@ -0,0 +1,227 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_u32: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_u32, svuint32_t, svuint32_t, + svst1_scatter_u32base_u32 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_u32_offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m4_u32_offset: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m4_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, -4, z0), + svst1_scatter_offset (p0, z1, -4, z0)) + +/* +** st1_scatter_0_u32_offset: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_5_u32_offset: +** mov (x[0-9]+), #?5 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 5, z0), + svst1_scatter_offset (p0, z1, 5, z0)) + +/* +** st1_scatter_6_u32_offset: +** mov (x[0-9]+), #?6 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_6_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 6, z0), + svst1_scatter_offset (p0, z1, 6, z0)) + +/* +** st1_scatter_7_u32_offset: +** mov (x[0-9]+), #?7 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_7_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 7, z0), + svst1_scatter_offset (p0, z1, 7, z0)) + +/* +** st1_scatter_8_u32_offset: +** st1w z0\.s, p0, \[z1\.s, #8\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_8_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 8, z0), + svst1_scatter_offset (p0, z1, 8, z0)) + +/* +** st1_scatter_124_u32_offset: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_124_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 124, z0), + svst1_scatter_offset (p0, z1, 124, z0)) + +/* +** st1_scatter_128_u32_offset: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_128_u32_offset, svuint32_t, svuint32_t, + svst1_scatter_u32base_offset_u32 (p0, z1, 128, z0), + svst1_scatter_offset (p0, z1, 128, z0)) + +/* +** st1_scatter_x0_u32_index: +** lsl (x[0-9]+), x0, #?2 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_u32_index: +** mov (x[0-9]+), #?-4 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_u32_index: +** st1w z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_u32_index: +** st1w z0\.s, p0, \[z1\.s, #20\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_u32_index: +** st1w z0\.s, p0, \[z1\.s, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_u32_index: +** mov (x[0-9]+), #?128 +** st1w z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_u32_index, svuint32_t, svuint32_t, + svst1_scatter_u32base_index_u32 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_u32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u32_s32offset, svuint32_t, uint32_t, svint32_t, + svst1_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_u32_s32offset: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u32_s32offset, svuint32_t, uint32_t, svint32_t, + svst1_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_u32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + svst1_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_u32_u32offset: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u32_u32offset, svuint32_t, uint32_t, svuint32_t, + svst1_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_u32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u32_s32index, svuint32_t, uint32_t, svint32_t, + svst1_scatter_s32index_u32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_u32_s32index: +** st1w z0\.s, p0, \[x0, z1\.s, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u32_s32index, svuint32_t, uint32_t, svint32_t, + svst1_scatter_s32index_u32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_x0_u32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u32_u32index, svuint32_t, uint32_t, svuint32_t, + svst1_scatter_u32index_u32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_u32_u32index: +** st1w z0\.s, p0, \[x0, z1\.s, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u32_u32index, svuint32_t, uint32_t, svuint32_t, + svst1_scatter_u32index_u32 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u64.c new file mode 100644 index 00000000000..930aa07086b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_scatter_u64.c @@ -0,0 +1,303 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_scatter_u64: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_u64, svuint64_t, svuint64_t, + svst1_scatter_u64base_u64 (p0, z1, z0), + svst1_scatter (p0, z1, z0)) + +/* +** st1_scatter_x0_u64_offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, x0, z0), + svst1_scatter_offset (p0, z1, x0, z0)) + +/* +** st1_scatter_m8_u64_offset: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m8_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, -8, z0), + svst1_scatter_offset (p0, z1, -8, z0)) + +/* +** st1_scatter_0_u64_offset: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 0, z0), + svst1_scatter_offset (p0, z1, 0, z0)) + +/* +** st1_scatter_9_u64_offset: +** mov (x[0-9]+), #?9 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_9_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 9, z0), + svst1_scatter_offset (p0, z1, 9, z0)) + +/* +** st1_scatter_10_u64_offset: +** mov (x[0-9]+), #?10 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_10_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 10, z0), + svst1_scatter_offset (p0, z1, 10, z0)) + +/* +** st1_scatter_11_u64_offset: +** mov (x[0-9]+), #?11 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_11_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 11, z0), + svst1_scatter_offset (p0, z1, 11, z0)) + +/* +** st1_scatter_12_u64_offset: +** mov (x[0-9]+), #?12 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_12_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 12, z0), + svst1_scatter_offset (p0, z1, 12, z0)) + +/* +** st1_scatter_13_u64_offset: +** mov (x[0-9]+), #?13 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_13_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 13, z0), + svst1_scatter_offset (p0, z1, 13, z0)) + +/* +** st1_scatter_14_u64_offset: +** mov (x[0-9]+), #?14 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_14_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 14, z0), + svst1_scatter_offset (p0, z1, 14, z0)) + +/* +** st1_scatter_15_u64_offset: +** mov (x[0-9]+), #?15 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_15_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 15, z0), + svst1_scatter_offset (p0, z1, 15, z0)) + +/* +** st1_scatter_16_u64_offset: +** st1d z0\.d, p0, \[z1\.d, #16\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_16_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 16, z0), + svst1_scatter_offset (p0, z1, 16, z0)) + +/* +** st1_scatter_248_u64_offset: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_248_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 248, z0), + svst1_scatter_offset (p0, z1, 248, z0)) + +/* +** st1_scatter_256_u64_offset: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_256_u64_offset, svuint64_t, svuint64_t, + svst1_scatter_u64base_offset_u64 (p0, z1, 256, z0), + svst1_scatter_offset (p0, z1, 256, z0)) + +/* +** st1_scatter_x0_u64_index: +** lsl (x[0-9]+), x0, #?3 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_x0_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, x0, z0), + svst1_scatter_index (p0, z1, x0, z0)) + +/* +** st1_scatter_m1_u64_index: +** mov (x[0-9]+), #?-8 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_m1_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, -1, z0), + svst1_scatter_index (p0, z1, -1, z0)) + +/* +** st1_scatter_0_u64_index: +** st1d z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_0_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, 0, z0), + svst1_scatter_index (p0, z1, 0, z0)) + +/* +** st1_scatter_5_u64_index: +** st1d z0\.d, p0, \[z1\.d, #40\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_5_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, 5, z0), + svst1_scatter_index (p0, z1, 5, z0)) + +/* +** st1_scatter_31_u64_index: +** st1d z0\.d, p0, \[z1\.d, #248\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_31_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, 31, z0), + svst1_scatter_index (p0, z1, 31, z0)) + +/* +** st1_scatter_32_u64_index: +** mov (x[0-9]+), #?256 +** st1d z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1_scatter_32_u64_index, svuint64_t, svuint64_t, + svst1_scatter_u64base_index_u64 (p0, z1, 32, z0), + svst1_scatter_index (p0, z1, 32, z0)) + +/* +** st1_scatter_x0_u64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u64_s64offset, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_u64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u64_s64offset, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_u64_s64offset: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_u64_s64offset, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_u64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_u64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1_scatter_offset (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_u64_u64offset: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_u64_u64offset, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_u64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u64_s64index, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64index_u64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_u64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u64_s64index, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64index_u64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_u64_s64index: +** st1d z0\.d, p0, \[x0, z1\.d, sxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_u64_s64index, svuint64_t, uint64_t, svint64_t, + svst1_scatter_s64index_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1_scatter_x0_u64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_x0_u64_u64index, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64index_u64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_u64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, lsl 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_u64_u64index, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64index_u64 (p0, x0, z1, z0), + svst1_scatter_index (p0, x0, z1, z0)) + +/* +** st1_scatter_ext_u64_u64index: +** st1d z0\.d, p0, \[x0, z1\.d, uxtw 3\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1_scatter_ext_u64_u64index, svuint64_t, uint64_t, svuint64_t, + svst1_scatter_u64index_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u16.c new file mode 100644 index 00000000000..7be6a030255 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_u16_base: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u16_base, svuint16_t, uint16_t, + svst1_u16 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_u16_index: +** st1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1_u16_index, svuint16_t, uint16_t, + svst1_u16 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_u16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_u16_1, svuint16_t, uint16_t, + svst1_u16 (p0, x0 + svcnth (), z0), + svst1 (p0, x0 + svcnth (), z0)) + +/* +** st1_u16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_u16_7, svuint16_t, uint16_t, + svst1_u16 (p0, x0 + svcnth () * 7, z0), + svst1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u16_8, svuint16_t, uint16_t, + svst1_u16 (p0, x0 + svcnth () * 8, z0), + svst1 (p0, x0 + svcnth () * 8, z0)) + +/* +** st1_u16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_u16_m1, svuint16_t, uint16_t, + svst1_u16 (p0, x0 - svcnth (), z0), + svst1 (p0, x0 - svcnth (), z0)) + +/* +** st1_u16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_u16_m8, svuint16_t, uint16_t, + svst1_u16 (p0, x0 - svcnth () * 8, z0), + svst1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u16_m9, svuint16_t, uint16_t, + svst1_u16 (p0, x0 - svcnth () * 9, z0), + svst1 (p0, x0 - svcnth () * 9, z0)) + +/* +** st1_vnum_u16_0: +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u16_0, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_u16_1: +** st1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u16_1, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_u16_7: +** st1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u16_7, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u16_8: +** incb x0, all, mul #8 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u16_8, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_u16_m1: +** st1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u16_m1, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_u16_m8: +** st1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u16_m8, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u16_m9: +** decb x0, all, mul #9 +** st1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u16_m9, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_u16_x1, svuint16_t, uint16_t, + svst1_vnum_u16 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u32.c new file mode 100644 index 00000000000..1a04ea83153 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_u32_base: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u32_base, svuint32_t, uint32_t, + svst1_u32 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_u32_index: +** st1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st1_u32_index, svuint32_t, uint32_t, + svst1_u32 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_u32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_u32_1, svuint32_t, uint32_t, + svst1_u32 (p0, x0 + svcntw (), z0), + svst1 (p0, x0 + svcntw (), z0)) + +/* +** st1_u32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_u32_7, svuint32_t, uint32_t, + svst1_u32 (p0, x0 + svcntw () * 7, z0), + svst1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u32_8, svuint32_t, uint32_t, + svst1_u32 (p0, x0 + svcntw () * 8, z0), + svst1 (p0, x0 + svcntw () * 8, z0)) + +/* +** st1_u32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_u32_m1, svuint32_t, uint32_t, + svst1_u32 (p0, x0 - svcntw (), z0), + svst1 (p0, x0 - svcntw (), z0)) + +/* +** st1_u32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_u32_m8, svuint32_t, uint32_t, + svst1_u32 (p0, x0 - svcntw () * 8, z0), + svst1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u32_m9, svuint32_t, uint32_t, + svst1_u32 (p0, x0 - svcntw () * 9, z0), + svst1 (p0, x0 - svcntw () * 9, z0)) + +/* +** st1_vnum_u32_0: +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u32_0, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_u32_1: +** st1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u32_1, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_u32_7: +** st1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u32_7, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u32_8: +** incb x0, all, mul #8 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u32_8, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_u32_m1: +** st1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u32_m1, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_u32_m8: +** st1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u32_m8, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u32_m9: +** decb x0, all, mul #9 +** st1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u32_m9, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_u32_x1, svuint32_t, uint32_t, + svst1_vnum_u32 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u64.c new file mode 100644 index 00000000000..675f6a9fb01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_u64_base: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u64_base, svuint64_t, uint64_t, + svst1_u64 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_u64_index: +** st1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st1_u64_index, svuint64_t, uint64_t, + svst1_u64 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_u64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_u64_1, svuint64_t, uint64_t, + svst1_u64 (p0, x0 + svcntd (), z0), + svst1 (p0, x0 + svcntd (), z0)) + +/* +** st1_u64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_u64_7, svuint64_t, uint64_t, + svst1_u64 (p0, x0 + svcntd () * 7, z0), + svst1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u64_8, svuint64_t, uint64_t, + svst1_u64 (p0, x0 + svcntd () * 8, z0), + svst1 (p0, x0 + svcntd () * 8, z0)) + +/* +** st1_u64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_u64_m1, svuint64_t, uint64_t, + svst1_u64 (p0, x0 - svcntd (), z0), + svst1 (p0, x0 - svcntd (), z0)) + +/* +** st1_u64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_u64_m8, svuint64_t, uint64_t, + svst1_u64 (p0, x0 - svcntd () * 8, z0), + svst1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u64_m9, svuint64_t, uint64_t, + svst1_u64 (p0, x0 - svcntd () * 9, z0), + svst1 (p0, x0 - svcntd () * 9, z0)) + +/* +** st1_vnum_u64_0: +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u64_0, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_u64_1: +** st1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u64_1, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_u64_7: +** st1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u64_7, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u64_8: +** incb x0, all, mul #8 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u64_8, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_u64_m1: +** st1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u64_m1, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_u64_m8: +** st1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u64_m8, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u64_m9: +** decb x0, all, mul #9 +** st1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u64_m9, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1_vnum_u64_x1, svuint64_t, uint64_t, + svst1_vnum_u64 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u8.c new file mode 100644 index 00000000000..7071c07844e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1_u8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1_u8_base: +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u8_base, svuint8_t, uint8_t, + svst1_u8 (p0, x0, z0), + svst1 (p0, x0, z0)) + +/* +** st1_u8_index: +** st1b z0\.b, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1_u8_index, svuint8_t, uint8_t, + svst1_u8 (p0, x0 + x1, z0), + svst1 (p0, x0 + x1, z0)) + +/* +** st1_u8_1: +** st1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_u8_1, svuint8_t, uint8_t, + svst1_u8 (p0, x0 + svcntb (), z0), + svst1 (p0, x0 + svcntb (), z0)) + +/* +** st1_u8_7: +** st1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_u8_7, svuint8_t, uint8_t, + svst1_u8 (p0, x0 + svcntb () * 7, z0), + svst1 (p0, x0 + svcntb () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u8_8: +** incb x0, all, mul #8 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u8_8, svuint8_t, uint8_t, + svst1_u8 (p0, x0 + svcntb () * 8, z0), + svst1 (p0, x0 + svcntb () * 8, z0)) + +/* +** st1_u8_m1: +** st1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_u8_m1, svuint8_t, uint8_t, + svst1_u8 (p0, x0 - svcntb (), z0), + svst1 (p0, x0 - svcntb (), z0)) + +/* +** st1_u8_m8: +** st1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_u8_m8, svuint8_t, uint8_t, + svst1_u8 (p0, x0 - svcntb () * 8, z0), + svst1 (p0, x0 - svcntb () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_u8_m9: +** decb x0, all, mul #9 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_u8_m9, svuint8_t, uint8_t, + svst1_u8 (p0, x0 - svcntb () * 9, z0), + svst1 (p0, x0 - svcntb () * 9, z0)) + +/* +** st1_vnum_u8_0: +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u8_0, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, 0, z0), + svst1_vnum (p0, x0, 0, z0)) + +/* +** st1_vnum_u8_1: +** st1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u8_1, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, 1, z0), + svst1_vnum (p0, x0, 1, z0)) + +/* +** st1_vnum_u8_7: +** st1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u8_7, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, 7, z0), + svst1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u8_8: +** incb x0, all, mul #8 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u8_8, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, 8, z0), + svst1_vnum (p0, x0, 8, z0)) + +/* +** st1_vnum_u8_m1: +** st1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u8_m1, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, -1, z0), + svst1_vnum (p0, x0, -1, z0)) + +/* +** st1_vnum_u8_m8: +** st1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1_vnum_u8_m8, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, -8, z0), + svst1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1_vnum_u8_m9: +** decb x0, all, mul #9 +** st1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (st1_vnum_u8_m9, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, -9, z0), + svst1_vnum (p0, x0, -9, z0)) + +/* +** st1_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.b, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.b, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1_vnum_u8_x1, svuint8_t, uint8_t, + svst1_vnum_u8 (p0, x0, x1, z0), + svst1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s16.c new file mode 100644 index 00000000000..d768bf6206b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_s16_base: +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s16_base, svint16_t, int8_t, + svst1b_s16 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_s16_index: +** st1b z0\.h, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_s16_index, svint16_t, int8_t, + svst1b_s16 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_s16_1: +** st1b z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s16_1, svint16_t, int8_t, + svst1b_s16 (p0, x0 + svcnth (), z0), + svst1b (p0, x0 + svcnth (), z0)) + +/* +** st1b_s16_7: +** st1b z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_s16_7, svint16_t, int8_t, + svst1b_s16 (p0, x0 + svcnth () * 7, z0), + svst1b (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s16_8: +** incb x0, all, mul #4 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s16_8, svint16_t, int8_t, + svst1b_s16 (p0, x0 + svcnth () * 8, z0), + svst1b (p0, x0 + svcnth () * 8, z0)) + +/* +** st1b_s16_m1: +** st1b z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s16_m1, svint16_t, int8_t, + svst1b_s16 (p0, x0 - svcnth (), z0), + svst1b (p0, x0 - svcnth (), z0)) + +/* +** st1b_s16_m8: +** st1b z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_s16_m8, svint16_t, int8_t, + svst1b_s16 (p0, x0 - svcnth () * 8, z0), + svst1b (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s16_m9: +** dech x0, all, mul #9 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s16_m9, svint16_t, int8_t, + svst1b_s16 (p0, x0 - svcnth () * 9, z0), + svst1b (p0, x0 - svcnth () * 9, z0)) + +/* +** st1b_vnum_s16_0: +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_0, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_s16_1: +** st1b z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_1, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_s16_7: +** st1b z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_7, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s16_8: +** incb x0, all, mul #4 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_8, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_s16_m1: +** st1b z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_m1, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_s16_m8: +** st1b z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_m8, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s16_m9: +** dech x0, all, mul #9 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s16_m9, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_s16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.h, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.h, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_s16_x1, svint16_t, int8_t, + svst1b_vnum_s16 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s32.c new file mode 100644 index 00000000000..052c8020f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_s32_base: +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s32_base, svint32_t, int8_t, + svst1b_s32 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_s32_index: +** st1b z0\.s, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_s32_index, svint32_t, int8_t, + svst1b_s32 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_s32_1: +** st1b z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s32_1, svint32_t, int8_t, + svst1b_s32 (p0, x0 + svcntw (), z0), + svst1b (p0, x0 + svcntw (), z0)) + +/* +** st1b_s32_7: +** st1b z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_s32_7, svint32_t, int8_t, + svst1b_s32 (p0, x0 + svcntw () * 7, z0), + svst1b (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s32_8: +** incb x0, all, mul #2 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s32_8, svint32_t, int8_t, + svst1b_s32 (p0, x0 + svcntw () * 8, z0), + svst1b (p0, x0 + svcntw () * 8, z0)) + +/* +** st1b_s32_m1: +** st1b z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s32_m1, svint32_t, int8_t, + svst1b_s32 (p0, x0 - svcntw (), z0), + svst1b (p0, x0 - svcntw (), z0)) + +/* +** st1b_s32_m8: +** st1b z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_s32_m8, svint32_t, int8_t, + svst1b_s32 (p0, x0 - svcntw () * 8, z0), + svst1b (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s32_m9: +** decw x0, all, mul #9 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s32_m9, svint32_t, int8_t, + svst1b_s32 (p0, x0 - svcntw () * 9, z0), + svst1b (p0, x0 - svcntw () * 9, z0)) + +/* +** st1b_vnum_s32_0: +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_0, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_s32_1: +** st1b z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_1, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_s32_7: +** st1b z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_7, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s32_8: +** incb x0, all, mul #2 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_8, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_s32_m1: +** st1b z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_m1, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_s32_m8: +** st1b z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_m8, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s32_m9: +** decw x0, all, mul #9 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s32_m9, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_s32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.s, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.s, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_s32_x1, svint32_t, int8_t, + svst1b_vnum_s32 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s64.c new file mode 100644 index 00000000000..2d7b7df5f51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_s64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_s64_base: +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s64_base, svint64_t, int8_t, + svst1b_s64 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_s64_index: +** st1b z0\.d, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_s64_index, svint64_t, int8_t, + svst1b_s64 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_s64_1: +** st1b z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s64_1, svint64_t, int8_t, + svst1b_s64 (p0, x0 + svcntd (), z0), + svst1b (p0, x0 + svcntd (), z0)) + +/* +** st1b_s64_7: +** st1b z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_s64_7, svint64_t, int8_t, + svst1b_s64 (p0, x0 + svcntd () * 7, z0), + svst1b (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s64_8: +** incb x0 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s64_8, svint64_t, int8_t, + svst1b_s64 (p0, x0 + svcntd () * 8, z0), + svst1b (p0, x0 + svcntd () * 8, z0)) + +/* +** st1b_s64_m1: +** st1b z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_s64_m1, svint64_t, int8_t, + svst1b_s64 (p0, x0 - svcntd (), z0), + svst1b (p0, x0 - svcntd (), z0)) + +/* +** st1b_s64_m8: +** st1b z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_s64_m8, svint64_t, int8_t, + svst1b_s64 (p0, x0 - svcntd () * 8, z0), + svst1b (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_s64_m9: +** decd x0, all, mul #9 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_s64_m9, svint64_t, int8_t, + svst1b_s64 (p0, x0 - svcntd () * 9, z0), + svst1b (p0, x0 - svcntd () * 9, z0)) + +/* +** st1b_vnum_s64_0: +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_0, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_s64_1: +** st1b z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_1, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_s64_7: +** st1b z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_7, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s64_8: +** incb x0 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_8, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_s64_m1: +** st1b z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_m1, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_s64_m8: +** st1b z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_m8, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_s64_m9: +** decd x0, all, mul #9 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_s64_m9, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_s64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.d, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.d, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_s64_x1, svint64_t, int8_t, + svst1b_vnum_s64 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s32.c new file mode 100644 index 00000000000..bfdeb07abe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s32.c @@ -0,0 +1,104 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_scatter_s32: +** st1b z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_s32, svint32_t, svuint32_t, + svst1b_scatter_u32base_s32 (p0, z1, z0), + svst1b_scatter (p0, z1, z0)) + +/* +** st1b_scatter_x0_s32_offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_x0_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, x0, z0), + svst1b_scatter_offset (p0, z1, x0, z0)) + +/* +** st1b_scatter_m1_s32_offset: +** mov (x[0-9]+), #?-1 +** st1b z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_m1_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, -1, z0), + svst1b_scatter_offset (p0, z1, -1, z0)) + +/* +** st1b_scatter_0_s32_offset: +** st1b z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_0_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, 0, z0), + svst1b_scatter_offset (p0, z1, 0, z0)) + +/* +** st1b_scatter_5_s32_offset: +** st1b z0\.s, p0, \[z1\.s, #5\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_5_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, 5, z0), + svst1b_scatter_offset (p0, z1, 5, z0)) + +/* +** st1b_scatter_31_s32_offset: +** st1b z0\.s, p0, \[z1\.s, #31\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_31_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, 31, z0), + svst1b_scatter_offset (p0, z1, 31, z0)) + +/* +** st1b_scatter_32_s32_offset: +** mov (x[0-9]+), #?32 +** st1b z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_32_s32_offset, svint32_t, svuint32_t, + svst1b_scatter_u32base_offset_s32 (p0, z1, 32, z0), + svst1b_scatter_offset (p0, z1, 32, z0)) + +/* +** st1b_scatter_x0_s32_s32offset: +** st1b z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_s32_s32offset, svint32_t, int8_t, svint32_t, + svst1b_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_s32_s32offset: +** st1b z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_s32_s32offset, svint32_t, int8_t, svint32_t, + svst1b_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_x0_s32_u32offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_s32_u32offset, svint32_t, int8_t, svuint32_t, + svst1b_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_s32_u32offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_s32_u32offset, svint32_t, int8_t, svuint32_t, + svst1b_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s64.c new file mode 100644 index 00000000000..a18bb840f49 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_s64.c @@ -0,0 +1,122 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_scatter_s64: +** st1b z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_s64, svint64_t, svuint64_t, + svst1b_scatter_u64base_s64 (p0, z1, z0), + svst1b_scatter (p0, z1, z0)) + +/* +** st1b_scatter_x0_s64_offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_x0_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, x0, z0), + svst1b_scatter_offset (p0, z1, x0, z0)) + +/* +** st1b_scatter_m1_s64_offset: +** mov (x[0-9]+), #?-1 +** st1b z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_m1_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, -1, z0), + svst1b_scatter_offset (p0, z1, -1, z0)) + +/* +** st1b_scatter_0_s64_offset: +** st1b z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_0_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, 0, z0), + svst1b_scatter_offset (p0, z1, 0, z0)) + +/* +** st1b_scatter_5_s64_offset: +** st1b z0\.d, p0, \[z1\.d, #5\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_5_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, 5, z0), + svst1b_scatter_offset (p0, z1, 5, z0)) + +/* +** st1b_scatter_31_s64_offset: +** st1b z0\.d, p0, \[z1\.d, #31\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_31_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, 31, z0), + svst1b_scatter_offset (p0, z1, 31, z0)) + +/* +** st1b_scatter_32_s64_offset: +** mov (x[0-9]+), #?32 +** st1b z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_32_s64_offset, svint64_t, svuint64_t, + svst1b_scatter_u64base_offset_s64 (p0, z1, 32, z0), + svst1b_scatter_offset (p0, z1, 32, z0)) + +/* +** st1b_scatter_x0_s64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_s64_s64offset, svint64_t, int8_t, svint64_t, + svst1b_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_s64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_s64_s64offset, svint64_t, int8_t, svint64_t, + svst1b_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_ext_s64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_ext_s64_s64offset, svint64_t, int8_t, svint64_t, + svst1b_scatter_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1b_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1b_scatter_x0_s64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_s64_u64offset, svint64_t, int8_t, svuint64_t, + svst1b_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_s64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_s64_u64offset, svint64_t, int8_t, svuint64_t, + svst1b_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_ext_s64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_ext_s64_u64offset, svint64_t, int8_t, svuint64_t, + svst1b_scatter_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1b_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u32.c new file mode 100644 index 00000000000..8039dc72f40 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u32.c @@ -0,0 +1,104 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_scatter_u32: +** st1b z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_u32, svuint32_t, svuint32_t, + svst1b_scatter_u32base_u32 (p0, z1, z0), + svst1b_scatter (p0, z1, z0)) + +/* +** st1b_scatter_x0_u32_offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_x0_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, x0, z0), + svst1b_scatter_offset (p0, z1, x0, z0)) + +/* +** st1b_scatter_m1_u32_offset: +** mov (x[0-9]+), #?-1 +** st1b z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_m1_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, -1, z0), + svst1b_scatter_offset (p0, z1, -1, z0)) + +/* +** st1b_scatter_0_u32_offset: +** st1b z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_0_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, 0, z0), + svst1b_scatter_offset (p0, z1, 0, z0)) + +/* +** st1b_scatter_5_u32_offset: +** st1b z0\.s, p0, \[z1\.s, #5\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_5_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, 5, z0), + svst1b_scatter_offset (p0, z1, 5, z0)) + +/* +** st1b_scatter_31_u32_offset: +** st1b z0\.s, p0, \[z1\.s, #31\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_31_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, 31, z0), + svst1b_scatter_offset (p0, z1, 31, z0)) + +/* +** st1b_scatter_32_u32_offset: +** mov (x[0-9]+), #?32 +** st1b z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_32_u32_offset, svuint32_t, svuint32_t, + svst1b_scatter_u32base_offset_u32 (p0, z1, 32, z0), + svst1b_scatter_offset (p0, z1, 32, z0)) + +/* +** st1b_scatter_x0_u32_s32offset: +** st1b z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_u32_s32offset, svuint32_t, uint8_t, svint32_t, + svst1b_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_u32_s32offset: +** st1b z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_u32_s32offset, svuint32_t, uint8_t, svint32_t, + svst1b_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_x0_u32_u32offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + svst1b_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_u32_u32offset: +** st1b z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_u32_u32offset, svuint32_t, uint8_t, svuint32_t, + svst1b_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u64.c new file mode 100644 index 00000000000..c888ea64472 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_scatter_u64.c @@ -0,0 +1,122 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_scatter_u64: +** st1b z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_u64, svuint64_t, svuint64_t, + svst1b_scatter_u64base_u64 (p0, z1, z0), + svst1b_scatter (p0, z1, z0)) + +/* +** st1b_scatter_x0_u64_offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_x0_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, x0, z0), + svst1b_scatter_offset (p0, z1, x0, z0)) + +/* +** st1b_scatter_m1_u64_offset: +** mov (x[0-9]+), #?-1 +** st1b z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_m1_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, -1, z0), + svst1b_scatter_offset (p0, z1, -1, z0)) + +/* +** st1b_scatter_0_u64_offset: +** st1b z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_0_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, 0, z0), + svst1b_scatter_offset (p0, z1, 0, z0)) + +/* +** st1b_scatter_5_u64_offset: +** st1b z0\.d, p0, \[z1\.d, #5\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_5_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, 5, z0), + svst1b_scatter_offset (p0, z1, 5, z0)) + +/* +** st1b_scatter_31_u64_offset: +** st1b z0\.d, p0, \[z1\.d, #31\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_31_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, 31, z0), + svst1b_scatter_offset (p0, z1, 31, z0)) + +/* +** st1b_scatter_32_u64_offset: +** mov (x[0-9]+), #?32 +** st1b z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1b_scatter_32_u64_offset, svuint64_t, svuint64_t, + svst1b_scatter_u64base_offset_u64 (p0, z1, 32, z0), + svst1b_scatter_offset (p0, z1, 32, z0)) + +/* +** st1b_scatter_x0_u64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_u64_s64offset, svuint64_t, uint8_t, svint64_t, + svst1b_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_u64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_u64_s64offset, svuint64_t, uint8_t, svint64_t, + svst1b_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_ext_u64_s64offset: +** st1b z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_ext_u64_s64offset, svuint64_t, uint8_t, svint64_t, + svst1b_scatter_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1b_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1b_scatter_x0_u64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_x0_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + svst1b_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_u64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + svst1b_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1b_scatter_offset (p0, x0, z1, z0)) + +/* +** st1b_scatter_ext_u64_u64offset: +** st1b z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1b_scatter_ext_u64_u64offset, svuint64_t, uint8_t, svuint64_t, + svst1b_scatter_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1b_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u16.c new file mode 100644 index 00000000000..3bc895e739f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u16.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_u16_base: +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u16_base, svuint16_t, uint8_t, + svst1b_u16 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_u16_index: +** st1b z0\.h, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_u16_index, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_u16_1: +** st1b z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u16_1, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 + svcnth (), z0), + svst1b (p0, x0 + svcnth (), z0)) + +/* +** st1b_u16_7: +** st1b z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_u16_7, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 + svcnth () * 7, z0), + svst1b (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u16_8: +** incb x0, all, mul #4 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u16_8, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 + svcnth () * 8, z0), + svst1b (p0, x0 + svcnth () * 8, z0)) + +/* +** st1b_u16_m1: +** st1b z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u16_m1, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 - svcnth (), z0), + svst1b (p0, x0 - svcnth (), z0)) + +/* +** st1b_u16_m8: +** st1b z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_u16_m8, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 - svcnth () * 8, z0), + svst1b (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u16_m9: +** dech x0, all, mul #9 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u16_m9, svuint16_t, uint8_t, + svst1b_u16 (p0, x0 - svcnth () * 9, z0), + svst1b (p0, x0 - svcnth () * 9, z0)) + +/* +** st1b_vnum_u16_0: +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_0, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_u16_1: +** st1b z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_1, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_u16_7: +** st1b z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_7, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u16_8: +** incb x0, all, mul #4 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_8, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_u16_m1: +** st1b z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_m1, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_u16_m8: +** st1b z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_m8, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u16_m9: +** dech x0, all, mul #9 +** st1b z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u16_m9, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_u16_x1: +** cnth (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.h, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.h, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_u16_x1, svuint16_t, uint8_t, + svst1b_vnum_u16 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u32.c new file mode 100644 index 00000000000..da03e89fd95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u32.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_u32_base: +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u32_base, svuint32_t, uint8_t, + svst1b_u32 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_u32_index: +** st1b z0\.s, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_u32_index, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_u32_1: +** st1b z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u32_1, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 + svcntw (), z0), + svst1b (p0, x0 + svcntw (), z0)) + +/* +** st1b_u32_7: +** st1b z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_u32_7, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 + svcntw () * 7, z0), + svst1b (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u32_8: +** incb x0, all, mul #2 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u32_8, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 + svcntw () * 8, z0), + svst1b (p0, x0 + svcntw () * 8, z0)) + +/* +** st1b_u32_m1: +** st1b z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u32_m1, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 - svcntw (), z0), + svst1b (p0, x0 - svcntw (), z0)) + +/* +** st1b_u32_m8: +** st1b z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_u32_m8, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 - svcntw () * 8, z0), + svst1b (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u32_m9: +** decw x0, all, mul #9 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u32_m9, svuint32_t, uint8_t, + svst1b_u32 (p0, x0 - svcntw () * 9, z0), + svst1b (p0, x0 - svcntw () * 9, z0)) + +/* +** st1b_vnum_u32_0: +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_0, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_u32_1: +** st1b z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_1, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_u32_7: +** st1b z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_7, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u32_8: +** incb x0, all, mul #2 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_8, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_u32_m1: +** st1b z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_m1, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_u32_m8: +** st1b z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_m8, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u32_m9: +** decw x0, all, mul #9 +** st1b z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u32_m9, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_u32_x1: +** cntw (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.s, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.s, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_u32_x1, svuint32_t, uint8_t, + svst1b_vnum_u32 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u64.c new file mode 100644 index 00000000000..69d04e02b4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1b_u64.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1b_u64_base: +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u64_base, svuint64_t, uint8_t, + svst1b_u64 (p0, x0, z0), + svst1b (p0, x0, z0)) + +/* +** st1b_u64_index: +** st1b z0\.d, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st1b_u64_index, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 + x1, z0), + svst1b (p0, x0 + x1, z0)) + +/* +** st1b_u64_1: +** st1b z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u64_1, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 + svcntd (), z0), + svst1b (p0, x0 + svcntd (), z0)) + +/* +** st1b_u64_7: +** st1b z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_u64_7, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 + svcntd () * 7, z0), + svst1b (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u64_8: +** incb x0 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u64_8, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 + svcntd () * 8, z0), + svst1b (p0, x0 + svcntd () * 8, z0)) + +/* +** st1b_u64_m1: +** st1b z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_u64_m1, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 - svcntd (), z0), + svst1b (p0, x0 - svcntd (), z0)) + +/* +** st1b_u64_m8: +** st1b z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_u64_m8, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 - svcntd () * 8, z0), + svst1b (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_u64_m9: +** decd x0, all, mul #9 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_u64_m9, svuint64_t, uint8_t, + svst1b_u64 (p0, x0 - svcntd () * 9, z0), + svst1b (p0, x0 - svcntd () * 9, z0)) + +/* +** st1b_vnum_u64_0: +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_0, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, 0, z0), + svst1b_vnum (p0, x0, 0, z0)) + +/* +** st1b_vnum_u64_1: +** st1b z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_1, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, 1, z0), + svst1b_vnum (p0, x0, 1, z0)) + +/* +** st1b_vnum_u64_7: +** st1b z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_7, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, 7, z0), + svst1b_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u64_8: +** incb x0 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_8, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, 8, z0), + svst1b_vnum (p0, x0, 8, z0)) + +/* +** st1b_vnum_u64_m1: +** st1b z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_m1, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, -1, z0), + svst1b_vnum (p0, x0, -1, z0)) + +/* +** st1b_vnum_u64_m8: +** st1b z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_m8, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, -8, z0), + svst1b_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1b_vnum_u64_m9: +** decd x0, all, mul #9 +** st1b z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1b_vnum_u64_m9, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, -9, z0), + svst1b_vnum (p0, x0, -9, z0)) + +/* +** st1b_vnum_u64_x1: +** cntd (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st1b z0\.d, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st1b z0\.d, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st1b_vnum_u64_x1, svuint64_t, uint8_t, + svst1b_vnum_u64 (p0, x0, x1, z0), + svst1b_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s32.c new file mode 100644 index 00000000000..215962612f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_s32_base: +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s32_base, svint32_t, int16_t, + svst1h_s32 (p0, x0, z0), + svst1h (p0, x0, z0)) + +/* +** st1h_s32_index: +** st1h z0\.s, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1h_s32_index, svint32_t, int16_t, + svst1h_s32 (p0, x0 + x1, z0), + svst1h (p0, x0 + x1, z0)) + +/* +** st1h_s32_1: +** st1h z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_s32_1, svint32_t, int16_t, + svst1h_s32 (p0, x0 + svcntw (), z0), + svst1h (p0, x0 + svcntw (), z0)) + +/* +** st1h_s32_7: +** st1h z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_s32_7, svint32_t, int16_t, + svst1h_s32 (p0, x0 + svcntw () * 7, z0), + svst1h (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_s32_8: +** incb x0, all, mul #4 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s32_8, svint32_t, int16_t, + svst1h_s32 (p0, x0 + svcntw () * 8, z0), + svst1h (p0, x0 + svcntw () * 8, z0)) + +/* +** st1h_s32_m1: +** st1h z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_s32_m1, svint32_t, int16_t, + svst1h_s32 (p0, x0 - svcntw (), z0), + svst1h (p0, x0 - svcntw (), z0)) + +/* +** st1h_s32_m8: +** st1h z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_s32_m8, svint32_t, int16_t, + svst1h_s32 (p0, x0 - svcntw () * 8, z0), + svst1h (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_s32_m9: +** dech x0, all, mul #9 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s32_m9, svint32_t, int16_t, + svst1h_s32 (p0, x0 - svcntw () * 9, z0), + svst1h (p0, x0 - svcntw () * 9, z0)) + +/* +** st1h_vnum_s32_0: +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_0, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, 0, z0), + svst1h_vnum (p0, x0, 0, z0)) + +/* +** st1h_vnum_s32_1: +** st1h z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_1, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, 1, z0), + svst1h_vnum (p0, x0, 1, z0)) + +/* +** st1h_vnum_s32_7: +** st1h z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_7, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, 7, z0), + svst1h_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_s32_8: +** incb x0, all, mul #4 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_8, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, 8, z0), + svst1h_vnum (p0, x0, 8, z0)) + +/* +** st1h_vnum_s32_m1: +** st1h z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_m1, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, -1, z0), + svst1h_vnum (p0, x0, -1, z0)) + +/* +** st1h_vnum_s32_m8: +** st1h z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_m8, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, -8, z0), + svst1h_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_s32_m9: +** dech x0, all, mul #9 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_m9, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, -9, z0), + svst1h_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1h_vnum_s32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (st1h_vnum_s32_x1, svint32_t, int16_t, + svst1h_vnum_s32 (p0, x0, x1, z0), + svst1h_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s64.c new file mode 100644 index 00000000000..011baccf4ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_s64_base: +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s64_base, svint64_t, int16_t, + svst1h_s64 (p0, x0, z0), + svst1h (p0, x0, z0)) + +/* +** st1h_s64_index: +** st1h z0\.d, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1h_s64_index, svint64_t, int16_t, + svst1h_s64 (p0, x0 + x1, z0), + svst1h (p0, x0 + x1, z0)) + +/* +** st1h_s64_1: +** st1h z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_s64_1, svint64_t, int16_t, + svst1h_s64 (p0, x0 + svcntd (), z0), + svst1h (p0, x0 + svcntd (), z0)) + +/* +** st1h_s64_7: +** st1h z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_s64_7, svint64_t, int16_t, + svst1h_s64 (p0, x0 + svcntd () * 7, z0), + svst1h (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_s64_8: +** incb x0, all, mul #2 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s64_8, svint64_t, int16_t, + svst1h_s64 (p0, x0 + svcntd () * 8, z0), + svst1h (p0, x0 + svcntd () * 8, z0)) + +/* +** st1h_s64_m1: +** st1h z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_s64_m1, svint64_t, int16_t, + svst1h_s64 (p0, x0 - svcntd (), z0), + svst1h (p0, x0 - svcntd (), z0)) + +/* +** st1h_s64_m8: +** st1h z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_s64_m8, svint64_t, int16_t, + svst1h_s64 (p0, x0 - svcntd () * 8, z0), + svst1h (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_s64_m9: +** decw x0, all, mul #9 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_s64_m9, svint64_t, int16_t, + svst1h_s64 (p0, x0 - svcntd () * 9, z0), + svst1h (p0, x0 - svcntd () * 9, z0)) + +/* +** st1h_vnum_s64_0: +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_0, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, 0, z0), + svst1h_vnum (p0, x0, 0, z0)) + +/* +** st1h_vnum_s64_1: +** st1h z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_1, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, 1, z0), + svst1h_vnum (p0, x0, 1, z0)) + +/* +** st1h_vnum_s64_7: +** st1h z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_7, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, 7, z0), + svst1h_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_s64_8: +** incb x0, all, mul #2 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_8, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, 8, z0), + svst1h_vnum (p0, x0, 8, z0)) + +/* +** st1h_vnum_s64_m1: +** st1h z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_m1, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, -1, z0), + svst1h_vnum (p0, x0, -1, z0)) + +/* +** st1h_vnum_s64_m8: +** st1h z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_m8, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, -8, z0), + svst1h_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_s64_m9: +** decw x0, all, mul #9 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_m9, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, -9, z0), + svst1h_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1h_vnum_s64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1h_vnum_s64_x1, svint64_t, int16_t, + svst1h_vnum_s64 (p0, x0, x1, z0), + svst1h_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s32.c new file mode 100644 index 00000000000..835709f7a2e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s32.c @@ -0,0 +1,207 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_scatter_s32: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_s32, svint32_t, svuint32_t, + svst1h_scatter_u32base_s32 (p0, z1, z0), + svst1h_scatter (p0, z1, z0)) + +/* +** st1h_scatter_x0_s32_offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, x0, z0), + svst1h_scatter_offset (p0, z1, x0, z0)) + +/* +** st1h_scatter_m2_s32_offset: +** mov (x[0-9]+), #?-2 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m2_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, -2, z0), + svst1h_scatter_offset (p0, z1, -2, z0)) + +/* +** st1h_scatter_0_s32_offset: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, 0, z0), + svst1h_scatter_offset (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_s32_offset: +** mov (x[0-9]+), #?5 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, 5, z0), + svst1h_scatter_offset (p0, z1, 5, z0)) + +/* +** st1h_scatter_6_s32_offset: +** st1h z0\.s, p0, \[z1\.s, #6\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_6_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, 6, z0), + svst1h_scatter_offset (p0, z1, 6, z0)) + +/* +** st1h_scatter_62_s32_offset: +** st1h z0\.s, p0, \[z1\.s, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_62_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, 62, z0), + svst1h_scatter_offset (p0, z1, 62, z0)) + +/* +** st1h_scatter_64_s32_offset: +** mov (x[0-9]+), #?64 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_64_s32_offset, svint32_t, svuint32_t, + svst1h_scatter_u32base_offset_s32 (p0, z1, 64, z0), + svst1h_scatter_offset (p0, z1, 64, z0)) + +/* +** st1h_scatter_x0_s32_index: +** lsl (x[0-9]+), x0, #?1 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, x0, z0), + svst1h_scatter_index (p0, z1, x0, z0)) + +/* +** st1h_scatter_m1_s32_index: +** mov (x[0-9]+), #?-2 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m1_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, -1, z0), + svst1h_scatter_index (p0, z1, -1, z0)) + +/* +** st1h_scatter_0_s32_index: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, 0, z0), + svst1h_scatter_index (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_s32_index: +** st1h z0\.s, p0, \[z1\.s, #10\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, 5, z0), + svst1h_scatter_index (p0, z1, 5, z0)) + +/* +** st1h_scatter_31_s32_index: +** st1h z0\.s, p0, \[z1\.s, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_31_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, 31, z0), + svst1h_scatter_index (p0, z1, 31, z0)) + +/* +** st1h_scatter_32_s32_index: +** mov (x[0-9]+), #?64 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_32_s32_index, svint32_t, svuint32_t, + svst1h_scatter_u32base_index_s32 (p0, z1, 32, z0), + svst1h_scatter_index (p0, z1, 32, z0)) + +/* +** st1h_scatter_x0_s32_s32offset: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s32_s32offset, svint32_t, int16_t, svint32_t, + svst1h_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_s32_s32offset: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s32_s32offset, svint32_t, int16_t, svint32_t, + svst1h_scatter_s32offset_s32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_s32_u32offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s32_u32offset, svint32_t, int16_t, svuint32_t, + svst1h_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_s32_u32offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s32_u32offset, svint32_t, int16_t, svuint32_t, + svst1h_scatter_u32offset_s32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_s32_s32index: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s32_s32index, svint32_t, int16_t, svint32_t, + svst1h_scatter_s32index_s32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_s32_s32index: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s32_s32index, svint32_t, int16_t, svint32_t, + svst1h_scatter_s32index_s32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_s32_u32index: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s32_u32index, svint32_t, int16_t, svuint32_t, + svst1h_scatter_u32index_s32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_s32_u32index: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s32_u32index, svint32_t, int16_t, svuint32_t, + svst1h_scatter_u32index_s32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s64.c new file mode 100644 index 00000000000..c499d2c734a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_s64.c @@ -0,0 +1,243 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_scatter_s64: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_s64, svint64_t, svuint64_t, + svst1h_scatter_u64base_s64 (p0, z1, z0), + svst1h_scatter (p0, z1, z0)) + +/* +** st1h_scatter_x0_s64_offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, x0, z0), + svst1h_scatter_offset (p0, z1, x0, z0)) + +/* +** st1h_scatter_m2_s64_offset: +** mov (x[0-9]+), #?-2 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m2_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, -2, z0), + svst1h_scatter_offset (p0, z1, -2, z0)) + +/* +** st1h_scatter_0_s64_offset: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, 0, z0), + svst1h_scatter_offset (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_s64_offset: +** mov (x[0-9]+), #?5 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, 5, z0), + svst1h_scatter_offset (p0, z1, 5, z0)) + +/* +** st1h_scatter_6_s64_offset: +** st1h z0\.d, p0, \[z1\.d, #6\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_6_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, 6, z0), + svst1h_scatter_offset (p0, z1, 6, z0)) + +/* +** st1h_scatter_62_s64_offset: +** st1h z0\.d, p0, \[z1\.d, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_62_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, 62, z0), + svst1h_scatter_offset (p0, z1, 62, z0)) + +/* +** st1h_scatter_64_s64_offset: +** mov (x[0-9]+), #?64 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_64_s64_offset, svint64_t, svuint64_t, + svst1h_scatter_u64base_offset_s64 (p0, z1, 64, z0), + svst1h_scatter_offset (p0, z1, 64, z0)) + +/* +** st1h_scatter_x0_s64_index: +** lsl (x[0-9]+), x0, #?1 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, x0, z0), + svst1h_scatter_index (p0, z1, x0, z0)) + +/* +** st1h_scatter_m1_s64_index: +** mov (x[0-9]+), #?-2 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m1_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, -1, z0), + svst1h_scatter_index (p0, z1, -1, z0)) + +/* +** st1h_scatter_0_s64_index: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, 0, z0), + svst1h_scatter_index (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_s64_index: +** st1h z0\.d, p0, \[z1\.d, #10\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, 5, z0), + svst1h_scatter_index (p0, z1, 5, z0)) + +/* +** st1h_scatter_31_s64_index: +** st1h z0\.d, p0, \[z1\.d, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_31_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, 31, z0), + svst1h_scatter_index (p0, z1, 31, z0)) + +/* +** st1h_scatter_32_s64_index: +** mov (x[0-9]+), #?64 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_32_s64_index, svint64_t, svuint64_t, + svst1h_scatter_u64base_index_s64 (p0, z1, 32, z0), + svst1h_scatter_index (p0, z1, 32, z0)) + +/* +** st1h_scatter_x0_s64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s64_s64offset, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_s64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s64_s64offset, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_s64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_s64_s64offset, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1h_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_s64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s64_u64offset, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_s64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s64_u64offset, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_s64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_s64_u64offset, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1h_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_s64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s64_s64index, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64index_s64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_s64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s64_s64index, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64index_s64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_s64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_s64_s64index, svint64_t, int16_t, svint64_t, + svst1h_scatter_s64index_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1h_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_s64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_s64_u64index, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64index_s64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_s64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_s64_u64index, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64index_s64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_s64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_s64_u64index, svint64_t, int16_t, svuint64_t, + svst1h_scatter_u64index_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1h_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u32.c new file mode 100644 index 00000000000..c90a92e42d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u32.c @@ -0,0 +1,207 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_scatter_u32: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_u32, svuint32_t, svuint32_t, + svst1h_scatter_u32base_u32 (p0, z1, z0), + svst1h_scatter (p0, z1, z0)) + +/* +** st1h_scatter_x0_u32_offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, x0, z0), + svst1h_scatter_offset (p0, z1, x0, z0)) + +/* +** st1h_scatter_m2_u32_offset: +** mov (x[0-9]+), #?-2 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m2_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, -2, z0), + svst1h_scatter_offset (p0, z1, -2, z0)) + +/* +** st1h_scatter_0_u32_offset: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, 0, z0), + svst1h_scatter_offset (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_u32_offset: +** mov (x[0-9]+), #?5 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, 5, z0), + svst1h_scatter_offset (p0, z1, 5, z0)) + +/* +** st1h_scatter_6_u32_offset: +** st1h z0\.s, p0, \[z1\.s, #6\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_6_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, 6, z0), + svst1h_scatter_offset (p0, z1, 6, z0)) + +/* +** st1h_scatter_62_u32_offset: +** st1h z0\.s, p0, \[z1\.s, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_62_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, 62, z0), + svst1h_scatter_offset (p0, z1, 62, z0)) + +/* +** st1h_scatter_64_u32_offset: +** mov (x[0-9]+), #?64 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_64_u32_offset, svuint32_t, svuint32_t, + svst1h_scatter_u32base_offset_u32 (p0, z1, 64, z0), + svst1h_scatter_offset (p0, z1, 64, z0)) + +/* +** st1h_scatter_x0_u32_index: +** lsl (x[0-9]+), x0, #?1 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, x0, z0), + svst1h_scatter_index (p0, z1, x0, z0)) + +/* +** st1h_scatter_m1_u32_index: +** mov (x[0-9]+), #?-2 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m1_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, -1, z0), + svst1h_scatter_index (p0, z1, -1, z0)) + +/* +** st1h_scatter_0_u32_index: +** st1h z0\.s, p0, \[z1\.s\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, 0, z0), + svst1h_scatter_index (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_u32_index: +** st1h z0\.s, p0, \[z1\.s, #10\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, 5, z0), + svst1h_scatter_index (p0, z1, 5, z0)) + +/* +** st1h_scatter_31_u32_index: +** st1h z0\.s, p0, \[z1\.s, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_31_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, 31, z0), + svst1h_scatter_index (p0, z1, 31, z0)) + +/* +** st1h_scatter_32_u32_index: +** mov (x[0-9]+), #?64 +** st1h z0\.s, p0, \[\1, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_32_u32_index, svuint32_t, svuint32_t, + svst1h_scatter_u32base_index_u32 (p0, z1, 32, z0), + svst1h_scatter_index (p0, z1, 32, z0)) + +/* +** st1h_scatter_x0_u32_s32offset: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u32_s32offset, svuint32_t, uint16_t, svint32_t, + svst1h_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_u32_s32offset: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u32_s32offset, svuint32_t, uint16_t, svint32_t, + svst1h_scatter_s32offset_u32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_u32_u32offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + svst1h_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_u32_u32offset: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u32_u32offset, svuint32_t, uint16_t, svuint32_t, + svst1h_scatter_u32offset_u32 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_u32_s32index: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u32_s32index, svuint32_t, uint16_t, svint32_t, + svst1h_scatter_s32index_u32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_u32_s32index: +** st1h z0\.s, p0, \[x0, z1\.s, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u32_s32index, svuint32_t, uint16_t, svint32_t, + svst1h_scatter_s32index_u32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_x0_u32_u32index: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u32_u32index, svuint32_t, uint16_t, svuint32_t, + svst1h_scatter_u32index_u32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_u32_u32index: +** st1h z0\.s, p0, \[x0, z1\.s, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u32_u32index, svuint32_t, uint16_t, svuint32_t, + svst1h_scatter_u32index_u32 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u64.c new file mode 100644 index 00000000000..41816a367f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_scatter_u64.c @@ -0,0 +1,243 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_scatter_u64: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_u64, svuint64_t, svuint64_t, + svst1h_scatter_u64base_u64 (p0, z1, z0), + svst1h_scatter (p0, z1, z0)) + +/* +** st1h_scatter_x0_u64_offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, x0, z0), + svst1h_scatter_offset (p0, z1, x0, z0)) + +/* +** st1h_scatter_m2_u64_offset: +** mov (x[0-9]+), #?-2 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m2_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, -2, z0), + svst1h_scatter_offset (p0, z1, -2, z0)) + +/* +** st1h_scatter_0_u64_offset: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, 0, z0), + svst1h_scatter_offset (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_u64_offset: +** mov (x[0-9]+), #?5 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, 5, z0), + svst1h_scatter_offset (p0, z1, 5, z0)) + +/* +** st1h_scatter_6_u64_offset: +** st1h z0\.d, p0, \[z1\.d, #6\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_6_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, 6, z0), + svst1h_scatter_offset (p0, z1, 6, z0)) + +/* +** st1h_scatter_62_u64_offset: +** st1h z0\.d, p0, \[z1\.d, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_62_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, 62, z0), + svst1h_scatter_offset (p0, z1, 62, z0)) + +/* +** st1h_scatter_64_u64_offset: +** mov (x[0-9]+), #?64 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_64_u64_offset, svuint64_t, svuint64_t, + svst1h_scatter_u64base_offset_u64 (p0, z1, 64, z0), + svst1h_scatter_offset (p0, z1, 64, z0)) + +/* +** st1h_scatter_x0_u64_index: +** lsl (x[0-9]+), x0, #?1 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_x0_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, x0, z0), + svst1h_scatter_index (p0, z1, x0, z0)) + +/* +** st1h_scatter_m1_u64_index: +** mov (x[0-9]+), #?-2 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_m1_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, -1, z0), + svst1h_scatter_index (p0, z1, -1, z0)) + +/* +** st1h_scatter_0_u64_index: +** st1h z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_0_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, 0, z0), + svst1h_scatter_index (p0, z1, 0, z0)) + +/* +** st1h_scatter_5_u64_index: +** st1h z0\.d, p0, \[z1\.d, #10\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_5_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, 5, z0), + svst1h_scatter_index (p0, z1, 5, z0)) + +/* +** st1h_scatter_31_u64_index: +** st1h z0\.d, p0, \[z1\.d, #62\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_31_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, 31, z0), + svst1h_scatter_index (p0, z1, 31, z0)) + +/* +** st1h_scatter_32_u64_index: +** mov (x[0-9]+), #?64 +** st1h z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1h_scatter_32_u64_index, svuint64_t, svuint64_t, + svst1h_scatter_u64base_index_u64 (p0, z1, 32, z0), + svst1h_scatter_index (p0, z1, 32, z0)) + +/* +** st1h_scatter_x0_u64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u64_s64offset, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_u64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u64_s64offset, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_u64_s64offset: +** st1h z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_u64_s64offset, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1h_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_u64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_u64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1h_scatter_offset (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_u64_u64offset: +** st1h z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_u64_u64offset, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1h_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_u64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u64_s64index, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64index_u64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_u64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u64_s64index, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64index_u64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_u64_s64index: +** st1h z0\.d, p0, \[x0, z1\.d, sxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_u64_s64index, svuint64_t, uint16_t, svint64_t, + svst1h_scatter_s64index_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1h_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1h_scatter_x0_u64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_x0_u64_u64index, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64index_u64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_u64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, lsl 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_u64_u64index, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64index_u64 (p0, x0, z1, z0), + svst1h_scatter_index (p0, x0, z1, z0)) + +/* +** st1h_scatter_ext_u64_u64index: +** st1h z0\.d, p0, \[x0, z1\.d, uxtw 1\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1h_scatter_ext_u64_u64index, svuint64_t, uint16_t, svuint64_t, + svst1h_scatter_u64index_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1h_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u32.c new file mode 100644 index 00000000000..c0502094fe7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_u32_base: +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u32_base, svuint32_t, uint16_t, + svst1h_u32 (p0, x0, z0), + svst1h (p0, x0, z0)) + +/* +** st1h_u32_index: +** st1h z0\.s, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1h_u32_index, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 + x1, z0), + svst1h (p0, x0 + x1, z0)) + +/* +** st1h_u32_1: +** st1h z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_u32_1, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 + svcntw (), z0), + svst1h (p0, x0 + svcntw (), z0)) + +/* +** st1h_u32_7: +** st1h z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_u32_7, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 + svcntw () * 7, z0), + svst1h (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_u32_8: +** incb x0, all, mul #4 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u32_8, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 + svcntw () * 8, z0), + svst1h (p0, x0 + svcntw () * 8, z0)) + +/* +** st1h_u32_m1: +** st1h z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_u32_m1, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 - svcntw (), z0), + svst1h (p0, x0 - svcntw (), z0)) + +/* +** st1h_u32_m8: +** st1h z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_u32_m8, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 - svcntw () * 8, z0), + svst1h (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_u32_m9: +** dech x0, all, mul #9 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u32_m9, svuint32_t, uint16_t, + svst1h_u32 (p0, x0 - svcntw () * 9, z0), + svst1h (p0, x0 - svcntw () * 9, z0)) + +/* +** st1h_vnum_u32_0: +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_0, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, 0, z0), + svst1h_vnum (p0, x0, 0, z0)) + +/* +** st1h_vnum_u32_1: +** st1h z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_1, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, 1, z0), + svst1h_vnum (p0, x0, 1, z0)) + +/* +** st1h_vnum_u32_7: +** st1h z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_7, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, 7, z0), + svst1h_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_u32_8: +** incb x0, all, mul #4 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_8, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, 8, z0), + svst1h_vnum (p0, x0, 8, z0)) + +/* +** st1h_vnum_u32_m1: +** st1h z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_m1, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, -1, z0), + svst1h_vnum (p0, x0, -1, z0)) + +/* +** st1h_vnum_u32_m8: +** st1h z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_m8, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, -8, z0), + svst1h_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_u32_m9: +** dech x0, all, mul #9 +** st1h z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_m9, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, -9, z0), + svst1h_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1h_vnum_u32_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (st1h_vnum_u32_x1, svuint32_t, uint16_t, + svst1h_vnum_u32 (p0, x0, x1, z0), + svst1h_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u64.c new file mode 100644 index 00000000000..4fea5913593 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1h_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1h_u64_base: +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u64_base, svuint64_t, uint16_t, + svst1h_u64 (p0, x0, z0), + svst1h (p0, x0, z0)) + +/* +** st1h_u64_index: +** st1h z0\.d, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st1h_u64_index, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 + x1, z0), + svst1h (p0, x0 + x1, z0)) + +/* +** st1h_u64_1: +** st1h z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_u64_1, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 + svcntd (), z0), + svst1h (p0, x0 + svcntd (), z0)) + +/* +** st1h_u64_7: +** st1h z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_u64_7, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 + svcntd () * 7, z0), + svst1h (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_u64_8: +** incb x0, all, mul #2 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u64_8, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 + svcntd () * 8, z0), + svst1h (p0, x0 + svcntd () * 8, z0)) + +/* +** st1h_u64_m1: +** st1h z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_u64_m1, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 - svcntd (), z0), + svst1h (p0, x0 - svcntd (), z0)) + +/* +** st1h_u64_m8: +** st1h z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_u64_m8, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 - svcntd () * 8, z0), + svst1h (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_u64_m9: +** decw x0, all, mul #9 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_u64_m9, svuint64_t, uint16_t, + svst1h_u64 (p0, x0 - svcntd () * 9, z0), + svst1h (p0, x0 - svcntd () * 9, z0)) + +/* +** st1h_vnum_u64_0: +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_0, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, 0, z0), + svst1h_vnum (p0, x0, 0, z0)) + +/* +** st1h_vnum_u64_1: +** st1h z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_1, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, 1, z0), + svst1h_vnum (p0, x0, 1, z0)) + +/* +** st1h_vnum_u64_7: +** st1h z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_7, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, 7, z0), + svst1h_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_u64_8: +** incb x0, all, mul #2 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_8, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, 8, z0), + svst1h_vnum (p0, x0, 8, z0)) + +/* +** st1h_vnum_u64_m1: +** st1h z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_m1, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, -1, z0), + svst1h_vnum (p0, x0, -1, z0)) + +/* +** st1h_vnum_u64_m8: +** st1h z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_m8, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, -8, z0), + svst1h_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1h_vnum_u64_m9: +** decw x0, all, mul #9 +** st1h z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_m9, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, -9, z0), + svst1h_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1h_vnum_u64_x1: +** cntw (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1h z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1h_vnum_u64_x1, svuint64_t, uint16_t, + svst1h_vnum_u64 (p0, x0, x1, z0), + svst1h_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_s64.c new file mode 100644 index 00000000000..86861d86c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1w_s64_base: +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_s64_base, svint64_t, int32_t, + svst1w_s64 (p0, x0, z0), + svst1w (p0, x0, z0)) + +/* +** st1w_s64_index: +** st1w z0\.d, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st1w_s64_index, svint64_t, int32_t, + svst1w_s64 (p0, x0 + x1, z0), + svst1w (p0, x0 + x1, z0)) + +/* +** st1w_s64_1: +** st1w z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1w_s64_1, svint64_t, int32_t, + svst1w_s64 (p0, x0 + svcntd (), z0), + svst1w (p0, x0 + svcntd (), z0)) + +/* +** st1w_s64_7: +** st1w z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1w_s64_7, svint64_t, int32_t, + svst1w_s64 (p0, x0 + svcntd () * 7, z0), + svst1w (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_s64_8: +** incb x0, all, mul #4 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_s64_8, svint64_t, int32_t, + svst1w_s64 (p0, x0 + svcntd () * 8, z0), + svst1w (p0, x0 + svcntd () * 8, z0)) + +/* +** st1w_s64_m1: +** st1w z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1w_s64_m1, svint64_t, int32_t, + svst1w_s64 (p0, x0 - svcntd (), z0), + svst1w (p0, x0 - svcntd (), z0)) + +/* +** st1w_s64_m8: +** st1w z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1w_s64_m8, svint64_t, int32_t, + svst1w_s64 (p0, x0 - svcntd () * 8, z0), + svst1w (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_s64_m9: +** dech x0, all, mul #9 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_s64_m9, svint64_t, int32_t, + svst1w_s64 (p0, x0 - svcntd () * 9, z0), + svst1w (p0, x0 - svcntd () * 9, z0)) + +/* +** st1w_vnum_s64_0: +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_0, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, 0, z0), + svst1w_vnum (p0, x0, 0, z0)) + +/* +** st1w_vnum_s64_1: +** st1w z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_1, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, 1, z0), + svst1w_vnum (p0, x0, 1, z0)) + +/* +** st1w_vnum_s64_7: +** st1w z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_7, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, 7, z0), + svst1w_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_vnum_s64_8: +** incb x0, all, mul #4 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_8, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, 8, z0), + svst1w_vnum (p0, x0, 8, z0)) + +/* +** st1w_vnum_s64_m1: +** st1w z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_m1, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, -1, z0), + svst1w_vnum (p0, x0, -1, z0)) + +/* +** st1w_vnum_s64_m8: +** st1w z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_m8, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, -8, z0), + svst1w_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_vnum_s64_m9: +** dech x0, all, mul #9 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_m9, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, -9, z0), + svst1w_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1w_vnum_s64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1w z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1w_vnum_s64_x1, svint64_t, int32_t, + svst1w_vnum_s64 (p0, x0, x1, z0), + svst1w_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_s64.c new file mode 100644 index 00000000000..bcf23581f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_s64.c @@ -0,0 +1,263 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1w_scatter_s64: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_s64, svint64_t, svuint64_t, + svst1w_scatter_u64base_s64 (p0, z1, z0), + svst1w_scatter (p0, z1, z0)) + +/* +** st1w_scatter_x0_s64_offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_x0_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, x0, z0), + svst1w_scatter_offset (p0, z1, x0, z0)) + +/* +** st1w_scatter_m4_s64_offset: +** mov (x[0-9]+), #?-4 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_m4_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, -4, z0), + svst1w_scatter_offset (p0, z1, -4, z0)) + +/* +** st1w_scatter_0_s64_offset: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_0_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 0, z0), + svst1w_scatter_offset (p0, z1, 0, z0)) + +/* +** st1w_scatter_5_s64_offset: +** mov (x[0-9]+), #?5 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_5_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 5, z0), + svst1w_scatter_offset (p0, z1, 5, z0)) + +/* +** st1w_scatter_6_s64_offset: +** mov (x[0-9]+), #?6 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_6_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 6, z0), + svst1w_scatter_offset (p0, z1, 6, z0)) + +/* +** st1w_scatter_7_s64_offset: +** mov (x[0-9]+), #?7 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_7_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 7, z0), + svst1w_scatter_offset (p0, z1, 7, z0)) + +/* +** st1w_scatter_8_s64_offset: +** st1w z0\.d, p0, \[z1\.d, #8\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_8_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 8, z0), + svst1w_scatter_offset (p0, z1, 8, z0)) + +/* +** st1w_scatter_124_s64_offset: +** st1w z0\.d, p0, \[z1\.d, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_124_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 124, z0), + svst1w_scatter_offset (p0, z1, 124, z0)) + +/* +** st1w_scatter_128_s64_offset: +** mov (x[0-9]+), #?128 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_128_s64_offset, svint64_t, svuint64_t, + svst1w_scatter_u64base_offset_s64 (p0, z1, 128, z0), + svst1w_scatter_offset (p0, z1, 128, z0)) + +/* +** st1w_scatter_x0_s64_index: +** lsl (x[0-9]+), x0, #?2 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_x0_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, x0, z0), + svst1w_scatter_index (p0, z1, x0, z0)) + +/* +** st1w_scatter_m1_s64_index: +** mov (x[0-9]+), #?-4 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_m1_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, -1, z0), + svst1w_scatter_index (p0, z1, -1, z0)) + +/* +** st1w_scatter_0_s64_index: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_0_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, 0, z0), + svst1w_scatter_index (p0, z1, 0, z0)) + +/* +** st1w_scatter_5_s64_index: +** st1w z0\.d, p0, \[z1\.d, #20\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_5_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, 5, z0), + svst1w_scatter_index (p0, z1, 5, z0)) + +/* +** st1w_scatter_31_s64_index: +** st1w z0\.d, p0, \[z1\.d, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_31_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, 31, z0), + svst1w_scatter_index (p0, z1, 31, z0)) + +/* +** st1w_scatter_32_s64_index: +** mov (x[0-9]+), #?128 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_32_s64_index, svint64_t, svuint64_t, + svst1w_scatter_u64base_index_s64 (p0, z1, 32, z0), + svst1w_scatter_index (p0, z1, 32, z0)) + +/* +** st1w_scatter_x0_s64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_s64_s64offset, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_s64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_s64_s64offset, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64offset_s64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_s64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_s64_s64offset, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64offset_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1w_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_s64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_s64_u64offset, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_s64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_s64_u64offset, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64offset_s64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_s64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_s64_u64offset, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64offset_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1w_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_s64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_s64_s64index, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64index_s64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_s64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_s64_s64index, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64index_s64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_s64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_s64_s64index, svint64_t, int32_t, svint64_t, + svst1w_scatter_s64index_s64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1w_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_s64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_s64_u64index, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64index_s64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_s64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_s64_u64index, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64index_s64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_s64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_s64_u64index, svint64_t, int32_t, svuint64_t, + svst1w_scatter_u64index_s64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1w_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_u64.c new file mode 100644 index 00000000000..defee0a542e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_scatter_u64.c @@ -0,0 +1,263 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1w_scatter_u64: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_u64, svuint64_t, svuint64_t, + svst1w_scatter_u64base_u64 (p0, z1, z0), + svst1w_scatter (p0, z1, z0)) + +/* +** st1w_scatter_x0_u64_offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_x0_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, x0, z0), + svst1w_scatter_offset (p0, z1, x0, z0)) + +/* +** st1w_scatter_m4_u64_offset: +** mov (x[0-9]+), #?-4 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_m4_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, -4, z0), + svst1w_scatter_offset (p0, z1, -4, z0)) + +/* +** st1w_scatter_0_u64_offset: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_0_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 0, z0), + svst1w_scatter_offset (p0, z1, 0, z0)) + +/* +** st1w_scatter_5_u64_offset: +** mov (x[0-9]+), #?5 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_5_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 5, z0), + svst1w_scatter_offset (p0, z1, 5, z0)) + +/* +** st1w_scatter_6_u64_offset: +** mov (x[0-9]+), #?6 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_6_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 6, z0), + svst1w_scatter_offset (p0, z1, 6, z0)) + +/* +** st1w_scatter_7_u64_offset: +** mov (x[0-9]+), #?7 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_7_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 7, z0), + svst1w_scatter_offset (p0, z1, 7, z0)) + +/* +** st1w_scatter_8_u64_offset: +** st1w z0\.d, p0, \[z1\.d, #8\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_8_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 8, z0), + svst1w_scatter_offset (p0, z1, 8, z0)) + +/* +** st1w_scatter_124_u64_offset: +** st1w z0\.d, p0, \[z1\.d, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_124_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 124, z0), + svst1w_scatter_offset (p0, z1, 124, z0)) + +/* +** st1w_scatter_128_u64_offset: +** mov (x[0-9]+), #?128 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_128_u64_offset, svuint64_t, svuint64_t, + svst1w_scatter_u64base_offset_u64 (p0, z1, 128, z0), + svst1w_scatter_offset (p0, z1, 128, z0)) + +/* +** st1w_scatter_x0_u64_index: +** lsl (x[0-9]+), x0, #?2 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_x0_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, x0, z0), + svst1w_scatter_index (p0, z1, x0, z0)) + +/* +** st1w_scatter_m1_u64_index: +** mov (x[0-9]+), #?-4 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_m1_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, -1, z0), + svst1w_scatter_index (p0, z1, -1, z0)) + +/* +** st1w_scatter_0_u64_index: +** st1w z0\.d, p0, \[z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_0_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, 0, z0), + svst1w_scatter_index (p0, z1, 0, z0)) + +/* +** st1w_scatter_5_u64_index: +** st1w z0\.d, p0, \[z1\.d, #20\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_5_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, 5, z0), + svst1w_scatter_index (p0, z1, 5, z0)) + +/* +** st1w_scatter_31_u64_index: +** st1w z0\.d, p0, \[z1\.d, #124\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_31_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, 31, z0), + svst1w_scatter_index (p0, z1, 31, z0)) + +/* +** st1w_scatter_32_u64_index: +** mov (x[0-9]+), #?128 +** st1w z0\.d, p0, \[\1, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_ZS (st1w_scatter_32_u64_index, svuint64_t, svuint64_t, + svst1w_scatter_u64base_index_u64 (p0, z1, 32, z0), + svst1w_scatter_index (p0, z1, 32, z0)) + +/* +** st1w_scatter_x0_u64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_u64_s64offset, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_u64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_u64_s64offset, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64offset_u64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_u64_s64offset: +** st1w z0\.d, p0, \[x0, z1\.d, sxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_u64_s64offset, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64offset_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1w_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_u64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_u64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64offset_u64 (p0, x0, z1, z0), + svst1w_scatter_offset (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_u64_u64offset: +** st1w z0\.d, p0, \[x0, z1\.d, uxtw\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_u64_u64offset, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64offset_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1w_scatter_offset (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_u64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_u64_s64index, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64index_u64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_u64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_u64_s64index, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64index_u64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_u64_s64index: +** st1w z0\.d, p0, \[x0, z1\.d, sxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_u64_s64index, svuint64_t, uint32_t, svint64_t, + svst1w_scatter_s64index_u64 (p0, x0, svextw_s64_x (p0, z1), z0), + svst1w_scatter_index (p0, x0, svextw_x (p0, z1), z0)) + +/* +** st1w_scatter_x0_u64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_x0_u64_u64index, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64index_u64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_u64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, lsl 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_u64_u64index, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64index_u64 (p0, x0, z1, z0), + svst1w_scatter_index (p0, x0, z1, z0)) + +/* +** st1w_scatter_ext_u64_u64index: +** st1w z0\.d, p0, \[x0, z1\.d, uxtw 2\] +** ret +*/ +TEST_STORE_SCATTER_SZ (st1w_scatter_ext_u64_u64index, svuint64_t, uint32_t, svuint64_t, + svst1w_scatter_u64index_u64 (p0, x0, svextw_u64_x (p0, z1), z0), + svst1w_scatter_index (p0, x0, svextw_x (p0, z1), z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_u64.c new file mode 100644 index 00000000000..8f89e953227 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st1w_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st1w_u64_base: +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_u64_base, svuint64_t, uint32_t, + svst1w_u64 (p0, x0, z0), + svst1w (p0, x0, z0)) + +/* +** st1w_u64_index: +** st1w z0\.d, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st1w_u64_index, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 + x1, z0), + svst1w (p0, x0 + x1, z0)) + +/* +** st1w_u64_1: +** st1w z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1w_u64_1, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 + svcntd (), z0), + svst1w (p0, x0 + svcntd (), z0)) + +/* +** st1w_u64_7: +** st1w z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1w_u64_7, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 + svcntd () * 7, z0), + svst1w (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_u64_8: +** incb x0, all, mul #4 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_u64_8, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 + svcntd () * 8, z0), + svst1w (p0, x0 + svcntd () * 8, z0)) + +/* +** st1w_u64_m1: +** st1w z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1w_u64_m1, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 - svcntd (), z0), + svst1w (p0, x0 - svcntd (), z0)) + +/* +** st1w_u64_m8: +** st1w z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1w_u64_m8, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 - svcntd () * 8, z0), + svst1w (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_u64_m9: +** dech x0, all, mul #9 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_u64_m9, svuint64_t, uint32_t, + svst1w_u64 (p0, x0 - svcntd () * 9, z0), + svst1w (p0, x0 - svcntd () * 9, z0)) + +/* +** st1w_vnum_u64_0: +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_0, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, 0, z0), + svst1w_vnum (p0, x0, 0, z0)) + +/* +** st1w_vnum_u64_1: +** st1w z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_1, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, 1, z0), + svst1w_vnum (p0, x0, 1, z0)) + +/* +** st1w_vnum_u64_7: +** st1w z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_7, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, 7, z0), + svst1w_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_vnum_u64_8: +** incb x0, all, mul #4 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_8, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, 8, z0), + svst1w_vnum (p0, x0, 8, z0)) + +/* +** st1w_vnum_u64_m1: +** st1w z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_m1, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, -1, z0), + svst1w_vnum (p0, x0, -1, z0)) + +/* +** st1w_vnum_u64_m8: +** st1w z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_m8, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, -8, z0), + svst1w_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st1w_vnum_u64_m9: +** dech x0, all, mul #9 +** st1w z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_m9, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, -9, z0), + svst1w_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st1w_vnum_u64_x1: +** cnth (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st1w z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (st1w_vnum_u64_x1, svuint64_t, uint32_t, + svst1w_vnum_u64 (p0, x0, x1, z0), + svst1w_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f16.c new file mode 100644 index 00000000000..cd68a7940e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_f16_base: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f16_base, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_f16_index: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st2_f16_index, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f16_1, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 + svcnth (), z0), + svst2 (p0, x0 + svcnth (), z0)) + +/* +** st2_f16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_f16_2, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 + svcnth () * 2, z0), + svst2 (p0, x0 + svcnth () * 2, z0)) + +/* +** st2_f16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_f16_14, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 + svcnth () * 14, z0), + svst2 (p0, x0 + svcnth () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f16_16, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 + svcnth () * 16, z0), + svst2 (p0, x0 + svcnth () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f16_m1, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 - svcnth (), z0), + svst2 (p0, x0 - svcnth (), z0)) + +/* +** st2_f16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_f16_m2, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 - svcnth () * 2, z0), + svst2 (p0, x0 - svcnth () * 2, z0)) + +/* +** st2_f16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_f16_m16, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 - svcnth () * 16, z0), + svst2 (p0, x0 - svcnth () * 16, z0)) + +/* +** st2_f16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_f16_m18, svfloat16x2_t, float16_t, + svst2_f16 (p0, x0 - svcnth () * 18, z0), + svst2 (p0, x0 - svcnth () * 18, z0)) + +/* +** st2_vnum_f16_0: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f16_0, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f16_1, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_f16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f16_2, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_f16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f16_14, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f16_16, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f16_m1, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_f16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f16_m2, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_f16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f16_m16, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_f16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_f16_m18, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_f16_x1, svfloat16x2_t, float16_t, + svst2_vnum_f16 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f32.c new file mode 100644 index 00000000000..858256c70c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_f32_base: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f32_base, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_f32_index: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st2_f32_index, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f32_1, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 + svcntw (), z0), + svst2 (p0, x0 + svcntw (), z0)) + +/* +** st2_f32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_f32_2, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 + svcntw () * 2, z0), + svst2 (p0, x0 + svcntw () * 2, z0)) + +/* +** st2_f32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_f32_14, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 + svcntw () * 14, z0), + svst2 (p0, x0 + svcntw () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f32_16, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 + svcntw () * 16, z0), + svst2 (p0, x0 + svcntw () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f32_m1, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 - svcntw (), z0), + svst2 (p0, x0 - svcntw (), z0)) + +/* +** st2_f32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_f32_m2, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 - svcntw () * 2, z0), + svst2 (p0, x0 - svcntw () * 2, z0)) + +/* +** st2_f32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_f32_m16, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 - svcntw () * 16, z0), + svst2 (p0, x0 - svcntw () * 16, z0)) + +/* +** st2_f32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_f32_m18, svfloat32x2_t, float32_t, + svst2_f32 (p0, x0 - svcntw () * 18, z0), + svst2 (p0, x0 - svcntw () * 18, z0)) + +/* +** st2_vnum_f32_0: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f32_0, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f32_1, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_f32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f32_2, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_f32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f32_14, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f32_16, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f32_m1, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_f32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f32_m2, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_f32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f32_m16, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_f32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_f32_m18, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_f32_x1, svfloat32x2_t, float32_t, + svst2_vnum_f32 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f64.c new file mode 100644 index 00000000000..115033bb6c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_f64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_f64_base: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f64_base, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_f64_index: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st2_f64_index, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f64_1, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 + svcntd (), z0), + svst2 (p0, x0 + svcntd (), z0)) + +/* +** st2_f64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_f64_2, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 + svcntd () * 2, z0), + svst2 (p0, x0 + svcntd () * 2, z0)) + +/* +** st2_f64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_f64_14, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 + svcntd () * 14, z0), + svst2 (p0, x0 + svcntd () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f64_16, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 + svcntd () * 16, z0), + svst2 (p0, x0 + svcntd () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_f64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_f64_m1, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 - svcntd (), z0), + svst2 (p0, x0 - svcntd (), z0)) + +/* +** st2_f64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_f64_m2, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 - svcntd () * 2, z0), + svst2 (p0, x0 - svcntd () * 2, z0)) + +/* +** st2_f64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_f64_m16, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 - svcntd () * 16, z0), + svst2 (p0, x0 - svcntd () * 16, z0)) + +/* +** st2_f64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_f64_m18, svfloat64x2_t, float64_t, + svst2_f64 (p0, x0 - svcntd () * 18, z0), + svst2 (p0, x0 - svcntd () * 18, z0)) + +/* +** st2_vnum_f64_0: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f64_0, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f64_1, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_f64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f64_2, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_f64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f64_14, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f64_16, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_f64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_f64_m1, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_f64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f64_m2, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_f64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_f64_m16, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_f64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_f64_m18, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_f64_x1, svfloat64x2_t, float64_t, + svst2_vnum_f64 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s16.c new file mode 100644 index 00000000000..4c713512612 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_s16_base: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s16_base, svint16x2_t, int16_t, + svst2_s16 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_s16_index: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st2_s16_index, svint16x2_t, int16_t, + svst2_s16 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s16_1, svint16x2_t, int16_t, + svst2_s16 (p0, x0 + svcnth (), z0), + svst2 (p0, x0 + svcnth (), z0)) + +/* +** st2_s16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_s16_2, svint16x2_t, int16_t, + svst2_s16 (p0, x0 + svcnth () * 2, z0), + svst2 (p0, x0 + svcnth () * 2, z0)) + +/* +** st2_s16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_s16_14, svint16x2_t, int16_t, + svst2_s16 (p0, x0 + svcnth () * 14, z0), + svst2 (p0, x0 + svcnth () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s16_16, svint16x2_t, int16_t, + svst2_s16 (p0, x0 + svcnth () * 16, z0), + svst2 (p0, x0 + svcnth () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s16_m1, svint16x2_t, int16_t, + svst2_s16 (p0, x0 - svcnth (), z0), + svst2 (p0, x0 - svcnth (), z0)) + +/* +** st2_s16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_s16_m2, svint16x2_t, int16_t, + svst2_s16 (p0, x0 - svcnth () * 2, z0), + svst2 (p0, x0 - svcnth () * 2, z0)) + +/* +** st2_s16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_s16_m16, svint16x2_t, int16_t, + svst2_s16 (p0, x0 - svcnth () * 16, z0), + svst2 (p0, x0 - svcnth () * 16, z0)) + +/* +** st2_s16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_s16_m18, svint16x2_t, int16_t, + svst2_s16 (p0, x0 - svcnth () * 18, z0), + svst2 (p0, x0 - svcnth () * 18, z0)) + +/* +** st2_vnum_s16_0: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s16_0, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s16_1, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_s16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s16_2, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_s16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s16_14, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s16_16, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s16_m1, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_s16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s16_m2, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_s16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s16_m16, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_s16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_s16_m18, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_s16_x1, svint16x2_t, int16_t, + svst2_vnum_s16 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s32.c new file mode 100644 index 00000000000..185754a72ce --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_s32_base: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s32_base, svint32x2_t, int32_t, + svst2_s32 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_s32_index: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st2_s32_index, svint32x2_t, int32_t, + svst2_s32 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s32_1, svint32x2_t, int32_t, + svst2_s32 (p0, x0 + svcntw (), z0), + svst2 (p0, x0 + svcntw (), z0)) + +/* +** st2_s32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_s32_2, svint32x2_t, int32_t, + svst2_s32 (p0, x0 + svcntw () * 2, z0), + svst2 (p0, x0 + svcntw () * 2, z0)) + +/* +** st2_s32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_s32_14, svint32x2_t, int32_t, + svst2_s32 (p0, x0 + svcntw () * 14, z0), + svst2 (p0, x0 + svcntw () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s32_16, svint32x2_t, int32_t, + svst2_s32 (p0, x0 + svcntw () * 16, z0), + svst2 (p0, x0 + svcntw () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s32_m1, svint32x2_t, int32_t, + svst2_s32 (p0, x0 - svcntw (), z0), + svst2 (p0, x0 - svcntw (), z0)) + +/* +** st2_s32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_s32_m2, svint32x2_t, int32_t, + svst2_s32 (p0, x0 - svcntw () * 2, z0), + svst2 (p0, x0 - svcntw () * 2, z0)) + +/* +** st2_s32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_s32_m16, svint32x2_t, int32_t, + svst2_s32 (p0, x0 - svcntw () * 16, z0), + svst2 (p0, x0 - svcntw () * 16, z0)) + +/* +** st2_s32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_s32_m18, svint32x2_t, int32_t, + svst2_s32 (p0, x0 - svcntw () * 18, z0), + svst2 (p0, x0 - svcntw () * 18, z0)) + +/* +** st2_vnum_s32_0: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s32_0, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s32_1, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_s32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s32_2, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_s32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s32_14, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s32_16, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s32_m1, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_s32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s32_m2, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_s32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s32_m16, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_s32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_s32_m18, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_s32_x1, svint32x2_t, int32_t, + svst2_vnum_s32 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s64.c new file mode 100644 index 00000000000..790f6ece8e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_s64_base: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s64_base, svint64x2_t, int64_t, + svst2_s64 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_s64_index: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st2_s64_index, svint64x2_t, int64_t, + svst2_s64 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s64_1, svint64x2_t, int64_t, + svst2_s64 (p0, x0 + svcntd (), z0), + svst2 (p0, x0 + svcntd (), z0)) + +/* +** st2_s64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_s64_2, svint64x2_t, int64_t, + svst2_s64 (p0, x0 + svcntd () * 2, z0), + svst2 (p0, x0 + svcntd () * 2, z0)) + +/* +** st2_s64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_s64_14, svint64x2_t, int64_t, + svst2_s64 (p0, x0 + svcntd () * 14, z0), + svst2 (p0, x0 + svcntd () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s64_16, svint64x2_t, int64_t, + svst2_s64 (p0, x0 + svcntd () * 16, z0), + svst2 (p0, x0 + svcntd () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s64_m1, svint64x2_t, int64_t, + svst2_s64 (p0, x0 - svcntd (), z0), + svst2 (p0, x0 - svcntd (), z0)) + +/* +** st2_s64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_s64_m2, svint64x2_t, int64_t, + svst2_s64 (p0, x0 - svcntd () * 2, z0), + svst2 (p0, x0 - svcntd () * 2, z0)) + +/* +** st2_s64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_s64_m16, svint64x2_t, int64_t, + svst2_s64 (p0, x0 - svcntd () * 16, z0), + svst2 (p0, x0 - svcntd () * 16, z0)) + +/* +** st2_s64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_s64_m18, svint64x2_t, int64_t, + svst2_s64 (p0, x0 - svcntd () * 18, z0), + svst2 (p0, x0 - svcntd () * 18, z0)) + +/* +** st2_vnum_s64_0: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s64_0, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s64_1, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_s64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s64_2, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_s64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s64_14, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s64_16, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s64_m1, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_s64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s64_m2, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_s64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s64_m16, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_s64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_s64_m18, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_s64_x1, svint64x2_t, int64_t, + svst2_vnum_s64 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s8.c new file mode 100644 index 00000000000..726258f6732 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_s8.c @@ -0,0 +1,204 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_s8_base: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s8_base, svint8x2_t, int8_t, + svst2_s8 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_s8_index: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st2_s8_index, svint8x2_t, int8_t, + svst2_s8 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s8_1: +** incb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s8_1, svint8x2_t, int8_t, + svst2_s8 (p0, x0 + svcntb (), z0), + svst2 (p0, x0 + svcntb (), z0)) + +/* +** st2_s8_2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_s8_2, svint8x2_t, int8_t, + svst2_s8 (p0, x0 + svcntb () * 2, z0), + svst2 (p0, x0 + svcntb () * 2, z0)) + +/* +** st2_s8_14: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_s8_14, svint8x2_t, int8_t, + svst2_s8 (p0, x0 + svcntb () * 14, z0), + svst2 (p0, x0 + svcntb () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s8_16: +** incb x0, all, mul #16 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s8_16, svint8x2_t, int8_t, + svst2_s8 (p0, x0 + svcntb () * 16, z0), + svst2 (p0, x0 + svcntb () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_s8_m1: +** decb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_s8_m1, svint8x2_t, int8_t, + svst2_s8 (p0, x0 - svcntb (), z0), + svst2 (p0, x0 - svcntb (), z0)) + +/* +** st2_s8_m2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_s8_m2, svint8x2_t, int8_t, + svst2_s8 (p0, x0 - svcntb () * 2, z0), + svst2 (p0, x0 - svcntb () * 2, z0)) + +/* +** st2_s8_m16: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_s8_m16, svint8x2_t, int8_t, + svst2_s8 (p0, x0 - svcntb () * 16, z0), + svst2 (p0, x0 - svcntb () * 16, z0)) + +/* +** st2_s8_m18: +** addvl (x[0-9]+), x0, #-18 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_s8_m18, svint8x2_t, int8_t, + svst2_s8 (p0, x0 - svcntb () * 18, z0), + svst2 (p0, x0 - svcntb () * 18, z0)) + +/* +** st2_vnum_s8_0: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s8_0, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s8_1: +** incb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s8_1, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_s8_2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s8_2, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_s8_14: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s8_14, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s8_16: +** incb x0, all, mul #16 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s8_16, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_s8_m1: +** decb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_s8_m1, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_s8_m2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s8_m2, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_s8_m16: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_s8_m16, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_s8_m18: +** addvl (x[0-9]+), x0, #-18 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_s8_m18, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* +** st2_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st2_vnum_s8_x1, svint8x2_t, int8_t, + svst2_vnum_s8 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u16.c new file mode 100644 index 00000000000..736adc5f757 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u16.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_u16_base: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u16_base, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_u16_index: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st2_u16_index, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u16_1, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 + svcnth (), z0), + svst2 (p0, x0 + svcnth (), z0)) + +/* +** st2_u16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_u16_2, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 + svcnth () * 2, z0), + svst2 (p0, x0 + svcnth () * 2, z0)) + +/* +** st2_u16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_u16_14, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 + svcnth () * 14, z0), + svst2 (p0, x0 + svcnth () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u16_16, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 + svcnth () * 16, z0), + svst2 (p0, x0 + svcnth () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u16_m1, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 - svcnth (), z0), + svst2 (p0, x0 - svcnth (), z0)) + +/* +** st2_u16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_u16_m2, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 - svcnth () * 2, z0), + svst2 (p0, x0 - svcnth () * 2, z0)) + +/* +** st2_u16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_u16_m16, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 - svcnth () * 16, z0), + svst2 (p0, x0 - svcnth () * 16, z0)) + +/* +** st2_u16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_u16_m18, svuint16x2_t, uint16_t, + svst2_u16 (p0, x0 - svcnth () * 18, z0), + svst2 (p0, x0 - svcnth () * 18, z0)) + +/* +** st2_vnum_u16_0: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u16_0, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u16_1: +** incb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u16_1, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_u16_2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u16_2, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_u16_14: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u16_14, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u16_16: +** incb x0, all, mul #16 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u16_16, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u16_m1: +** decb x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u16_m1, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_u16_m2: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u16_m2, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_u16_m16: +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u16_m16, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_u16_m18: +** addvl (x[0-9]+), x0, #-18 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_u16_m18, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2h {z0\.h(?: - |, )z1\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_u16_x1, svuint16x2_t, uint16_t, + svst2_vnum_u16 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u32.c new file mode 100644 index 00000000000..53a2f1c6beb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u32.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_u32_base: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u32_base, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_u32_index: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st2_u32_index, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u32_1, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 + svcntw (), z0), + svst2 (p0, x0 + svcntw (), z0)) + +/* +** st2_u32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_u32_2, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 + svcntw () * 2, z0), + svst2 (p0, x0 + svcntw () * 2, z0)) + +/* +** st2_u32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_u32_14, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 + svcntw () * 14, z0), + svst2 (p0, x0 + svcntw () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u32_16, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 + svcntw () * 16, z0), + svst2 (p0, x0 + svcntw () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u32_m1, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 - svcntw (), z0), + svst2 (p0, x0 - svcntw (), z0)) + +/* +** st2_u32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_u32_m2, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 - svcntw () * 2, z0), + svst2 (p0, x0 - svcntw () * 2, z0)) + +/* +** st2_u32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_u32_m16, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 - svcntw () * 16, z0), + svst2 (p0, x0 - svcntw () * 16, z0)) + +/* +** st2_u32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_u32_m18, svuint32x2_t, uint32_t, + svst2_u32 (p0, x0 - svcntw () * 18, z0), + svst2 (p0, x0 - svcntw () * 18, z0)) + +/* +** st2_vnum_u32_0: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u32_0, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u32_1: +** incb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u32_1, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_u32_2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u32_2, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_u32_14: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u32_14, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u32_16: +** incb x0, all, mul #16 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u32_16, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u32_m1: +** decb x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u32_m1, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_u32_m2: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u32_m2, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_u32_m16: +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u32_m16, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_u32_m18: +** addvl (x[0-9]+), x0, #-18 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_u32_m18, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2w {z0\.s(?: - |, )z1\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_u32_x1, svuint32x2_t, uint32_t, + svst2_vnum_u32 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u64.c new file mode 100644 index 00000000000..09a81891d54 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u64.c @@ -0,0 +1,200 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_u64_base: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u64_base, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_u64_index: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st2_u64_index, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u64_1, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 + svcntd (), z0), + svst2 (p0, x0 + svcntd (), z0)) + +/* +** st2_u64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_u64_2, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 + svcntd () * 2, z0), + svst2 (p0, x0 + svcntd () * 2, z0)) + +/* +** st2_u64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_u64_14, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 + svcntd () * 14, z0), + svst2 (p0, x0 + svcntd () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u64_16, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 + svcntd () * 16, z0), + svst2 (p0, x0 + svcntd () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u64_m1, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 - svcntd (), z0), + svst2 (p0, x0 - svcntd (), z0)) + +/* +** st2_u64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_u64_m2, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 - svcntd () * 2, z0), + svst2 (p0, x0 - svcntd () * 2, z0)) + +/* +** st2_u64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_u64_m16, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 - svcntd () * 16, z0), + svst2 (p0, x0 - svcntd () * 16, z0)) + +/* +** st2_u64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_u64_m18, svuint64x2_t, uint64_t, + svst2_u64 (p0, x0 - svcntd () * 18, z0), + svst2 (p0, x0 - svcntd () * 18, z0)) + +/* +** st2_vnum_u64_0: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u64_0, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u64_1: +** incb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u64_1, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_u64_2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u64_2, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_u64_14: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u64_14, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u64_16: +** incb x0, all, mul #16 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u64_16, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u64_m1: +** decb x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u64_m1, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_u64_m2: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u64_m2, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_u64_m16: +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u64_m16, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_u64_m18: +** addvl (x[0-9]+), x0, #-18 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_u64_m18, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st2_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st2d {z0\.d(?: - |, )z1\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st2_vnum_u64_x1, svuint64x2_t, uint64_t, + svst2_vnum_u64 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u8.c new file mode 100644 index 00000000000..4f15869f6da --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st2_u8.c @@ -0,0 +1,204 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st2_u8_base: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u8_base, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0, z0), + svst2 (p0, x0, z0)) + +/* +** st2_u8_index: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st2_u8_index, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 + x1, z0), + svst2 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u8_1: +** incb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u8_1, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 + svcntb (), z0), + svst2 (p0, x0 + svcntb (), z0)) + +/* +** st2_u8_2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_u8_2, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 + svcntb () * 2, z0), + svst2 (p0, x0 + svcntb () * 2, z0)) + +/* +** st2_u8_14: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_u8_14, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 + svcntb () * 14, z0), + svst2 (p0, x0 + svcntb () * 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u8_16: +** incb x0, all, mul #16 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u8_16, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 + svcntb () * 16, z0), + svst2 (p0, x0 + svcntb () * 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_u8_m1: +** decb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_u8_m1, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 - svcntb (), z0), + svst2 (p0, x0 - svcntb (), z0)) + +/* +** st2_u8_m2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_u8_m2, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 - svcntb () * 2, z0), + svst2 (p0, x0 - svcntb () * 2, z0)) + +/* +** st2_u8_m16: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_u8_m16, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 - svcntb () * 16, z0), + svst2 (p0, x0 - svcntb () * 16, z0)) + +/* +** st2_u8_m18: +** addvl (x[0-9]+), x0, #-18 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_u8_m18, svuint8x2_t, uint8_t, + svst2_u8 (p0, x0 - svcntb () * 18, z0), + svst2 (p0, x0 - svcntb () * 18, z0)) + +/* +** st2_vnum_u8_0: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u8_0, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, 0, z0), + svst2_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u8_1: +** incb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u8_1, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, 1, z0), + svst2_vnum (p0, x0, 1, z0)) + +/* +** st2_vnum_u8_2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u8_2, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, 2, z0), + svst2_vnum (p0, x0, 2, z0)) + +/* +** st2_vnum_u8_14: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #14, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u8_14, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, 14, z0), + svst2_vnum (p0, x0, 14, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u8_16: +** incb x0, all, mul #16 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u8_16, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, 16, z0), + svst2_vnum (p0, x0, 16, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st2_vnum_u8_m1: +** decb x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st2_vnum_u8_m1, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, -1, z0), + svst2_vnum (p0, x0, -1, z0)) + +/* +** st2_vnum_u8_m2: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-2, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u8_m2, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, -2, z0), + svst2_vnum (p0, x0, -2, z0)) + +/* +** st2_vnum_u8_m16: +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, #-16, mul vl\] +** ret +*/ +TEST_STORE (st2_vnum_u8_m16, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, -16, z0), + svst2_vnum (p0, x0, -16, z0)) + +/* +** st2_vnum_u8_m18: +** addvl (x[0-9]+), x0, #-18 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st2_vnum_u8_m18, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, -18, z0), + svst2_vnum (p0, x0, -18, z0)) + +/* +** st2_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st2b {z0\.b(?: - |, )z1\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st2_vnum_u8_x1, svuint8x2_t, uint8_t, + svst2_vnum_u8 (p0, x0, x1, z0), + svst2_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f16.c new file mode 100644 index 00000000000..1cf4a6908ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_f16_base: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f16_base, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_f16_index: +** st3h {z0\.h - z2\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st3_f16_index, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f16_1, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + svcnth (), z0), + svst3 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f16_2, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + svcnth () * 2, z0), + svst3 (p0, x0 + svcnth () * 2, z0)) + +/* +** st3_f16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_f16_3, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + svcnth () * 3, z0), + svst3 (p0, x0 + svcnth () * 3, z0)) + +/* +** st3_f16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_f16_21, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + svcnth () * 21, z0), + svst3 (p0, x0 + svcnth () * 21, z0)) + +/* +** st3_f16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f16_24, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 + svcnth () * 24, z0), + svst3 (p0, x0 + svcnth () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f16_m1, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 - svcnth (), z0), + svst3 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f16_m2, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 - svcnth () * 2, z0), + svst3 (p0, x0 - svcnth () * 2, z0)) + +/* +** st3_f16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_f16_m3, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 - svcnth () * 3, z0), + svst3 (p0, x0 - svcnth () * 3, z0)) + +/* +** st3_f16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_f16_m24, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 - svcnth () * 24, z0), + svst3 (p0, x0 - svcnth () * 24, z0)) + +/* +** st3_f16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f16_m27, svfloat16x3_t, float16_t, + svst3_f16 (p0, x0 - svcnth () * 27, z0), + svst3 (p0, x0 - svcnth () * 27, z0)) + +/* +** st3_vnum_f16_0: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f16_0, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f16_1, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f16_2, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_f16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f16_3, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_f16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f16_21, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_f16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f16_24, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f16_m1, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f16_m2, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_f16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f16_m3, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_f16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f16_m24, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_f16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f16_m27, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3h {z0\.h - z2\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_f16_x1, svfloat16x3_t, float16_t, + svst3_vnum_f16 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f32.c new file mode 100644 index 00000000000..4d12f81e589 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_f32_base: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f32_base, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_f32_index: +** st3w {z0\.s - z2\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st3_f32_index, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f32_1, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + svcntw (), z0), + svst3 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f32_2, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + svcntw () * 2, z0), + svst3 (p0, x0 + svcntw () * 2, z0)) + +/* +** st3_f32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_f32_3, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + svcntw () * 3, z0), + svst3 (p0, x0 + svcntw () * 3, z0)) + +/* +** st3_f32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_f32_21, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + svcntw () * 21, z0), + svst3 (p0, x0 + svcntw () * 21, z0)) + +/* +** st3_f32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f32_24, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 + svcntw () * 24, z0), + svst3 (p0, x0 + svcntw () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f32_m1, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 - svcntw (), z0), + svst3 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f32_m2, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 - svcntw () * 2, z0), + svst3 (p0, x0 - svcntw () * 2, z0)) + +/* +** st3_f32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_f32_m3, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 - svcntw () * 3, z0), + svst3 (p0, x0 - svcntw () * 3, z0)) + +/* +** st3_f32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_f32_m24, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 - svcntw () * 24, z0), + svst3 (p0, x0 - svcntw () * 24, z0)) + +/* +** st3_f32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f32_m27, svfloat32x3_t, float32_t, + svst3_f32 (p0, x0 - svcntw () * 27, z0), + svst3 (p0, x0 - svcntw () * 27, z0)) + +/* +** st3_vnum_f32_0: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f32_0, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f32_1, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f32_2, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_f32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f32_3, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_f32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f32_21, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_f32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f32_24, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f32_m1, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f32_m2, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_f32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f32_m3, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_f32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f32_m24, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_f32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f32_m27, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3w {z0\.s - z2\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_f32_x1, svfloat32x3_t, float32_t, + svst3_vnum_f32 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f64.c new file mode 100644 index 00000000000..b1485bd4575 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_f64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_f64_base: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f64_base, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_f64_index: +** st3d {z0\.d - z2\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st3_f64_index, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f64_1, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + svcntd (), z0), + svst3 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f64_2, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + svcntd () * 2, z0), + svst3 (p0, x0 + svcntd () * 2, z0)) + +/* +** st3_f64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_f64_3, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + svcntd () * 3, z0), + svst3 (p0, x0 + svcntd () * 3, z0)) + +/* +** st3_f64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_f64_21, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + svcntd () * 21, z0), + svst3 (p0, x0 + svcntd () * 21, z0)) + +/* +** st3_f64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f64_24, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 + svcntd () * 24, z0), + svst3 (p0, x0 + svcntd () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f64_m1, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 - svcntd (), z0), + svst3 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_f64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_f64_m2, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 - svcntd () * 2, z0), + svst3 (p0, x0 - svcntd () * 2, z0)) + +/* +** st3_f64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_f64_m3, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 - svcntd () * 3, z0), + svst3 (p0, x0 - svcntd () * 3, z0)) + +/* +** st3_f64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_f64_m24, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 - svcntd () * 24, z0), + svst3 (p0, x0 - svcntd () * 24, z0)) + +/* +** st3_f64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_f64_m27, svfloat64x3_t, float64_t, + svst3_f64 (p0, x0 - svcntd () * 27, z0), + svst3 (p0, x0 - svcntd () * 27, z0)) + +/* +** st3_vnum_f64_0: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f64_0, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f64_1, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f64_2, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_f64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f64_3, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_f64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f64_21, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_f64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f64_24, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f64_m1, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_f64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_f64_m2, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_f64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f64_m3, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_f64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_f64_m24, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_f64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_f64_m27, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3d {z0\.d - z2\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_f64_x1, svfloat64x3_t, float64_t, + svst3_vnum_f64 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s16.c new file mode 100644 index 00000000000..623be007006 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_s16_base: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s16_base, svint16x3_t, int16_t, + svst3_s16 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_s16_index: +** st3h {z0\.h - z2\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st3_s16_index, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s16_1, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + svcnth (), z0), + svst3 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s16_2, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + svcnth () * 2, z0), + svst3 (p0, x0 + svcnth () * 2, z0)) + +/* +** st3_s16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_s16_3, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + svcnth () * 3, z0), + svst3 (p0, x0 + svcnth () * 3, z0)) + +/* +** st3_s16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_s16_21, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + svcnth () * 21, z0), + svst3 (p0, x0 + svcnth () * 21, z0)) + +/* +** st3_s16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s16_24, svint16x3_t, int16_t, + svst3_s16 (p0, x0 + svcnth () * 24, z0), + svst3 (p0, x0 + svcnth () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s16_m1, svint16x3_t, int16_t, + svst3_s16 (p0, x0 - svcnth (), z0), + svst3 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s16_m2, svint16x3_t, int16_t, + svst3_s16 (p0, x0 - svcnth () * 2, z0), + svst3 (p0, x0 - svcnth () * 2, z0)) + +/* +** st3_s16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_s16_m3, svint16x3_t, int16_t, + svst3_s16 (p0, x0 - svcnth () * 3, z0), + svst3 (p0, x0 - svcnth () * 3, z0)) + +/* +** st3_s16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_s16_m24, svint16x3_t, int16_t, + svst3_s16 (p0, x0 - svcnth () * 24, z0), + svst3 (p0, x0 - svcnth () * 24, z0)) + +/* +** st3_s16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s16_m27, svint16x3_t, int16_t, + svst3_s16 (p0, x0 - svcnth () * 27, z0), + svst3 (p0, x0 - svcnth () * 27, z0)) + +/* +** st3_vnum_s16_0: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s16_0, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s16_1, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s16_2, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_s16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s16_3, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_s16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s16_21, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_s16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s16_24, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s16_m1, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s16_m2, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_s16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s16_m3, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_s16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s16_m24, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_s16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s16_m27, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3h {z0\.h - z2\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_s16_x1, svint16x3_t, int16_t, + svst3_vnum_s16 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s32.c new file mode 100644 index 00000000000..04431d1311b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_s32_base: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s32_base, svint32x3_t, int32_t, + svst3_s32 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_s32_index: +** st3w {z0\.s - z2\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st3_s32_index, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s32_1, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + svcntw (), z0), + svst3 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s32_2, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + svcntw () * 2, z0), + svst3 (p0, x0 + svcntw () * 2, z0)) + +/* +** st3_s32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_s32_3, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + svcntw () * 3, z0), + svst3 (p0, x0 + svcntw () * 3, z0)) + +/* +** st3_s32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_s32_21, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + svcntw () * 21, z0), + svst3 (p0, x0 + svcntw () * 21, z0)) + +/* +** st3_s32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s32_24, svint32x3_t, int32_t, + svst3_s32 (p0, x0 + svcntw () * 24, z0), + svst3 (p0, x0 + svcntw () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s32_m1, svint32x3_t, int32_t, + svst3_s32 (p0, x0 - svcntw (), z0), + svst3 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s32_m2, svint32x3_t, int32_t, + svst3_s32 (p0, x0 - svcntw () * 2, z0), + svst3 (p0, x0 - svcntw () * 2, z0)) + +/* +** st3_s32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_s32_m3, svint32x3_t, int32_t, + svst3_s32 (p0, x0 - svcntw () * 3, z0), + svst3 (p0, x0 - svcntw () * 3, z0)) + +/* +** st3_s32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_s32_m24, svint32x3_t, int32_t, + svst3_s32 (p0, x0 - svcntw () * 24, z0), + svst3 (p0, x0 - svcntw () * 24, z0)) + +/* +** st3_s32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s32_m27, svint32x3_t, int32_t, + svst3_s32 (p0, x0 - svcntw () * 27, z0), + svst3 (p0, x0 - svcntw () * 27, z0)) + +/* +** st3_vnum_s32_0: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s32_0, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s32_1, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s32_2, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_s32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s32_3, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_s32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s32_21, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_s32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s32_24, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s32_m1, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s32_m2, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_s32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s32_m3, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_s32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s32_m24, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_s32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s32_m27, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3w {z0\.s - z2\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_s32_x1, svint32x3_t, int32_t, + svst3_vnum_s32 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s64.c new file mode 100644 index 00000000000..094bf73a0ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_s64_base: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s64_base, svint64x3_t, int64_t, + svst3_s64 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_s64_index: +** st3d {z0\.d - z2\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st3_s64_index, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s64_1, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + svcntd (), z0), + svst3 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s64_2, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + svcntd () * 2, z0), + svst3 (p0, x0 + svcntd () * 2, z0)) + +/* +** st3_s64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_s64_3, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + svcntd () * 3, z0), + svst3 (p0, x0 + svcntd () * 3, z0)) + +/* +** st3_s64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_s64_21, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + svcntd () * 21, z0), + svst3 (p0, x0 + svcntd () * 21, z0)) + +/* +** st3_s64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s64_24, svint64x3_t, int64_t, + svst3_s64 (p0, x0 + svcntd () * 24, z0), + svst3 (p0, x0 + svcntd () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s64_m1, svint64x3_t, int64_t, + svst3_s64 (p0, x0 - svcntd (), z0), + svst3 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s64_m2, svint64x3_t, int64_t, + svst3_s64 (p0, x0 - svcntd () * 2, z0), + svst3 (p0, x0 - svcntd () * 2, z0)) + +/* +** st3_s64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_s64_m3, svint64x3_t, int64_t, + svst3_s64 (p0, x0 - svcntd () * 3, z0), + svst3 (p0, x0 - svcntd () * 3, z0)) + +/* +** st3_s64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_s64_m24, svint64x3_t, int64_t, + svst3_s64 (p0, x0 - svcntd () * 24, z0), + svst3 (p0, x0 - svcntd () * 24, z0)) + +/* +** st3_s64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s64_m27, svint64x3_t, int64_t, + svst3_s64 (p0, x0 - svcntd () * 27, z0), + svst3 (p0, x0 - svcntd () * 27, z0)) + +/* +** st3_vnum_s64_0: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s64_0, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s64_1, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s64_2, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_s64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s64_3, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_s64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s64_21, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_s64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s64_24, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s64_m1, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s64_m2, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_s64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s64_m3, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_s64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s64_m24, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_s64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s64_m27, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3d {z0\.d - z2\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_s64_x1, svint64x3_t, int64_t, + svst3_vnum_s64 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s8.c new file mode 100644 index 00000000000..8709d6bbb51 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_s8.c @@ -0,0 +1,246 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_s8_base: +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s8_base, svint8x3_t, int8_t, + svst3_s8 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_s8_index: +** st3b {z0\.b - z2\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st3_s8_index, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s8_1: +** incb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s8_1, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + svcntb (), z0), + svst3 (p0, x0 + svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s8_2: +** incb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s8_2, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + svcntb () * 2, z0), + svst3 (p0, x0 + svcntb () * 2, z0)) + +/* +** st3_s8_3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_s8_3, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + svcntb () * 3, z0), + svst3 (p0, x0 + svcntb () * 3, z0)) + +/* +** st3_s8_21: +** st3b {z0\.b - z2\.b}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_s8_21, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + svcntb () * 21, z0), + svst3 (p0, x0 + svcntb () * 21, z0)) + +/* +** st3_s8_24: +** addvl (x[0-9]+), x0, #24 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s8_24, svint8x3_t, int8_t, + svst3_s8 (p0, x0 + svcntb () * 24, z0), + svst3 (p0, x0 + svcntb () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s8_m1: +** decb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s8_m1, svint8x3_t, int8_t, + svst3_s8 (p0, x0 - svcntb (), z0), + svst3 (p0, x0 - svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_s8_m2: +** decb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_s8_m2, svint8x3_t, int8_t, + svst3_s8 (p0, x0 - svcntb () * 2, z0), + svst3 (p0, x0 - svcntb () * 2, z0)) + +/* +** st3_s8_m3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_s8_m3, svint8x3_t, int8_t, + svst3_s8 (p0, x0 - svcntb () * 3, z0), + svst3 (p0, x0 - svcntb () * 3, z0)) + +/* +** st3_s8_m24: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_s8_m24, svint8x3_t, int8_t, + svst3_s8 (p0, x0 - svcntb () * 24, z0), + svst3 (p0, x0 - svcntb () * 24, z0)) + +/* +** st3_s8_m27: +** addvl (x[0-9]+), x0, #-27 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_s8_m27, svint8x3_t, int8_t, + svst3_s8 (p0, x0 - svcntb () * 27, z0), + svst3 (p0, x0 - svcntb () * 27, z0)) + +/* +** st3_vnum_s8_0: +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s8_0, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s8_1: +** incb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s8_1, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s8_2: +** incb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s8_2, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_s8_3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s8_3, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_s8_21: +** st3b {z0\.b - z2\.b}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s8_21, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_s8_24: +** addvl (x[0-9]+), x0, #24 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s8_24, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s8_m1: +** decb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s8_m1, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_s8_m2: +** decb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_s8_m2, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_s8_m3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s8_m3, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_s8_m24: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_s8_m24, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_s8_m27: +** addvl (x[0-9]+), x0, #-27 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_s8_m27, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* +** st3_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st3b {z0\.b - z2\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st3b {z0\.b - z2\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st3_vnum_s8_x1, svint8x3_t, int8_t, + svst3_vnum_s8 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u16.c new file mode 100644 index 00000000000..e464d083e69 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u16.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_u16_base: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u16_base, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_u16_index: +** st3h {z0\.h - z2\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st3_u16_index, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u16_1, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + svcnth (), z0), + svst3 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u16_2, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + svcnth () * 2, z0), + svst3 (p0, x0 + svcnth () * 2, z0)) + +/* +** st3_u16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_u16_3, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + svcnth () * 3, z0), + svst3 (p0, x0 + svcnth () * 3, z0)) + +/* +** st3_u16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_u16_21, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + svcnth () * 21, z0), + svst3 (p0, x0 + svcnth () * 21, z0)) + +/* +** st3_u16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u16_24, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 + svcnth () * 24, z0), + svst3 (p0, x0 + svcnth () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u16_m1, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 - svcnth (), z0), + svst3 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u16_m2, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 - svcnth () * 2, z0), + svst3 (p0, x0 - svcnth () * 2, z0)) + +/* +** st3_u16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_u16_m3, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 - svcnth () * 3, z0), + svst3 (p0, x0 - svcnth () * 3, z0)) + +/* +** st3_u16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_u16_m24, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 - svcnth () * 24, z0), + svst3 (p0, x0 - svcnth () * 24, z0)) + +/* +** st3_u16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u16_m27, svuint16x3_t, uint16_t, + svst3_u16 (p0, x0 - svcnth () * 27, z0), + svst3 (p0, x0 - svcnth () * 27, z0)) + +/* +** st3_vnum_u16_0: +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u16_0, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u16_1: +** incb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u16_1, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u16_2: +** incb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u16_2, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_u16_3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u16_3, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_u16_21: +** st3h {z0\.h - z2\.h}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u16_21, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_u16_24: +** addvl (x[0-9]+), x0, #24 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u16_24, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u16_m1: +** decb x0 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u16_m1, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u16_m2: +** decb x0, all, mul #2 +** st3h {z0\.h - z2\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u16_m2, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_u16_m3: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u16_m3, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_u16_m24: +** st3h {z0\.h - z2\.h}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u16_m24, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_u16_m27: +** addvl (x[0-9]+), x0, #-27 +** st3h {z0\.h - z2\.h}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u16_m27, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3h {z0\.h - z2\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_u16_x1, svuint16x3_t, uint16_t, + svst3_vnum_u16 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u32.c new file mode 100644 index 00000000000..7b9a19a6a4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u32.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_u32_base: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u32_base, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_u32_index: +** st3w {z0\.s - z2\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st3_u32_index, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u32_1, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + svcntw (), z0), + svst3 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u32_2, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + svcntw () * 2, z0), + svst3 (p0, x0 + svcntw () * 2, z0)) + +/* +** st3_u32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_u32_3, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + svcntw () * 3, z0), + svst3 (p0, x0 + svcntw () * 3, z0)) + +/* +** st3_u32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_u32_21, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + svcntw () * 21, z0), + svst3 (p0, x0 + svcntw () * 21, z0)) + +/* +** st3_u32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u32_24, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 + svcntw () * 24, z0), + svst3 (p0, x0 + svcntw () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u32_m1, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 - svcntw (), z0), + svst3 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u32_m2, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 - svcntw () * 2, z0), + svst3 (p0, x0 - svcntw () * 2, z0)) + +/* +** st3_u32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_u32_m3, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 - svcntw () * 3, z0), + svst3 (p0, x0 - svcntw () * 3, z0)) + +/* +** st3_u32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_u32_m24, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 - svcntw () * 24, z0), + svst3 (p0, x0 - svcntw () * 24, z0)) + +/* +** st3_u32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u32_m27, svuint32x3_t, uint32_t, + svst3_u32 (p0, x0 - svcntw () * 27, z0), + svst3 (p0, x0 - svcntw () * 27, z0)) + +/* +** st3_vnum_u32_0: +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u32_0, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u32_1: +** incb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u32_1, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u32_2: +** incb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u32_2, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_u32_3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u32_3, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_u32_21: +** st3w {z0\.s - z2\.s}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u32_21, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_u32_24: +** addvl (x[0-9]+), x0, #24 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u32_24, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u32_m1: +** decb x0 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u32_m1, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u32_m2: +** decb x0, all, mul #2 +** st3w {z0\.s - z2\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u32_m2, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_u32_m3: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u32_m3, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_u32_m24: +** st3w {z0\.s - z2\.s}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u32_m24, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_u32_m27: +** addvl (x[0-9]+), x0, #-27 +** st3w {z0\.s - z2\.s}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u32_m27, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3w {z0\.s - z2\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_u32_x1, svuint32x3_t, uint32_t, + svst3_vnum_u32 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u64.c new file mode 100644 index 00000000000..f3dc4352a23 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u64.c @@ -0,0 +1,242 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_u64_base: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u64_base, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_u64_index: +** st3d {z0\.d - z2\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st3_u64_index, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u64_1, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + svcntd (), z0), + svst3 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u64_2, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + svcntd () * 2, z0), + svst3 (p0, x0 + svcntd () * 2, z0)) + +/* +** st3_u64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_u64_3, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + svcntd () * 3, z0), + svst3 (p0, x0 + svcntd () * 3, z0)) + +/* +** st3_u64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_u64_21, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + svcntd () * 21, z0), + svst3 (p0, x0 + svcntd () * 21, z0)) + +/* +** st3_u64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u64_24, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 + svcntd () * 24, z0), + svst3 (p0, x0 + svcntd () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u64_m1, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 - svcntd (), z0), + svst3 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u64_m2, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 - svcntd () * 2, z0), + svst3 (p0, x0 - svcntd () * 2, z0)) + +/* +** st3_u64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_u64_m3, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 - svcntd () * 3, z0), + svst3 (p0, x0 - svcntd () * 3, z0)) + +/* +** st3_u64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_u64_m24, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 - svcntd () * 24, z0), + svst3 (p0, x0 - svcntd () * 24, z0)) + +/* +** st3_u64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u64_m27, svuint64x3_t, uint64_t, + svst3_u64 (p0, x0 - svcntd () * 27, z0), + svst3 (p0, x0 - svcntd () * 27, z0)) + +/* +** st3_vnum_u64_0: +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u64_0, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u64_1: +** incb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u64_1, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u64_2: +** incb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u64_2, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_u64_3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u64_3, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_u64_21: +** st3d {z0\.d - z2\.d}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u64_21, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_u64_24: +** addvl (x[0-9]+), x0, #24 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u64_24, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u64_m1: +** decb x0 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u64_m1, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u64_m2: +** decb x0, all, mul #2 +** st3d {z0\.d - z2\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u64_m2, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_u64_m3: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u64_m3, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_u64_m24: +** st3d {z0\.d - z2\.d}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u64_m24, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_u64_m27: +** addvl (x[0-9]+), x0, #-27 +** st3d {z0\.d - z2\.d}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u64_m27, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st3_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st3d {z0\.d - z2\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st3_vnum_u64_x1, svuint64x3_t, uint64_t, + svst3_vnum_u64 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u8.c new file mode 100644 index 00000000000..9d7dc62bf24 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st3_u8.c @@ -0,0 +1,246 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st3_u8_base: +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u8_base, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0, z0), + svst3 (p0, x0, z0)) + +/* +** st3_u8_index: +** st3b {z0\.b - z2\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st3_u8_index, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + x1, z0), + svst3 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u8_1: +** incb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u8_1, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + svcntb (), z0), + svst3 (p0, x0 + svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u8_2: +** incb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u8_2, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + svcntb () * 2, z0), + svst3 (p0, x0 + svcntb () * 2, z0)) + +/* +** st3_u8_3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_u8_3, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + svcntb () * 3, z0), + svst3 (p0, x0 + svcntb () * 3, z0)) + +/* +** st3_u8_21: +** st3b {z0\.b - z2\.b}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_u8_21, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + svcntb () * 21, z0), + svst3 (p0, x0 + svcntb () * 21, z0)) + +/* +** st3_u8_24: +** addvl (x[0-9]+), x0, #24 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u8_24, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 + svcntb () * 24, z0), + svst3 (p0, x0 + svcntb () * 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u8_m1: +** decb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u8_m1, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 - svcntb (), z0), + svst3 (p0, x0 - svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_u8_m2: +** decb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_u8_m2, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 - svcntb () * 2, z0), + svst3 (p0, x0 - svcntb () * 2, z0)) + +/* +** st3_u8_m3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_u8_m3, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 - svcntb () * 3, z0), + svst3 (p0, x0 - svcntb () * 3, z0)) + +/* +** st3_u8_m24: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_u8_m24, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 - svcntb () * 24, z0), + svst3 (p0, x0 - svcntb () * 24, z0)) + +/* +** st3_u8_m27: +** addvl (x[0-9]+), x0, #-27 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_u8_m27, svuint8x3_t, uint8_t, + svst3_u8 (p0, x0 - svcntb () * 27, z0), + svst3 (p0, x0 - svcntb () * 27, z0)) + +/* +** st3_vnum_u8_0: +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u8_0, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 0, z0), + svst3_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u8_1: +** incb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u8_1, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 1, z0), + svst3_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u8_2: +** incb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u8_2, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 2, z0), + svst3_vnum (p0, x0, 2, z0)) + +/* +** st3_vnum_u8_3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u8_3, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 3, z0), + svst3_vnum (p0, x0, 3, z0)) + +/* +** st3_vnum_u8_21: +** st3b {z0\.b - z2\.b}, p0, \[x0, #21, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u8_21, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 21, z0), + svst3_vnum (p0, x0, 21, z0)) + +/* +** st3_vnum_u8_24: +** addvl (x[0-9]+), x0, #24 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u8_24, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, 24, z0), + svst3_vnum (p0, x0, 24, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u8_m1: +** decb x0 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u8_m1, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, -1, z0), + svst3_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st3_vnum_u8_m2: +** decb x0, all, mul #2 +** st3b {z0\.b - z2\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st3_vnum_u8_m2, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, -2, z0), + svst3_vnum (p0, x0, -2, z0)) + +/* +** st3_vnum_u8_m3: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-3, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u8_m3, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, -3, z0), + svst3_vnum (p0, x0, -3, z0)) + +/* +** st3_vnum_u8_m24: +** st3b {z0\.b - z2\.b}, p0, \[x0, #-24, mul vl\] +** ret +*/ +TEST_STORE (st3_vnum_u8_m24, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, -24, z0), + svst3_vnum (p0, x0, -24, z0)) + +/* +** st3_vnum_u8_m27: +** addvl (x[0-9]+), x0, #-27 +** st3b {z0\.b - z2\.b}, p0, \[\1\] +** ret +*/ +TEST_STORE (st3_vnum_u8_m27, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, -27, z0), + svst3_vnum (p0, x0, -27, z0)) + +/* +** st3_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st3b {z0\.b - z2\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st3b {z0\.b - z2\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st3_vnum_u8_x1, svuint8x3_t, uint8_t, + svst3_vnum_u8 (p0, x0, x1, z0), + svst3_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f16.c new file mode 100644 index 00000000000..177b531340f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_f16_base: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_base, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_f16_index: +** st4h {z0\.h - z3\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st4_f16_index, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_1, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth (), z0), + svst4 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_2, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth () * 2, z0), + svst4 (p0, x0 + svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_3, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth () * 3, z0), + svst4 (p0, x0 + svcnth () * 3, z0)) + +/* +** st4_f16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_f16_4, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth () * 4, z0), + svst4 (p0, x0 + svcnth () * 4, z0)) + +/* +** st4_f16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_f16_28, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth () * 28, z0), + svst4 (p0, x0 + svcnth () * 28, z0)) + +/* +** st4_f16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f16_32, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 + svcnth () * 32, z0), + svst4 (p0, x0 + svcnth () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_m1, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth (), z0), + svst4 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_m2, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth () * 2, z0), + svst4 (p0, x0 - svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f16_m3, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth () * 3, z0), + svst4 (p0, x0 - svcnth () * 3, z0)) + +/* +** st4_f16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_f16_m4, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth () * 4, z0), + svst4 (p0, x0 - svcnth () * 4, z0)) + +/* +** st4_f16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_f16_m32, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth () * 32, z0), + svst4 (p0, x0 - svcnth () * 32, z0)) + +/* +** st4_f16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f16_m36, svfloat16x4_t, float16_t, + svst4_f16 (p0, x0 - svcnth () * 36, z0), + svst4 (p0, x0 - svcnth () * 36, z0)) + +/* +** st4_vnum_f16_0: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_0, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_1, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_2, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_3, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_f16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f16_4, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_f16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f16_28, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_f16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f16_32, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m1, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m2, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m3, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_f16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m4, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_f16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m32, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_f16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f16_m36, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4h {z0\.h - z3\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_f16_x1, svfloat16x4_t, float16_t, + svst4_vnum_f16 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f32.c new file mode 100644 index 00000000000..316d2141e81 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_f32_base: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_base, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_f32_index: +** st4w {z0\.s - z3\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st4_f32_index, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_1, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw (), z0), + svst4 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_2, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw () * 2, z0), + svst4 (p0, x0 + svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_3, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw () * 3, z0), + svst4 (p0, x0 + svcntw () * 3, z0)) + +/* +** st4_f32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_f32_4, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw () * 4, z0), + svst4 (p0, x0 + svcntw () * 4, z0)) + +/* +** st4_f32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_f32_28, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw () * 28, z0), + svst4 (p0, x0 + svcntw () * 28, z0)) + +/* +** st4_f32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f32_32, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 + svcntw () * 32, z0), + svst4 (p0, x0 + svcntw () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_m1, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw (), z0), + svst4 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_m2, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw () * 2, z0), + svst4 (p0, x0 - svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f32_m3, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw () * 3, z0), + svst4 (p0, x0 - svcntw () * 3, z0)) + +/* +** st4_f32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_f32_m4, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw () * 4, z0), + svst4 (p0, x0 - svcntw () * 4, z0)) + +/* +** st4_f32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_f32_m32, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw () * 32, z0), + svst4 (p0, x0 - svcntw () * 32, z0)) + +/* +** st4_f32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f32_m36, svfloat32x4_t, float32_t, + svst4_f32 (p0, x0 - svcntw () * 36, z0), + svst4 (p0, x0 - svcntw () * 36, z0)) + +/* +** st4_vnum_f32_0: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_0, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_1, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_2, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_3, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_f32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f32_4, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_f32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f32_28, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_f32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f32_32, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m1, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m2, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m3, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_f32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m4, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_f32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m32, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_f32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f32_m36, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4w {z0\.s - z3\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_f32_x1, svfloat32x4_t, float32_t, + svst4_vnum_f32 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f64.c new file mode 100644 index 00000000000..7c572088ec3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_f64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_f64_base: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_base, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_f64_index: +** st4d {z0\.d - z3\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st4_f64_index, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_1, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd (), z0), + svst4 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_2, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd () * 2, z0), + svst4 (p0, x0 + svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_3, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd () * 3, z0), + svst4 (p0, x0 + svcntd () * 3, z0)) + +/* +** st4_f64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_f64_4, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd () * 4, z0), + svst4 (p0, x0 + svcntd () * 4, z0)) + +/* +** st4_f64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_f64_28, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd () * 28, z0), + svst4 (p0, x0 + svcntd () * 28, z0)) + +/* +** st4_f64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f64_32, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 + svcntd () * 32, z0), + svst4 (p0, x0 + svcntd () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_m1, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd (), z0), + svst4 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_m2, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd () * 2, z0), + svst4 (p0, x0 - svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_f64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_f64_m3, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd () * 3, z0), + svst4 (p0, x0 - svcntd () * 3, z0)) + +/* +** st4_f64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_f64_m4, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd () * 4, z0), + svst4 (p0, x0 - svcntd () * 4, z0)) + +/* +** st4_f64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_f64_m32, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd () * 32, z0), + svst4 (p0, x0 - svcntd () * 32, z0)) + +/* +** st4_f64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_f64_m36, svfloat64x4_t, float64_t, + svst4_f64 (p0, x0 - svcntd () * 36, z0), + svst4 (p0, x0 - svcntd () * 36, z0)) + +/* +** st4_vnum_f64_0: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_0, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_1, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_2, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_3, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_f64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f64_4, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_f64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f64_28, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_f64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f64_32, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m1, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m2, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_f64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m3, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_f64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m4, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_f64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m32, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_f64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_f64_m36, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4d {z0\.d - z3\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_f64_x1, svfloat64x4_t, float64_t, + svst4_vnum_f64 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s16.c new file mode 100644 index 00000000000..6c7ca347dde --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_s16_base: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_base, svint16x4_t, int16_t, + svst4_s16 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_s16_index: +** st4h {z0\.h - z3\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st4_s16_index, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_1, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth (), z0), + svst4 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_2, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth () * 2, z0), + svst4 (p0, x0 + svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_3, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth () * 3, z0), + svst4 (p0, x0 + svcnth () * 3, z0)) + +/* +** st4_s16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_s16_4, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth () * 4, z0), + svst4 (p0, x0 + svcnth () * 4, z0)) + +/* +** st4_s16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_s16_28, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth () * 28, z0), + svst4 (p0, x0 + svcnth () * 28, z0)) + +/* +** st4_s16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s16_32, svint16x4_t, int16_t, + svst4_s16 (p0, x0 + svcnth () * 32, z0), + svst4 (p0, x0 + svcnth () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_m1, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth (), z0), + svst4 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_m2, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth () * 2, z0), + svst4 (p0, x0 - svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s16_m3, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth () * 3, z0), + svst4 (p0, x0 - svcnth () * 3, z0)) + +/* +** st4_s16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_s16_m4, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth () * 4, z0), + svst4 (p0, x0 - svcnth () * 4, z0)) + +/* +** st4_s16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_s16_m32, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth () * 32, z0), + svst4 (p0, x0 - svcnth () * 32, z0)) + +/* +** st4_s16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s16_m36, svint16x4_t, int16_t, + svst4_s16 (p0, x0 - svcnth () * 36, z0), + svst4 (p0, x0 - svcnth () * 36, z0)) + +/* +** st4_vnum_s16_0: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_0, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_1, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_2, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_3, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_s16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s16_4, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_s16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s16_28, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_s16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s16_32, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m1, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m2, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m3, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_s16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m4, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_s16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m32, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_s16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s16_m36, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4h {z0\.h - z3\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_s16_x1, svint16x4_t, int16_t, + svst4_vnum_s16 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s32.c new file mode 100644 index 00000000000..7c37d485c0f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_s32_base: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_base, svint32x4_t, int32_t, + svst4_s32 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_s32_index: +** st4w {z0\.s - z3\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st4_s32_index, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_1, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw (), z0), + svst4 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_2, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw () * 2, z0), + svst4 (p0, x0 + svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_3, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw () * 3, z0), + svst4 (p0, x0 + svcntw () * 3, z0)) + +/* +** st4_s32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_s32_4, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw () * 4, z0), + svst4 (p0, x0 + svcntw () * 4, z0)) + +/* +** st4_s32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_s32_28, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw () * 28, z0), + svst4 (p0, x0 + svcntw () * 28, z0)) + +/* +** st4_s32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s32_32, svint32x4_t, int32_t, + svst4_s32 (p0, x0 + svcntw () * 32, z0), + svst4 (p0, x0 + svcntw () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_m1, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw (), z0), + svst4 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_m2, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw () * 2, z0), + svst4 (p0, x0 - svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s32_m3, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw () * 3, z0), + svst4 (p0, x0 - svcntw () * 3, z0)) + +/* +** st4_s32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_s32_m4, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw () * 4, z0), + svst4 (p0, x0 - svcntw () * 4, z0)) + +/* +** st4_s32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_s32_m32, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw () * 32, z0), + svst4 (p0, x0 - svcntw () * 32, z0)) + +/* +** st4_s32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s32_m36, svint32x4_t, int32_t, + svst4_s32 (p0, x0 - svcntw () * 36, z0), + svst4 (p0, x0 - svcntw () * 36, z0)) + +/* +** st4_vnum_s32_0: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_0, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_1, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_2, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_3, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_s32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s32_4, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_s32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s32_28, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_s32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s32_32, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m1, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m2, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m3, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_s32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m4, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_s32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m32, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_s32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s32_m36, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4w {z0\.s - z3\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_s32_x1, svint32x4_t, int32_t, + svst4_vnum_s32 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s64.c new file mode 100644 index 00000000000..0faf5f244cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_s64_base: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_base, svint64x4_t, int64_t, + svst4_s64 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_s64_index: +** st4d {z0\.d - z3\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st4_s64_index, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_1, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd (), z0), + svst4 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_2, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd () * 2, z0), + svst4 (p0, x0 + svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_3, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd () * 3, z0), + svst4 (p0, x0 + svcntd () * 3, z0)) + +/* +** st4_s64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_s64_4, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd () * 4, z0), + svst4 (p0, x0 + svcntd () * 4, z0)) + +/* +** st4_s64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_s64_28, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd () * 28, z0), + svst4 (p0, x0 + svcntd () * 28, z0)) + +/* +** st4_s64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s64_32, svint64x4_t, int64_t, + svst4_s64 (p0, x0 + svcntd () * 32, z0), + svst4 (p0, x0 + svcntd () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_m1, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd (), z0), + svst4 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_m2, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd () * 2, z0), + svst4 (p0, x0 - svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s64_m3, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd () * 3, z0), + svst4 (p0, x0 - svcntd () * 3, z0)) + +/* +** st4_s64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_s64_m4, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd () * 4, z0), + svst4 (p0, x0 - svcntd () * 4, z0)) + +/* +** st4_s64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_s64_m32, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd () * 32, z0), + svst4 (p0, x0 - svcntd () * 32, z0)) + +/* +** st4_s64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s64_m36, svint64x4_t, int64_t, + svst4_s64 (p0, x0 - svcntd () * 36, z0), + svst4 (p0, x0 - svcntd () * 36, z0)) + +/* +** st4_vnum_s64_0: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_0, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_1, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_2, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_3, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_s64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s64_4, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_s64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s64_28, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_s64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s64_32, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m1, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m2, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m3, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_s64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m4, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_s64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m32, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_s64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s64_m36, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4d {z0\.d - z3\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_s64_x1, svint64x4_t, int64_t, + svst4_vnum_s64 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s8.c new file mode 100644 index 00000000000..3808ab305e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_s8.c @@ -0,0 +1,290 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_s8_base: +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_base, svint8x4_t, int8_t, + svst4_s8 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_s8_index: +** st4b {z0\.b - z3\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st4_s8_index, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_1: +** incb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_1, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb (), z0), + svst4 (p0, x0 + svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_2: +** incb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_2, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb () * 2, z0), + svst4 (p0, x0 + svcntb () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_3: +** incb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_3, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb () * 3, z0), + svst4 (p0, x0 + svcntb () * 3, z0)) + +/* +** st4_s8_4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_s8_4, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb () * 4, z0), + svst4 (p0, x0 + svcntb () * 4, z0)) + +/* +** st4_s8_28: +** st4b {z0\.b - z3\.b}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_s8_28, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb () * 28, z0), + svst4 (p0, x0 + svcntb () * 28, z0)) + +/* +** st4_s8_32: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s8_32, svint8x4_t, int8_t, + svst4_s8 (p0, x0 + svcntb () * 32, z0), + svst4 (p0, x0 + svcntb () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_m1: +** decb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_m1, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb (), z0), + svst4 (p0, x0 - svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_m2: +** decb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_m2, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb () * 2, z0), + svst4 (p0, x0 - svcntb () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_s8_m3: +** decb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_s8_m3, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb () * 3, z0), + svst4 (p0, x0 - svcntb () * 3, z0)) + +/* +** st4_s8_m4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_s8_m4, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb () * 4, z0), + svst4 (p0, x0 - svcntb () * 4, z0)) + +/* +** st4_s8_m32: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_s8_m32, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb () * 32, z0), + svst4 (p0, x0 - svcntb () * 32, z0)) + +/* +** st4_s8_m36: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_s8_m36, svint8x4_t, int8_t, + svst4_s8 (p0, x0 - svcntb () * 36, z0), + svst4 (p0, x0 - svcntb () * 36, z0)) + +/* +** st4_vnum_s8_0: +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_0, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_1: +** incb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_1, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_2: +** incb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_2, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_3: +** incb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_3, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_s8_4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s8_4, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_s8_28: +** st4b {z0\.b - z3\.b}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s8_28, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_s8_32: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s8_32, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_m1: +** decb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m1, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_m2: +** decb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m2, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_s8_m3: +** decb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m3, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_s8_m4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m4, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_s8_m32: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m32, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_s8_m36: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_s8_m36, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* +** st4_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st4b {z0\.b - z3\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st4b {z0\.b - z3\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st4_vnum_s8_x1, svint8x4_t, int8_t, + svst4_vnum_s8 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u16.c new file mode 100644 index 00000000000..f6b8f298f1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u16.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_u16_base: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_base, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_u16_index: +** st4h {z0\.h - z3\.h}, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (st4_u16_index, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_1, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth (), z0), + svst4 (p0, x0 + svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_2, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth () * 2, z0), + svst4 (p0, x0 + svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_3, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth () * 3, z0), + svst4 (p0, x0 + svcnth () * 3, z0)) + +/* +** st4_u16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_u16_4, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth () * 4, z0), + svst4 (p0, x0 + svcnth () * 4, z0)) + +/* +** st4_u16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_u16_28, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth () * 28, z0), + svst4 (p0, x0 + svcnth () * 28, z0)) + +/* +** st4_u16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u16_32, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 + svcnth () * 32, z0), + svst4 (p0, x0 + svcnth () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_m1, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth (), z0), + svst4 (p0, x0 - svcnth (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_m2, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth () * 2, z0), + svst4 (p0, x0 - svcnth () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u16_m3, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth () * 3, z0), + svst4 (p0, x0 - svcnth () * 3, z0)) + +/* +** st4_u16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_u16_m4, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth () * 4, z0), + svst4 (p0, x0 - svcnth () * 4, z0)) + +/* +** st4_u16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_u16_m32, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth () * 32, z0), + svst4 (p0, x0 - svcnth () * 32, z0)) + +/* +** st4_u16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u16_m36, svuint16x4_t, uint16_t, + svst4_u16 (p0, x0 - svcnth () * 36, z0), + svst4 (p0, x0 - svcnth () * 36, z0)) + +/* +** st4_vnum_u16_0: +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_0, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_1: +** incb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_1, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_2: +** incb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_2, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_3: +** incb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_3, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_u16_4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u16_4, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_u16_28: +** st4h {z0\.h - z3\.h}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u16_28, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_u16_32: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u16_32, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_m1: +** decb x0 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m1, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_m2: +** decb x0, all, mul #2 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m2, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u16_m3: +** decb x0, all, mul #3 +** st4h {z0\.h - z3\.h}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m3, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_u16_m4: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m4, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_u16_m32: +** st4h {z0\.h - z3\.h}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m32, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_u16_m36: +** [^{]* +** st4h {z0\.h - z3\.h}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u16_m36, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4h {z0\.h - z3\.h}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_u16_x1, svuint16x4_t, uint16_t, + svst4_vnum_u16 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u32.c new file mode 100644 index 00000000000..85685b6479c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u32.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_u32_base: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_base, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_u32_index: +** st4w {z0\.s - z3\.s}, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (st4_u32_index, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_1, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw (), z0), + svst4 (p0, x0 + svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_2, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw () * 2, z0), + svst4 (p0, x0 + svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_3, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw () * 3, z0), + svst4 (p0, x0 + svcntw () * 3, z0)) + +/* +** st4_u32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_u32_4, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw () * 4, z0), + svst4 (p0, x0 + svcntw () * 4, z0)) + +/* +** st4_u32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_u32_28, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw () * 28, z0), + svst4 (p0, x0 + svcntw () * 28, z0)) + +/* +** st4_u32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u32_32, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 + svcntw () * 32, z0), + svst4 (p0, x0 + svcntw () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_m1, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw (), z0), + svst4 (p0, x0 - svcntw (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_m2, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw () * 2, z0), + svst4 (p0, x0 - svcntw () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u32_m3, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw () * 3, z0), + svst4 (p0, x0 - svcntw () * 3, z0)) + +/* +** st4_u32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_u32_m4, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw () * 4, z0), + svst4 (p0, x0 - svcntw () * 4, z0)) + +/* +** st4_u32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_u32_m32, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw () * 32, z0), + svst4 (p0, x0 - svcntw () * 32, z0)) + +/* +** st4_u32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u32_m36, svuint32x4_t, uint32_t, + svst4_u32 (p0, x0 - svcntw () * 36, z0), + svst4 (p0, x0 - svcntw () * 36, z0)) + +/* +** st4_vnum_u32_0: +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_0, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_1: +** incb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_1, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_2: +** incb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_2, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_3: +** incb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_3, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_u32_4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u32_4, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_u32_28: +** st4w {z0\.s - z3\.s}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u32_28, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_u32_32: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u32_32, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_m1: +** decb x0 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m1, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_m2: +** decb x0, all, mul #2 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m2, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u32_m3: +** decb x0, all, mul #3 +** st4w {z0\.s - z3\.s}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m3, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_u32_m4: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m4, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_u32_m32: +** st4w {z0\.s - z3\.s}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m32, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_u32_m36: +** [^{]* +** st4w {z0\.s - z3\.s}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u32_m36, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4w {z0\.s - z3\.s}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_u32_x1, svuint32x4_t, uint32_t, + svst4_vnum_u32 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u64.c new file mode 100644 index 00000000000..13bec17cfbc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u64.c @@ -0,0 +1,286 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_u64_base: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_base, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_u64_index: +** st4d {z0\.d - z3\.d}, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (st4_u64_index, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_1, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd (), z0), + svst4 (p0, x0 + svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_2, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd () * 2, z0), + svst4 (p0, x0 + svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_3, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd () * 3, z0), + svst4 (p0, x0 + svcntd () * 3, z0)) + +/* +** st4_u64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_u64_4, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd () * 4, z0), + svst4 (p0, x0 + svcntd () * 4, z0)) + +/* +** st4_u64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_u64_28, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd () * 28, z0), + svst4 (p0, x0 + svcntd () * 28, z0)) + +/* +** st4_u64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u64_32, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 + svcntd () * 32, z0), + svst4 (p0, x0 + svcntd () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_m1, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd (), z0), + svst4 (p0, x0 - svcntd (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_m2, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd () * 2, z0), + svst4 (p0, x0 - svcntd () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u64_m3, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd () * 3, z0), + svst4 (p0, x0 - svcntd () * 3, z0)) + +/* +** st4_u64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_u64_m4, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd () * 4, z0), + svst4 (p0, x0 - svcntd () * 4, z0)) + +/* +** st4_u64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_u64_m32, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd () * 32, z0), + svst4 (p0, x0 - svcntd () * 32, z0)) + +/* +** st4_u64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u64_m36, svuint64x4_t, uint64_t, + svst4_u64 (p0, x0 - svcntd () * 36, z0), + svst4 (p0, x0 - svcntd () * 36, z0)) + +/* +** st4_vnum_u64_0: +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_0, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_1: +** incb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_1, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_2: +** incb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_2, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_3: +** incb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_3, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_u64_4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u64_4, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_u64_28: +** st4d {z0\.d - z3\.d}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u64_28, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_u64_32: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u64_32, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_m1: +** decb x0 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m1, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_m2: +** decb x0, all, mul #2 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m2, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u64_m3: +** decb x0, all, mul #3 +** st4d {z0\.d - z3\.d}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m3, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_u64_m4: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m4, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_u64_m32: +** st4d {z0\.d - z3\.d}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m32, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_u64_m36: +** [^{]* +** st4d {z0\.d - z3\.d}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u64_m36, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** st4_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** st4d {z0\.d - z3\.d}, p0, \[\2\] +** ret +*/ +TEST_STORE (st4_vnum_u64_x1, svuint64x4_t, uint64_t, + svst4_vnum_u64 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u8.c new file mode 100644 index 00000000000..e1fc5b6cd1c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/st4_u8.c @@ -0,0 +1,290 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** st4_u8_base: +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_base, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0, z0), + svst4 (p0, x0, z0)) + +/* +** st4_u8_index: +** st4b {z0\.b - z3\.b}, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (st4_u8_index, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + x1, z0), + svst4 (p0, x0 + x1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_1: +** incb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_1, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb (), z0), + svst4 (p0, x0 + svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_2: +** incb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_2, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb () * 2, z0), + svst4 (p0, x0 + svcntb () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_3: +** incb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_3, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb () * 3, z0), + svst4 (p0, x0 + svcntb () * 3, z0)) + +/* +** st4_u8_4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_u8_4, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb () * 4, z0), + svst4 (p0, x0 + svcntb () * 4, z0)) + +/* +** st4_u8_28: +** st4b {z0\.b - z3\.b}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_u8_28, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb () * 28, z0), + svst4 (p0, x0 + svcntb () * 28, z0)) + +/* +** st4_u8_32: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u8_32, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 + svcntb () * 32, z0), + svst4 (p0, x0 + svcntb () * 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_m1: +** decb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_m1, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb (), z0), + svst4 (p0, x0 - svcntb (), z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_m2: +** decb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_m2, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb () * 2, z0), + svst4 (p0, x0 - svcntb () * 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_u8_m3: +** decb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_u8_m3, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb () * 3, z0), + svst4 (p0, x0 - svcntb () * 3, z0)) + +/* +** st4_u8_m4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_u8_m4, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb () * 4, z0), + svst4 (p0, x0 - svcntb () * 4, z0)) + +/* +** st4_u8_m32: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_u8_m32, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb () * 32, z0), + svst4 (p0, x0 - svcntb () * 32, z0)) + +/* +** st4_u8_m36: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_u8_m36, svuint8x4_t, uint8_t, + svst4_u8 (p0, x0 - svcntb () * 36, z0), + svst4 (p0, x0 - svcntb () * 36, z0)) + +/* +** st4_vnum_u8_0: +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_0, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 0, z0), + svst4_vnum (p0, x0, 0, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_1: +** incb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_1, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 1, z0), + svst4_vnum (p0, x0, 1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_2: +** incb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_2, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 2, z0), + svst4_vnum (p0, x0, 2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_3: +** incb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_3, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 3, z0), + svst4_vnum (p0, x0, 3, z0)) + +/* +** st4_vnum_u8_4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u8_4, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 4, z0), + svst4_vnum (p0, x0, 4, z0)) + +/* +** st4_vnum_u8_28: +** st4b {z0\.b - z3\.b}, p0, \[x0, #28, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u8_28, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 28, z0), + svst4_vnum (p0, x0, 28, z0)) + +/* +** st4_vnum_u8_32: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u8_32, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, 32, z0), + svst4_vnum (p0, x0, 32, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_m1: +** decb x0 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m1, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -1, z0), + svst4_vnum (p0, x0, -1, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_m2: +** decb x0, all, mul #2 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m2, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -2, z0), + svst4_vnum (p0, x0, -2, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** st4_vnum_u8_m3: +** decb x0, all, mul #3 +** st4b {z0\.b - z3\.b}, p0, \[x0\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m3, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -3, z0), + svst4_vnum (p0, x0, -3, z0)) + +/* +** st4_vnum_u8_m4: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-4, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m4, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -4, z0), + svst4_vnum (p0, x0, -4, z0)) + +/* +** st4_vnum_u8_m32: +** st4b {z0\.b - z3\.b}, p0, \[x0, #-32, mul vl\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m32, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -32, z0), + svst4_vnum (p0, x0, -32, z0)) + +/* +** st4_vnum_u8_m36: +** [^{]* +** st4b {z0\.b - z3\.b}, p0, \[x[0-9]+\] +** ret +*/ +TEST_STORE (st4_vnum_u8_m36, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, -36, z0), + svst4_vnum (p0, x0, -36, z0)) + +/* +** st4_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** st4b {z0\.b - z3\.b}, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** st4b {z0\.b - z3\.b}, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (st4_vnum_u8_x1, svuint8x4_t, uint8_t, + svst4_vnum_u8 (p0, x0, x1, z0), + svst4_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f16.c new file mode 100644 index 00000000000..4fb75ff36a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_f16_base: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f16_base, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_f16_index: +** stnt1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (stnt1_f16_index, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_f16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f16_1, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 + svcnth (), z0), + svstnt1 (p0, x0 + svcnth (), z0)) + +/* +** stnt1_f16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f16_7, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 + svcnth () * 7, z0), + svstnt1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f16_8, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 + svcnth () * 8, z0), + svstnt1 (p0, x0 + svcnth () * 8, z0)) + +/* +** stnt1_f16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f16_m1, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 - svcnth (), z0), + svstnt1 (p0, x0 - svcnth (), z0)) + +/* +** stnt1_f16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f16_m8, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 - svcnth () * 8, z0), + svstnt1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f16_m9, svfloat16_t, float16_t, + svstnt1_f16 (p0, x0 - svcnth () * 9, z0), + svstnt1 (p0, x0 - svcnth () * 9, z0)) + +/* +** stnt1_vnum_f16_0: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_0, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_f16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_1, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_f16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_7, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_8, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_f16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_m1, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_f16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_m8, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_m9, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_f16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_f16_x1, svfloat16_t, float16_t, + svstnt1_vnum_f16 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f32.c new file mode 100644 index 00000000000..2e17eed92b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_f32_base: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f32_base, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_f32_index: +** stnt1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (stnt1_f32_index, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_f32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f32_1, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 + svcntw (), z0), + svstnt1 (p0, x0 + svcntw (), z0)) + +/* +** stnt1_f32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f32_7, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 + svcntw () * 7, z0), + svstnt1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f32_8, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 + svcntw () * 8, z0), + svstnt1 (p0, x0 + svcntw () * 8, z0)) + +/* +** stnt1_f32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f32_m1, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 - svcntw (), z0), + svstnt1 (p0, x0 - svcntw (), z0)) + +/* +** stnt1_f32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f32_m8, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 - svcntw () * 8, z0), + svstnt1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f32_m9, svfloat32_t, float32_t, + svstnt1_f32 (p0, x0 - svcntw () * 9, z0), + svstnt1 (p0, x0 - svcntw () * 9, z0)) + +/* +** stnt1_vnum_f32_0: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_0, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_f32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_1, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_f32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_7, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_8, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_f32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_m1, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_f32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_m8, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_m9, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_f32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_f32_x1, svfloat32_t, float32_t, + svstnt1_vnum_f32 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f64.c new file mode 100644 index 00000000000..491528e307b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_f64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_f64_base: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f64_base, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_f64_index: +** stnt1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (stnt1_f64_index, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_f64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f64_1, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 + svcntd (), z0), + svstnt1 (p0, x0 + svcntd (), z0)) + +/* +** stnt1_f64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f64_7, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 + svcntd () * 7, z0), + svstnt1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f64_8, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 + svcntd () * 8, z0), + svstnt1 (p0, x0 + svcntd () * 8, z0)) + +/* +** stnt1_f64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f64_m1, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 - svcntd (), z0), + svstnt1 (p0, x0 - svcntd (), z0)) + +/* +** stnt1_f64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_f64_m8, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 - svcntd () * 8, z0), + svstnt1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_f64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_f64_m9, svfloat64_t, float64_t, + svstnt1_f64 (p0, x0 - svcntd () * 9, z0), + svstnt1 (p0, x0 - svcntd () * 9, z0)) + +/* +** stnt1_vnum_f64_0: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_0, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_f64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_1, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_f64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_7, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_8, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_f64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_m1, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_f64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_m8, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_f64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_m9, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_f64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_f64_x1, svfloat64_t, float64_t, + svstnt1_vnum_f64 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s16.c new file mode 100644 index 00000000000..2a98fbbb874 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_s16_base: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s16_base, svint16_t, int16_t, + svstnt1_s16 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_s16_index: +** stnt1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (stnt1_s16_index, svint16_t, int16_t, + svstnt1_s16 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_s16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s16_1, svint16_t, int16_t, + svstnt1_s16 (p0, x0 + svcnth (), z0), + svstnt1 (p0, x0 + svcnth (), z0)) + +/* +** stnt1_s16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s16_7, svint16_t, int16_t, + svstnt1_s16 (p0, x0 + svcnth () * 7, z0), + svstnt1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s16_8, svint16_t, int16_t, + svstnt1_s16 (p0, x0 + svcnth () * 8, z0), + svstnt1 (p0, x0 + svcnth () * 8, z0)) + +/* +** stnt1_s16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s16_m1, svint16_t, int16_t, + svstnt1_s16 (p0, x0 - svcnth (), z0), + svstnt1 (p0, x0 - svcnth (), z0)) + +/* +** stnt1_s16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s16_m8, svint16_t, int16_t, + svstnt1_s16 (p0, x0 - svcnth () * 8, z0), + svstnt1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s16_m9, svint16_t, int16_t, + svstnt1_s16 (p0, x0 - svcnth () * 9, z0), + svstnt1 (p0, x0 - svcnth () * 9, z0)) + +/* +** stnt1_vnum_s16_0: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_0, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_s16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_1, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_s16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_7, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_8, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_s16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_m1, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_s16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_m8, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_m9, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_s16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_s16_x1, svint16_t, int16_t, + svstnt1_vnum_s16 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s32.c new file mode 100644 index 00000000000..80a26819270 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_s32_base: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s32_base, svint32_t, int32_t, + svstnt1_s32 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_s32_index: +** stnt1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (stnt1_s32_index, svint32_t, int32_t, + svstnt1_s32 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_s32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s32_1, svint32_t, int32_t, + svstnt1_s32 (p0, x0 + svcntw (), z0), + svstnt1 (p0, x0 + svcntw (), z0)) + +/* +** stnt1_s32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s32_7, svint32_t, int32_t, + svstnt1_s32 (p0, x0 + svcntw () * 7, z0), + svstnt1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s32_8, svint32_t, int32_t, + svstnt1_s32 (p0, x0 + svcntw () * 8, z0), + svstnt1 (p0, x0 + svcntw () * 8, z0)) + +/* +** stnt1_s32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s32_m1, svint32_t, int32_t, + svstnt1_s32 (p0, x0 - svcntw (), z0), + svstnt1 (p0, x0 - svcntw (), z0)) + +/* +** stnt1_s32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s32_m8, svint32_t, int32_t, + svstnt1_s32 (p0, x0 - svcntw () * 8, z0), + svstnt1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s32_m9, svint32_t, int32_t, + svstnt1_s32 (p0, x0 - svcntw () * 9, z0), + svstnt1 (p0, x0 - svcntw () * 9, z0)) + +/* +** stnt1_vnum_s32_0: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_0, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_s32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_1, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_s32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_7, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_8, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_s32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_m1, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_s32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_m8, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_m9, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_s32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_s32_x1, svint32_t, int32_t, + svstnt1_vnum_s32 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s64.c new file mode 100644 index 00000000000..f5f4ed568f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_s64_base: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s64_base, svint64_t, int64_t, + svstnt1_s64 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_s64_index: +** stnt1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (stnt1_s64_index, svint64_t, int64_t, + svstnt1_s64 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_s64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s64_1, svint64_t, int64_t, + svstnt1_s64 (p0, x0 + svcntd (), z0), + svstnt1 (p0, x0 + svcntd (), z0)) + +/* +** stnt1_s64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s64_7, svint64_t, int64_t, + svstnt1_s64 (p0, x0 + svcntd () * 7, z0), + svstnt1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s64_8, svint64_t, int64_t, + svstnt1_s64 (p0, x0 + svcntd () * 8, z0), + svstnt1 (p0, x0 + svcntd () * 8, z0)) + +/* +** stnt1_s64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s64_m1, svint64_t, int64_t, + svstnt1_s64 (p0, x0 - svcntd (), z0), + svstnt1 (p0, x0 - svcntd (), z0)) + +/* +** stnt1_s64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s64_m8, svint64_t, int64_t, + svstnt1_s64 (p0, x0 - svcntd () * 8, z0), + svstnt1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s64_m9, svint64_t, int64_t, + svstnt1_s64 (p0, x0 - svcntd () * 9, z0), + svstnt1 (p0, x0 - svcntd () * 9, z0)) + +/* +** stnt1_vnum_s64_0: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_0, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_s64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_1, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_s64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_7, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_8, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_s64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_m1, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_s64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_m8, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_m9, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_s64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_s64_x1, svint64_t, int64_t, + svstnt1_vnum_s64 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s8.c new file mode 100644 index 00000000000..fd615931b3d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_s8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_s8_base: +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s8_base, svint8_t, int8_t, + svstnt1_s8 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_s8_index: +** stnt1b z0\.b, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (stnt1_s8_index, svint8_t, int8_t, + svstnt1_s8 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_s8_1: +** stnt1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s8_1, svint8_t, int8_t, + svstnt1_s8 (p0, x0 + svcntb (), z0), + svstnt1 (p0, x0 + svcntb (), z0)) + +/* +** stnt1_s8_7: +** stnt1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s8_7, svint8_t, int8_t, + svstnt1_s8 (p0, x0 + svcntb () * 7, z0), + svstnt1 (p0, x0 + svcntb () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s8_8: +** incb x0, all, mul #8 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s8_8, svint8_t, int8_t, + svstnt1_s8 (p0, x0 + svcntb () * 8, z0), + svstnt1 (p0, x0 + svcntb () * 8, z0)) + +/* +** stnt1_s8_m1: +** stnt1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s8_m1, svint8_t, int8_t, + svstnt1_s8 (p0, x0 - svcntb (), z0), + svstnt1 (p0, x0 - svcntb (), z0)) + +/* +** stnt1_s8_m8: +** stnt1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_s8_m8, svint8_t, int8_t, + svstnt1_s8 (p0, x0 - svcntb () * 8, z0), + svstnt1 (p0, x0 - svcntb () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_s8_m9: +** decb x0, all, mul #9 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_s8_m9, svint8_t, int8_t, + svstnt1_s8 (p0, x0 - svcntb () * 9, z0), + svstnt1 (p0, x0 - svcntb () * 9, z0)) + +/* +** stnt1_vnum_s8_0: +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_0, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_s8_1: +** stnt1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_1, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_s8_7: +** stnt1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_7, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s8_8: +** incb x0, all, mul #8 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_8, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_s8_m1: +** stnt1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_m1, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_s8_m8: +** stnt1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_m8, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_s8_m9: +** decb x0, all, mul #9 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_s8_m9, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* +** stnt1_vnum_s8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** stnt1b z0\.b, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** stnt1b z0\.b, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (stnt1_vnum_s8_x1, svint8_t, int8_t, + svstnt1_vnum_s8 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u16.c new file mode 100644 index 00000000000..81e06ffe365 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u16.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_u16_base: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u16_base, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_u16_index: +** stnt1h z0\.h, p0, \[x0, x1, lsl 1\] +** ret +*/ +TEST_STORE (stnt1_u16_index, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_u16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u16_1, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 + svcnth (), z0), + svstnt1 (p0, x0 + svcnth (), z0)) + +/* +** stnt1_u16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u16_7, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 + svcnth () * 7, z0), + svstnt1 (p0, x0 + svcnth () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u16_8, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 + svcnth () * 8, z0), + svstnt1 (p0, x0 + svcnth () * 8, z0)) + +/* +** stnt1_u16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u16_m1, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 - svcnth (), z0), + svstnt1 (p0, x0 - svcnth (), z0)) + +/* +** stnt1_u16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u16_m8, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 - svcnth () * 8, z0), + svstnt1 (p0, x0 - svcnth () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u16_m9, svuint16_t, uint16_t, + svstnt1_u16 (p0, x0 - svcnth () * 9, z0), + svstnt1 (p0, x0 - svcnth () * 9, z0)) + +/* +** stnt1_vnum_u16_0: +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_0, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_u16_1: +** stnt1h z0\.h, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_1, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_u16_7: +** stnt1h z0\.h, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_7, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u16_8: +** incb x0, all, mul #8 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_8, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_u16_m1: +** stnt1h z0\.h, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_m1, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_u16_m8: +** stnt1h z0\.h, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_m8, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u16_m9: +** decb x0, all, mul #9 +** stnt1h z0\.h, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_m9, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_u16_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1h z0\.h, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_u16_x1, svuint16_t, uint16_t, + svstnt1_vnum_u16 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u32.c new file mode 100644 index 00000000000..8f5870ff27d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u32.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_u32_base: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u32_base, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_u32_index: +** stnt1w z0\.s, p0, \[x0, x1, lsl 2\] +** ret +*/ +TEST_STORE (stnt1_u32_index, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_u32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u32_1, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 + svcntw (), z0), + svstnt1 (p0, x0 + svcntw (), z0)) + +/* +** stnt1_u32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u32_7, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 + svcntw () * 7, z0), + svstnt1 (p0, x0 + svcntw () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u32_8, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 + svcntw () * 8, z0), + svstnt1 (p0, x0 + svcntw () * 8, z0)) + +/* +** stnt1_u32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u32_m1, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 - svcntw (), z0), + svstnt1 (p0, x0 - svcntw (), z0)) + +/* +** stnt1_u32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u32_m8, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 - svcntw () * 8, z0), + svstnt1 (p0, x0 - svcntw () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u32_m9, svuint32_t, uint32_t, + svstnt1_u32 (p0, x0 - svcntw () * 9, z0), + svstnt1 (p0, x0 - svcntw () * 9, z0)) + +/* +** stnt1_vnum_u32_0: +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_0, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_u32_1: +** stnt1w z0\.s, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_1, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_u32_7: +** stnt1w z0\.s, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_7, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u32_8: +** incb x0, all, mul #8 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_8, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_u32_m1: +** stnt1w z0\.s, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_m1, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_u32_m8: +** stnt1w z0\.s, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_m8, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u32_m9: +** decb x0, all, mul #9 +** stnt1w z0\.s, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_m9, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_u32_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1w z0\.s, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_u32_x1, svuint32_t, uint32_t, + svstnt1_vnum_u32 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u64.c new file mode 100644 index 00000000000..03121160551 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u64.c @@ -0,0 +1,158 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_u64_base: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u64_base, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_u64_index: +** stnt1d z0\.d, p0, \[x0, x1, lsl 3\] +** ret +*/ +TEST_STORE (stnt1_u64_index, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_u64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u64_1, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 + svcntd (), z0), + svstnt1 (p0, x0 + svcntd (), z0)) + +/* +** stnt1_u64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u64_7, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 + svcntd () * 7, z0), + svstnt1 (p0, x0 + svcntd () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u64_8, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 + svcntd () * 8, z0), + svstnt1 (p0, x0 + svcntd () * 8, z0)) + +/* +** stnt1_u64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u64_m1, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 - svcntd (), z0), + svstnt1 (p0, x0 - svcntd (), z0)) + +/* +** stnt1_u64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u64_m8, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 - svcntd () * 8, z0), + svstnt1 (p0, x0 - svcntd () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u64_m9, svuint64_t, uint64_t, + svstnt1_u64 (p0, x0 - svcntd () * 9, z0), + svstnt1 (p0, x0 - svcntd () * 9, z0)) + +/* +** stnt1_vnum_u64_0: +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_0, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_u64_1: +** stnt1d z0\.d, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_1, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_u64_7: +** stnt1d z0\.d, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_7, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u64_8: +** incb x0, all, mul #8 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_8, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_u64_m1: +** stnt1d z0\.d, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_m1, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_u64_m8: +** stnt1d z0\.d, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_m8, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u64_m9: +** decb x0, all, mul #9 +** stnt1d z0\.d, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_m9, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* Using MUL to calculate an index would also be OK. */ +/* +** stnt1_vnum_u64_x1: +** cntb (x[0-9]+) +** madd (x[0-9]+), (x1, \1|\1, x1), x0 +** stnt1d z0\.d, p0, \[\2\] +** ret +*/ +TEST_STORE (stnt1_vnum_u64_x1, svuint64_t, uint64_t, + svstnt1_vnum_u64 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u8.c new file mode 100644 index 00000000000..90d18110dbd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/stnt1_u8.c @@ -0,0 +1,162 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** stnt1_u8_base: +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u8_base, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0, z0), + svstnt1 (p0, x0, z0)) + +/* +** stnt1_u8_index: +** stnt1b z0\.b, p0, \[x0, x1\] +** ret +*/ +TEST_STORE (stnt1_u8_index, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 + x1, z0), + svstnt1 (p0, x0 + x1, z0)) + +/* +** stnt1_u8_1: +** stnt1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u8_1, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 + svcntb (), z0), + svstnt1 (p0, x0 + svcntb (), z0)) + +/* +** stnt1_u8_7: +** stnt1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u8_7, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 + svcntb () * 7, z0), + svstnt1 (p0, x0 + svcntb () * 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u8_8: +** incb x0, all, mul #8 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u8_8, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 + svcntb () * 8, z0), + svstnt1 (p0, x0 + svcntb () * 8, z0)) + +/* +** stnt1_u8_m1: +** stnt1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u8_m1, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 - svcntb (), z0), + svstnt1 (p0, x0 - svcntb (), z0)) + +/* +** stnt1_u8_m8: +** stnt1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_u8_m8, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 - svcntb () * 8, z0), + svstnt1 (p0, x0 - svcntb () * 8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_u8_m9: +** decb x0, all, mul #9 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_u8_m9, svuint8_t, uint8_t, + svstnt1_u8 (p0, x0 - svcntb () * 9, z0), + svstnt1 (p0, x0 - svcntb () * 9, z0)) + +/* +** stnt1_vnum_u8_0: +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_0, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, 0, z0), + svstnt1_vnum (p0, x0, 0, z0)) + +/* +** stnt1_vnum_u8_1: +** stnt1b z0\.b, p0, \[x0, #1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_1, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, 1, z0), + svstnt1_vnum (p0, x0, 1, z0)) + +/* +** stnt1_vnum_u8_7: +** stnt1b z0\.b, p0, \[x0, #7, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_7, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, 7, z0), + svstnt1_vnum (p0, x0, 7, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u8_8: +** incb x0, all, mul #8 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_8, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, 8, z0), + svstnt1_vnum (p0, x0, 8, z0)) + +/* +** stnt1_vnum_u8_m1: +** stnt1b z0\.b, p0, \[x0, #-1, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_m1, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, -1, z0), + svstnt1_vnum (p0, x0, -1, z0)) + +/* +** stnt1_vnum_u8_m8: +** stnt1b z0\.b, p0, \[x0, #-8, mul vl\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_m8, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, -8, z0), + svstnt1_vnum (p0, x0, -8, z0)) + +/* Moving the constant into a register would also be OK. */ +/* +** stnt1_vnum_u8_m9: +** decb x0, all, mul #9 +** stnt1b z0\.b, p0, \[x0\] +** ret +*/ +TEST_STORE (stnt1_vnum_u8_m9, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, -9, z0), + svstnt1_vnum (p0, x0, -9, z0)) + +/* +** stnt1_vnum_u8_x1: +** cntb (x[0-9]+) +** ( +** madd (x[0-9]+), (?:x1, \1|\1, x1), x0 +** stnt1b z0\.b, p0, \[\2\] +** | +** mul (x[0-9]+), (?:x1, \1|\1, x1) +** stnt1b z0\.b, p0, \[x0, \3\] +** ) +** ret +*/ +TEST_STORE (stnt1_vnum_u8_x1, svuint8_t, uint8_t, + svstnt1_vnum_u8 (p0, x0, x1, z0), + svstnt1_vnum (p0, x0, x1, z0)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16.c new file mode 100644 index 00000000000..bf4a0ab1ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_tied1, svfloat16_t, + z0 = svsub_f16_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_tied2, svfloat16_t, + z0 = svsub_f16_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_untied, svfloat16_t, + z0 = svsub_f16_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f16_m, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_tied1, svfloat16_t, + z0 = svsub_f16_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_tied2, svfloat16_t, + z0 = svsub_f16_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_untied, svfloat16_t, + z0 = svsub_f16_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f16_z, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_tied1, svfloat16_t, + z0 = svsub_f16_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f16_x_tied2: +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_tied2, svfloat16_t, + z0 = svsub_f16_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f16_x_untied: +** ( +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_untied, svfloat16_t, + z0 = svsub_f16_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_2_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f16_x_untied: +** fmov z0\.h, #-2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_2_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f16_x_tied1: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_tied1, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z0, z1), + z0 = svsub_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_sub_f16_x_tied2: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_tied2, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z1, z0), + z0 = svsub_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_sub_f16_x_untied: +** fsub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_untied, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z1, z2), + z0 = svsub_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_sub_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svsub_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_sub_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svsub_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_sub_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svsub_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svsub_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svsub_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_sub_m1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svsub_x (svptrue_b16 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, -0.5), + z0 = svsub_x (svptrue_b16 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, -0.5), + z0 = svsub_x (svptrue_b16 (), z1, -0.5)) + +/* +** ptrue_sub_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svsub_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_sub_2_f16_x_untied: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svsub_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16_notrap.c new file mode 100644 index 00000000000..e45098944f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f16_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_tied1, svfloat16_t, + z0 = svsub_f16_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_tied2, svfloat16_t, + z0 = svsub_f16_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_m_untied, svfloat16_t, + z0 = svsub_f16_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f16_m_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f16_m_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f16_m_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_m_tied1, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_m_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_m_untied, svfloat16_t, + z0 = svsub_n_f16_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f16_m: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f16_m, svfloat16_t, + z0 = svsub_n_f16_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_tied1, svfloat16_t, + z0 = svsub_f16_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_tied2, svfloat16_t, + z0 = svsub_f16_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f16_z_untied, svfloat16_t, + z0 = svsub_f16_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_z_tied1, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_z_untied, svfloat16_t, + z0 = svsub_n_f16_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f16_z: +** fmov (z[0-9]+\.h), #2\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fadd z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f16_z, svfloat16_t, + z0 = svsub_n_f16_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f16_x_tied1: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_tied1, svfloat16_t, + z0 = svsub_f16_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f16_x_tied2: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_tied2, svfloat16_t, + z0 = svsub_f16_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f16_x_untied: +** fsub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_f16_x_untied, svfloat16_t, + z0 = svsub_f16_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svsub_n_f16_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_h4_f16_x_untied: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svsub_n_f16_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f16_x_tied1: +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f16_x_untied: +** movprfx z0, z1 +** fsub z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f16_x_tied1: +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f16_x_untied: +** movprfx z0, z1 +** fadd z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f16_x_untied: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f16_x_tied1: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_tied1, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z0, z1), + z0 = svsub_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_sub_f16_x_tied2: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_tied2, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z1, z0), + z0 = svsub_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_sub_f16_x_untied: +** fsub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f16_x_untied, svfloat16_t, + z0 = svsub_f16_x (svptrue_b16 (), z1, z2), + z0 = svsub_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_sub_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svsub_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_sub_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svsub_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_sub_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svsub_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svsub_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svsub_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_sub_m1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svsub_x (svptrue_b16 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, -0.5), + z0 = svsub_x (svptrue_b16 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, -0.5), + z0 = svsub_x (svptrue_b16 (), z1, -0.5)) + +/* +** ptrue_sub_2_f16_x_tied1: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f16_x_tied1, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z0, 2), + z0 = svsub_x (svptrue_b16 (), z0, 2)) + +/* +** ptrue_sub_2_f16_x_untied: +** fmov (z[0-9]+\.h), #-2\.0(?:e\+0)? +** fadd z0\.h, (z1\.h, \1|\1, z1\.h) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f16_x_untied, svfloat16_t, + z0 = svsub_n_f16_x (svptrue_b16 (), z1, 2), + z0 = svsub_x (svptrue_b16 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32.c new file mode 100644 index 00000000000..05be52bade8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_tied1, svfloat32_t, + z0 = svsub_f32_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_tied2, svfloat32_t, + z0 = svsub_f32_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_untied, svfloat32_t, + z0 = svsub_f32_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_m_tied1, svfloat32_t, float, + z0 = svsub_n_f32_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_m_untied, svfloat32_t, float, + z0 = svsub_n_f32_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f32_m, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_tied1, svfloat32_t, + z0 = svsub_f32_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_tied2, svfloat32_t, + z0 = svsub_f32_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_untied, svfloat32_t, + z0 = svsub_f32_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_z_tied1, svfloat32_t, float, + z0 = svsub_n_f32_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_z_untied, svfloat32_t, float, + z0 = svsub_n_f32_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f32_z, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_tied1, svfloat32_t, + z0 = svsub_f32_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f32_x_tied2: +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_tied2, svfloat32_t, + z0 = svsub_f32_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f32_x_untied: +** ( +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_untied, svfloat32_t, + z0 = svsub_f32_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_x_tied1, svfloat32_t, float, + z0 = svsub_n_f32_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_x_untied, svfloat32_t, float, + z0 = svsub_n_f32_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_2_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f32_x_untied: +** fmov z0\.s, #-2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_2_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f32_x_tied1: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_tied1, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z0, z1), + z0 = svsub_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_sub_f32_x_tied2: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_tied2, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z1, z0), + z0 = svsub_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_sub_f32_x_untied: +** fsub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_untied, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z1, z2), + z0 = svsub_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_sub_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svsub_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_sub_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svsub_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_sub_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svsub_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svsub_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svsub_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_sub_m1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svsub_x (svptrue_b32 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, -0.5), + z0 = svsub_x (svptrue_b32 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, -0.5), + z0 = svsub_x (svptrue_b32 (), z1, -0.5)) + +/* +** ptrue_sub_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svsub_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_sub_2_f32_x_untied: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svsub_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32_notrap.c new file mode 100644 index 00000000000..eb79a253ad1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f32_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_tied1, svfloat32_t, + z0 = svsub_f32_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_tied2, svfloat32_t, + z0 = svsub_f32_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_m_untied, svfloat32_t, + z0 = svsub_f32_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_m_tied1, svfloat32_t, float, + z0 = svsub_n_f32_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_m_untied, svfloat32_t, float, + z0 = svsub_n_f32_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f32_m_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f32_m_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f32_m_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_m_tied1, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_m_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_m_untied, svfloat32_t, + z0 = svsub_n_f32_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f32_m: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f32_m, svfloat32_t, + z0 = svsub_n_f32_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_tied1, svfloat32_t, + z0 = svsub_f32_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_tied2, svfloat32_t, + z0 = svsub_f32_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f32_z_untied, svfloat32_t, + z0 = svsub_f32_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_z_tied1, svfloat32_t, float, + z0 = svsub_n_f32_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_z_untied, svfloat32_t, float, + z0 = svsub_n_f32_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_z_tied1, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_z_untied, svfloat32_t, + z0 = svsub_n_f32_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f32_z: +** fmov (z[0-9]+\.s), #2\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fadd z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f32_z, svfloat32_t, + z0 = svsub_n_f32_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f32_x_tied1: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_tied1, svfloat32_t, + z0 = svsub_f32_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f32_x_tied2: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_tied2, svfloat32_t, + z0 = svsub_f32_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f32_x_untied: +** fsub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_f32_x_untied, svfloat32_t, + z0 = svsub_f32_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_x_tied1, svfloat32_t, float, + z0 = svsub_n_f32_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_s4_f32_x_untied: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_s4_f32_x_untied, svfloat32_t, float, + z0 = svsub_n_f32_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f32_x_tied1: +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f32_x_untied: +** movprfx z0, z1 +** fsub z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f32_x_tied1: +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f32_x_untied: +** movprfx z0, z1 +** fadd z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f32_x_untied: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f32_x_tied1: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_tied1, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z0, z1), + z0 = svsub_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_sub_f32_x_tied2: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_tied2, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z1, z0), + z0 = svsub_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_sub_f32_x_untied: +** fsub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f32_x_untied, svfloat32_t, + z0 = svsub_f32_x (svptrue_b32 (), z1, z2), + z0 = svsub_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_sub_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svsub_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_sub_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svsub_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_sub_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svsub_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svsub_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svsub_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_sub_m1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svsub_x (svptrue_b32 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, -0.5), + z0 = svsub_x (svptrue_b32 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, -0.5), + z0 = svsub_x (svptrue_b32 (), z1, -0.5)) + +/* +** ptrue_sub_2_f32_x_tied1: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f32_x_tied1, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z0, 2), + z0 = svsub_x (svptrue_b32 (), z0, 2)) + +/* +** ptrue_sub_2_f32_x_untied: +** fmov (z[0-9]+\.s), #-2\.0(?:e\+0)? +** fadd z0\.s, (z1\.s, \1|\1, z1\.s) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f32_x_untied, svfloat32_t, + z0 = svsub_n_f32_x (svptrue_b32 (), z1, 2), + z0 = svsub_x (svptrue_b32 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64.c new file mode 100644 index 00000000000..2179382c3f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64.c @@ -0,0 +1,577 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_tied1, svfloat64_t, + z0 = svsub_f64_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_tied2, svfloat64_t, + z0 = svsub_f64_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_untied, svfloat64_t, + z0 = svsub_f64_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_m_tied1, svfloat64_t, double, + z0 = svsub_n_f64_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_m_untied, svfloat64_t, double, + z0 = svsub_n_f64_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f64_m, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_tied1, svfloat64_t, + z0 = svsub_f64_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_tied2, svfloat64_t, + z0 = svsub_f64_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_untied, svfloat64_t, + z0 = svsub_f64_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_z_tied1, svfloat64_t, double, + z0 = svsub_n_f64_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_z_untied, svfloat64_t, double, + z0 = svsub_n_f64_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f64_z, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_tied1, svfloat64_t, + z0 = svsub_f64_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f64_x_tied2: +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_tied2, svfloat64_t, + z0 = svsub_f64_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f64_x_untied: +** ( +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_untied, svfloat64_t, + z0 = svsub_f64_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_x_tied1, svfloat64_t, double, + z0 = svsub_n_f64_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_x_untied, svfloat64_t, double, + z0 = svsub_n_f64_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_2_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f64_x_untied: +** fmov z0\.d, #-2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_2_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f64_x_tied1: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_tied1, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z0, z1), + z0 = svsub_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_sub_f64_x_tied2: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_tied2, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z1, z0), + z0 = svsub_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_sub_f64_x_untied: +** fsub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_untied, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z1, z2), + z0 = svsub_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_sub_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svsub_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_sub_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svsub_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_sub_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svsub_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svsub_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svsub_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_sub_m1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svsub_x (svptrue_b64 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, -0.5), + z0 = svsub_x (svptrue_b64 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, -0.5), + z0 = svsub_x (svptrue_b64 (), z1, -0.5)) + +/* +** ptrue_sub_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svsub_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_sub_2_f64_x_untied: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svsub_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64_notrap.c new file mode 100644 index 00000000000..bd89f44b4b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_f64_notrap.c @@ -0,0 +1,572 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_tied1, svfloat64_t, + z0 = svsub_f64_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_tied2, svfloat64_t, + z0 = svsub_f64_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_m_untied, svfloat64_t, + z0 = svsub_f64_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_m_tied1, svfloat64_t, double, + z0 = svsub_n_f64_m (p0, z0, d4), + z0 = svsub_m (p0, z0, d4)) + +/* +** sub_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_m_untied, svfloat64_t, double, + z0 = svsub_n_f64_m (p0, z1, d4), + z0 = svsub_m (p0, z1, d4)) + +/* +** sub_1_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_0p5_f64_m_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, 0.5), + z0 = svsub_m (p0, z0, 0.5)) + +/* +** sub_0p5_f64_m_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, 0.5), + z0 = svsub_m (p0, z1, 0.5)) + +/* +** sub_m1_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_m1_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, -1), + z0 = svsub_m (p0, z1, -1)) + +/* +** sub_m0p5_f64_m_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_m_tied1, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -0.5), + z0 = svsub_m (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_m_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_m_untied, svfloat64_t, + z0 = svsub_n_f64_m (p0, z1, -0.5), + z0 = svsub_m (p0, z1, -0.5)) + +/* +** sub_m2_f64_m: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f64_m, svfloat64_t, + z0 = svsub_n_f64_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_tied1, svfloat64_t, + z0 = svsub_f64_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_tied2, svfloat64_t, + z0 = svsub_f64_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_f64_z_untied, svfloat64_t, + z0 = svsub_f64_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_z_tied1, svfloat64_t, double, + z0 = svsub_n_f64_z (p0, z0, d4), + z0 = svsub_z (p0, z0, d4)) + +/* +** sub_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_z_untied, svfloat64_t, double, + z0 = svsub_n_f64_z (p0, z1, d4), + z0 = svsub_z (p0, z1, d4)) + +/* +** sub_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, 0.5), + z0 = svsub_z (p0, z0, 0.5)) + +/* +** sub_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, 0.5), + z0 = svsub_z (p0, z1, 0.5)) + +/* +** sub_m1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -1), + z0 = svsub_z (p0, z0, -1)) + +/* +** sub_m1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, -1), + z0 = svsub_z (p0, z1, -1)) + +/* +** sub_m0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_z_tied1, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -0.5), + z0 = svsub_z (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_z_untied, svfloat64_t, + z0 = svsub_n_f64_z (p0, z1, -0.5), + z0 = svsub_z (p0, z1, -0.5)) + +/* +** sub_m2_f64_z: +** fmov (z[0-9]+\.d), #2\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fadd z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_f64_z, svfloat64_t, + z0 = svsub_n_f64_z (p0, z0, -2), + z0 = svsub_z (p0, z0, -2)) + +/* +** sub_f64_x_tied1: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_tied1, svfloat64_t, + z0 = svsub_f64_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_f64_x_tied2: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_tied2, svfloat64_t, + z0 = svsub_f64_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_f64_x_untied: +** fsub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_f64_x_untied, svfloat64_t, + z0 = svsub_f64_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_x_tied1, svfloat64_t, double, + z0 = svsub_n_f64_x (p0, z0, d4), + z0 = svsub_x (p0, z0, d4)) + +/* +** sub_d4_f64_x_untied: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (sub_d4_f64_x_untied, svfloat64_t, double, + z0 = svsub_n_f64_x (p0, z1, d4), + z0 = svsub_x (p0, z1, d4)) + +/* +** sub_1_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_0p5_f64_x_tied1: +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 0.5), + z0 = svsub_x (p0, z0, 0.5)) + +/* +** sub_0p5_f64_x_untied: +** movprfx z0, z1 +** fsub z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 0.5), + z0 = svsub_x (p0, z1, 0.5)) + +/* +** sub_m1_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m1_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, -1), + z0 = svsub_x (p0, z1, -1)) + +/* +** sub_m0p5_f64_x_tied1: +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, -0.5), + z0 = svsub_x (p0, z0, -0.5)) + +/* +** sub_m0p5_f64_x_untied: +** movprfx z0, z1 +** fadd z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (sub_m0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, -0.5), + z0 = svsub_x (p0, z1, -0.5)) + +/* +** sub_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (p0, z0, 2), + z0 = svsub_x (p0, z0, 2)) + +/* +** sub_2_f64_x_untied: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_2_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (p0, z1, 2), + z0 = svsub_x (p0, z1, 2)) + +/* +** ptrue_sub_f64_x_tied1: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_tied1, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z0, z1), + z0 = svsub_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_sub_f64_x_tied2: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_tied2, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z1, z0), + z0 = svsub_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_sub_f64_x_untied: +** fsub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_f64_x_untied, svfloat64_t, + z0 = svsub_f64_x (svptrue_b64 (), z1, z2), + z0 = svsub_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_sub_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svsub_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_sub_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svsub_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_sub_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svsub_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_sub_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svsub_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_sub_m1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svsub_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_sub_m1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m1_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svsub_x (svptrue_b64 (), z1, -1)) + +/* +** ptrue_sub_m0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, -0.5), + z0 = svsub_x (svptrue_b64 (), z0, -0.5)) + +/* +** ptrue_sub_m0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_m0p5_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, -0.5), + z0 = svsub_x (svptrue_b64 (), z1, -0.5)) + +/* +** ptrue_sub_2_f64_x_tied1: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f64_x_tied1, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z0, 2), + z0 = svsub_x (svptrue_b64 (), z0, 2)) + +/* +** ptrue_sub_2_f64_x_untied: +** fmov (z[0-9]+\.d), #-2\.0(?:e\+0)? +** fadd z0\.d, (z1\.d, \1|\1, z1\.d) +** ret +*/ +TEST_UNIFORM_Z (ptrue_sub_2_f64_x_untied, svfloat64_t, + z0 = svsub_n_f64_x (svptrue_b64 (), z1, 2), + z0 = svsub_x (svptrue_b64 (), z1, 2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c new file mode 100644 index 00000000000..aea8ea2b4aa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c @@ -0,0 +1,377 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_s16_m_tied1: +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_m_tied1, svint16_t, + z0 = svsub_s16_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_m_tied2, svint16_t, + z0 = svsub_s16_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_s16_m_untied: +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_m_untied, svint16_t, + z0 = svsub_s16_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svsub_n_s16_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_m_untied, svint16_t, int16_t, + z0 = svsub_n_s16_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_s16_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_m_tied1, svint16_t, + z0 = svsub_n_s16_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_m_untied, svint16_t, + z0 = svsub_n_s16_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_s16_m: +** mov (z[0-9]+\.h), #2 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_s16_m, svint16_t, + z0 = svsub_n_s16_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_z_tied1, svint16_t, + z0 = svsub_s16_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_z_tied2, svint16_t, + z0 = svsub_s16_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** sub z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_s16_z_untied, svint16_t, + z0 = svsub_s16_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svsub_n_s16_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** sub z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** subr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_z_untied, svint16_t, int16_t, + z0 = svsub_n_s16_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_s16_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_z_tied1, svint16_t, + z0 = svsub_n_s16_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_s16_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1\.h +** | +** movprfx z0\.h, p0/z, \1\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_z_untied, svint16_t, + z0 = svsub_n_s16_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_s16_x_tied1: +** sub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_x_tied1, svint16_t, + z0 = svsub_s16_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_s16_x_tied2: +** sub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_x_tied2, svint16_t, + z0 = svsub_s16_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_s16_x_untied: +** sub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_s16_x_untied, svint16_t, + z0 = svsub_s16_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svsub_n_s16_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_s16_x_untied: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s16_x_untied, svint16_t, int16_t, + z0 = svsub_n_s16_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_s16_x_tied1: +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_x_tied1, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_s16_x_untied: +** movprfx z0, z1 +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s16_x_untied, svint16_t, + z0 = svsub_n_s16_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_s16_x: +** sub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_s16_x: +** sub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_s16_x: +** sub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_s16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_256_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_257_s16_x: +** mov (z[0-9]+\.h), #-257 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_257_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 257), + z0 = svsub_x (p0, z0, 257)) + +/* +** sub_512_s16_x: +** add z0\.h, z0\.h, #65024 +** ret +*/ +TEST_UNIFORM_Z (sub_512_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_s16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_m1_s16_x: +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_s16_x: +** add z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_s16_x: +** add z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_s16_x: +** add z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_s16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m257_s16_x: +** mov (z[0-9]+)\.b, #1 +** add z0\.h, (z0\.h, \1\.h|\1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_m257_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -257), + z0 = svsub_x (p0, z0, -257)) + +/* +** sub_m512_s16_x: +** add z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_s16_x: +** add z0\.h, z0\.h, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_s16_x, svint16_t, + z0 = svsub_n_s16_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s32.c new file mode 100644 index 00000000000..db6f3df9019 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s32.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_s32_m_tied1: +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_m_tied1, svint32_t, + z0 = svsub_s32_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_m_tied2, svint32_t, + z0 = svsub_s32_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_s32_m_untied: +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_m_untied, svint32_t, + z0 = svsub_s32_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svsub_n_s32_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_m_untied, svint32_t, int32_t, + z0 = svsub_n_s32_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_s32_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_m_tied1, svint32_t, + z0 = svsub_n_s32_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_m_untied, svint32_t, + z0 = svsub_n_s32_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_s32_m: +** mov (z[0-9]+\.s), #2 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_s32_m, svint32_t, + z0 = svsub_n_s32_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_z_tied1, svint32_t, + z0 = svsub_s32_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_z_tied2, svint32_t, + z0 = svsub_s32_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** sub z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_s32_z_untied, svint32_t, + z0 = svsub_s32_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svsub_n_s32_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sub z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** subr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_z_untied, svint32_t, int32_t, + z0 = svsub_n_s32_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_s32_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_z_tied1, svint32_t, + z0 = svsub_n_s32_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_s32_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1\.s +** | +** movprfx z0\.s, p0/z, \1\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_z_untied, svint32_t, + z0 = svsub_n_s32_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_s32_x_tied1: +** sub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_x_tied1, svint32_t, + z0 = svsub_s32_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_s32_x_tied2: +** sub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_x_tied2, svint32_t, + z0 = svsub_s32_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_s32_x_untied: +** sub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_s32_x_untied, svint32_t, + z0 = svsub_s32_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svsub_n_s32_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_s32_x_untied: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s32_x_untied, svint32_t, int32_t, + z0 = svsub_n_s32_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_s32_x_tied1: +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_x_tied1, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_s32_x_untied: +** movprfx z0, z1 +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s32_x_untied, svint32_t, + z0 = svsub_n_s32_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_s32_x: +** sub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_s32_x: +** sub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_s32_x: +** sub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_s32_x: +** sub z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_256_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_511_s32_x: +** mov (z[0-9]+\.s), #-511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_511_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 511), + z0 = svsub_x (p0, z0, 511)) + +/* +** sub_512_s32_x: +** sub z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_512_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_s32_x: +** sub z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_65535_s32_x: +** mov (z[0-9]+\.s), #-65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_65535_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 65535), + z0 = svsub_x (p0, z0, 65535)) + +/* +** sub_65536_s32_x: +** mov (z[0-9]+\.s), #-65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_65536_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, 65536), + z0 = svsub_x (p0, z0, 65536)) + +/* +** sub_m1_s32_x: +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_s32_x: +** add z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_s32_x: +** add z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_s32_x: +** add z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_s32_x: +** add z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m511_s32_x: +** mov (z[0-9]+\.s), #511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m511_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -511), + z0 = svsub_x (p0, z0, -511)) + +/* +** sub_m512_s32_x: +** add z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_s32_x: +** add z0\.s, z0\.s, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) + +/* +** sub_m65280_s32_x: +** add z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_m65280_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -0xff00), + z0 = svsub_x (p0, z0, -0xff00)) + +/* +** sub_m65535_s32_x: +** mov (z[0-9]+\.s), #65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m65535_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -65535), + z0 = svsub_x (p0, z0, -65535)) + +/* +** sub_m65536_s32_x: +** mov (z[0-9]+\.s), #65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m65536_s32_x, svint32_t, + z0 = svsub_n_s32_x (p0, z0, -65536), + z0 = svsub_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s64.c new file mode 100644 index 00000000000..b9184c3a821 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s64.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_s64_m_tied1: +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_m_tied1, svint64_t, + z0 = svsub_s64_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_s64_m_tied2, svint64_t, + z0 = svsub_s64_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_s64_m_untied: +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_m_untied, svint64_t, + z0 = svsub_s64_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svsub_n_s64_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_m_untied, svint64_t, int64_t, + z0 = svsub_n_s64_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_s64_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_m_tied1, svint64_t, + z0 = svsub_n_s64_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_m_untied, svint64_t, + z0 = svsub_n_s64_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_s64_m: +** mov (z[0-9]+\.d), #2 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_s64_m, svint64_t, + z0 = svsub_n_s64_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_z_tied1, svint64_t, + z0 = svsub_s64_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_z_tied2, svint64_t, + z0 = svsub_s64_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** sub z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_s64_z_untied, svint64_t, + z0 = svsub_s64_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svsub_n_s64_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sub z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** subr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_z_untied, svint64_t, int64_t, + z0 = svsub_n_s64_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_s64_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_z_tied1, svint64_t, + z0 = svsub_n_s64_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_s64_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1\.d +** | +** movprfx z0\.d, p0/z, \1\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_z_untied, svint64_t, + z0 = svsub_n_s64_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_s64_x_tied1: +** sub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_x_tied1, svint64_t, + z0 = svsub_s64_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_s64_x_tied2: +** sub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_x_tied2, svint64_t, + z0 = svsub_s64_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_s64_x_untied: +** sub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_s64_x_untied, svint64_t, + z0 = svsub_s64_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svsub_n_s64_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_s64_x_untied, svint64_t, int64_t, + z0 = svsub_n_s64_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_s64_x_tied1: +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_x_tied1, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_s64_x_untied: +** movprfx z0, z1 +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s64_x_untied, svint64_t, + z0 = svsub_n_s64_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_s64_x: +** sub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_s64_x: +** sub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_s64_x: +** sub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_s64_x: +** sub z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_256_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_511_s64_x: +** mov (z[0-9]+\.d), #-511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_511_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 511), + z0 = svsub_x (p0, z0, 511)) + +/* +** sub_512_s64_x: +** sub z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_512_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_s64_x: +** sub z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_65535_s64_x: +** mov (z[0-9]+\.d), #-65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_65535_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 65535), + z0 = svsub_x (p0, z0, 65535)) + +/* +** sub_65536_s64_x: +** mov (z[0-9]+\.d), #-65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_65536_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, 65536), + z0 = svsub_x (p0, z0, 65536)) + +/* +** sub_m1_s64_x: +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_s64_x: +** add z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_s64_x: +** add z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_s64_x: +** add z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_s64_x: +** add z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m511_s64_x: +** mov (z[0-9]+\.d), #511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m511_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -511), + z0 = svsub_x (p0, z0, -511)) + +/* +** sub_m512_s64_x: +** add z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_s64_x: +** add z0\.d, z0\.d, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) + +/* +** sub_m65280_s64_x: +** add z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_m65280_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -0xff00), + z0 = svsub_x (p0, z0, -0xff00)) + +/* +** sub_m65535_s64_x: +** mov (z[0-9]+\.d), #65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m65535_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -65535), + z0 = svsub_x (p0, z0, -65535)) + +/* +** sub_m65536_s64_x: +** mov (z[0-9]+\.d), #65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m65536_s64_x, svint64_t, + z0 = svsub_n_s64_x (p0, z0, -65536), + z0 = svsub_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c new file mode 100644 index 00000000000..0d7ba99aa56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_s8_m_tied1: +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_m_tied1, svint8_t, + z0 = svsub_s8_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_m_tied2, svint8_t, + z0 = svsub_s8_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_s8_m_untied: +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_m_untied, svint8_t, + z0 = svsub_s8_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svsub_n_s8_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_m_untied, svint8_t, int8_t, + z0 = svsub_n_s8_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_s8_m_tied1: +** mov (z[0-9]+\.b), #-1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_m_tied1, svint8_t, + z0 = svsub_n_s8_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #-1 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_m_untied, svint8_t, + z0 = svsub_n_s8_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m1_s8_m: +** mov (z[0-9]+\.b), #1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_s8_m, svint8_t, + z0 = svsub_n_s8_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_z_tied1, svint8_t, + z0 = svsub_s8_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_z_tied2, svint8_t, + z0 = svsub_s8_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** sub z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_s8_z_untied, svint8_t, + z0 = svsub_s8_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svsub_n_s8_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** sub z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** subr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_z_untied, svint8_t, int8_t, + z0 = svsub_n_s8_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_s8_z_tied1: +** mov (z[0-9]+\.b), #-1 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_z_tied1, svint8_t, + z0 = svsub_n_s8_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_s8_z_untied: +** mov (z[0-9]+\.b), #-1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_z_untied, svint8_t, + z0 = svsub_n_s8_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_s8_x_tied1: +** sub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_x_tied1, svint8_t, + z0 = svsub_s8_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_s8_x_tied2: +** sub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_x_tied2, svint8_t, + z0 = svsub_s8_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_s8_x_untied: +** sub z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sub_s8_x_untied, svint8_t, + z0 = svsub_s8_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svsub_n_s8_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_s8_x_untied: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_s8_x_untied, svint8_t, int8_t, + z0 = svsub_n_s8_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_s8_x_tied1: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_x_tied1, svint8_t, + z0 = svsub_n_s8_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_s8_x_untied: +** movprfx z0, z1 +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_1_s8_x_untied, svint8_t, + z0 = svsub_n_s8_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_s8_x: +** add z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (sub_127_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_s8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_s8_x: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_255_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_m1_s8_x: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_s8_x: +** add z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_s8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_s8_x, svint8_t, + z0 = svsub_n_s8_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c new file mode 100644 index 00000000000..89620e159bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c @@ -0,0 +1,377 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_u16_m_tied1: +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_m_tied1, svuint16_t, + z0 = svsub_u16_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_m_tied2, svuint16_t, + z0 = svsub_u16_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_u16_m_untied: +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_m_untied, svuint16_t, + z0 = svsub_u16_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svsub_n_u16_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svsub_n_u16_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_u16_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_m_tied1, svuint16_t, + z0 = svsub_n_u16_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_m_untied, svuint16_t, + z0 = svsub_n_u16_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_u16_m: +** mov (z[0-9]+\.h), #2 +** add z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_u16_m, svuint16_t, + z0 = svsub_n_u16_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_z_tied1, svuint16_t, + z0 = svsub_u16_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_z_tied2, svuint16_t, + z0 = svsub_u16_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** sub z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_u16_z_untied, svuint16_t, + z0 = svsub_u16_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svsub_n_u16_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** sub z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** subr z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svsub_n_u16_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_u16_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.h, p0/z, z0\.h +** add z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_z_tied1, svuint16_t, + z0 = svsub_n_u16_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_u16_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** add z0\.h, p0/m, z0\.h, \1\.h +** | +** movprfx z0\.h, p0/z, \1\.h +** add z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_z_untied, svuint16_t, + z0 = svsub_n_u16_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_u16_x_tied1: +** sub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_x_tied1, svuint16_t, + z0 = svsub_u16_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_u16_x_tied2: +** sub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_x_tied2, svuint16_t, + z0 = svsub_u16_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_u16_x_untied: +** sub z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (sub_u16_x_untied, svuint16_t, + z0 = svsub_u16_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svsub_n_u16_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_u16_x_untied: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svsub_n_u16_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_u16_x_tied1: +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_x_tied1, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_u16_x_untied: +** movprfx z0, z1 +** sub z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u16_x_untied, svuint16_t, + z0 = svsub_n_u16_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_u16_x: +** sub z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_u16_x: +** sub z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_u16_x: +** sub z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_u16_x: +** add z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_256_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_257_u16_x: +** mov (z[0-9]+\.h), #-257 +** add z0\.h, (z0\.h, \1|\1, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_257_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 257), + z0 = svsub_x (p0, z0, 257)) + +/* +** sub_512_u16_x: +** add z0\.h, z0\.h, #65024 +** ret +*/ +TEST_UNIFORM_Z (sub_512_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_u16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_m1_u16_x: +** add z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_u16_x: +** add z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_u16_x: +** add z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_u16_x: +** add z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_u16_x: +** add z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m257_u16_x: +** mov (z[0-9]+)\.b, #1 +** add z0\.h, (z0\.h, \1\.h|\1\.h, z0\.h) +** ret +*/ +TEST_UNIFORM_Z (sub_m257_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -257), + z0 = svsub_x (p0, z0, -257)) + +/* +** sub_m512_u16_x: +** add z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_u16_x: +** add z0\.h, z0\.h, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_u16_x, svuint16_t, + z0 = svsub_n_u16_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u32.c new file mode 100644 index 00000000000..c4b405d4dd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u32.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_u32_m_tied1: +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_m_tied1, svuint32_t, + z0 = svsub_u32_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_m_tied2, svuint32_t, + z0 = svsub_u32_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_u32_m_untied: +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_m_untied, svuint32_t, + z0 = svsub_u32_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svsub_n_u32_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svsub_n_u32_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_u32_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_m_tied1, svuint32_t, + z0 = svsub_n_u32_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_m_untied, svuint32_t, + z0 = svsub_n_u32_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_u32_m: +** mov (z[0-9]+\.s), #2 +** add z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_u32_m, svuint32_t, + z0 = svsub_n_u32_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_z_tied1, svuint32_t, + z0 = svsub_u32_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_z_tied2, svuint32_t, + z0 = svsub_u32_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** sub z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_u32_z_untied, svuint32_t, + z0 = svsub_u32_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svsub_n_u32_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** sub z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** subr z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svsub_n_u32_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_u32_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.s, p0/z, z0\.s +** add z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_z_tied1, svuint32_t, + z0 = svsub_n_u32_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_u32_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** add z0\.s, p0/m, z0\.s, \1\.s +** | +** movprfx z0\.s, p0/z, \1\.s +** add z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_z_untied, svuint32_t, + z0 = svsub_n_u32_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_u32_x_tied1: +** sub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_x_tied1, svuint32_t, + z0 = svsub_u32_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_u32_x_tied2: +** sub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_x_tied2, svuint32_t, + z0 = svsub_u32_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_u32_x_untied: +** sub z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (sub_u32_x_untied, svuint32_t, + z0 = svsub_u32_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svsub_n_u32_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_u32_x_untied: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svsub_n_u32_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_u32_x_tied1: +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_x_tied1, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_u32_x_untied: +** movprfx z0, z1 +** sub z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u32_x_untied, svuint32_t, + z0 = svsub_n_u32_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_u32_x: +** sub z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_u32_x: +** sub z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_u32_x: +** sub z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_u32_x: +** sub z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_256_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_511_u32_x: +** mov (z[0-9]+\.s), #-511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_511_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 511), + z0 = svsub_x (p0, z0, 511)) + +/* +** sub_512_u32_x: +** sub z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_512_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_u32_x: +** sub z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_65535_u32_x: +** mov (z[0-9]+\.s), #-65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_65535_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 65535), + z0 = svsub_x (p0, z0, 65535)) + +/* +** sub_65536_u32_x: +** mov (z[0-9]+\.s), #-65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_65536_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, 65536), + z0 = svsub_x (p0, z0, 65536)) + +/* +** sub_m1_u32_x: +** add z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_u32_x: +** add z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_u32_x: +** add z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_u32_x: +** add z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_u32_x: +** add z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m511_u32_x: +** mov (z[0-9]+\.s), #511 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m511_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -511), + z0 = svsub_x (p0, z0, -511)) + +/* +** sub_m512_u32_x: +** add z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_u32_x: +** add z0\.s, z0\.s, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) + +/* +** sub_m65280_u32_x: +** add z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_m65280_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -0xff00), + z0 = svsub_x (p0, z0, -0xff00)) + +/* +** sub_m65535_u32_x: +** mov (z[0-9]+\.s), #65535 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m65535_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -65535), + z0 = svsub_x (p0, z0, -65535)) + +/* +** sub_m65536_u32_x: +** mov (z[0-9]+\.s), #65536 +** add z0\.s, (z0\.s, \1|\1, z0\.s) +** ret +*/ +TEST_UNIFORM_Z (sub_m65536_u32_x, svuint32_t, + z0 = svsub_n_u32_x (p0, z0, -65536), + z0 = svsub_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u64.c new file mode 100644 index 00000000000..fb7f7173a00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u64.c @@ -0,0 +1,426 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_u64_m_tied1: +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_m_tied1, svuint64_t, + z0 = svsub_u64_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_u64_m_tied2, svuint64_t, + z0 = svsub_u64_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_u64_m_untied: +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_m_untied, svuint64_t, + z0 = svsub_u64_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svsub_n_u64_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svsub_n_u64_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_u64_m_tied1: +** mov (z[0-9]+)\.b, #-1 +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_m_tied1, svuint64_t, + z0 = svsub_n_u64_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+)\.b, #-1 +** movprfx z0, z1 +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_m_untied, svuint64_t, + z0 = svsub_n_u64_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m2_u64_m: +** mov (z[0-9]+\.d), #2 +** add z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m2_u64_m, svuint64_t, + z0 = svsub_n_u64_m (p0, z0, -2), + z0 = svsub_m (p0, z0, -2)) + +/* +** sub_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_z_tied1, svuint64_t, + z0 = svsub_u64_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_z_tied2, svuint64_t, + z0 = svsub_u64_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** sub z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_u64_z_untied, svuint64_t, + z0 = svsub_u64_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svsub_n_u64_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** sub z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** subr z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svsub_n_u64_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_u64_z_tied1: +** mov (z[0-9]+)\.b, #-1 +** movprfx z0\.d, p0/z, z0\.d +** add z0\.d, p0/m, z0\.d, \1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_z_tied1, svuint64_t, + z0 = svsub_n_u64_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_u64_z_untied: +** mov (z[0-9]+)\.b, #-1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** add z0\.d, p0/m, z0\.d, \1\.d +** | +** movprfx z0\.d, p0/z, \1\.d +** add z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_z_untied, svuint64_t, + z0 = svsub_n_u64_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_u64_x_tied1: +** sub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_x_tied1, svuint64_t, + z0 = svsub_u64_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_u64_x_tied2: +** sub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_x_tied2, svuint64_t, + z0 = svsub_u64_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_u64_x_untied: +** sub z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (sub_u64_x_untied, svuint64_t, + z0 = svsub_u64_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svsub_n_u64_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svsub_n_u64_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_u64_x_tied1: +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_x_tied1, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_u64_x_untied: +** movprfx z0, z1 +** sub z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u64_x_untied, svuint64_t, + z0 = svsub_n_u64_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_u64_x: +** sub z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_127_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_u64_x: +** sub z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_u64_x: +** sub z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_255_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_256_u64_x: +** sub z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_256_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 256), + z0 = svsub_x (p0, z0, 256)) + +/* +** sub_511_u64_x: +** mov (z[0-9]+\.d), #-511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_511_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 511), + z0 = svsub_x (p0, z0, 511)) + +/* +** sub_512_u64_x: +** sub z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_512_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 512), + z0 = svsub_x (p0, z0, 512)) + +/* +** sub_65280_u64_x: +** sub z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_65280_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 0xff00), + z0 = svsub_x (p0, z0, 0xff00)) + +/* +** sub_65535_u64_x: +** mov (z[0-9]+\.d), #-65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_65535_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 65535), + z0 = svsub_x (p0, z0, 65535)) + +/* +** sub_65536_u64_x: +** mov (z[0-9]+\.d), #-65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_65536_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, 65536), + z0 = svsub_x (p0, z0, 65536)) + +/* +** sub_m1_u64_x: +** add z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_u64_x: +** add z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_u64_x: +** add z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) + +/* +** sub_m255_u64_x: +** add z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_m255_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -255), + z0 = svsub_x (p0, z0, -255)) + +/* +** sub_m256_u64_x: +** add z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (sub_m256_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -256), + z0 = svsub_x (p0, z0, -256)) + +/* +** sub_m511_u64_x: +** mov (z[0-9]+\.d), #511 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m511_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -511), + z0 = svsub_x (p0, z0, -511)) + +/* +** sub_m512_u64_x: +** add z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (sub_m512_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -512), + z0 = svsub_x (p0, z0, -512)) + +/* +** sub_m32768_u64_x: +** add z0\.d, z0\.d, #32768 +** ret +*/ +TEST_UNIFORM_Z (sub_m32768_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -0x8000), + z0 = svsub_x (p0, z0, -0x8000)) + +/* +** sub_m65280_u64_x: +** add z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (sub_m65280_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -0xff00), + z0 = svsub_x (p0, z0, -0xff00)) + +/* +** sub_m65535_u64_x: +** mov (z[0-9]+\.d), #65535 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m65535_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -65535), + z0 = svsub_x (p0, z0, -65535)) + +/* +** sub_m65536_u64_x: +** mov (z[0-9]+\.d), #65536 +** add z0\.d, (z0\.d, \1|\1, z0\.d) +** ret +*/ +TEST_UNIFORM_Z (sub_m65536_u64_x, svuint64_t, + z0 = svsub_n_u64_x (p0, z0, -65536), + z0 = svsub_x (p0, z0, -65536)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c new file mode 100644 index 00000000000..4552041910f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** sub_u8_m_tied1: +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_m_tied1, svuint8_t, + z0 = svsub_u8_m (p0, z0, z1), + z0 = svsub_m (p0, z0, z1)) + +/* +** sub_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_m_tied2, svuint8_t, + z0 = svsub_u8_m (p0, z1, z0), + z0 = svsub_m (p0, z1, z0)) + +/* +** sub_u8_m_untied: +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_m_untied, svuint8_t, + z0 = svsub_u8_m (p0, z1, z2), + z0 = svsub_m (p0, z1, z2)) + +/* +** sub_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svsub_n_u8_m (p0, z0, x0), + z0 = svsub_m (p0, z0, x0)) + +/* +** sub_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svsub_n_u8_m (p0, z1, x0), + z0 = svsub_m (p0, z1, x0)) + +/* +** sub_1_u8_m_tied1: +** mov (z[0-9]+\.b), #-1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_m_tied1, svuint8_t, + z0 = svsub_n_u8_m (p0, z0, 1), + z0 = svsub_m (p0, z0, 1)) + +/* +** sub_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #-1 +** movprfx z0, z1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_m_untied, svuint8_t, + z0 = svsub_n_u8_m (p0, z1, 1), + z0 = svsub_m (p0, z1, 1)) + +/* +** sub_m1_u8_m: +** mov (z[0-9]+\.b), #1 +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_u8_m, svuint8_t, + z0 = svsub_n_u8_m (p0, z0, -1), + z0 = svsub_m (p0, z0, -1)) + +/* +** sub_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_z_tied1, svuint8_t, + z0 = svsub_u8_z (p0, z0, z1), + z0 = svsub_z (p0, z0, z1)) + +/* +** sub_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_z_tied2, svuint8_t, + z0 = svsub_u8_z (p0, z1, z0), + z0 = svsub_z (p0, z1, z0)) + +/* +** sub_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** sub z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_u8_z_untied, svuint8_t, + z0 = svsub_u8_z (p0, z1, z2), + z0 = svsub_z (p0, z1, z2)) + +/* +** sub_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svsub_n_u8_z (p0, z0, x0), + z0 = svsub_z (p0, z0, x0)) + +/* +** sub_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** sub z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** subr z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svsub_n_u8_z (p0, z1, x0), + z0 = svsub_z (p0, z1, x0)) + +/* +** sub_1_u8_z_tied1: +** mov (z[0-9]+\.b), #-1 +** movprfx z0\.b, p0/z, z0\.b +** add z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_z_tied1, svuint8_t, + z0 = svsub_n_u8_z (p0, z0, 1), + z0 = svsub_z (p0, z0, 1)) + +/* +** sub_1_u8_z_untied: +** mov (z[0-9]+\.b), #-1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** add z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** add z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_z_untied, svuint8_t, + z0 = svsub_n_u8_z (p0, z1, 1), + z0 = svsub_z (p0, z1, 1)) + +/* +** sub_u8_x_tied1: +** sub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_x_tied1, svuint8_t, + z0 = svsub_u8_x (p0, z0, z1), + z0 = svsub_x (p0, z0, z1)) + +/* +** sub_u8_x_tied2: +** sub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_x_tied2, svuint8_t, + z0 = svsub_u8_x (p0, z1, z0), + z0 = svsub_x (p0, z1, z0)) + +/* +** sub_u8_x_untied: +** sub z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (sub_u8_x_untied, svuint8_t, + z0 = svsub_u8_x (p0, z1, z2), + z0 = svsub_x (p0, z1, z2)) + +/* +** sub_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svsub_n_u8_x (p0, z0, x0), + z0 = svsub_x (p0, z0, x0)) + +/* +** sub_w0_u8_x_untied: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (sub_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svsub_n_u8_x (p0, z1, x0), + z0 = svsub_x (p0, z1, x0)) + +/* +** sub_1_u8_x_tied1: +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_x_tied1, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, 1), + z0 = svsub_x (p0, z0, 1)) + +/* +** sub_1_u8_x_untied: +** movprfx z0, z1 +** add z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (sub_1_u8_x_untied, svuint8_t, + z0 = svsub_n_u8_x (p0, z1, 1), + z0 = svsub_x (p0, z1, 1)) + +/* +** sub_127_u8_x: +** add z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (sub_127_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, 127), + z0 = svsub_x (p0, z0, 127)) + +/* +** sub_128_u8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_128_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, 128), + z0 = svsub_x (p0, z0, 128)) + +/* +** sub_255_u8_x: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_255_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, 255), + z0 = svsub_x (p0, z0, 255)) + +/* +** sub_m1_u8_x: +** add z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (sub_m1_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, -1), + z0 = svsub_x (p0, z0, -1)) + +/* +** sub_m127_u8_x: +** add z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (sub_m127_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, -127), + z0 = svsub_x (p0, z0, -127)) + +/* +** sub_m128_u8_x: +** add z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (sub_m128_u8_x, svuint8_t, + z0 = svsub_n_u8_x (p0, z0, -128), + z0 = svsub_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16.c new file mode 100644 index 00000000000..e14357db27f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_tied1, svfloat16_t, + z0 = svsubr_f16_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_tied2, svfloat16_t, + z0 = svsubr_f16_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_untied, svfloat16_t, + z0 = svsubr_f16_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f16_m_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_tied1, svfloat16_t, + z0 = svsubr_f16_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_tied2, svfloat16_t, + z0 = svsubr_f16_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_untied, svfloat16_t, + z0 = svsubr_f16_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f16_z_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f16_z_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f16_x_tied1: +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_tied1, svfloat16_t, + z0 = svsubr_f16_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f16_x_tied2: +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_tied2, svfloat16_t, + z0 = svsubr_f16_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f16_x_untied: +** ( +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0, z2 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_untied, svfloat16_t, + z0 = svsubr_f16_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_h4_f16_x_untied: { xfail *-*-* } +** mov z0\.h, h4 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f16_x_tied1: +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f16_x_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f16_x_tied1: +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f16_x_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f16_x_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f16_x_untied: +** fmov z0\.h, #-1\.0(?:e\+0)? +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f16_x_tied1: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_tied1, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z0, z1), + z0 = svsubr_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_subr_f16_x_tied2: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_tied2, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z1, z0), + z0 = svsubr_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_subr_f16_x_untied: +** fsub z0\.h, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_untied, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z1, z2), + z0 = svsubr_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_subr_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svsubr_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_subr_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svsubr_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_subr_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svsubr_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svsubr_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f16_x_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svsubr_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_subr_m1_f16_x_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svsubr_x (svptrue_b16 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16_notrap.c new file mode 100644 index 00000000000..a31ebd2ef7f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f16_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_tied1, svfloat16_t, + z0 = svsubr_f16_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_tied2, svfloat16_t, + z0 = svsubr_f16_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_m_untied, svfloat16_t, + z0 = svsubr_f16_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_h4_f16_m_tied1: +** mov (z[0-9]+\.h), h4 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_m_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_h4_f16_m_untied: +** mov (z[0-9]+\.h), h4 +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_m_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f16_m_tied1: +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f16_m_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f16_m_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_m_tied1, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f16_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_m_untied, svfloat16_t, + z0 = svsubr_n_f16_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_tied1, svfloat16_t, + z0 = svsubr_f16_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_tied2, svfloat16_t, + z0 = svsubr_f16_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f16_z_untied, svfloat16_t, + z0 = svsubr_f16_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_h4_f16_z_tied1: +** mov (z[0-9]+\.h), h4 +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_z_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_h4_f16_z_untied: +** mov (z[0-9]+\.h), h4 +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_z_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f16_z_untied: +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f16_z_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** movprfx z0\.h, p0/z, z0\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_z_tied1, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f16_z_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.h, p0/z, z1\.h +** fsubr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** fsub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_z_untied, svfloat16_t, + z0 = svsubr_n_f16_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f16_x_tied1: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_tied1, svfloat16_t, + z0 = svsubr_f16_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f16_x_tied2: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_tied2, svfloat16_t, + z0 = svsubr_f16_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f16_x_untied: +** fsub z0\.h, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_f16_x_untied, svfloat16_t, + z0 = svsubr_f16_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_h4_f16_x_tied1: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_x_tied1, svfloat16_t, __fp16, + z0 = svsubr_n_f16_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_h4_f16_x_untied: +** mov (z[0-9]+\.h), h4 +** fsub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZD (subr_h4_f16_x_untied, svfloat16_t, __fp16, + z0 = svsubr_n_f16_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f16_x_tied1: +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f16_x_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f16_x_tied1: +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f16_x_untied: +** movprfx z0, z1 +** fsubr z0\.h, p0/m, z0\.h, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f16_x_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f16_x_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f16_x_tied1: +** fsub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_tied1, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z0, z1), + z0 = svsubr_x (svptrue_b16 (), z0, z1)) + +/* +** ptrue_subr_f16_x_tied2: +** fsub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_tied2, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z1, z0), + z0 = svsubr_x (svptrue_b16 (), z1, z0)) + +/* +** ptrue_subr_f16_x_untied: +** fsub z0\.h, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f16_x_untied, svfloat16_t, + z0 = svsubr_f16_x (svptrue_b16 (), z1, z2), + z0 = svsubr_x (svptrue_b16 (), z1, z2)) + +/* +** ptrue_subr_1_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, 1), + z0 = svsubr_x (svptrue_b16 (), z0, 1)) + +/* +** ptrue_subr_1_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, 1), + z0 = svsubr_x (svptrue_b16 (), z1, 1)) + +/* +** ptrue_subr_0p5_f16_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, 0.5), + z0 = svsubr_x (svptrue_b16 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f16_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, 0.5), + z0 = svsubr_x (svptrue_b16 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f16_x_tied1: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f16_x_tied1, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z0, -1), + z0 = svsubr_x (svptrue_b16 (), z0, -1)) + +/* +** ptrue_subr_m1_f16_x_untied: +** fmov (z[0-9]+\.h), #-1\.0(?:e\+0)? +** fsub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f16_x_untied, svfloat16_t, + z0 = svsubr_n_f16_x (svptrue_b16 (), z1, -1), + z0 = svsubr_x (svptrue_b16 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32.c new file mode 100644 index 00000000000..98dc7ad2b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_tied1, svfloat32_t, + z0 = svsubr_f32_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_tied2, svfloat32_t, + z0 = svsubr_f32_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_untied, svfloat32_t, + z0 = svsubr_f32_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_m_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_m_untied, svfloat32_t, float, + z0 = svsubr_n_f32_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f32_m_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_tied1, svfloat32_t, + z0 = svsubr_f32_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_tied2, svfloat32_t, + z0 = svsubr_f32_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_untied, svfloat32_t, + z0 = svsubr_f32_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_z_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_z_untied, svfloat32_t, float, + z0 = svsubr_n_f32_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f32_z_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f32_z_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f32_x_tied1: +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_tied1, svfloat32_t, + z0 = svsubr_f32_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f32_x_tied2: +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_tied2, svfloat32_t, + z0 = svsubr_f32_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f32_x_untied: +** ( +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0, z2 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_untied, svfloat32_t, + z0 = svsubr_f32_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_x_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_s4_f32_x_untied: { xfail *-*-* } +** mov z0\.s, s4 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_x_untied, svfloat32_t, float, + z0 = svsubr_n_f32_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f32_x_tied1: +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f32_x_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f32_x_tied1: +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f32_x_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f32_x_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f32_x_untied: +** fmov z0\.s, #-1\.0(?:e\+0)? +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f32_x_tied1: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_tied1, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z0, z1), + z0 = svsubr_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_subr_f32_x_tied2: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_tied2, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z1, z0), + z0 = svsubr_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_subr_f32_x_untied: +** fsub z0\.s, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_untied, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z1, z2), + z0 = svsubr_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_subr_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svsubr_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_subr_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svsubr_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_subr_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svsubr_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svsubr_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f32_x_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svsubr_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_subr_m1_f32_x_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svsubr_x (svptrue_b32 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32_notrap.c new file mode 100644 index 00000000000..75ae0dc6164 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f32_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_tied1, svfloat32_t, + z0 = svsubr_f32_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_tied2, svfloat32_t, + z0 = svsubr_f32_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_m_untied, svfloat32_t, + z0 = svsubr_f32_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_s4_f32_m_tied1: +** mov (z[0-9]+\.s), s4 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_m_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_s4_f32_m_untied: +** mov (z[0-9]+\.s), s4 +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_m_untied, svfloat32_t, float, + z0 = svsubr_n_f32_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f32_m_tied1: +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f32_m_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f32_m_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_m_tied1, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f32_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_m_untied, svfloat32_t, + z0 = svsubr_n_f32_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_tied1, svfloat32_t, + z0 = svsubr_f32_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_tied2, svfloat32_t, + z0 = svsubr_f32_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f32_z_untied, svfloat32_t, + z0 = svsubr_f32_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_s4_f32_z_tied1: +** mov (z[0-9]+\.s), s4 +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_z_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_s4_f32_z_untied: +** mov (z[0-9]+\.s), s4 +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_z_untied, svfloat32_t, float, + z0 = svsubr_n_f32_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f32_z_untied: +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f32_z_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** movprfx z0\.s, p0/z, z0\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_z_tied1, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f32_z_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.s, p0/z, z1\.s +** fsubr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** fsub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_z_untied, svfloat32_t, + z0 = svsubr_n_f32_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f32_x_tied1: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_tied1, svfloat32_t, + z0 = svsubr_f32_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f32_x_tied2: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_tied2, svfloat32_t, + z0 = svsubr_f32_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f32_x_untied: +** fsub z0\.s, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_f32_x_untied, svfloat32_t, + z0 = svsubr_f32_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_s4_f32_x_tied1: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_x_tied1, svfloat32_t, float, + z0 = svsubr_n_f32_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_s4_f32_x_untied: +** mov (z[0-9]+\.s), s4 +** fsub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZD (subr_s4_f32_x_untied, svfloat32_t, float, + z0 = svsubr_n_f32_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f32_x_tied1: +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f32_x_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f32_x_tied1: +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f32_x_untied: +** movprfx z0, z1 +** fsubr z0\.s, p0/m, z0\.s, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f32_x_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f32_x_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f32_x_tied1: +** fsub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_tied1, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z0, z1), + z0 = svsubr_x (svptrue_b32 (), z0, z1)) + +/* +** ptrue_subr_f32_x_tied2: +** fsub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_tied2, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z1, z0), + z0 = svsubr_x (svptrue_b32 (), z1, z0)) + +/* +** ptrue_subr_f32_x_untied: +** fsub z0\.s, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f32_x_untied, svfloat32_t, + z0 = svsubr_f32_x (svptrue_b32 (), z1, z2), + z0 = svsubr_x (svptrue_b32 (), z1, z2)) + +/* +** ptrue_subr_1_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, 1), + z0 = svsubr_x (svptrue_b32 (), z0, 1)) + +/* +** ptrue_subr_1_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, 1), + z0 = svsubr_x (svptrue_b32 (), z1, 1)) + +/* +** ptrue_subr_0p5_f32_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, 0.5), + z0 = svsubr_x (svptrue_b32 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f32_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, 0.5), + z0 = svsubr_x (svptrue_b32 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f32_x_tied1: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f32_x_tied1, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z0, -1), + z0 = svsubr_x (svptrue_b32 (), z0, -1)) + +/* +** ptrue_subr_m1_f32_x_untied: +** fmov (z[0-9]+\.s), #-1\.0(?:e\+0)? +** fsub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f32_x_untied, svfloat32_t, + z0 = svsubr_n_f32_x (svptrue_b32 (), z1, -1), + z0 = svsubr_x (svptrue_b32 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64.c new file mode 100644 index 00000000000..81f1112d762 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64.c @@ -0,0 +1,444 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_tied1, svfloat64_t, + z0 = svsubr_f64_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_tied2, svfloat64_t, + z0 = svsubr_f64_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_untied, svfloat64_t, + z0 = svsubr_f64_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_m_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_m_untied, svfloat64_t, double, + z0 = svsubr_n_f64_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f64_m_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_tied1, svfloat64_t, + z0 = svsubr_f64_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_tied2, svfloat64_t, + z0 = svsubr_f64_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_untied, svfloat64_t, + z0 = svsubr_f64_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_z_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_z_untied, svfloat64_t, double, + z0 = svsubr_n_f64_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f64_z_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f64_z_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f64_x_tied1: +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_tied1, svfloat64_t, + z0 = svsubr_f64_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f64_x_tied2: +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_tied2, svfloat64_t, + z0 = svsubr_f64_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f64_x_untied: +** ( +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0, z2 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_untied, svfloat64_t, + z0 = svsubr_f64_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_x_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_d4_f64_x_untied: { xfail *-*-* } +** mov z0\.d, d4 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_x_untied, svfloat64_t, double, + z0 = svsubr_n_f64_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f64_x_tied1: +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f64_x_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f64_x_tied1: +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f64_x_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f64_x_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f64_x_untied: +** fmov z0\.d, #-1\.0(?:e\+0)? +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f64_x_tied1: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_tied1, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z0, z1), + z0 = svsubr_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_subr_f64_x_tied2: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_tied2, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z1, z0), + z0 = svsubr_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_subr_f64_x_untied: +** fsub z0\.d, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_untied, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z1, z2), + z0 = svsubr_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_subr_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svsubr_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_subr_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svsubr_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_subr_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svsubr_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svsubr_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f64_x_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svsubr_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_subr_m1_f64_x_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svsubr_x (svptrue_b64 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64_notrap.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64_notrap.c new file mode 100644 index 00000000000..98598dd7702 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_f64_notrap.c @@ -0,0 +1,439 @@ +/* { dg-additional-options "-fno-trapping-math" } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_tied1, svfloat64_t, + z0 = svsubr_f64_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_f64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_tied2, svfloat64_t, + z0 = svsubr_f64_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_m_untied, svfloat64_t, + z0 = svsubr_f64_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_d4_f64_m_tied1: +** mov (z[0-9]+\.d), d4 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_m_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_m (p0, z0, d4), + z0 = svsubr_m (p0, z0, d4)) + +/* +** subr_d4_f64_m_untied: +** mov (z[0-9]+\.d), d4 +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_m_untied, svfloat64_t, double, + z0 = svsubr_n_f64_m (p0, z1, d4), + z0 = svsubr_m (p0, z1, d4)) + +/* +** subr_1_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_0p5_f64_m_tied1: +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, 0.5), + z0 = svsubr_m (p0, z0, 0.5)) + +/* +** subr_0p5_f64_m_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, 0.5), + z0 = svsubr_m (p0, z1, 0.5)) + +/* +** subr_m1_f64_m_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_m_tied1, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_m1_f64_m_untied: { xfail *-*-* } +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_m_untied, svfloat64_t, + z0 = svsubr_n_f64_m (p0, z1, -1), + z0 = svsubr_m (p0, z1, -1)) + +/* +** subr_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_tied1, svfloat64_t, + z0 = svsubr_f64_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_f64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_tied2, svfloat64_t, + z0 = svsubr_f64_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_f64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_f64_z_untied, svfloat64_t, + z0 = svsubr_f64_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_d4_f64_z_tied1: +** mov (z[0-9]+\.d), d4 +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_z_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_z (p0, z0, d4), + z0 = svsubr_z (p0, z0, d4)) + +/* +** subr_d4_f64_z_untied: +** mov (z[0-9]+\.d), d4 +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_z_untied, svfloat64_t, double, + z0 = svsubr_n_f64_z (p0, z1, d4), + z0 = svsubr_z (p0, z1, d4)) + +/* +** subr_1_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_0p5_f64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, 0.5), + z0 = svsubr_z (p0, z0, 0.5)) + +/* +** subr_0p5_f64_z_untied: +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, 0.5), + z0 = svsubr_z (p0, z1, 0.5)) + +/* +** subr_m1_f64_z_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** movprfx z0\.d, p0/z, z0\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_z_tied1, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z0, -1), + z0 = svsubr_z (p0, z0, -1)) + +/* +** subr_m1_f64_z_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** ( +** movprfx z0\.d, p0/z, z1\.d +** fsubr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** fsub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_z_untied, svfloat64_t, + z0 = svsubr_n_f64_z (p0, z1, -1), + z0 = svsubr_z (p0, z1, -1)) + +/* +** subr_f64_x_tied1: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_tied1, svfloat64_t, + z0 = svsubr_f64_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_f64_x_tied2: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_tied2, svfloat64_t, + z0 = svsubr_f64_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_f64_x_untied: +** fsub z0\.d, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_f64_x_untied, svfloat64_t, + z0 = svsubr_f64_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_d4_f64_x_tied1: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_x_tied1, svfloat64_t, double, + z0 = svsubr_n_f64_x (p0, z0, d4), + z0 = svsubr_x (p0, z0, d4)) + +/* +** subr_d4_f64_x_untied: +** mov (z[0-9]+\.d), d4 +** fsub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZD (subr_d4_f64_x_untied, svfloat64_t, double, + z0 = svsubr_n_f64_x (p0, z1, d4), + z0 = svsubr_x (p0, z1, d4)) + +/* +** subr_1_f64_x_tied1: +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_f64_x_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #1\.0 +** ret +*/ +TEST_UNIFORM_Z (subr_1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_0p5_f64_x_tied1: +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, 0.5), + z0 = svsubr_x (p0, z0, 0.5)) + +/* +** subr_0p5_f64_x_untied: +** movprfx z0, z1 +** fsubr z0\.d, p0/m, z0\.d, #0\.5 +** ret +*/ +TEST_UNIFORM_Z (subr_0p5_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, 0.5), + z0 = svsubr_x (p0, z1, 0.5)) + +/* +** subr_m1_f64_x_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_f64_x_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) + +/* +** ptrue_subr_f64_x_tied1: +** fsub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_tied1, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z0, z1), + z0 = svsubr_x (svptrue_b64 (), z0, z1)) + +/* +** ptrue_subr_f64_x_tied2: +** fsub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_tied2, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z1, z0), + z0 = svsubr_x (svptrue_b64 (), z1, z0)) + +/* +** ptrue_subr_f64_x_untied: +** fsub z0\.d, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_f64_x_untied, svfloat64_t, + z0 = svsubr_f64_x (svptrue_b64 (), z1, z2), + z0 = svsubr_x (svptrue_b64 (), z1, z2)) + +/* +** ptrue_subr_1_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, 1), + z0 = svsubr_x (svptrue_b64 (), z0, 1)) + +/* +** ptrue_subr_1_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, 1), + z0 = svsubr_x (svptrue_b64 (), z1, 1)) + +/* +** ptrue_subr_0p5_f64_x_tied1: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, 0.5), + z0 = svsubr_x (svptrue_b64 (), z0, 0.5)) + +/* +** ptrue_subr_0p5_f64_x_untied: +** ... +** ptrue p[0-9]+\.b[^\n]* +** ... +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_0p5_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, 0.5), + z0 = svsubr_x (svptrue_b64 (), z1, 0.5)) + +/* +** ptrue_subr_m1_f64_x_tied1: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f64_x_tied1, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z0, -1), + z0 = svsubr_x (svptrue_b64 (), z0, -1)) + +/* +** ptrue_subr_m1_f64_x_untied: +** fmov (z[0-9]+\.d), #-1\.0(?:e\+0)? +** fsub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_Z (ptrue_subr_m1_f64_x_untied, svfloat64_t, + z0 = svsubr_n_f64_x (svptrue_b64 (), z1, -1), + z0 = svsubr_x (svptrue_b64 (), z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c new file mode 100644 index 00000000000..d3dad62dafe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c @@ -0,0 +1,324 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_s16_m_tied1: +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_m_tied1, svint16_t, + z0 = svsubr_s16_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_s16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_m_tied2, svint16_t, + z0 = svsubr_s16_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_s16_m_untied: +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_m_untied, svint16_t, + z0 = svsubr_s16_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_s16_m_tied1: +** mov (z[0-9]+\.h), w0 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_m_tied1, svint16_t, int16_t, + z0 = svsubr_n_s16_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_m_untied, svint16_t, int16_t, + z0 = svsubr_n_s16_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_s16_m_tied1: +** mov (z[0-9]+\.h), #1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_m_tied1, svint16_t, + z0 = svsubr_n_s16_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_s16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_m_untied, svint16_t, + z0 = svsubr_n_s16_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_s16_m: +** mov (z[0-9]+\.h), #-2 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_s16_m, svint16_t, + z0 = svsubr_n_s16_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_s16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_z_tied1, svint16_t, + z0 = svsubr_s16_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_s16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_z_tied2, svint16_t, + z0 = svsubr_s16_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_s16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_s16_z_untied, svint16_t, + z0 = svsubr_s16_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_s16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_z_tied1, svint16_t, int16_t, + z0 = svsubr_n_s16_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_s16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_z_untied, svint16_t, int16_t, + z0 = svsubr_n_s16_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_s16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_z_tied1, svint16_t, + z0 = svsubr_n_s16_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_s16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_z_untied, svint16_t, + z0 = svsubr_n_s16_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_s16_x_tied1: +** sub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_x_tied1, svint16_t, + z0 = svsubr_s16_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_s16_x_tied2: +** sub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_x_tied2, svint16_t, + z0 = svsubr_s16_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_s16_x_untied: +** sub z0\.h, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_s16_x_untied, svint16_t, + z0 = svsubr_s16_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_s16_x_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_x_tied1, svint16_t, int16_t, + z0 = svsubr_n_s16_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_s16_x_untied: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s16_x_untied, svint16_t, int16_t, + z0 = svsubr_n_s16_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_s16_x_tied1: +** subr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_x_tied1, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_s16_x_untied: +** movprfx z0, z1 +** subr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s16_x_untied, svint16_t, + z0 = svsubr_n_s16_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_s16_x: +** subr z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_s16_x: +** subr z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_s16_x: +** subr z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_s16_x: +** subr z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_257_s16_x: +** mov (z[0-9]+)\.b, #1 +** sub z0\.h, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_257_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 257), + z0 = svsubr_x (p0, z0, 257)) + +/* +** subr_512_s16_x: +** subr z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_s16_x: +** subr z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_s16_x, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_m1_s16_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.h, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s16_x_tied1, svint16_t, + z0 = svsubr_n_s16_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_s16_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.h, \1\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s16_x_untied, svint16_t, + z0 = svsubr_n_s16_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s32.c new file mode 100644 index 00000000000..ce62e2f210a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s32.c @@ -0,0 +1,344 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_s32_m_tied1: +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_m_tied1, svint32_t, + z0 = svsubr_s32_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_s32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_m_tied2, svint32_t, + z0 = svsubr_s32_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_s32_m_untied: +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_m_untied, svint32_t, + z0 = svsubr_s32_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_s32_m_tied1: +** mov (z[0-9]+\.s), w0 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_m_tied1, svint32_t, int32_t, + z0 = svsubr_n_s32_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_s32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_m_untied, svint32_t, int32_t, + z0 = svsubr_n_s32_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_s32_m_tied1: +** mov (z[0-9]+\.s), #1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_m_tied1, svint32_t, + z0 = svsubr_n_s32_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_s32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_m_untied, svint32_t, + z0 = svsubr_n_s32_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_s32_m: +** mov (z[0-9]+\.s), #-2 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_s32_m, svint32_t, + z0 = svsubr_n_s32_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_s32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_z_tied1, svint32_t, + z0 = svsubr_s32_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_s32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_z_tied2, svint32_t, + z0 = svsubr_s32_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_s32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_s32_z_untied, svint32_t, + z0 = svsubr_s32_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_s32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_z_tied1, svint32_t, int32_t, + z0 = svsubr_n_s32_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_s32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_z_untied, svint32_t, int32_t, + z0 = svsubr_n_s32_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_s32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_z_tied1, svint32_t, + z0 = svsubr_n_s32_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_s32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_z_untied, svint32_t, + z0 = svsubr_n_s32_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_s32_x_tied1: +** sub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_x_tied1, svint32_t, + z0 = svsubr_s32_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_s32_x_tied2: +** sub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_x_tied2, svint32_t, + z0 = svsubr_s32_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_s32_x_untied: +** sub z0\.s, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_s32_x_untied, svint32_t, + z0 = svsubr_s32_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_s32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_x_tied1, svint32_t, int32_t, + z0 = svsubr_n_s32_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_s32_x_untied: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s32_x_untied, svint32_t, int32_t, + z0 = svsubr_n_s32_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_s32_x_tied1: +** subr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_x_tied1, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_s32_x_untied: +** movprfx z0, z1 +** subr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s32_x_untied, svint32_t, + z0 = svsubr_n_s32_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_s32_x: +** subr z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_s32_x: +** subr z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_s32_x: +** subr z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_s32_x: +** subr z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_511_s32_x: +** mov (z[0-9]+\.s), #511 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_511_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 511), + z0 = svsubr_x (p0, z0, 511)) + +/* +** subr_512_s32_x: +** subr z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_s32_x: +** subr z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_65535_s32_x: +** mov (z[0-9]+\.s), #65535 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_65535_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 65535), + z0 = svsubr_x (p0, z0, 65535)) + +/* +** subr_65536_s32_x: +** mov (z[0-9]+\.s), #65536 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_65536_s32_x, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, 65536), + z0 = svsubr_x (p0, z0, 65536)) + +/* +** subr_m1_s32_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.s, \1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s32_x_tied1, svint32_t, + z0 = svsubr_n_s32_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_s32_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.s, \1\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s32_x_untied, svint32_t, + z0 = svsubr_n_s32_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s64.c new file mode 100644 index 00000000000..ada9e977c99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s64.c @@ -0,0 +1,344 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_s64_m_tied1: +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_m_tied1, svint64_t, + z0 = svsubr_s64_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_s64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_s64_m_tied2, svint64_t, + z0 = svsubr_s64_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_s64_m_untied: +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_m_untied, svint64_t, + z0 = svsubr_s64_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_x0_s64_m_tied1: +** mov (z[0-9]+\.d), x0 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_m_tied1, svint64_t, int64_t, + z0 = svsubr_n_s64_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_x0_s64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_m_untied, svint64_t, int64_t, + z0 = svsubr_n_s64_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_s64_m_tied1: +** mov (z[0-9]+\.d), #1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_m_tied1, svint64_t, + z0 = svsubr_n_s64_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_s64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_m_untied, svint64_t, + z0 = svsubr_n_s64_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_s64_m: +** mov (z[0-9]+\.d), #-2 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_s64_m, svint64_t, + z0 = svsubr_n_s64_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_s64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_z_tied1, svint64_t, + z0 = svsubr_s64_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_s64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_z_tied2, svint64_t, + z0 = svsubr_s64_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_s64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_s64_z_untied, svint64_t, + z0 = svsubr_s64_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_x0_s64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_z_tied1, svint64_t, int64_t, + z0 = svsubr_n_s64_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_x0_s64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_z_untied, svint64_t, int64_t, + z0 = svsubr_n_s64_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_s64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_z_tied1, svint64_t, + z0 = svsubr_n_s64_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_s64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_z_untied, svint64_t, + z0 = svsubr_n_s64_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_s64_x_tied1: +** sub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_x_tied1, svint64_t, + z0 = svsubr_s64_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_s64_x_tied2: +** sub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_x_tied2, svint64_t, + z0 = svsubr_s64_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_s64_x_untied: +** sub z0\.d, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_s64_x_untied, svint64_t, + z0 = svsubr_s64_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_x0_s64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_x_tied1, svint64_t, int64_t, + z0 = svsubr_n_s64_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_x0_s64_x_untied: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_s64_x_untied, svint64_t, int64_t, + z0 = svsubr_n_s64_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_s64_x_tied1: +** subr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_x_tied1, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_s64_x_untied: +** movprfx z0, z1 +** subr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s64_x_untied, svint64_t, + z0 = svsubr_n_s64_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_s64_x: +** subr z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_s64_x: +** subr z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_s64_x: +** subr z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_s64_x: +** subr z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_511_s64_x: +** mov (z[0-9]+\.d), #511 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_511_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 511), + z0 = svsubr_x (p0, z0, 511)) + +/* +** subr_512_s64_x: +** subr z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_s64_x: +** subr z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_65535_s64_x: +** mov (z[0-9]+\.d), #65535 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_65535_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 65535), + z0 = svsubr_x (p0, z0, 65535)) + +/* +** subr_65536_s64_x: +** mov (z[0-9]+\.d), #65536 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_65536_s64_x, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, 65536), + z0 = svsubr_x (p0, z0, 65536)) + +/* +** subr_m1_s64_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.d, \1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s64_x_tied1, svint64_t, + z0 = svsubr_n_s64_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_s64_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.d, \1\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s64_x_untied, svint64_t, + z0 = svsubr_n_s64_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c new file mode 100644 index 00000000000..90d2a6de9a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_s8_m_tied1: +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_m_tied1, svint8_t, + z0 = svsubr_s8_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_s8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_m_tied2, svint8_t, + z0 = svsubr_s8_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_s8_m_untied: +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_m_untied, svint8_t, + z0 = svsubr_s8_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_s8_m_tied1: +** mov (z[0-9]+\.b), w0 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_m_tied1, svint8_t, int8_t, + z0 = svsubr_n_s8_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_m_untied, svint8_t, int8_t, + z0 = svsubr_n_s8_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_s8_m_tied1: +** mov (z[0-9]+\.b), #1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_m_tied1, svint8_t, + z0 = svsubr_n_s8_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_s8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_m_untied, svint8_t, + z0 = svsubr_n_s8_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m1_s8_m: +** mov (z[0-9]+\.b), #-1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s8_m, svint8_t, + z0 = svsubr_n_s8_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_s8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_z_tied1, svint8_t, + z0 = svsubr_s8_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_s8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_z_tied2, svint8_t, + z0 = svsubr_s8_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_s8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_s8_z_untied, svint8_t, + z0 = svsubr_s8_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_s8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_z_tied1, svint8_t, int8_t, + z0 = svsubr_n_s8_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_s8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_z_untied, svint8_t, int8_t, + z0 = svsubr_n_s8_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_s8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_z_tied1, svint8_t, + z0 = svsubr_n_s8_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_s8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_z_untied, svint8_t, + z0 = svsubr_n_s8_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_s8_x_tied1: +** sub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_x_tied1, svint8_t, + z0 = svsubr_s8_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_s8_x_tied2: +** sub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_x_tied2, svint8_t, + z0 = svsubr_s8_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_s8_x_untied: +** sub z0\.b, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_s8_x_untied, svint8_t, + z0 = svsubr_s8_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_s8_x_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, \1, z0\.b +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_x_tied1, svint8_t, int8_t, + z0 = svsubr_n_s8_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_s8_x_untied: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_s8_x_untied, svint8_t, int8_t, + z0 = svsubr_n_s8_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_s8_x_tied1: +** subr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_x_tied1, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_s8_x_untied: +** movprfx z0, z1 +** subr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_s8_x_untied, svint8_t, + z0 = svsubr_n_s8_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_s8_x: +** subr z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_s8_x: +** subr z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_s8_x: +** subr z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_m1_s8_x: +** subr z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m127_s8_x: +** subr z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (subr_m127_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, -127), + z0 = svsubr_x (p0, z0, -127)) + +/* +** subr_m128_s8_x: +** subr z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_m128_s8_x, svint8_t, + z0 = svsubr_n_s8_x (p0, z0, -128), + z0 = svsubr_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c new file mode 100644 index 00000000000..379a80fb189 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c @@ -0,0 +1,324 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_u16_m_tied1: +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_m_tied1, svuint16_t, + z0 = svsubr_u16_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_u16_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_m_tied2, svuint16_t, + z0 = svsubr_u16_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_u16_m_untied: +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_m_untied, svuint16_t, + z0 = svsubr_u16_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_u16_m_tied1: +** mov (z[0-9]+\.h), w0 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_m_tied1, svuint16_t, uint16_t, + z0 = svsubr_n_u16_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), w0 +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_m_untied, svuint16_t, uint16_t, + z0 = svsubr_n_u16_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_u16_m_tied1: +** mov (z[0-9]+\.h), #1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_m_tied1, svuint16_t, + z0 = svsubr_n_u16_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_u16_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.h), #1 +** movprfx z0, z1 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_m_untied, svuint16_t, + z0 = svsubr_n_u16_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_u16_m: +** mov (z[0-9]+\.h), #-2 +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_u16_m, svuint16_t, + z0 = svsubr_n_u16_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_u16_z_tied1: +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_z_tied1, svuint16_t, + z0 = svsubr_u16_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_u16_z_tied2: +** movprfx z0\.h, p0/z, z0\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_z_tied2, svuint16_t, + z0 = svsubr_u16_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_u16_z_untied: +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, z2\.h +** | +** movprfx z0\.h, p0/z, z2\.h +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_u16_z_untied, svuint16_t, + z0 = svsubr_u16_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_u16_z_tied1: +** mov (z[0-9]+\.h), w0 +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_z_tied1, svuint16_t, uint16_t, + z0 = svsubr_n_u16_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_u16_z_untied: +** mov (z[0-9]+\.h), w0 +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_z_untied, svuint16_t, uint16_t, + z0 = svsubr_n_u16_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_u16_z_tied1: +** mov (z[0-9]+\.h), #1 +** movprfx z0\.h, p0/z, z0\.h +** subr z0\.h, p0/m, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_z_tied1, svuint16_t, + z0 = svsubr_n_u16_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_u16_z_untied: +** mov (z[0-9]+\.h), #1 +** ( +** movprfx z0\.h, p0/z, z1\.h +** subr z0\.h, p0/m, z0\.h, \1 +** | +** movprfx z0\.h, p0/z, \1 +** sub z0\.h, p0/m, z0\.h, z1\.h +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_z_untied, svuint16_t, + z0 = svsubr_n_u16_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_u16_x_tied1: +** sub z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_x_tied1, svuint16_t, + z0 = svsubr_u16_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_u16_x_tied2: +** sub z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_x_tied2, svuint16_t, + z0 = svsubr_u16_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_u16_x_untied: +** sub z0\.h, z2\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_u16_x_untied, svuint16_t, + z0 = svsubr_u16_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_u16_x_tied1: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, \1, z0\.h +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_x_tied1, svuint16_t, uint16_t, + z0 = svsubr_n_u16_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_u16_x_untied: +** mov (z[0-9]+\.h), w0 +** sub z0\.h, \1, z1\.h +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u16_x_untied, svuint16_t, uint16_t, + z0 = svsubr_n_u16_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_u16_x_tied1: +** subr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_x_tied1, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_u16_x_untied: +** movprfx z0, z1 +** subr z0\.h, z0\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u16_x_untied, svuint16_t, + z0 = svsubr_n_u16_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_u16_x: +** subr z0\.h, z0\.h, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_u16_x: +** subr z0\.h, z0\.h, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_u16_x: +** subr z0\.h, z0\.h, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_u16_x: +** subr z0\.h, z0\.h, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_257_u16_x: +** mov (z[0-9]+)\.b, #1 +** sub z0\.h, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_257_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 257), + z0 = svsubr_x (p0, z0, 257)) + +/* +** subr_512_u16_x: +** subr z0\.h, z0\.h, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_u16_x: +** subr z0\.h, z0\.h, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_u16_x, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_m1_u16_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.h, \1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u16_x_tied1, svuint16_t, + z0 = svsubr_n_u16_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_u16_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.h, \1\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u16_x_untied, svuint16_t, + z0 = svsubr_n_u16_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u32.c new file mode 100644 index 00000000000..215f8b44922 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u32.c @@ -0,0 +1,344 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_u32_m_tied1: +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_m_tied1, svuint32_t, + z0 = svsubr_u32_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_u32_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_m_tied2, svuint32_t, + z0 = svsubr_u32_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_u32_m_untied: +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_m_untied, svuint32_t, + z0 = svsubr_u32_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_u32_m_tied1: +** mov (z[0-9]+\.s), w0 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_m_tied1, svuint32_t, uint32_t, + z0 = svsubr_n_u32_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_u32_m_untied: +** mov (z[0-9]+\.s), w0 +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_m_untied, svuint32_t, uint32_t, + z0 = svsubr_n_u32_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_u32_m_tied1: +** mov (z[0-9]+\.s), #1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_m_tied1, svuint32_t, + z0 = svsubr_n_u32_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_u32_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.s), #1 +** movprfx z0, z1 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_m_untied, svuint32_t, + z0 = svsubr_n_u32_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_u32_m: +** mov (z[0-9]+\.s), #-2 +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_u32_m, svuint32_t, + z0 = svsubr_n_u32_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_u32_z_tied1: +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_z_tied1, svuint32_t, + z0 = svsubr_u32_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_u32_z_tied2: +** movprfx z0\.s, p0/z, z0\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_z_tied2, svuint32_t, + z0 = svsubr_u32_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_u32_z_untied: +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, z2\.s +** | +** movprfx z0\.s, p0/z, z2\.s +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_u32_z_untied, svuint32_t, + z0 = svsubr_u32_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_u32_z_tied1: +** mov (z[0-9]+\.s), w0 +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_z_tied1, svuint32_t, uint32_t, + z0 = svsubr_n_u32_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_u32_z_untied: +** mov (z[0-9]+\.s), w0 +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_z_untied, svuint32_t, uint32_t, + z0 = svsubr_n_u32_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_u32_z_tied1: +** mov (z[0-9]+\.s), #1 +** movprfx z0\.s, p0/z, z0\.s +** subr z0\.s, p0/m, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_z_tied1, svuint32_t, + z0 = svsubr_n_u32_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_u32_z_untied: +** mov (z[0-9]+\.s), #1 +** ( +** movprfx z0\.s, p0/z, z1\.s +** subr z0\.s, p0/m, z0\.s, \1 +** | +** movprfx z0\.s, p0/z, \1 +** sub z0\.s, p0/m, z0\.s, z1\.s +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_z_untied, svuint32_t, + z0 = svsubr_n_u32_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_u32_x_tied1: +** sub z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_x_tied1, svuint32_t, + z0 = svsubr_u32_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_u32_x_tied2: +** sub z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_x_tied2, svuint32_t, + z0 = svsubr_u32_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_u32_x_untied: +** sub z0\.s, z2\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_u32_x_untied, svuint32_t, + z0 = svsubr_u32_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_u32_x_tied1: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_x_tied1, svuint32_t, uint32_t, + z0 = svsubr_n_u32_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_u32_x_untied: +** mov (z[0-9]+\.s), w0 +** sub z0\.s, \1, z1\.s +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u32_x_untied, svuint32_t, uint32_t, + z0 = svsubr_n_u32_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_u32_x_tied1: +** subr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_x_tied1, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_u32_x_untied: +** movprfx z0, z1 +** subr z0\.s, z0\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u32_x_untied, svuint32_t, + z0 = svsubr_n_u32_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_u32_x: +** subr z0\.s, z0\.s, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_u32_x: +** subr z0\.s, z0\.s, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_u32_x: +** subr z0\.s, z0\.s, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_u32_x: +** subr z0\.s, z0\.s, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_511_u32_x: +** mov (z[0-9]+\.s), #511 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_511_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 511), + z0 = svsubr_x (p0, z0, 511)) + +/* +** subr_512_u32_x: +** subr z0\.s, z0\.s, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_u32_x: +** subr z0\.s, z0\.s, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_65535_u32_x: +** mov (z[0-9]+\.s), #65535 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_65535_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 65535), + z0 = svsubr_x (p0, z0, 65535)) + +/* +** subr_65536_u32_x: +** mov (z[0-9]+\.s), #65536 +** sub z0\.s, \1, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_65536_u32_x, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, 65536), + z0 = svsubr_x (p0, z0, 65536)) + +/* +** subr_m1_u32_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.s, \1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u32_x_tied1, svuint32_t, + z0 = svsubr_n_u32_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_u32_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.s, \1\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u32_x_untied, svuint32_t, + z0 = svsubr_n_u32_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u64.c new file mode 100644 index 00000000000..78d94515bd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u64.c @@ -0,0 +1,344 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_u64_m_tied1: +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_m_tied1, svuint64_t, + z0 = svsubr_u64_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_u64_m_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_u64_m_tied2, svuint64_t, + z0 = svsubr_u64_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_u64_m_untied: +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_m_untied, svuint64_t, + z0 = svsubr_u64_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_x0_u64_m_tied1: +** mov (z[0-9]+\.d), x0 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_m_tied1, svuint64_t, uint64_t, + z0 = svsubr_n_u64_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_x0_u64_m_untied: +** mov (z[0-9]+\.d), x0 +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_m_untied, svuint64_t, uint64_t, + z0 = svsubr_n_u64_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_u64_m_tied1: +** mov (z[0-9]+\.d), #1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_m_tied1, svuint64_t, + z0 = svsubr_n_u64_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_u64_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.d), #1 +** movprfx z0, z1 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_m_untied, svuint64_t, + z0 = svsubr_n_u64_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m2_u64_m: +** mov (z[0-9]+\.d), #-2 +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m2_u64_m, svuint64_t, + z0 = svsubr_n_u64_m (p0, z0, -2), + z0 = svsubr_m (p0, z0, -2)) + +/* +** subr_u64_z_tied1: +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_z_tied1, svuint64_t, + z0 = svsubr_u64_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_u64_z_tied2: +** movprfx z0\.d, p0/z, z0\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_z_tied2, svuint64_t, + z0 = svsubr_u64_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_u64_z_untied: +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, z2\.d +** | +** movprfx z0\.d, p0/z, z2\.d +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_u64_z_untied, svuint64_t, + z0 = svsubr_u64_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_x0_u64_z_tied1: +** mov (z[0-9]+\.d), x0 +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_z_tied1, svuint64_t, uint64_t, + z0 = svsubr_n_u64_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_x0_u64_z_untied: +** mov (z[0-9]+\.d), x0 +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_z_untied, svuint64_t, uint64_t, + z0 = svsubr_n_u64_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_u64_z_tied1: +** mov (z[0-9]+\.d), #1 +** movprfx z0\.d, p0/z, z0\.d +** subr z0\.d, p0/m, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_z_tied1, svuint64_t, + z0 = svsubr_n_u64_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_u64_z_untied: +** mov (z[0-9]+\.d), #1 +** ( +** movprfx z0\.d, p0/z, z1\.d +** subr z0\.d, p0/m, z0\.d, \1 +** | +** movprfx z0\.d, p0/z, \1 +** sub z0\.d, p0/m, z0\.d, z1\.d +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_z_untied, svuint64_t, + z0 = svsubr_n_u64_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_u64_x_tied1: +** sub z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_x_tied1, svuint64_t, + z0 = svsubr_u64_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_u64_x_tied2: +** sub z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_x_tied2, svuint64_t, + z0 = svsubr_u64_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_u64_x_untied: +** sub z0\.d, z2\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_u64_x_untied, svuint64_t, + z0 = svsubr_u64_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_x0_u64_x_tied1: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_x_tied1, svuint64_t, uint64_t, + z0 = svsubr_n_u64_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_x0_u64_x_untied: +** mov (z[0-9]+\.d), x0 +** sub z0\.d, \1, z1\.d +** ret +*/ +TEST_UNIFORM_ZX (subr_x0_u64_x_untied, svuint64_t, uint64_t, + z0 = svsubr_n_u64_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_u64_x_tied1: +** subr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_x_tied1, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_u64_x_untied: +** movprfx z0, z1 +** subr z0\.d, z0\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u64_x_untied, svuint64_t, + z0 = svsubr_n_u64_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_u64_x: +** subr z0\.d, z0\.d, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_u64_x: +** subr z0\.d, z0\.d, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_u64_x: +** subr z0\.d, z0\.d, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_256_u64_x: +** subr z0\.d, z0\.d, #256 +** ret +*/ +TEST_UNIFORM_Z (subr_256_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 256), + z0 = svsubr_x (p0, z0, 256)) + +/* +** subr_511_u64_x: +** mov (z[0-9]+\.d), #511 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_511_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 511), + z0 = svsubr_x (p0, z0, 511)) + +/* +** subr_512_u64_x: +** subr z0\.d, z0\.d, #512 +** ret +*/ +TEST_UNIFORM_Z (subr_512_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 512), + z0 = svsubr_x (p0, z0, 512)) + +/* +** subr_65280_u64_x: +** subr z0\.d, z0\.d, #65280 +** ret +*/ +TEST_UNIFORM_Z (subr_65280_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 0xff00), + z0 = svsubr_x (p0, z0, 0xff00)) + +/* +** subr_65535_u64_x: +** mov (z[0-9]+\.d), #65535 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_65535_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 65535), + z0 = svsubr_x (p0, z0, 65535)) + +/* +** subr_65536_u64_x: +** mov (z[0-9]+\.d), #65536 +** sub z0\.d, \1, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_65536_u64_x, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, 65536), + z0 = svsubr_x (p0, z0, 65536)) + +/* +** subr_m1_u64_x_tied1: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.d, \1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u64_x_tied1, svuint64_t, + z0 = svsubr_n_u64_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m1_u64_x_untied: +** mov (z[0-9]+)\.b, #-1 +** sub z0\.d, \1\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u64_x_untied, svuint64_t, + z0 = svsubr_n_u64_x (p0, z1, -1), + z0 = svsubr_x (p0, z1, -1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c new file mode 100644 index 00000000000..fe5f96da833 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c @@ -0,0 +1,294 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** subr_u8_m_tied1: +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_m_tied1, svuint8_t, + z0 = svsubr_u8_m (p0, z0, z1), + z0 = svsubr_m (p0, z0, z1)) + +/* +** subr_u8_m_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_m_tied2, svuint8_t, + z0 = svsubr_u8_m (p0, z1, z0), + z0 = svsubr_m (p0, z1, z0)) + +/* +** subr_u8_m_untied: +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_m_untied, svuint8_t, + z0 = svsubr_u8_m (p0, z1, z2), + z0 = svsubr_m (p0, z1, z2)) + +/* +** subr_w0_u8_m_tied1: +** mov (z[0-9]+\.b), w0 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_m_tied1, svuint8_t, uint8_t, + z0 = svsubr_n_u8_m (p0, z0, x0), + z0 = svsubr_m (p0, z0, x0)) + +/* +** subr_w0_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), w0 +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_m_untied, svuint8_t, uint8_t, + z0 = svsubr_n_u8_m (p0, z1, x0), + z0 = svsubr_m (p0, z1, x0)) + +/* +** subr_1_u8_m_tied1: +** mov (z[0-9]+\.b), #1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_m_tied1, svuint8_t, + z0 = svsubr_n_u8_m (p0, z0, 1), + z0 = svsubr_m (p0, z0, 1)) + +/* +** subr_1_u8_m_untied: { xfail *-*-* } +** mov (z[0-9]+\.b), #1 +** movprfx z0, z1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_m_untied, svuint8_t, + z0 = svsubr_n_u8_m (p0, z1, 1), + z0 = svsubr_m (p0, z1, 1)) + +/* +** subr_m1_u8_m: +** mov (z[0-9]+\.b), #-1 +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u8_m, svuint8_t, + z0 = svsubr_n_u8_m (p0, z0, -1), + z0 = svsubr_m (p0, z0, -1)) + +/* +** subr_u8_z_tied1: +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_z_tied1, svuint8_t, + z0 = svsubr_u8_z (p0, z0, z1), + z0 = svsubr_z (p0, z0, z1)) + +/* +** subr_u8_z_tied2: +** movprfx z0\.b, p0/z, z0\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_z_tied2, svuint8_t, + z0 = svsubr_u8_z (p0, z1, z0), + z0 = svsubr_z (p0, z1, z0)) + +/* +** subr_u8_z_untied: +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, z2\.b +** | +** movprfx z0\.b, p0/z, z2\.b +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_u8_z_untied, svuint8_t, + z0 = svsubr_u8_z (p0, z1, z2), + z0 = svsubr_z (p0, z1, z2)) + +/* +** subr_w0_u8_z_tied1: +** mov (z[0-9]+\.b), w0 +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_z_tied1, svuint8_t, uint8_t, + z0 = svsubr_n_u8_z (p0, z0, x0), + z0 = svsubr_z (p0, z0, x0)) + +/* +** subr_w0_u8_z_untied: +** mov (z[0-9]+\.b), w0 +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_z_untied, svuint8_t, uint8_t, + z0 = svsubr_n_u8_z (p0, z1, x0), + z0 = svsubr_z (p0, z1, x0)) + +/* +** subr_1_u8_z_tied1: +** mov (z[0-9]+\.b), #1 +** movprfx z0\.b, p0/z, z0\.b +** subr z0\.b, p0/m, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_z_tied1, svuint8_t, + z0 = svsubr_n_u8_z (p0, z0, 1), + z0 = svsubr_z (p0, z0, 1)) + +/* +** subr_1_u8_z_untied: +** mov (z[0-9]+\.b), #1 +** ( +** movprfx z0\.b, p0/z, z1\.b +** subr z0\.b, p0/m, z0\.b, \1 +** | +** movprfx z0\.b, p0/z, \1 +** sub z0\.b, p0/m, z0\.b, z1\.b +** ) +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_z_untied, svuint8_t, + z0 = svsubr_n_u8_z (p0, z1, 1), + z0 = svsubr_z (p0, z1, 1)) + +/* +** subr_u8_x_tied1: +** sub z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_x_tied1, svuint8_t, + z0 = svsubr_u8_x (p0, z0, z1), + z0 = svsubr_x (p0, z0, z1)) + +/* +** subr_u8_x_tied2: +** sub z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_x_tied2, svuint8_t, + z0 = svsubr_u8_x (p0, z1, z0), + z0 = svsubr_x (p0, z1, z0)) + +/* +** subr_u8_x_untied: +** sub z0\.b, z2\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (subr_u8_x_untied, svuint8_t, + z0 = svsubr_u8_x (p0, z1, z2), + z0 = svsubr_x (p0, z1, z2)) + +/* +** subr_w0_u8_x_tied1: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, \1, z0\.b +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_x_tied1, svuint8_t, uint8_t, + z0 = svsubr_n_u8_x (p0, z0, x0), + z0 = svsubr_x (p0, z0, x0)) + +/* +** subr_w0_u8_x_untied: +** mov (z[0-9]+\.b), w0 +** sub z0\.b, \1, z1\.b +** ret +*/ +TEST_UNIFORM_ZX (subr_w0_u8_x_untied, svuint8_t, uint8_t, + z0 = svsubr_n_u8_x (p0, z1, x0), + z0 = svsubr_x (p0, z1, x0)) + +/* +** subr_1_u8_x_tied1: +** subr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_x_tied1, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, 1), + z0 = svsubr_x (p0, z0, 1)) + +/* +** subr_1_u8_x_untied: +** movprfx z0, z1 +** subr z0\.b, z0\.b, #1 +** ret +*/ +TEST_UNIFORM_Z (subr_1_u8_x_untied, svuint8_t, + z0 = svsubr_n_u8_x (p0, z1, 1), + z0 = svsubr_x (p0, z1, 1)) + +/* +** subr_127_u8_x: +** subr z0\.b, z0\.b, #127 +** ret +*/ +TEST_UNIFORM_Z (subr_127_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, 127), + z0 = svsubr_x (p0, z0, 127)) + +/* +** subr_128_u8_x: +** subr z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_128_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, 128), + z0 = svsubr_x (p0, z0, 128)) + +/* +** subr_255_u8_x: +** subr z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_255_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, 255), + z0 = svsubr_x (p0, z0, 255)) + +/* +** subr_m1_u8_x: +** subr z0\.b, z0\.b, #255 +** ret +*/ +TEST_UNIFORM_Z (subr_m1_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, -1), + z0 = svsubr_x (p0, z0, -1)) + +/* +** subr_m127_u8_x: +** subr z0\.b, z0\.b, #129 +** ret +*/ +TEST_UNIFORM_Z (subr_m127_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, -127), + z0 = svsubr_x (p0, z0, -127)) + +/* +** subr_m128_u8_x: +** subr z0\.b, z0\.b, #128 +** ret +*/ +TEST_UNIFORM_Z (subr_m128_u8_x, svuint8_t, + z0 = svsubr_n_u8_x (p0, z0, -128), + z0 = svsubr_x (p0, z0, -128)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f16.c new file mode 100644 index 00000000000..94b6104123d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_f16_tied1: +** tbl z0\.h, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_f16_tied1, svfloat16_t, svuint16_t, + z0 = svtbl_f16 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_f16_tied2: +** tbl z0\.h, z4\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (tbl_f16_tied2, svfloat16_t, svuint16_t, + z0_res = svtbl_f16 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_f16_untied: +** tbl z0\.h, z1\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_f16_untied, svfloat16_t, svuint16_t, + z0 = svtbl_f16 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f32.c new file mode 100644 index 00000000000..741d3bdcf72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_f32_tied1: +** tbl z0\.s, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_f32_tied1, svfloat32_t, svuint32_t, + z0 = svtbl_f32 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_f32_tied2: +** tbl z0\.s, z4\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (tbl_f32_tied2, svfloat32_t, svuint32_t, + z0_res = svtbl_f32 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_f32_untied: +** tbl z0\.s, z1\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_f32_untied, svfloat32_t, svuint32_t, + z0 = svtbl_f32 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f64.c new file mode 100644 index 00000000000..3c24e9a59e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_f64_tied1: +** tbl z0\.d, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_f64_tied1, svfloat64_t, svuint64_t, + z0 = svtbl_f64 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_f64_tied2: +** tbl z0\.d, z4\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (tbl_f64_tied2, svfloat64_t, svuint64_t, + z0_res = svtbl_f64 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_f64_untied: +** tbl z0\.d, z1\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_f64_untied, svfloat64_t, svuint64_t, + z0 = svtbl_f64 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s16.c new file mode 100644 index 00000000000..2ec9c389a01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_s16_tied1: +** tbl z0\.h, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_s16_tied1, svint16_t, svuint16_t, + z0 = svtbl_s16 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_s16_tied2: +** tbl z0\.h, z4\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (tbl_s16_tied2, svint16_t, svuint16_t, + z0_res = svtbl_s16 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_s16_untied: +** tbl z0\.h, z1\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_s16_untied, svint16_t, svuint16_t, + z0 = svtbl_s16 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s32.c new file mode 100644 index 00000000000..98b2d8d8bc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_s32_tied1: +** tbl z0\.s, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_s32_tied1, svint32_t, svuint32_t, + z0 = svtbl_s32 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_s32_tied2: +** tbl z0\.s, z4\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (tbl_s32_tied2, svint32_t, svuint32_t, + z0_res = svtbl_s32 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_s32_untied: +** tbl z0\.s, z1\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_s32_untied, svint32_t, svuint32_t, + z0 = svtbl_s32 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s64.c new file mode 100644 index 00000000000..0138a80d2e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_s64_tied1: +** tbl z0\.d, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_s64_tied1, svint64_t, svuint64_t, + z0 = svtbl_s64 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_s64_tied2: +** tbl z0\.d, z4\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (tbl_s64_tied2, svint64_t, svuint64_t, + z0_res = svtbl_s64 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_s64_untied: +** tbl z0\.d, z1\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_s64_untied, svint64_t, svuint64_t, + z0 = svtbl_s64 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s8.c new file mode 100644 index 00000000000..7818d1b6d58 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_s8_tied1: +** tbl z0\.b, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (tbl_s8_tied1, svint8_t, svuint8_t, + z0 = svtbl_s8 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_s8_tied2: +** tbl z0\.b, z4\.b, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (tbl_s8_tied2, svint8_t, svuint8_t, + z0_res = svtbl_s8 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_s8_untied: +** tbl z0\.b, z1\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (tbl_s8_untied, svint8_t, svuint8_t, + z0 = svtbl_s8 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u16.c new file mode 100644 index 00000000000..f15da921162 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_u16_tied1: +** tbl z0\.h, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_u16_tied1, svuint16_t, svuint16_t, + z0 = svtbl_u16 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_u16_tied2: +** tbl z0\.h, z4\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (tbl_u16_tied2, svuint16_t, svuint16_t, + z0_res = svtbl_u16 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_u16_untied: +** tbl z0\.h, z1\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tbl_u16_untied, svuint16_t, svuint16_t, + z0 = svtbl_u16 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u32.c new file mode 100644 index 00000000000..494300436f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_u32_tied1: +** tbl z0\.s, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_u32_tied1, svuint32_t, svuint32_t, + z0 = svtbl_u32 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_u32_tied2: +** tbl z0\.s, z4\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (tbl_u32_tied2, svuint32_t, svuint32_t, + z0_res = svtbl_u32 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_u32_untied: +** tbl z0\.s, z1\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tbl_u32_untied, svuint32_t, svuint32_t, + z0 = svtbl_u32 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u64.c new file mode 100644 index 00000000000..158990e12c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_u64_tied1: +** tbl z0\.d, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_u64_tied1, svuint64_t, svuint64_t, + z0 = svtbl_u64 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_u64_tied2: +** tbl z0\.d, z4\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (tbl_u64_tied2, svuint64_t, svuint64_t, + z0_res = svtbl_u64 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_u64_untied: +** tbl z0\.d, z1\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tbl_u64_untied, svuint64_t, svuint64_t, + z0 = svtbl_u64 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u8.c new file mode 100644 index 00000000000..a46309a95f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tbl_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tbl_u8_tied1: +** tbl z0\.b, z0\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (tbl_u8_tied1, svuint8_t, svuint8_t, + z0 = svtbl_u8 (z0, z4), + z0 = svtbl (z0, z4)) + +/* +** tbl_u8_tied2: +** tbl z0\.b, z4\.b, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (tbl_u8_tied2, svuint8_t, svuint8_t, + z0_res = svtbl_u8 (z4, z0), + z0_res = svtbl (z4, z0)) + +/* +** tbl_u8_untied: +** tbl z0\.b, z1\.b, z4\.b +** ret +*/ +TEST_DUAL_Z (tbl_u8_untied, svuint8_t, svuint8_t, + z0 = svtbl_u8 (z1, z4), + z0 = svtbl (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h new file mode 100644 index 00000000000..8cc72915b05 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h @@ -0,0 +1,330 @@ +#ifndef TEST_SVE_ACLE_H +#define TEST_SVE_ACLE_H 1 + +#include + +#if defined (TEST_OVERLOADS) +#define INVOKE(CODE1, CODE2) CODE2 +#elif defined (TEST_FULL) +#define INVOKE(CODE1, CODE2) CODE1 +#else +#error "Please define -DTEST_OVERLOADS or -DTEST_FULL" +#endif + +#ifdef __cplusplus +#define PROTO(NAME, RET, ARGS) extern "C" RET NAME ARGS; RET NAME ARGS +#else +#define PROTO(NAME, RET, ARGS) RET NAME ARGS +#endif + +#define TEST_UNIFORM_Z(NAME, TYPE, CODE1, CODE2) \ + PROTO (NAME, TYPE, (TYPE z0, TYPE z1, TYPE z2, TYPE z3, \ + svbool_t p0, svbool_t p1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_UNIFORM_P(NAME, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (svbool_t p0, svbool_t p1, \ + svbool_t p2, svbool_t p3)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_UNIFORM_P_SINGLE(NAME, CODE) \ + PROTO (NAME, svbool_t, (svbool_t p0, svbool_t p1, \ + svbool_t p2, svbool_t p3)) \ + { \ + CODE; \ + return p0; \ + } + +#define TEST_UNIFORM_S(NAME, TYPE, CODE1, CODE2) \ + PROTO (NAME, TYPE, (TYPE x0, TYPE x1, TYPE x2, TYPE x3, \ + svbool_t p0, svbool_t p1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return x0; \ + } + +#define TEST_DUAL_Z(NAME, TYPE1, TYPE2, CODE1, CODE2) \ + PROTO (NAME, TYPE1, (TYPE1 z0, TYPE1 z1, TYPE1 z2, TYPE1 z3, \ + TYPE2 z4, TYPE2 z5, TYPE2 z6, TYPE2 z7, \ + svbool_t p0, svbool_t p1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_DUAL_Z_REV(NAME, TYPE1, TYPE2, CODE1, CODE2) \ + PROTO (NAME, TYPE1, (TYPE2 z0, TYPE2 z1, TYPE2 z2, TYPE2 z3, \ + TYPE1 z4, TYPE1 z5, TYPE1 z6, TYPE1 z7, \ + svbool_t p0, svbool_t p1)) \ + { \ + TYPE1 z0_res; \ + INVOKE (CODE1, CODE2); \ + return z0_res; \ + } + +#define TEST_DUAL_LANE_REG(NAME, ZTYPE1, ZTYPE2, REG, CODE1, CODE2) \ + PROTO (NAME, void, (void)) \ + { \ + register ZTYPE1 z0 __asm ("z0"); \ + register ZTYPE2 z1 __asm ("z1"); \ + register ZTYPE2 REG __asm (#REG); \ + __asm volatile ("" : "=w" (z0), "=w" (z1), "=w" (REG)); \ + INVOKE (CODE1, CODE2); \ + __asm volatile ("" :: "w" (z0)); \ + } + +#define TEST_UNIFORM_ZX(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, ZTYPE, (ZTYPE z0, ZTYPE z1, ZTYPE z2, ZTYPE z3, \ + svbool_t p0, STYPE x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_UNIFORM_ZD(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, ZTYPE, (ZTYPE z0, ZTYPE z1, ZTYPE z2, ZTYPE z3, \ + svbool_t p0, STYPE d4)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_UNIFORM_PS(NAME, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (svbool_t p0, svbool_t p1, \ + svbool_t p2, svbool_t p3, bool x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_DUAL_ZX(NAME, ZTYPE1, ZTYPE2, STYPE, CODE1, CODE2) \ + PROTO (NAME, ZTYPE1, (ZTYPE1 z0, ZTYPE1 z1, ZTYPE1 z2, \ + ZTYPE1 z3, ZTYPE2 z4, ZTYPE2 z5, \ + ZTYPE2 z6, ZTYPE2 z7, svbool_t p0, \ + svbool_t p1, STYPE x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_LOAD(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, ZTYPE, (svbool_t p0, const STYPE *x0, \ + intptr_t x1)) \ + { \ + ZTYPE z0; \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_LOAD_GATHER_SZ(NAME, RES_TYPE, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, RES_TYPE, (ZTYPE z0, ZTYPE z1, svbool_t p0, \ + const STYPE *x0)) \ + { \ + RES_TYPE z0_res; \ + INVOKE (CODE1, CODE2); \ + return z0_res; \ + } + +#define TEST_LOAD_GATHER_ZS(NAME, RES_TYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, RES_TYPE, (ZTYPE z0, ZTYPE z1, svbool_t p0, \ + int64_t x0)) \ + { \ + RES_TYPE z0_res; \ + INVOKE (CODE1, CODE2); \ + return z0_res; \ + } + +#define TEST_PREFETCH(NAME, STYPE, CODE1, CODE2) \ + PROTO (NAME, void, (svbool_t p0, const STYPE *x0, \ + intptr_t x1)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_PREFETCH_GATHER_SZ(NAME, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (ZTYPE z0, ZTYPE z1, svbool_t p0, \ + const void *x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_PREFETCH_GATHER_ZS(NAME, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (ZTYPE z0, ZTYPE z1, svbool_t p0, \ + int64_t x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_STORE(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, void, (ZTYPE z0, svbool_t p0, STYPE *x0, \ + intptr_t x1)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_STORE_SCATTER_SZ(NAME, DATA_TYPE, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (DATA_TYPE z0, ZTYPE z1, svbool_t p0, \ + STYPE *x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_STORE_SCATTER_ZS(NAME, DATA_TYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (DATA_TYPE z0, ZTYPE z1, svbool_t p0, \ + int64_t x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + } + +#define TEST_P(NAME, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (void)) \ + { \ + svbool_t p0; \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_PTEST(NAME, TYPE, CODE) \ + PROTO (NAME, TYPE, (svbool_t p0, svbool_t p1, svbool_t p2, \ + svbool_t p3, TYPE x0, TYPE x1)) \ + { \ + INVOKE (CODE, CODE); \ + return x0; \ + } + +#define TEST_COMPARE_S(NAME, TYPE, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (TYPE x0, TYPE x1)) \ + { \ + svbool_t p0; \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_COMPARE_Z(NAME, TYPE, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (TYPE z0, TYPE z1, \ + svbool_t p0, svbool_t p1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_COMPARE_ZX(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (ZTYPE z0, ZTYPE z1, svbool_t p0, \ + svbool_t p1, STYPE x0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_COMPARE_ZD(NAME, ZTYPE, STYPE, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (ZTYPE z0, ZTYPE z1, ZTYPE z2, \ + ZTYPE z3, svbool_t p0, svbool_t p1, \ + STYPE d4)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_COMPARE_DUAL_Z(NAME, TYPE1, TYPE2, CODE1, CODE2) \ + PROTO (NAME, svbool_t, (TYPE1 z0, TYPE2 z1, \ + svbool_t p0, svbool_t p1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return p0; \ + } + +#define TEST_REDUCTION_X(NAME, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, STYPE, (ZTYPE z0, ZTYPE z1, svbool_t p0)) \ + { \ + STYPE x0; \ + INVOKE (CODE1, CODE2); \ + return x0; \ + } + +#define TEST_REDUCTION_D(NAME, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, STYPE, (ZTYPE z0, ZTYPE z1, svbool_t p0)) \ + { \ + STYPE d0; \ + INVOKE (CODE1, CODE2); \ + return d0; \ + } + +#define TEST_FOLD_LEFT_D(NAME, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, STYPE, (STYPE d0, STYPE d1, ZTYPE z2, \ + svbool_t p0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return d0; \ + } + +#define TEST_FOLD_LEFT_X(NAME, STYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, STYPE, (STYPE x0, STYPE x1, ZTYPE z0, \ + svbool_t p0)) \ + { \ + INVOKE (CODE1, CODE2); \ + return x0; \ + } + +#define TEST_S(NAME, ZTYPE, STYPE, CODE) \ + PROTO (NAME, ZTYPE, (STYPE x0, STYPE x1)) \ + { \ + ZTYPE z0; \ + CODE; \ + return z0; \ + } + +#define TEST_ADR(NAME, TYPE1, TYPE2, CODE1, CODE2) \ + PROTO (NAME, TYPE1, (TYPE1 z0, TYPE2 z1)) \ + { \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_UNDEF(NAME, TYPE, CODE) \ + PROTO (NAME, TYPE, (void)) \ + { \ + TYPE z0; \ + CODE; \ + return z0; \ + } + +#define TEST_CREATE(NAME, TTYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, TTYPE, (ZTYPE unused0, ZTYPE unused1, \ + ZTYPE unused2, ZTYPE unused3, \ + ZTYPE z4, ZTYPE z5, ZTYPE z6, ZTYPE z7)) \ + { \ + TTYPE z0; \ + INVOKE (CODE1, CODE2); \ + return z0; \ + } + +#define TEST_GET(NAME, TTYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (ZTYPE unused0, ZTYPE unused1, \ + ZTYPE unused2, ZTYPE unused3, TTYPE z4)) \ + { \ + register ZTYPE z0 __asm ("z0"); \ + register ZTYPE z4_res __asm ("z4"); \ + register ZTYPE z5_res __asm ("z5"); \ + register ZTYPE z6_res __asm ("z6"); \ + register ZTYPE z7_res __asm ("z7"); \ + INVOKE (CODE1, CODE2); \ + __asm volatile ("" :: "w" (z0), "w" (z4_res), "w" (z5_res), \ + "w" (z6_res), "w" (z7_res)); \ + } + +#define TEST_SET(NAME, TTYPE, ZTYPE, CODE1, CODE2) \ + PROTO (NAME, void, (ZTYPE z0, ZTYPE z1, ZTYPE z2, ZTYPE z3, \ + TTYPE z4)) \ + { \ + register TTYPE z24 __asm ("z24"); \ + INVOKE (CODE1, CODE2); \ + __asm volatile ("" :: "w" (z4), "w" (z24)); \ + } + +#endif diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f16.c new file mode 100644 index 00000000000..3a00716e37f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f16.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tmad_0_f16_tied1: +** ftmad z0\.h, z0\.h, z1\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f16_tied1, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 0), + z0 = svtmad (z0, z1, 0)) + +/* +** tmad_0_f16_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ftmad z0\.h, z0\.h, \1\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f16_tied2, svfloat16_t, + z0 = svtmad_f16 (z1, z0, 0), + z0 = svtmad (z1, z0, 0)) + +/* +** tmad_0_f16_untied: +** movprfx z0, z1 +** ftmad z0\.h, z0\.h, z2\.h, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f16_untied, svfloat16_t, + z0 = svtmad_f16 (z1, z2, 0), + z0 = svtmad (z1, z2, 0)) + +/* +** tmad_1_f16: +** ftmad z0\.h, z0\.h, z1\.h, #1 +** ret +*/ +TEST_UNIFORM_Z (tmad_1_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 1), + z0 = svtmad (z0, z1, 1)) + +/* +** tmad_2_f16: +** ftmad z0\.h, z0\.h, z1\.h, #2 +** ret +*/ +TEST_UNIFORM_Z (tmad_2_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 2), + z0 = svtmad (z0, z1, 2)) + +/* +** tmad_3_f16: +** ftmad z0\.h, z0\.h, z1\.h, #3 +** ret +*/ +TEST_UNIFORM_Z (tmad_3_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 3), + z0 = svtmad (z0, z1, 3)) + +/* +** tmad_4_f16: +** ftmad z0\.h, z0\.h, z1\.h, #4 +** ret +*/ +TEST_UNIFORM_Z (tmad_4_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 4), + z0 = svtmad (z0, z1, 4)) + +/* +** tmad_5_f16: +** ftmad z0\.h, z0\.h, z1\.h, #5 +** ret +*/ +TEST_UNIFORM_Z (tmad_5_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 5), + z0 = svtmad (z0, z1, 5)) + +/* +** tmad_6_f16: +** ftmad z0\.h, z0\.h, z1\.h, #6 +** ret +*/ +TEST_UNIFORM_Z (tmad_6_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 6), + z0 = svtmad (z0, z1, 6)) + +/* +** tmad_7_f16: +** ftmad z0\.h, z0\.h, z1\.h, #7 +** ret +*/ +TEST_UNIFORM_Z (tmad_7_f16, svfloat16_t, + z0 = svtmad_f16 (z0, z1, 7), + z0 = svtmad (z0, z1, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f32.c new file mode 100644 index 00000000000..b73d420fbac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f32.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tmad_0_f32_tied1: +** ftmad z0\.s, z0\.s, z1\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f32_tied1, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 0), + z0 = svtmad (z0, z1, 0)) + +/* +** tmad_0_f32_tied2: +** mov (z[0-9]+)\.d, z0\.d +** movprfx z0, z1 +** ftmad z0\.s, z0\.s, \1\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f32_tied2, svfloat32_t, + z0 = svtmad_f32 (z1, z0, 0), + z0 = svtmad (z1, z0, 0)) + +/* +** tmad_0_f32_untied: +** movprfx z0, z1 +** ftmad z0\.s, z0\.s, z2\.s, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f32_untied, svfloat32_t, + z0 = svtmad_f32 (z1, z2, 0), + z0 = svtmad (z1, z2, 0)) + +/* +** tmad_1_f32: +** ftmad z0\.s, z0\.s, z1\.s, #1 +** ret +*/ +TEST_UNIFORM_Z (tmad_1_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 1), + z0 = svtmad (z0, z1, 1)) + +/* +** tmad_2_f32: +** ftmad z0\.s, z0\.s, z1\.s, #2 +** ret +*/ +TEST_UNIFORM_Z (tmad_2_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 2), + z0 = svtmad (z0, z1, 2)) + +/* +** tmad_3_f32: +** ftmad z0\.s, z0\.s, z1\.s, #3 +** ret +*/ +TEST_UNIFORM_Z (tmad_3_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 3), + z0 = svtmad (z0, z1, 3)) + +/* +** tmad_4_f32: +** ftmad z0\.s, z0\.s, z1\.s, #4 +** ret +*/ +TEST_UNIFORM_Z (tmad_4_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 4), + z0 = svtmad (z0, z1, 4)) + +/* +** tmad_5_f32: +** ftmad z0\.s, z0\.s, z1\.s, #5 +** ret +*/ +TEST_UNIFORM_Z (tmad_5_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 5), + z0 = svtmad (z0, z1, 5)) + +/* +** tmad_6_f32: +** ftmad z0\.s, z0\.s, z1\.s, #6 +** ret +*/ +TEST_UNIFORM_Z (tmad_6_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 6), + z0 = svtmad (z0, z1, 6)) + +/* +** tmad_7_f32: +** ftmad z0\.s, z0\.s, z1\.s, #7 +** ret +*/ +TEST_UNIFORM_Z (tmad_7_f32, svfloat32_t, + z0 = svtmad_f32 (z0, z1, 7), + z0 = svtmad (z0, z1, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f64.c new file mode 100644 index 00000000000..fc31928a6c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tmad_f64.c @@ -0,0 +1,96 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tmad_0_f64_tied1: +** ftmad z0\.d, z0\.d, z1\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f64_tied1, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 0), + z0 = svtmad (z0, z1, 0)) + +/* +** tmad_0_f64_tied2: +** mov (z[0-9]+\.d), z0\.d +** movprfx z0, z1 +** ftmad z0\.d, z0\.d, \1, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f64_tied2, svfloat64_t, + z0 = svtmad_f64 (z1, z0, 0), + z0 = svtmad (z1, z0, 0)) + +/* +** tmad_0_f64_untied: +** movprfx z0, z1 +** ftmad z0\.d, z0\.d, z2\.d, #0 +** ret +*/ +TEST_UNIFORM_Z (tmad_0_f64_untied, svfloat64_t, + z0 = svtmad_f64 (z1, z2, 0), + z0 = svtmad (z1, z2, 0)) + +/* +** tmad_1_f64: +** ftmad z0\.d, z0\.d, z1\.d, #1 +** ret +*/ +TEST_UNIFORM_Z (tmad_1_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 1), + z0 = svtmad (z0, z1, 1)) + +/* +** tmad_2_f64: +** ftmad z0\.d, z0\.d, z1\.d, #2 +** ret +*/ +TEST_UNIFORM_Z (tmad_2_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 2), + z0 = svtmad (z0, z1, 2)) + +/* +** tmad_3_f64: +** ftmad z0\.d, z0\.d, z1\.d, #3 +** ret +*/ +TEST_UNIFORM_Z (tmad_3_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 3), + z0 = svtmad (z0, z1, 3)) + +/* +** tmad_4_f64: +** ftmad z0\.d, z0\.d, z1\.d, #4 +** ret +*/ +TEST_UNIFORM_Z (tmad_4_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 4), + z0 = svtmad (z0, z1, 4)) + +/* +** tmad_5_f64: +** ftmad z0\.d, z0\.d, z1\.d, #5 +** ret +*/ +TEST_UNIFORM_Z (tmad_5_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 5), + z0 = svtmad (z0, z1, 5)) + +/* +** tmad_6_f64: +** ftmad z0\.d, z0\.d, z1\.d, #6 +** ret +*/ +TEST_UNIFORM_Z (tmad_6_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 6), + z0 = svtmad (z0, z1, 6)) + +/* +** tmad_7_f64: +** ftmad z0\.d, z0\.d, z1\.d, #7 +** ret +*/ +TEST_UNIFORM_Z (tmad_7_f64, svfloat64_t, + z0 = svtmad_f64 (z0, z1, 7), + z0 = svtmad (z0, z1, 7)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b16.c new file mode 100644 index 00000000000..902f8c39722 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_b16_tied1: +** trn1 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (trn1_b16_tied1, + p0 = svtrn1_b16 (p0, p1), + p0 = svtrn1_b16 (p0, p1)) + +/* +** trn1_b16_tied2: +** trn1 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (trn1_b16_tied2, + p0 = svtrn1_b16 (p1, p0), + p0 = svtrn1_b16 (p1, p0)) + +/* +** trn1_b16_untied: +** trn1 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (trn1_b16_untied, + p0 = svtrn1_b16 (p1, p2), + p0 = svtrn1_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b32.c new file mode 100644 index 00000000000..8c9ed515232 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_b32_tied1: +** trn1 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (trn1_b32_tied1, + p0 = svtrn1_b32 (p0, p1), + p0 = svtrn1_b32 (p0, p1)) + +/* +** trn1_b32_tied2: +** trn1 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (trn1_b32_tied2, + p0 = svtrn1_b32 (p1, p0), + p0 = svtrn1_b32 (p1, p0)) + +/* +** trn1_b32_untied: +** trn1 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (trn1_b32_untied, + p0 = svtrn1_b32 (p1, p2), + p0 = svtrn1_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b64.c new file mode 100644 index 00000000000..55b00571d70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_b64_tied1: +** trn1 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (trn1_b64_tied1, + p0 = svtrn1_b64 (p0, p1), + p0 = svtrn1_b64 (p0, p1)) + +/* +** trn1_b64_tied2: +** trn1 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (trn1_b64_tied2, + p0 = svtrn1_b64 (p1, p0), + p0 = svtrn1_b64 (p1, p0)) + +/* +** trn1_b64_untied: +** trn1 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (trn1_b64_untied, + p0 = svtrn1_b64 (p1, p2), + p0 = svtrn1_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b8.c new file mode 100644 index 00000000000..4b5e80fbe2c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_b8_tied1: +** trn1 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (trn1_b8_tied1, + p0 = svtrn1_b8 (p0, p1), + p0 = svtrn1_b8 (p0, p1)) + +/* +** trn1_b8_tied2: +** trn1 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (trn1_b8_tied2, + p0 = svtrn1_b8 (p1, p0), + p0 = svtrn1_b8 (p1, p0)) + +/* +** trn1_b8_untied: +** trn1 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (trn1_b8_untied, + p0 = svtrn1_b8 (p1, p2), + p0 = svtrn1_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f16.c new file mode 100644 index 00000000000..373eb9dd9ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_f16_tied1: +** trn1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_f16_tied1, svfloat16_t, + z0 = svtrn1_f16 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_f16_tied2: +** trn1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_f16_tied2, svfloat16_t, + z0 = svtrn1_f16 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_f16_untied: +** trn1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_f16_untied, svfloat16_t, + z0 = svtrn1_f16 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f32.c new file mode 100644 index 00000000000..ccd84d94e6a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_f32_tied1: +** trn1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_f32_tied1, svfloat32_t, + z0 = svtrn1_f32 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_f32_tied2: +** trn1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_f32_tied2, svfloat32_t, + z0 = svtrn1_f32 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_f32_untied: +** trn1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_f32_untied, svfloat32_t, + z0 = svtrn1_f32 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f64.c new file mode 100644 index 00000000000..d3cc519483d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_f64_tied1: +** trn1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_f64_tied1, svfloat64_t, + z0 = svtrn1_f64 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_f64_tied2: +** trn1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_f64_tied2, svfloat64_t, + z0 = svtrn1_f64 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_f64_untied: +** trn1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_f64_untied, svfloat64_t, + z0 = svtrn1_f64 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s16.c new file mode 100644 index 00000000000..466bb8c0217 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_s16_tied1: +** trn1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_s16_tied1, svint16_t, + z0 = svtrn1_s16 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_s16_tied2: +** trn1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_s16_tied2, svint16_t, + z0 = svtrn1_s16 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_s16_untied: +** trn1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_s16_untied, svint16_t, + z0 = svtrn1_s16 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s32.c new file mode 100644 index 00000000000..24655e622ef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_s32_tied1: +** trn1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_s32_tied1, svint32_t, + z0 = svtrn1_s32 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_s32_tied2: +** trn1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_s32_tied2, svint32_t, + z0 = svtrn1_s32 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_s32_untied: +** trn1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_s32_untied, svint32_t, + z0 = svtrn1_s32 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s64.c new file mode 100644 index 00000000000..553fb610b05 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_s64_tied1: +** trn1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_s64_tied1, svint64_t, + z0 = svtrn1_s64 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_s64_tied2: +** trn1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_s64_tied2, svint64_t, + z0 = svtrn1_s64 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_s64_untied: +** trn1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_s64_untied, svint64_t, + z0 = svtrn1_s64 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s8.c new file mode 100644 index 00000000000..1fa150792f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_s8_tied1: +** trn1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_s8_tied1, svint8_t, + z0 = svtrn1_s8 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_s8_tied2: +** trn1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_s8_tied2, svint8_t, + z0 = svtrn1_s8 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_s8_untied: +** trn1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_s8_untied, svint8_t, + z0 = svtrn1_s8 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u16.c new file mode 100644 index 00000000000..a3ce936f38b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_u16_tied1: +** trn1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_u16_tied1, svuint16_t, + z0 = svtrn1_u16 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_u16_tied2: +** trn1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_u16_tied2, svuint16_t, + z0 = svtrn1_u16 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_u16_untied: +** trn1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn1_u16_untied, svuint16_t, + z0 = svtrn1_u16 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u32.c new file mode 100644 index 00000000000..b14d7a67ab2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_u32_tied1: +** trn1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_u32_tied1, svuint32_t, + z0 = svtrn1_u32 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_u32_tied2: +** trn1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_u32_tied2, svuint32_t, + z0 = svtrn1_u32 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_u32_untied: +** trn1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn1_u32_untied, svuint32_t, + z0 = svtrn1_u32 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u64.c new file mode 100644 index 00000000000..2ccda1d722c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_u64_tied1: +** trn1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_u64_tied1, svuint64_t, + z0 = svtrn1_u64 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_u64_tied2: +** trn1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_u64_tied2, svuint64_t, + z0 = svtrn1_u64 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_u64_untied: +** trn1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn1_u64_untied, svuint64_t, + z0 = svtrn1_u64 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u8.c new file mode 100644 index 00000000000..84f8d31e8e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn1_u8_tied1: +** trn1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_u8_tied1, svuint8_t, + z0 = svtrn1_u8 (z0, z1), + z0 = svtrn1 (z0, z1)) + +/* +** trn1_u8_tied2: +** trn1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_u8_tied2, svuint8_t, + z0 = svtrn1_u8 (z1, z0), + z0 = svtrn1 (z1, z0)) + +/* +** trn1_u8_untied: +** trn1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (trn1_u8_untied, svuint8_t, + z0 = svtrn1_u8 (z1, z2), + z0 = svtrn1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b16.c new file mode 100644 index 00000000000..54b593afe2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_b16_tied1: +** trn2 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (trn2_b16_tied1, + p0 = svtrn2_b16 (p0, p1), + p0 = svtrn2_b16 (p0, p1)) + +/* +** trn2_b16_tied2: +** trn2 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (trn2_b16_tied2, + p0 = svtrn2_b16 (p1, p0), + p0 = svtrn2_b16 (p1, p0)) + +/* +** trn2_b16_untied: +** trn2 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (trn2_b16_untied, + p0 = svtrn2_b16 (p1, p2), + p0 = svtrn2_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b32.c new file mode 100644 index 00000000000..ead3d85cf52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_b32_tied1: +** trn2 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (trn2_b32_tied1, + p0 = svtrn2_b32 (p0, p1), + p0 = svtrn2_b32 (p0, p1)) + +/* +** trn2_b32_tied2: +** trn2 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (trn2_b32_tied2, + p0 = svtrn2_b32 (p1, p0), + p0 = svtrn2_b32 (p1, p0)) + +/* +** trn2_b32_untied: +** trn2 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (trn2_b32_untied, + p0 = svtrn2_b32 (p1, p2), + p0 = svtrn2_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b64.c new file mode 100644 index 00000000000..ccca0355724 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_b64_tied1: +** trn2 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (trn2_b64_tied1, + p0 = svtrn2_b64 (p0, p1), + p0 = svtrn2_b64 (p0, p1)) + +/* +** trn2_b64_tied2: +** trn2 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (trn2_b64_tied2, + p0 = svtrn2_b64 (p1, p0), + p0 = svtrn2_b64 (p1, p0)) + +/* +** trn2_b64_untied: +** trn2 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (trn2_b64_untied, + p0 = svtrn2_b64 (p1, p2), + p0 = svtrn2_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b8.c new file mode 100644 index 00000000000..7b0803e79a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_b8_tied1: +** trn2 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (trn2_b8_tied1, + p0 = svtrn2_b8 (p0, p1), + p0 = svtrn2_b8 (p0, p1)) + +/* +** trn2_b8_tied2: +** trn2 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (trn2_b8_tied2, + p0 = svtrn2_b8 (p1, p0), + p0 = svtrn2_b8 (p1, p0)) + +/* +** trn2_b8_untied: +** trn2 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (trn2_b8_untied, + p0 = svtrn2_b8 (p1, p2), + p0 = svtrn2_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f16.c new file mode 100644 index 00000000000..11256772507 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_f16_tied1: +** trn2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_f16_tied1, svfloat16_t, + z0 = svtrn2_f16 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_f16_tied2: +** trn2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_f16_tied2, svfloat16_t, + z0 = svtrn2_f16 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_f16_untied: +** trn2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_f16_untied, svfloat16_t, + z0 = svtrn2_f16 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f32.c new file mode 100644 index 00000000000..daee566cc59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_f32_tied1: +** trn2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_f32_tied1, svfloat32_t, + z0 = svtrn2_f32 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_f32_tied2: +** trn2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_f32_tied2, svfloat32_t, + z0 = svtrn2_f32 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_f32_untied: +** trn2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_f32_untied, svfloat32_t, + z0 = svtrn2_f32 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f64.c new file mode 100644 index 00000000000..338fee49f80 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_f64_tied1: +** trn2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_f64_tied1, svfloat64_t, + z0 = svtrn2_f64 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_f64_tied2: +** trn2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_f64_tied2, svfloat64_t, + z0 = svtrn2_f64 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_f64_untied: +** trn2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_f64_untied, svfloat64_t, + z0 = svtrn2_f64 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s16.c new file mode 100644 index 00000000000..93f63de5e88 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_s16_tied1: +** trn2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_s16_tied1, svint16_t, + z0 = svtrn2_s16 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_s16_tied2: +** trn2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_s16_tied2, svint16_t, + z0 = svtrn2_s16 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_s16_untied: +** trn2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_s16_untied, svint16_t, + z0 = svtrn2_s16 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s32.c new file mode 100644 index 00000000000..82edd72f703 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_s32_tied1: +** trn2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_s32_tied1, svint32_t, + z0 = svtrn2_s32 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_s32_tied2: +** trn2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_s32_tied2, svint32_t, + z0 = svtrn2_s32 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_s32_untied: +** trn2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_s32_untied, svint32_t, + z0 = svtrn2_s32 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s64.c new file mode 100644 index 00000000000..5f43441d5c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_s64_tied1: +** trn2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_s64_tied1, svint64_t, + z0 = svtrn2_s64 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_s64_tied2: +** trn2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_s64_tied2, svint64_t, + z0 = svtrn2_s64 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_s64_untied: +** trn2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_s64_untied, svint64_t, + z0 = svtrn2_s64 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s8.c new file mode 100644 index 00000000000..7165381199c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_s8_tied1: +** trn2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_s8_tied1, svint8_t, + z0 = svtrn2_s8 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_s8_tied2: +** trn2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_s8_tied2, svint8_t, + z0 = svtrn2_s8 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_s8_untied: +** trn2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_s8_untied, svint8_t, + z0 = svtrn2_s8 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u16.c new file mode 100644 index 00000000000..e68d233b850 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_u16_tied1: +** trn2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_u16_tied1, svuint16_t, + z0 = svtrn2_u16 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_u16_tied2: +** trn2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_u16_tied2, svuint16_t, + z0 = svtrn2_u16 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_u16_untied: +** trn2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (trn2_u16_untied, svuint16_t, + z0 = svtrn2_u16 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u32.c new file mode 100644 index 00000000000..e48aad179ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_u32_tied1: +** trn2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_u32_tied1, svuint32_t, + z0 = svtrn2_u32 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_u32_tied2: +** trn2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_u32_tied2, svuint32_t, + z0 = svtrn2_u32 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_u32_untied: +** trn2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (trn2_u32_untied, svuint32_t, + z0 = svtrn2_u32 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u64.c new file mode 100644 index 00000000000..aa452275b68 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_u64_tied1: +** trn2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_u64_tied1, svuint64_t, + z0 = svtrn2_u64 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_u64_tied2: +** trn2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_u64_tied2, svuint64_t, + z0 = svtrn2_u64 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_u64_untied: +** trn2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (trn2_u64_untied, svuint64_t, + z0 = svtrn2_u64 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u8.c new file mode 100644 index 00000000000..cb26b233824 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** trn2_u8_tied1: +** trn2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_u8_tied1, svuint8_t, + z0 = svtrn2_u8 (z0, z1), + z0 = svtrn2 (z0, z1)) + +/* +** trn2_u8_tied2: +** trn2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_u8_tied2, svuint8_t, + z0 = svtrn2_u8 (z1, z0), + z0 = svtrn2 (z1, z0)) + +/* +** trn2_u8_untied: +** trn2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (trn2_u8_untied, svuint8_t, + z0 = svtrn2_u8 (z1, z2), + z0 = svtrn2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f16.c new file mode 100644 index 00000000000..94bc696eb07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tsmul_f16_tied1: +** ftsmul z0\.h, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tsmul_f16_tied1, svfloat16_t, svuint16_t, + z0 = svtsmul_f16 (z0, z4), + z0 = svtsmul (z0, z4)) + +/* +** tsmul_f16_tied2: +** ftsmul z0\.h, z4\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (tsmul_f16_tied2, svfloat16_t, svuint16_t, + z0_res = svtsmul_f16 (z4, z0), + z0_res = svtsmul (z4, z0)) + +/* +** tsmul_f16_untied: +** ftsmul z0\.h, z1\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tsmul_f16_untied, svfloat16_t, svuint16_t, + z0 = svtsmul_f16 (z1, z4), + z0 = svtsmul (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f32.c new file mode 100644 index 00000000000..d0ec91882d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tsmul_f32_tied1: +** ftsmul z0\.s, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tsmul_f32_tied1, svfloat32_t, svuint32_t, + z0 = svtsmul_f32 (z0, z4), + z0 = svtsmul (z0, z4)) + +/* +** tsmul_f32_tied2: +** ftsmul z0\.s, z4\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (tsmul_f32_tied2, svfloat32_t, svuint32_t, + z0_res = svtsmul_f32 (z4, z0), + z0_res = svtsmul (z4, z0)) + +/* +** tsmul_f32_untied: +** ftsmul z0\.s, z1\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tsmul_f32_untied, svfloat32_t, svuint32_t, + z0 = svtsmul_f32 (z1, z4), + z0 = svtsmul (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f64.c new file mode 100644 index 00000000000..23e0da3f7a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tsmul_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tsmul_f64_tied1: +** ftsmul z0\.d, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tsmul_f64_tied1, svfloat64_t, svuint64_t, + z0 = svtsmul_f64 (z0, z4), + z0 = svtsmul (z0, z4)) + +/* +** tsmul_f64_tied2: +** ftsmul z0\.d, z4\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (tsmul_f64_tied2, svfloat64_t, svuint64_t, + z0_res = svtsmul_f64 (z4, z0), + z0_res = svtsmul (z4, z0)) + +/* +** tsmul_f64_untied: +** ftsmul z0\.d, z1\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tsmul_f64_untied, svfloat64_t, svuint64_t, + z0 = svtsmul_f64 (z1, z4), + z0 = svtsmul (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f16.c new file mode 100644 index 00000000000..e7c3ea03b81 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tssel_f16_tied1: +** ftssel z0\.h, z0\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tssel_f16_tied1, svfloat16_t, svuint16_t, + z0 = svtssel_f16 (z0, z4), + z0 = svtssel (z0, z4)) + +/* +** tssel_f16_tied2: +** ftssel z0\.h, z4\.h, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (tssel_f16_tied2, svfloat16_t, svuint16_t, + z0_res = svtssel_f16 (z4, z0), + z0_res = svtssel (z4, z0)) + +/* +** tssel_f16_untied: +** ftssel z0\.h, z1\.h, z4\.h +** ret +*/ +TEST_DUAL_Z (tssel_f16_untied, svfloat16_t, svuint16_t, + z0 = svtssel_f16 (z1, z4), + z0 = svtssel (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f32.c new file mode 100644 index 00000000000..022573a191d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tssel_f32_tied1: +** ftssel z0\.s, z0\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tssel_f32_tied1, svfloat32_t, svuint32_t, + z0 = svtssel_f32 (z0, z4), + z0 = svtssel (z0, z4)) + +/* +** tssel_f32_tied2: +** ftssel z0\.s, z4\.s, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (tssel_f32_tied2, svfloat32_t, svuint32_t, + z0_res = svtssel_f32 (z4, z0), + z0_res = svtssel (z4, z0)) + +/* +** tssel_f32_untied: +** ftssel z0\.s, z1\.s, z4\.s +** ret +*/ +TEST_DUAL_Z (tssel_f32_untied, svfloat32_t, svuint32_t, + z0 = svtssel_f32 (z1, z4), + z0 = svtssel (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f64.c new file mode 100644 index 00000000000..ffcdf4224b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/tssel_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** tssel_f64_tied1: +** ftssel z0\.d, z0\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tssel_f64_tied1, svfloat64_t, svuint64_t, + z0 = svtssel_f64 (z0, z4), + z0 = svtssel (z0, z4)) + +/* +** tssel_f64_tied2: +** ftssel z0\.d, z4\.d, z0\.d +** ret +*/ +TEST_DUAL_Z_REV (tssel_f64_tied2, svfloat64_t, svuint64_t, + z0_res = svtssel_f64 (z4, z0), + z0_res = svtssel (z4, z0)) + +/* +** tssel_f64_untied: +** ftssel z0\.d, z1\.d, z4\.d +** ret +*/ +TEST_DUAL_Z (tssel_f64_untied, svfloat64_t, svuint64_t, + z0 = svtssel_f64 (z1, z4), + z0 = svtssel (z1, z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef2_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef2_1.c new file mode 100644 index 00000000000..c1439bf8c90 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef2_1.c @@ -0,0 +1,80 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** int8: +** ret +*/ +TEST_UNDEF (int8, svint8x2_t, + z0 = svundef2_s8 ()) + +/* +** uint8: +** ret +*/ +TEST_UNDEF (uint8, svuint8x2_t, + z0 = svundef2_u8 ()) + +/* +** int16: +** ret +*/ +TEST_UNDEF (int16, svint16x2_t, + z0 = svundef2_s16 ()) + +/* +** uint16: +** ret +*/ +TEST_UNDEF (uint16, svuint16x2_t, + z0 = svundef2_u16 ()) + +/* +** float16: +** ret +*/ +TEST_UNDEF (float16, svfloat16x2_t, + z0 = svundef2_f16 ()) + +/* +** int32: +** ret +*/ +TEST_UNDEF (int32, svint32x2_t, + z0 = svundef2_s32 ()) + +/* +** uint32: +** ret +*/ +TEST_UNDEF (uint32, svuint32x2_t, + z0 = svundef2_u32 ()) + +/* +** float32: +** ret +*/ +TEST_UNDEF (float32, svfloat32x2_t, + z0 = svundef2_f32 ()) + +/* +** int64: +** ret +*/ +TEST_UNDEF (int64, svint64x2_t, + z0 = svundef2_s64 ()) + +/* +** uint64: +** ret +*/ +TEST_UNDEF (uint64, svuint64x2_t, + z0 = svundef2_u64 ()) + +/* +** float64: +** ret +*/ +TEST_UNDEF (float64, svfloat64x2_t, + z0 = svundef2_f64 ()) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef3_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef3_1.c new file mode 100644 index 00000000000..1944d5c7a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef3_1.c @@ -0,0 +1,80 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** int8: +** ret +*/ +TEST_UNDEF (int8, svint8x3_t, + z0 = svundef3_s8 ()) + +/* +** uint8: +** ret +*/ +TEST_UNDEF (uint8, svuint8x3_t, + z0 = svundef3_u8 ()) + +/* +** int16: +** ret +*/ +TEST_UNDEF (int16, svint16x3_t, + z0 = svundef3_s16 ()) + +/* +** uint16: +** ret +*/ +TEST_UNDEF (uint16, svuint16x3_t, + z0 = svundef3_u16 ()) + +/* +** float16: +** ret +*/ +TEST_UNDEF (float16, svfloat16x3_t, + z0 = svundef3_f16 ()) + +/* +** int32: +** ret +*/ +TEST_UNDEF (int32, svint32x3_t, + z0 = svundef3_s32 ()) + +/* +** uint32: +** ret +*/ +TEST_UNDEF (uint32, svuint32x3_t, + z0 = svundef3_u32 ()) + +/* +** float32: +** ret +*/ +TEST_UNDEF (float32, svfloat32x3_t, + z0 = svundef3_f32 ()) + +/* +** int64: +** ret +*/ +TEST_UNDEF (int64, svint64x3_t, + z0 = svundef3_s64 ()) + +/* +** uint64: +** ret +*/ +TEST_UNDEF (uint64, svuint64x3_t, + z0 = svundef3_u64 ()) + +/* +** float64: +** ret +*/ +TEST_UNDEF (float64, svfloat64x3_t, + z0 = svundef3_f64 ()) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef4_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef4_1.c new file mode 100644 index 00000000000..b745e1319c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef4_1.c @@ -0,0 +1,80 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** int8: +** ret +*/ +TEST_UNDEF (int8, svint8x4_t, + z0 = svundef4_s8 ()) + +/* +** uint8: +** ret +*/ +TEST_UNDEF (uint8, svuint8x4_t, + z0 = svundef4_u8 ()) + +/* +** int16: +** ret +*/ +TEST_UNDEF (int16, svint16x4_t, + z0 = svundef4_s16 ()) + +/* +** uint16: +** ret +*/ +TEST_UNDEF (uint16, svuint16x4_t, + z0 = svundef4_u16 ()) + +/* +** float16: +** ret +*/ +TEST_UNDEF (float16, svfloat16x4_t, + z0 = svundef4_f16 ()) + +/* +** int32: +** ret +*/ +TEST_UNDEF (int32, svint32x4_t, + z0 = svundef4_s32 ()) + +/* +** uint32: +** ret +*/ +TEST_UNDEF (uint32, svuint32x4_t, + z0 = svundef4_u32 ()) + +/* +** float32: +** ret +*/ +TEST_UNDEF (float32, svfloat32x4_t, + z0 = svundef4_f32 ()) + +/* +** int64: +** ret +*/ +TEST_UNDEF (int64, svint64x4_t, + z0 = svundef4_s64 ()) + +/* +** uint64: +** ret +*/ +TEST_UNDEF (uint64, svuint64x4_t, + z0 = svundef4_u64 ()) + +/* +** float64: +** ret +*/ +TEST_UNDEF (float64, svfloat64x4_t, + z0 = svundef4_f64 ()) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef_1.c new file mode 100644 index 00000000000..9c80791570f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/undef_1.c @@ -0,0 +1,80 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** int8: +** ret +*/ +TEST_UNDEF (int8, svint8_t, + z0 = svundef_s8 ()) + +/* +** uint8: +** ret +*/ +TEST_UNDEF (uint8, svuint8_t, + z0 = svundef_u8 ()) + +/* +** int16: +** ret +*/ +TEST_UNDEF (int16, svint16_t, + z0 = svundef_s16 ()) + +/* +** uint16: +** ret +*/ +TEST_UNDEF (uint16, svuint16_t, + z0 = svundef_u16 ()) + +/* +** float16: +** ret +*/ +TEST_UNDEF (float16, svfloat16_t, + z0 = svundef_f16 ()) + +/* +** int32: +** ret +*/ +TEST_UNDEF (int32, svint32_t, + z0 = svundef_s32 ()) + +/* +** uint32: +** ret +*/ +TEST_UNDEF (uint32, svuint32_t, + z0 = svundef_u32 ()) + +/* +** float32: +** ret +*/ +TEST_UNDEF (float32, svfloat32_t, + z0 = svundef_f32 ()) + +/* +** int64: +** ret +*/ +TEST_UNDEF (int64, svint64_t, + z0 = svundef_s64 ()) + +/* +** uint64: +** ret +*/ +TEST_UNDEF (uint64, svuint64_t, + z0 = svundef_u64 ()) + +/* +** float64: +** ret +*/ +TEST_UNDEF (float64, svfloat64_t, + z0 = svundef_f64 ()) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_b.c new file mode 100644 index 00000000000..ff1a84aacc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_b.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_b_tied1: +** punpkhi p0\.h, p0\.b +** ret +*/ +TEST_UNIFORM_P (unpkhi_b_tied1, + p0 = svunpkhi_b (p0), + p0 = svunpkhi (p0)) + +/* +** unpkhi_b_untied: +** punpkhi p0\.h, p1\.b +** ret +*/ +TEST_UNIFORM_P (unpkhi_b_untied, + p0 = svunpkhi_b (p1), + p0 = svunpkhi (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s16.c new file mode 100644 index 00000000000..3f79ac65fa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_s16_tied1: +** sunpkhi z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_s16_tied1, svint16_t, svint8_t, + z0_res = svunpkhi_s16 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_s16_untied: +** sunpkhi z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (unpkhi_s16_untied, svint16_t, svint8_t, + z0 = svunpkhi_s16 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s32.c new file mode 100644 index 00000000000..619fb088247 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_s32_tied1: +** sunpkhi z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_s32_tied1, svint32_t, svint16_t, + z0_res = svunpkhi_s32 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_s32_untied: +** sunpkhi z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (unpkhi_s32_untied, svint32_t, svint16_t, + z0 = svunpkhi_s32 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s64.c new file mode 100644 index 00000000000..5d6da176864 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_s64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_s64_tied1: +** sunpkhi z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_s64_tied1, svint64_t, svint32_t, + z0_res = svunpkhi_s64 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_s64_untied: +** sunpkhi z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (unpkhi_s64_untied, svint64_t, svint32_t, + z0 = svunpkhi_s64 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u16.c new file mode 100644 index 00000000000..68f47a28202 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_u16_tied1: +** uunpkhi z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_u16_tied1, svuint16_t, svuint8_t, + z0_res = svunpkhi_u16 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_u16_untied: +** uunpkhi z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (unpkhi_u16_untied, svuint16_t, svuint8_t, + z0 = svunpkhi_u16 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u32.c new file mode 100644 index 00000000000..3c4b161e4a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_u32_tied1: +** uunpkhi z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_u32_tied1, svuint32_t, svuint16_t, + z0_res = svunpkhi_u32 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_u32_untied: +** uunpkhi z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (unpkhi_u32_untied, svuint32_t, svuint16_t, + z0 = svunpkhi_u32 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u64.c new file mode 100644 index 00000000000..94cfbd49383 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpkhi_u64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpkhi_u64_tied1: +** uunpkhi z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (unpkhi_u64_tied1, svuint64_t, svuint32_t, + z0_res = svunpkhi_u64 (z0), + z0_res = svunpkhi (z0)) + +/* +** unpkhi_u64_untied: +** uunpkhi z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (unpkhi_u64_untied, svuint64_t, svuint32_t, + z0 = svunpkhi_u64 (z4), + z0 = svunpkhi (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_b.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_b.c new file mode 100644 index 00000000000..476ec8bc34d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_b.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_b_tied1: +** punpklo p0\.h, p0\.b +** ret +*/ +TEST_UNIFORM_P (unpklo_b_tied1, + p0 = svunpklo_b (p0), + p0 = svunpklo (p0)) + +/* +** unpklo_b_untied: +** punpklo p0\.h, p1\.b +** ret +*/ +TEST_UNIFORM_P (unpklo_b_untied, + p0 = svunpklo_b (p1), + p0 = svunpklo (p1)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s16.c new file mode 100644 index 00000000000..a0e83ff1be7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_s16_tied1: +** sunpklo z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (unpklo_s16_tied1, svint16_t, svint8_t, + z0_res = svunpklo_s16 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_s16_untied: +** sunpklo z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (unpklo_s16_untied, svint16_t, svint8_t, + z0 = svunpklo_s16 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s32.c new file mode 100644 index 00000000000..49a14fb7b97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_s32_tied1: +** sunpklo z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (unpklo_s32_tied1, svint32_t, svint16_t, + z0_res = svunpklo_s32 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_s32_untied: +** sunpklo z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (unpklo_s32_untied, svint32_t, svint16_t, + z0 = svunpklo_s32 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s64.c new file mode 100644 index 00000000000..c430047e19a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_s64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_s64_tied1: +** sunpklo z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (unpklo_s64_tied1, svint64_t, svint32_t, + z0_res = svunpklo_s64 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_s64_untied: +** sunpklo z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (unpklo_s64_untied, svint64_t, svint32_t, + z0 = svunpklo_s64 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u16.c new file mode 100644 index 00000000000..6feee44276b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u16.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_u16_tied1: +** uunpklo z0\.h, z0\.b +** ret +*/ +TEST_DUAL_Z_REV (unpklo_u16_tied1, svuint16_t, svuint8_t, + z0_res = svunpklo_u16 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_u16_untied: +** uunpklo z0\.h, z4\.b +** ret +*/ +TEST_DUAL_Z (unpklo_u16_untied, svuint16_t, svuint8_t, + z0 = svunpklo_u16 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u32.c new file mode 100644 index 00000000000..c4d4efc8621 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u32.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_u32_tied1: +** uunpklo z0\.s, z0\.h +** ret +*/ +TEST_DUAL_Z_REV (unpklo_u32_tied1, svuint32_t, svuint16_t, + z0_res = svunpklo_u32 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_u32_untied: +** uunpklo z0\.s, z4\.h +** ret +*/ +TEST_DUAL_Z (unpklo_u32_untied, svuint32_t, svuint16_t, + z0 = svunpklo_u32 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u64.c new file mode 100644 index 00000000000..2845e37a508 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/unpklo_u64.c @@ -0,0 +1,21 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** unpklo_u64_tied1: +** uunpklo z0\.d, z0\.s +** ret +*/ +TEST_DUAL_Z_REV (unpklo_u64_tied1, svuint64_t, svuint32_t, + z0_res = svunpklo_u64 (z0), + z0_res = svunpklo (z0)) + +/* +** unpklo_u64_untied: +** uunpklo z0\.d, z4\.s +** ret +*/ +TEST_DUAL_Z (unpklo_u64_untied, svuint64_t, svuint32_t, + z0 = svunpklo_u64 (z4), + z0 = svunpklo (z4)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b16.c new file mode 100644 index 00000000000..245e401aa09 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_b16_tied1: +** uzp1 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (uzp1_b16_tied1, + p0 = svuzp1_b16 (p0, p1), + p0 = svuzp1_b16 (p0, p1)) + +/* +** uzp1_b16_tied2: +** uzp1 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (uzp1_b16_tied2, + p0 = svuzp1_b16 (p1, p0), + p0 = svuzp1_b16 (p1, p0)) + +/* +** uzp1_b16_untied: +** uzp1 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (uzp1_b16_untied, + p0 = svuzp1_b16 (p1, p2), + p0 = svuzp1_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b32.c new file mode 100644 index 00000000000..c8803449252 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_b32_tied1: +** uzp1 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (uzp1_b32_tied1, + p0 = svuzp1_b32 (p0, p1), + p0 = svuzp1_b32 (p0, p1)) + +/* +** uzp1_b32_tied2: +** uzp1 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (uzp1_b32_tied2, + p0 = svuzp1_b32 (p1, p0), + p0 = svuzp1_b32 (p1, p0)) + +/* +** uzp1_b32_untied: +** uzp1 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (uzp1_b32_untied, + p0 = svuzp1_b32 (p1, p2), + p0 = svuzp1_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b64.c new file mode 100644 index 00000000000..71ac5c15028 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_b64_tied1: +** uzp1 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (uzp1_b64_tied1, + p0 = svuzp1_b64 (p0, p1), + p0 = svuzp1_b64 (p0, p1)) + +/* +** uzp1_b64_tied2: +** uzp1 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (uzp1_b64_tied2, + p0 = svuzp1_b64 (p1, p0), + p0 = svuzp1_b64 (p1, p0)) + +/* +** uzp1_b64_untied: +** uzp1 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (uzp1_b64_untied, + p0 = svuzp1_b64 (p1, p2), + p0 = svuzp1_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b8.c new file mode 100644 index 00000000000..250054bb660 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_b8_tied1: +** uzp1 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (uzp1_b8_tied1, + p0 = svuzp1_b8 (p0, p1), + p0 = svuzp1_b8 (p0, p1)) + +/* +** uzp1_b8_tied2: +** uzp1 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (uzp1_b8_tied2, + p0 = svuzp1_b8 (p1, p0), + p0 = svuzp1_b8 (p1, p0)) + +/* +** uzp1_b8_untied: +** uzp1 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (uzp1_b8_untied, + p0 = svuzp1_b8 (p1, p2), + p0 = svuzp1_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f16.c new file mode 100644 index 00000000000..313673e9d6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_f16_tied1: +** uzp1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_f16_tied1, svfloat16_t, + z0 = svuzp1_f16 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_f16_tied2: +** uzp1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_f16_tied2, svfloat16_t, + z0 = svuzp1_f16 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_f16_untied: +** uzp1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_f16_untied, svfloat16_t, + z0 = svuzp1_f16 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f32.c new file mode 100644 index 00000000000..5bbac2c6075 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_f32_tied1: +** uzp1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_f32_tied1, svfloat32_t, + z0 = svuzp1_f32 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_f32_tied2: +** uzp1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_f32_tied2, svfloat32_t, + z0 = svuzp1_f32 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_f32_untied: +** uzp1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_f32_untied, svfloat32_t, + z0 = svuzp1_f32 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f64.c new file mode 100644 index 00000000000..ef97b1765dc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_f64_tied1: +** uzp1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_f64_tied1, svfloat64_t, + z0 = svuzp1_f64 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_f64_tied2: +** uzp1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_f64_tied2, svfloat64_t, + z0 = svuzp1_f64 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_f64_untied: +** uzp1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_f64_untied, svfloat64_t, + z0 = svuzp1_f64 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s16.c new file mode 100644 index 00000000000..b77832b078d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_s16_tied1: +** uzp1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_s16_tied1, svint16_t, + z0 = svuzp1_s16 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_s16_tied2: +** uzp1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_s16_tied2, svint16_t, + z0 = svuzp1_s16 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_s16_untied: +** uzp1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_s16_untied, svint16_t, + z0 = svuzp1_s16 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s32.c new file mode 100644 index 00000000000..64291afbe7f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_s32_tied1: +** uzp1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_s32_tied1, svint32_t, + z0 = svuzp1_s32 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_s32_tied2: +** uzp1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_s32_tied2, svint32_t, + z0 = svuzp1_s32 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_s32_untied: +** uzp1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_s32_untied, svint32_t, + z0 = svuzp1_s32 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s64.c new file mode 100644 index 00000000000..e8f7799f6ac --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_s64_tied1: +** uzp1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_s64_tied1, svint64_t, + z0 = svuzp1_s64 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_s64_tied2: +** uzp1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_s64_tied2, svint64_t, + z0 = svuzp1_s64 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_s64_untied: +** uzp1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_s64_untied, svint64_t, + z0 = svuzp1_s64 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s8.c new file mode 100644 index 00000000000..98464b79058 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_s8_tied1: +** uzp1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_s8_tied1, svint8_t, + z0 = svuzp1_s8 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_s8_tied2: +** uzp1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_s8_tied2, svint8_t, + z0 = svuzp1_s8 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_s8_untied: +** uzp1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_s8_untied, svint8_t, + z0 = svuzp1_s8 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u16.c new file mode 100644 index 00000000000..da95171fe72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_u16_tied1: +** uzp1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_u16_tied1, svuint16_t, + z0 = svuzp1_u16 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_u16_tied2: +** uzp1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_u16_tied2, svuint16_t, + z0 = svuzp1_u16 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_u16_untied: +** uzp1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp1_u16_untied, svuint16_t, + z0 = svuzp1_u16 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u32.c new file mode 100644 index 00000000000..a57cdcc065b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_u32_tied1: +** uzp1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_u32_tied1, svuint32_t, + z0 = svuzp1_u32 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_u32_tied2: +** uzp1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_u32_tied2, svuint32_t, + z0 = svuzp1_u32 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_u32_untied: +** uzp1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp1_u32_untied, svuint32_t, + z0 = svuzp1_u32 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u64.c new file mode 100644 index 00000000000..24d8203593d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_u64_tied1: +** uzp1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_u64_tied1, svuint64_t, + z0 = svuzp1_u64 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_u64_tied2: +** uzp1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_u64_tied2, svuint64_t, + z0 = svuzp1_u64 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_u64_untied: +** uzp1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp1_u64_untied, svuint64_t, + z0 = svuzp1_u64 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u8.c new file mode 100644 index 00000000000..359d4c5f8f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp1_u8_tied1: +** uzp1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_u8_tied1, svuint8_t, + z0 = svuzp1_u8 (z0, z1), + z0 = svuzp1 (z0, z1)) + +/* +** uzp1_u8_tied2: +** uzp1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_u8_tied2, svuint8_t, + z0 = svuzp1_u8 (z1, z0), + z0 = svuzp1 (z1, z0)) + +/* +** uzp1_u8_untied: +** uzp1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (uzp1_u8_untied, svuint8_t, + z0 = svuzp1_u8 (z1, z2), + z0 = svuzp1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b16.c new file mode 100644 index 00000000000..c3a91e7fc15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_b16_tied1: +** uzp2 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (uzp2_b16_tied1, + p0 = svuzp2_b16 (p0, p1), + p0 = svuzp2_b16 (p0, p1)) + +/* +** uzp2_b16_tied2: +** uzp2 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (uzp2_b16_tied2, + p0 = svuzp2_b16 (p1, p0), + p0 = svuzp2_b16 (p1, p0)) + +/* +** uzp2_b16_untied: +** uzp2 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (uzp2_b16_untied, + p0 = svuzp2_b16 (p1, p2), + p0 = svuzp2_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b32.c new file mode 100644 index 00000000000..e3294a6f3fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_b32_tied1: +** uzp2 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (uzp2_b32_tied1, + p0 = svuzp2_b32 (p0, p1), + p0 = svuzp2_b32 (p0, p1)) + +/* +** uzp2_b32_tied2: +** uzp2 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (uzp2_b32_tied2, + p0 = svuzp2_b32 (p1, p0), + p0 = svuzp2_b32 (p1, p0)) + +/* +** uzp2_b32_untied: +** uzp2 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (uzp2_b32_untied, + p0 = svuzp2_b32 (p1, p2), + p0 = svuzp2_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b64.c new file mode 100644 index 00000000000..3ae72e10c97 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_b64_tied1: +** uzp2 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (uzp2_b64_tied1, + p0 = svuzp2_b64 (p0, p1), + p0 = svuzp2_b64 (p0, p1)) + +/* +** uzp2_b64_tied2: +** uzp2 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (uzp2_b64_tied2, + p0 = svuzp2_b64 (p1, p0), + p0 = svuzp2_b64 (p1, p0)) + +/* +** uzp2_b64_untied: +** uzp2 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (uzp2_b64_untied, + p0 = svuzp2_b64 (p1, p2), + p0 = svuzp2_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b8.c new file mode 100644 index 00000000000..726a9a0793e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_b8_tied1: +** uzp2 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (uzp2_b8_tied1, + p0 = svuzp2_b8 (p0, p1), + p0 = svuzp2_b8 (p0, p1)) + +/* +** uzp2_b8_tied2: +** uzp2 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (uzp2_b8_tied2, + p0 = svuzp2_b8 (p1, p0), + p0 = svuzp2_b8 (p1, p0)) + +/* +** uzp2_b8_untied: +** uzp2 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (uzp2_b8_untied, + p0 = svuzp2_b8 (p1, p2), + p0 = svuzp2_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f16.c new file mode 100644 index 00000000000..d4847ef37a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_f16_tied1: +** uzp2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_f16_tied1, svfloat16_t, + z0 = svuzp2_f16 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_f16_tied2: +** uzp2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_f16_tied2, svfloat16_t, + z0 = svuzp2_f16 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_f16_untied: +** uzp2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_f16_untied, svfloat16_t, + z0 = svuzp2_f16 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f32.c new file mode 100644 index 00000000000..c1699fc9cb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_f32_tied1: +** uzp2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_f32_tied1, svfloat32_t, + z0 = svuzp2_f32 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_f32_tied2: +** uzp2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_f32_tied2, svfloat32_t, + z0 = svuzp2_f32 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_f32_untied: +** uzp2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_f32_untied, svfloat32_t, + z0 = svuzp2_f32 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f64.c new file mode 100644 index 00000000000..afbf5c11a8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_f64_tied1: +** uzp2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_f64_tied1, svfloat64_t, + z0 = svuzp2_f64 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_f64_tied2: +** uzp2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_f64_tied2, svfloat64_t, + z0 = svuzp2_f64 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_f64_untied: +** uzp2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_f64_untied, svfloat64_t, + z0 = svuzp2_f64 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s16.c new file mode 100644 index 00000000000..e88df8734ca --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_s16_tied1: +** uzp2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_s16_tied1, svint16_t, + z0 = svuzp2_s16 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_s16_tied2: +** uzp2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_s16_tied2, svint16_t, + z0 = svuzp2_s16 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_s16_untied: +** uzp2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_s16_untied, svint16_t, + z0 = svuzp2_s16 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s32.c new file mode 100644 index 00000000000..2e9a73d1f4a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_s32_tied1: +** uzp2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_s32_tied1, svint32_t, + z0 = svuzp2_s32 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_s32_tied2: +** uzp2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_s32_tied2, svint32_t, + z0 = svuzp2_s32 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_s32_untied: +** uzp2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_s32_untied, svint32_t, + z0 = svuzp2_s32 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s64.c new file mode 100644 index 00000000000..ffec78cccee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_s64_tied1: +** uzp2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_s64_tied1, svint64_t, + z0 = svuzp2_s64 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_s64_tied2: +** uzp2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_s64_tied2, svint64_t, + z0 = svuzp2_s64 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_s64_untied: +** uzp2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_s64_untied, svint64_t, + z0 = svuzp2_s64 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s8.c new file mode 100644 index 00000000000..72037a08852 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_s8_tied1: +** uzp2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_s8_tied1, svint8_t, + z0 = svuzp2_s8 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_s8_tied2: +** uzp2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_s8_tied2, svint8_t, + z0 = svuzp2_s8 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_s8_untied: +** uzp2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_s8_untied, svint8_t, + z0 = svuzp2_s8 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u16.c new file mode 100644 index 00000000000..d84f8c9eda4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_u16_tied1: +** uzp2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_u16_tied1, svuint16_t, + z0 = svuzp2_u16 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_u16_tied2: +** uzp2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_u16_tied2, svuint16_t, + z0 = svuzp2_u16 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_u16_untied: +** uzp2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (uzp2_u16_untied, svuint16_t, + z0 = svuzp2_u16 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u32.c new file mode 100644 index 00000000000..0285ff91f22 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_u32_tied1: +** uzp2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_u32_tied1, svuint32_t, + z0 = svuzp2_u32 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_u32_tied2: +** uzp2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_u32_tied2, svuint32_t, + z0 = svuzp2_u32 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_u32_untied: +** uzp2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (uzp2_u32_untied, svuint32_t, + z0 = svuzp2_u32 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u64.c new file mode 100644 index 00000000000..1b51baf90ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_u64_tied1: +** uzp2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_u64_tied1, svuint64_t, + z0 = svuzp2_u64 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_u64_tied2: +** uzp2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_u64_tied2, svuint64_t, + z0 = svuzp2_u64 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_u64_untied: +** uzp2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (uzp2_u64_untied, svuint64_t, + z0 = svuzp2_u64 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u8.c new file mode 100644 index 00000000000..662e0b81861 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** uzp2_u8_tied1: +** uzp2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_u8_tied1, svuint8_t, + z0 = svuzp2_u8 (z0, z1), + z0 = svuzp2 (z0, z1)) + +/* +** uzp2_u8_tied2: +** uzp2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_u8_tied2, svuint8_t, + z0 = svuzp2_u8 (z1, z0), + z0 = svuzp2 (z1, z0)) + +/* +** uzp2_u8_untied: +** uzp2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (uzp2_u8_untied, svuint8_t, + z0 = svuzp2_u8 (z1, z2), + z0 = svuzp2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b16.c new file mode 100644 index 00000000000..c285a7a73e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b16.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilele_rr_b16_s32: +** whilele p0\.h, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b16_s32, int32_t, + p0 = svwhilele_b16_s32 (x0, x1), + p0 = svwhilele_b16 (x0, x1)) + +/* +** whilele_0r_b16_s32: +** whilele p0\.h, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b16_s32, int32_t, + p0 = svwhilele_b16_s32 (0, x1), + p0 = svwhilele_b16 (0, x1)) + +/* +** whilele_5r_b16_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.h, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b16_s32, int32_t, + p0 = svwhilele_b16_s32 (5, x1), + p0 = svwhilele_b16 (5, x1)) + +/* +** whilele_r0_b16_s32: +** whilele p0\.h, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b16_s32, int32_t, + p0 = svwhilele_b16_s32 (x0, 0), + p0 = svwhilele_b16 (x0, 0)) + +/* +** whilele_r5_b16_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.h, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b16_s32, int32_t, + p0 = svwhilele_b16_s32 (x0, 5), + p0 = svwhilele_b16 (x0, 5)) + +/* +** whilele_rr_b16_s64: +** whilele p0\.h, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b16_s64, int64_t, + p0 = svwhilele_b16_s64 (x0, x1), + p0 = svwhilele_b16 (x0, x1)) + +/* +** whilele_0r_b16_s64: +** whilele p0\.h, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b16_s64, int64_t, + p0 = svwhilele_b16_s64 (0, x1), + p0 = svwhilele_b16 ((int64_t) 0, x1)) + +/* +** whilele_5r_b16_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.h, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b16_s64, int64_t, + p0 = svwhilele_b16_s64 (5, x1), + p0 = svwhilele_b16 ((int64_t) 5, x1)) + +/* +** whilele_r0_b16_s64: +** whilele p0\.h, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b16_s64, int64_t, + p0 = svwhilele_b16_s64 (x0, 0), + p0 = svwhilele_b16 (x0, (int64_t) 0)) + +/* +** whilele_r5_b16_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.h, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b16_s64, int64_t, + p0 = svwhilele_b16_s64 (x0, 5), + p0 = svwhilele_b16 (x0, (int64_t) 5)) + +/* +** whilele_rr_b16_u32: +** whilels p0\.h, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b16_u32, uint32_t, + p0 = svwhilele_b16_u32 (x0, x1), + p0 = svwhilele_b16 (x0, x1)) + +/* +** whilele_0r_b16_u32: +** whilels p0\.h, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b16_u32, uint32_t, + p0 = svwhilele_b16_u32 (0, x1), + p0 = svwhilele_b16 ((uint32_t) 0, x1)) + +/* +** whilele_5r_b16_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.h, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b16_u32, uint32_t, + p0 = svwhilele_b16_u32 (5, x1), + p0 = svwhilele_b16 ((uint32_t) 5, x1)) + +/* +** whilele_r5_b16_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.h, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b16_u32, uint32_t, + p0 = svwhilele_b16_u32 (x0, 5), + p0 = svwhilele_b16 (x0, (uint32_t) 5)) + +/* +** whilele_rr_b16_u64: +** whilels p0\.h, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b16_u64, uint64_t, + p0 = svwhilele_b16_u64 (x0, x1), + p0 = svwhilele_b16 (x0, x1)) + +/* +** whilele_0r_b16_u64: +** whilels p0\.h, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b16_u64, uint64_t, + p0 = svwhilele_b16_u64 (0, x1), + p0 = svwhilele_b16 ((uint64_t) 0, x1)) + +/* +** whilele_5r_b16_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.h, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b16_u64, uint64_t, + p0 = svwhilele_b16_u64 (5, x1), + p0 = svwhilele_b16 ((uint64_t) 5, x1)) + +/* +** whilele_r5_b16_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.h, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b16_u64, uint64_t, + p0 = svwhilele_b16_u64 (x0, 5), + p0 = svwhilele_b16 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b32.c new file mode 100644 index 00000000000..d369ccfa3ec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b32.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilele_rr_b32_s32: +** whilele p0\.s, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b32_s32, int32_t, + p0 = svwhilele_b32_s32 (x0, x1), + p0 = svwhilele_b32 (x0, x1)) + +/* +** whilele_0r_b32_s32: +** whilele p0\.s, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b32_s32, int32_t, + p0 = svwhilele_b32_s32 (0, x1), + p0 = svwhilele_b32 (0, x1)) + +/* +** whilele_5r_b32_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.s, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b32_s32, int32_t, + p0 = svwhilele_b32_s32 (5, x1), + p0 = svwhilele_b32 (5, x1)) + +/* +** whilele_r0_b32_s32: +** whilele p0\.s, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b32_s32, int32_t, + p0 = svwhilele_b32_s32 (x0, 0), + p0 = svwhilele_b32 (x0, 0)) + +/* +** whilele_r5_b32_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.s, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b32_s32, int32_t, + p0 = svwhilele_b32_s32 (x0, 5), + p0 = svwhilele_b32 (x0, 5)) + +/* +** whilele_rr_b32_s64: +** whilele p0\.s, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b32_s64, int64_t, + p0 = svwhilele_b32_s64 (x0, x1), + p0 = svwhilele_b32 (x0, x1)) + +/* +** whilele_0r_b32_s64: +** whilele p0\.s, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b32_s64, int64_t, + p0 = svwhilele_b32_s64 (0, x1), + p0 = svwhilele_b32 ((int64_t) 0, x1)) + +/* +** whilele_5r_b32_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.s, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b32_s64, int64_t, + p0 = svwhilele_b32_s64 (5, x1), + p0 = svwhilele_b32 ((int64_t) 5, x1)) + +/* +** whilele_r0_b32_s64: +** whilele p0\.s, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b32_s64, int64_t, + p0 = svwhilele_b32_s64 (x0, 0), + p0 = svwhilele_b32 (x0, (int64_t) 0)) + +/* +** whilele_r5_b32_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.s, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b32_s64, int64_t, + p0 = svwhilele_b32_s64 (x0, 5), + p0 = svwhilele_b32 (x0, (int64_t) 5)) + +/* +** whilele_rr_b32_u32: +** whilels p0\.s, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b32_u32, uint32_t, + p0 = svwhilele_b32_u32 (x0, x1), + p0 = svwhilele_b32 (x0, x1)) + +/* +** whilele_0r_b32_u32: +** whilels p0\.s, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b32_u32, uint32_t, + p0 = svwhilele_b32_u32 (0, x1), + p0 = svwhilele_b32 ((uint32_t) 0, x1)) + +/* +** whilele_5r_b32_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.s, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b32_u32, uint32_t, + p0 = svwhilele_b32_u32 (5, x1), + p0 = svwhilele_b32 ((uint32_t) 5, x1)) + +/* +** whilele_r5_b32_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.s, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b32_u32, uint32_t, + p0 = svwhilele_b32_u32 (x0, 5), + p0 = svwhilele_b32 (x0, (uint32_t) 5)) + +/* +** whilele_rr_b32_u64: +** whilels p0\.s, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b32_u64, uint64_t, + p0 = svwhilele_b32_u64 (x0, x1), + p0 = svwhilele_b32 (x0, x1)) + +/* +** whilele_0r_b32_u64: +** whilels p0\.s, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b32_u64, uint64_t, + p0 = svwhilele_b32_u64 (0, x1), + p0 = svwhilele_b32 ((uint64_t) 0, x1)) + +/* +** whilele_5r_b32_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.s, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b32_u64, uint64_t, + p0 = svwhilele_b32_u64 (5, x1), + p0 = svwhilele_b32 ((uint64_t) 5, x1)) + +/* +** whilele_r5_b32_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.s, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b32_u64, uint64_t, + p0 = svwhilele_b32_u64 (x0, 5), + p0 = svwhilele_b32 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b64.c new file mode 100644 index 00000000000..394f51f44b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b64.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilele_rr_b64_s32: +** whilele p0\.d, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b64_s32, int32_t, + p0 = svwhilele_b64_s32 (x0, x1), + p0 = svwhilele_b64 (x0, x1)) + +/* +** whilele_0r_b64_s32: +** whilele p0\.d, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b64_s32, int32_t, + p0 = svwhilele_b64_s32 (0, x1), + p0 = svwhilele_b64 (0, x1)) + +/* +** whilele_5r_b64_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.d, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b64_s32, int32_t, + p0 = svwhilele_b64_s32 (5, x1), + p0 = svwhilele_b64 (5, x1)) + +/* +** whilele_r0_b64_s32: +** whilele p0\.d, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b64_s32, int32_t, + p0 = svwhilele_b64_s32 (x0, 0), + p0 = svwhilele_b64 (x0, 0)) + +/* +** whilele_r5_b64_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.d, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b64_s32, int32_t, + p0 = svwhilele_b64_s32 (x0, 5), + p0 = svwhilele_b64 (x0, 5)) + +/* +** whilele_rr_b64_s64: +** whilele p0\.d, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b64_s64, int64_t, + p0 = svwhilele_b64_s64 (x0, x1), + p0 = svwhilele_b64 (x0, x1)) + +/* +** whilele_0r_b64_s64: +** whilele p0\.d, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b64_s64, int64_t, + p0 = svwhilele_b64_s64 (0, x1), + p0 = svwhilele_b64 ((int64_t) 0, x1)) + +/* +** whilele_5r_b64_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.d, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b64_s64, int64_t, + p0 = svwhilele_b64_s64 (5, x1), + p0 = svwhilele_b64 ((int64_t) 5, x1)) + +/* +** whilele_r0_b64_s64: +** whilele p0\.d, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b64_s64, int64_t, + p0 = svwhilele_b64_s64 (x0, 0), + p0 = svwhilele_b64 (x0, (int64_t) 0)) + +/* +** whilele_r5_b64_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.d, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b64_s64, int64_t, + p0 = svwhilele_b64_s64 (x0, 5), + p0 = svwhilele_b64 (x0, (int64_t) 5)) + +/* +** whilele_rr_b64_u32: +** whilels p0\.d, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b64_u32, uint32_t, + p0 = svwhilele_b64_u32 (x0, x1), + p0 = svwhilele_b64 (x0, x1)) + +/* +** whilele_0r_b64_u32: +** whilels p0\.d, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b64_u32, uint32_t, + p0 = svwhilele_b64_u32 (0, x1), + p0 = svwhilele_b64 ((uint32_t) 0, x1)) + +/* +** whilele_5r_b64_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.d, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b64_u32, uint32_t, + p0 = svwhilele_b64_u32 (5, x1), + p0 = svwhilele_b64 ((uint32_t) 5, x1)) + +/* +** whilele_r5_b64_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.d, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b64_u32, uint32_t, + p0 = svwhilele_b64_u32 (x0, 5), + p0 = svwhilele_b64 (x0, (uint32_t) 5)) + +/* +** whilele_rr_b64_u64: +** whilels p0\.d, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b64_u64, uint64_t, + p0 = svwhilele_b64_u64 (x0, x1), + p0 = svwhilele_b64 (x0, x1)) + +/* +** whilele_0r_b64_u64: +** whilels p0\.d, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b64_u64, uint64_t, + p0 = svwhilele_b64_u64 (0, x1), + p0 = svwhilele_b64 ((uint64_t) 0, x1)) + +/* +** whilele_5r_b64_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.d, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b64_u64, uint64_t, + p0 = svwhilele_b64_u64 (5, x1), + p0 = svwhilele_b64 ((uint64_t) 5, x1)) + +/* +** whilele_r5_b64_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.d, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b64_u64, uint64_t, + p0 = svwhilele_b64_u64 (x0, 5), + p0 = svwhilele_b64 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b8.c new file mode 100644 index 00000000000..2ec101473f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilele_b8.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilele_rr_b8_s32: +** whilele p0\.b, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b8_s32, int32_t, + p0 = svwhilele_b8_s32 (x0, x1), + p0 = svwhilele_b8 (x0, x1)) + +/* +** whilele_0r_b8_s32: +** whilele p0\.b, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b8_s32, int32_t, + p0 = svwhilele_b8_s32 (0, x1), + p0 = svwhilele_b8 (0, x1)) + +/* +** whilele_5r_b8_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.b, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b8_s32, int32_t, + p0 = svwhilele_b8_s32 (5, x1), + p0 = svwhilele_b8 (5, x1)) + +/* +** whilele_r0_b8_s32: +** whilele p0\.b, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b8_s32, int32_t, + p0 = svwhilele_b8_s32 (x0, 0), + p0 = svwhilele_b8 (x0, 0)) + +/* +** whilele_r5_b8_s32: +** mov (w[0-9]+), #?5 +** whilele p0\.b, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b8_s32, int32_t, + p0 = svwhilele_b8_s32 (x0, 5), + p0 = svwhilele_b8 (x0, 5)) + +/* +** whilele_rr_b8_s64: +** whilele p0\.b, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b8_s64, int64_t, + p0 = svwhilele_b8_s64 (x0, x1), + p0 = svwhilele_b8 (x0, x1)) + +/* +** whilele_0r_b8_s64: +** whilele p0\.b, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b8_s64, int64_t, + p0 = svwhilele_b8_s64 (0, x1), + p0 = svwhilele_b8 ((int64_t) 0, x1)) + +/* +** whilele_5r_b8_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.b, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b8_s64, int64_t, + p0 = svwhilele_b8_s64 (5, x1), + p0 = svwhilele_b8 ((int64_t) 5, x1)) + +/* +** whilele_r0_b8_s64: +** whilele p0\.b, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilele_r0_b8_s64, int64_t, + p0 = svwhilele_b8_s64 (x0, 0), + p0 = svwhilele_b8 (x0, (int64_t) 0)) + +/* +** whilele_r5_b8_s64: +** mov (x[0-9]+), #?5 +** whilele p0\.b, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b8_s64, int64_t, + p0 = svwhilele_b8_s64 (x0, 5), + p0 = svwhilele_b8 (x0, (int64_t) 5)) + +/* +** whilele_rr_b8_u32: +** whilels p0\.b, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b8_u32, uint32_t, + p0 = svwhilele_b8_u32 (x0, x1), + p0 = svwhilele_b8 (x0, x1)) + +/* +** whilele_0r_b8_u32: +** whilels p0\.b, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b8_u32, uint32_t, + p0 = svwhilele_b8_u32 (0, x1), + p0 = svwhilele_b8 ((uint32_t) 0, x1)) + +/* +** whilele_5r_b8_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.b, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b8_u32, uint32_t, + p0 = svwhilele_b8_u32 (5, x1), + p0 = svwhilele_b8 ((uint32_t) 5, x1)) + +/* +** whilele_r5_b8_u32: +** mov (w[0-9]+), #?5 +** whilels p0\.b, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b8_u32, uint32_t, + p0 = svwhilele_b8_u32 (x0, 5), + p0 = svwhilele_b8 (x0, (uint32_t) 5)) + +/* +** whilele_rr_b8_u64: +** whilels p0\.b, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilele_rr_b8_u64, uint64_t, + p0 = svwhilele_b8_u64 (x0, x1), + p0 = svwhilele_b8 (x0, x1)) + +/* +** whilele_0r_b8_u64: +** whilels p0\.b, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilele_0r_b8_u64, uint64_t, + p0 = svwhilele_b8_u64 (0, x1), + p0 = svwhilele_b8 ((uint64_t) 0, x1)) + +/* +** whilele_5r_b8_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.b, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilele_5r_b8_u64, uint64_t, + p0 = svwhilele_b8_u64 (5, x1), + p0 = svwhilele_b8 ((uint64_t) 5, x1)) + +/* +** whilele_r5_b8_u64: +** mov (x[0-9]+), #?5 +** whilels p0\.b, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilele_r5_b8_u64, uint64_t, + p0 = svwhilele_b8_u64 (x0, 5), + p0 = svwhilele_b8 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b16.c new file mode 100644 index 00000000000..14a60432b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b16.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilelt_rr_b16_s32: +** whilelt p0\.h, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b16_s32, int32_t, + p0 = svwhilelt_b16_s32 (x0, x1), + p0 = svwhilelt_b16 (x0, x1)) + +/* +** whilelt_0r_b16_s32: +** whilelt p0\.h, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b16_s32, int32_t, + p0 = svwhilelt_b16_s32 (0, x1), + p0 = svwhilelt_b16 (0, x1)) + +/* +** whilelt_5r_b16_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.h, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b16_s32, int32_t, + p0 = svwhilelt_b16_s32 (5, x1), + p0 = svwhilelt_b16 (5, x1)) + +/* +** whilelt_r0_b16_s32: +** whilelt p0\.h, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b16_s32, int32_t, + p0 = svwhilelt_b16_s32 (x0, 0), + p0 = svwhilelt_b16 (x0, 0)) + +/* +** whilelt_r5_b16_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.h, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b16_s32, int32_t, + p0 = svwhilelt_b16_s32 (x0, 5), + p0 = svwhilelt_b16 (x0, 5)) + +/* +** whilelt_rr_b16_s64: +** whilelt p0\.h, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b16_s64, int64_t, + p0 = svwhilelt_b16_s64 (x0, x1), + p0 = svwhilelt_b16 (x0, x1)) + +/* +** whilelt_0r_b16_s64: +** whilelt p0\.h, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b16_s64, int64_t, + p0 = svwhilelt_b16_s64 (0, x1), + p0 = svwhilelt_b16 ((int64_t) 0, x1)) + +/* +** whilelt_5r_b16_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.h, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b16_s64, int64_t, + p0 = svwhilelt_b16_s64 (5, x1), + p0 = svwhilelt_b16 ((int64_t) 5, x1)) + +/* +** whilelt_r0_b16_s64: +** whilelt p0\.h, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b16_s64, int64_t, + p0 = svwhilelt_b16_s64 (x0, 0), + p0 = svwhilelt_b16 (x0, (int64_t) 0)) + +/* +** whilelt_r5_b16_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.h, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b16_s64, int64_t, + p0 = svwhilelt_b16_s64 (x0, 5), + p0 = svwhilelt_b16 (x0, (int64_t) 5)) + +/* +** whilelt_rr_b16_u32: +** whilelo p0\.h, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b16_u32, uint32_t, + p0 = svwhilelt_b16_u32 (x0, x1), + p0 = svwhilelt_b16 (x0, x1)) + +/* +** whilelt_0r_b16_u32: +** whilelo p0\.h, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b16_u32, uint32_t, + p0 = svwhilelt_b16_u32 (0, x1), + p0 = svwhilelt_b16 ((uint32_t) 0, x1)) + +/* +** whilelt_5r_b16_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.h, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b16_u32, uint32_t, + p0 = svwhilelt_b16_u32 (5, x1), + p0 = svwhilelt_b16 ((uint32_t) 5, x1)) + +/* +** whilelt_r5_b16_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.h, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b16_u32, uint32_t, + p0 = svwhilelt_b16_u32 (x0, 5), + p0 = svwhilelt_b16 (x0, (uint32_t) 5)) + +/* +** whilelt_rr_b16_u64: +** whilelo p0\.h, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b16_u64, uint64_t, + p0 = svwhilelt_b16_u64 (x0, x1), + p0 = svwhilelt_b16 (x0, x1)) + +/* +** whilelt_0r_b16_u64: +** whilelo p0\.h, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b16_u64, uint64_t, + p0 = svwhilelt_b16_u64 (0, x1), + p0 = svwhilelt_b16 ((uint64_t) 0, x1)) + +/* +** whilelt_5r_b16_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.h, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b16_u64, uint64_t, + p0 = svwhilelt_b16_u64 (5, x1), + p0 = svwhilelt_b16 ((uint64_t) 5, x1)) + +/* +** whilelt_r5_b16_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.h, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b16_u64, uint64_t, + p0 = svwhilelt_b16_u64 (x0, 5), + p0 = svwhilelt_b16 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b32.c new file mode 100644 index 00000000000..0e50bb07a8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b32.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilelt_rr_b32_s32: +** whilelt p0\.s, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b32_s32, int32_t, + p0 = svwhilelt_b32_s32 (x0, x1), + p0 = svwhilelt_b32 (x0, x1)) + +/* +** whilelt_0r_b32_s32: +** whilelt p0\.s, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b32_s32, int32_t, + p0 = svwhilelt_b32_s32 (0, x1), + p0 = svwhilelt_b32 (0, x1)) + +/* +** whilelt_5r_b32_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.s, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b32_s32, int32_t, + p0 = svwhilelt_b32_s32 (5, x1), + p0 = svwhilelt_b32 (5, x1)) + +/* +** whilelt_r0_b32_s32: +** whilelt p0\.s, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b32_s32, int32_t, + p0 = svwhilelt_b32_s32 (x0, 0), + p0 = svwhilelt_b32 (x0, 0)) + +/* +** whilelt_r5_b32_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.s, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b32_s32, int32_t, + p0 = svwhilelt_b32_s32 (x0, 5), + p0 = svwhilelt_b32 (x0, 5)) + +/* +** whilelt_rr_b32_s64: +** whilelt p0\.s, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b32_s64, int64_t, + p0 = svwhilelt_b32_s64 (x0, x1), + p0 = svwhilelt_b32 (x0, x1)) + +/* +** whilelt_0r_b32_s64: +** whilelt p0\.s, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b32_s64, int64_t, + p0 = svwhilelt_b32_s64 (0, x1), + p0 = svwhilelt_b32 ((int64_t) 0, x1)) + +/* +** whilelt_5r_b32_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.s, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b32_s64, int64_t, + p0 = svwhilelt_b32_s64 (5, x1), + p0 = svwhilelt_b32 ((int64_t) 5, x1)) + +/* +** whilelt_r0_b32_s64: +** whilelt p0\.s, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b32_s64, int64_t, + p0 = svwhilelt_b32_s64 (x0, 0), + p0 = svwhilelt_b32 (x0, (int64_t) 0)) + +/* +** whilelt_r5_b32_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.s, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b32_s64, int64_t, + p0 = svwhilelt_b32_s64 (x0, 5), + p0 = svwhilelt_b32 (x0, (int64_t) 5)) + +/* +** whilelt_rr_b32_u32: +** whilelo p0\.s, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b32_u32, uint32_t, + p0 = svwhilelt_b32_u32 (x0, x1), + p0 = svwhilelt_b32 (x0, x1)) + +/* +** whilelt_0r_b32_u32: +** whilelo p0\.s, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b32_u32, uint32_t, + p0 = svwhilelt_b32_u32 (0, x1), + p0 = svwhilelt_b32 ((uint32_t) 0, x1)) + +/* +** whilelt_5r_b32_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.s, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b32_u32, uint32_t, + p0 = svwhilelt_b32_u32 (5, x1), + p0 = svwhilelt_b32 ((uint32_t) 5, x1)) + +/* +** whilelt_r5_b32_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.s, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b32_u32, uint32_t, + p0 = svwhilelt_b32_u32 (x0, 5), + p0 = svwhilelt_b32 (x0, (uint32_t) 5)) + +/* +** whilelt_rr_b32_u64: +** whilelo p0\.s, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b32_u64, uint64_t, + p0 = svwhilelt_b32_u64 (x0, x1), + p0 = svwhilelt_b32 (x0, x1)) + +/* +** whilelt_0r_b32_u64: +** whilelo p0\.s, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b32_u64, uint64_t, + p0 = svwhilelt_b32_u64 (0, x1), + p0 = svwhilelt_b32 ((uint64_t) 0, x1)) + +/* +** whilelt_5r_b32_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.s, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b32_u64, uint64_t, + p0 = svwhilelt_b32_u64 (5, x1), + p0 = svwhilelt_b32 ((uint64_t) 5, x1)) + +/* +** whilelt_r5_b32_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.s, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b32_u64, uint64_t, + p0 = svwhilelt_b32_u64 (x0, 5), + p0 = svwhilelt_b32 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b64.c new file mode 100644 index 00000000000..539c933479b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b64.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilelt_rr_b64_s32: +** whilelt p0\.d, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b64_s32, int32_t, + p0 = svwhilelt_b64_s32 (x0, x1), + p0 = svwhilelt_b64 (x0, x1)) + +/* +** whilelt_0r_b64_s32: +** whilelt p0\.d, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b64_s32, int32_t, + p0 = svwhilelt_b64_s32 (0, x1), + p0 = svwhilelt_b64 (0, x1)) + +/* +** whilelt_5r_b64_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.d, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b64_s32, int32_t, + p0 = svwhilelt_b64_s32 (5, x1), + p0 = svwhilelt_b64 (5, x1)) + +/* +** whilelt_r0_b64_s32: +** whilelt p0\.d, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b64_s32, int32_t, + p0 = svwhilelt_b64_s32 (x0, 0), + p0 = svwhilelt_b64 (x0, 0)) + +/* +** whilelt_r5_b64_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.d, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b64_s32, int32_t, + p0 = svwhilelt_b64_s32 (x0, 5), + p0 = svwhilelt_b64 (x0, 5)) + +/* +** whilelt_rr_b64_s64: +** whilelt p0\.d, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b64_s64, int64_t, + p0 = svwhilelt_b64_s64 (x0, x1), + p0 = svwhilelt_b64 (x0, x1)) + +/* +** whilelt_0r_b64_s64: +** whilelt p0\.d, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b64_s64, int64_t, + p0 = svwhilelt_b64_s64 (0, x1), + p0 = svwhilelt_b64 ((int64_t) 0, x1)) + +/* +** whilelt_5r_b64_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.d, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b64_s64, int64_t, + p0 = svwhilelt_b64_s64 (5, x1), + p0 = svwhilelt_b64 ((int64_t) 5, x1)) + +/* +** whilelt_r0_b64_s64: +** whilelt p0\.d, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b64_s64, int64_t, + p0 = svwhilelt_b64_s64 (x0, 0), + p0 = svwhilelt_b64 (x0, (int64_t) 0)) + +/* +** whilelt_r5_b64_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.d, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b64_s64, int64_t, + p0 = svwhilelt_b64_s64 (x0, 5), + p0 = svwhilelt_b64 (x0, (int64_t) 5)) + +/* +** whilelt_rr_b64_u32: +** whilelo p0\.d, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b64_u32, uint32_t, + p0 = svwhilelt_b64_u32 (x0, x1), + p0 = svwhilelt_b64 (x0, x1)) + +/* +** whilelt_0r_b64_u32: +** whilelo p0\.d, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b64_u32, uint32_t, + p0 = svwhilelt_b64_u32 (0, x1), + p0 = svwhilelt_b64 ((uint32_t) 0, x1)) + +/* +** whilelt_5r_b64_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.d, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b64_u32, uint32_t, + p0 = svwhilelt_b64_u32 (5, x1), + p0 = svwhilelt_b64 ((uint32_t) 5, x1)) + +/* +** whilelt_r5_b64_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.d, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b64_u32, uint32_t, + p0 = svwhilelt_b64_u32 (x0, 5), + p0 = svwhilelt_b64 (x0, (uint32_t) 5)) + +/* +** whilelt_rr_b64_u64: +** whilelo p0\.d, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b64_u64, uint64_t, + p0 = svwhilelt_b64_u64 (x0, x1), + p0 = svwhilelt_b64 (x0, x1)) + +/* +** whilelt_0r_b64_u64: +** whilelo p0\.d, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b64_u64, uint64_t, + p0 = svwhilelt_b64_u64 (0, x1), + p0 = svwhilelt_b64 ((uint64_t) 0, x1)) + +/* +** whilelt_5r_b64_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.d, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b64_u64, uint64_t, + p0 = svwhilelt_b64_u64 (5, x1), + p0 = svwhilelt_b64 ((uint64_t) 5, x1)) + +/* +** whilelt_r5_b64_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.d, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b64_u64, uint64_t, + p0 = svwhilelt_b64_u64 (x0, 5), + p0 = svwhilelt_b64 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b8.c new file mode 100644 index 00000000000..5b6a5c44d3f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/whilelt_b8.c @@ -0,0 +1,173 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** whilelt_rr_b8_s32: +** whilelt p0\.b, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b8_s32, int32_t, + p0 = svwhilelt_b8_s32 (x0, x1), + p0 = svwhilelt_b8 (x0, x1)) + +/* +** whilelt_0r_b8_s32: +** whilelt p0\.b, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b8_s32, int32_t, + p0 = svwhilelt_b8_s32 (0, x1), + p0 = svwhilelt_b8 (0, x1)) + +/* +** whilelt_5r_b8_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.b, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b8_s32, int32_t, + p0 = svwhilelt_b8_s32 (5, x1), + p0 = svwhilelt_b8 (5, x1)) + +/* +** whilelt_r0_b8_s32: +** whilelt p0\.b, w0, wzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b8_s32, int32_t, + p0 = svwhilelt_b8_s32 (x0, 0), + p0 = svwhilelt_b8 (x0, 0)) + +/* +** whilelt_r5_b8_s32: +** mov (w[0-9]+), #?5 +** whilelt p0\.b, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b8_s32, int32_t, + p0 = svwhilelt_b8_s32 (x0, 5), + p0 = svwhilelt_b8 (x0, 5)) + +/* +** whilelt_rr_b8_s64: +** whilelt p0\.b, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b8_s64, int64_t, + p0 = svwhilelt_b8_s64 (x0, x1), + p0 = svwhilelt_b8 (x0, x1)) + +/* +** whilelt_0r_b8_s64: +** whilelt p0\.b, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b8_s64, int64_t, + p0 = svwhilelt_b8_s64 (0, x1), + p0 = svwhilelt_b8 ((int64_t) 0, x1)) + +/* +** whilelt_5r_b8_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.b, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b8_s64, int64_t, + p0 = svwhilelt_b8_s64 (5, x1), + p0 = svwhilelt_b8 ((int64_t) 5, x1)) + +/* +** whilelt_r0_b8_s64: +** whilelt p0\.b, x0, xzr +** ret +*/ +TEST_COMPARE_S (whilelt_r0_b8_s64, int64_t, + p0 = svwhilelt_b8_s64 (x0, 0), + p0 = svwhilelt_b8 (x0, (int64_t) 0)) + +/* +** whilelt_r5_b8_s64: +** mov (x[0-9]+), #?5 +** whilelt p0\.b, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b8_s64, int64_t, + p0 = svwhilelt_b8_s64 (x0, 5), + p0 = svwhilelt_b8 (x0, (int64_t) 5)) + +/* +** whilelt_rr_b8_u32: +** whilelo p0\.b, w0, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b8_u32, uint32_t, + p0 = svwhilelt_b8_u32 (x0, x1), + p0 = svwhilelt_b8 (x0, x1)) + +/* +** whilelt_0r_b8_u32: +** whilelo p0\.b, wzr, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b8_u32, uint32_t, + p0 = svwhilelt_b8_u32 (0, x1), + p0 = svwhilelt_b8 ((uint32_t) 0, x1)) + +/* +** whilelt_5r_b8_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.b, \1, w1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b8_u32, uint32_t, + p0 = svwhilelt_b8_u32 (5, x1), + p0 = svwhilelt_b8 ((uint32_t) 5, x1)) + +/* +** whilelt_r5_b8_u32: +** mov (w[0-9]+), #?5 +** whilelo p0\.b, w0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b8_u32, uint32_t, + p0 = svwhilelt_b8_u32 (x0, 5), + p0 = svwhilelt_b8 (x0, (uint32_t) 5)) + +/* +** whilelt_rr_b8_u64: +** whilelo p0\.b, x0, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_rr_b8_u64, uint64_t, + p0 = svwhilelt_b8_u64 (x0, x1), + p0 = svwhilelt_b8 (x0, x1)) + +/* +** whilelt_0r_b8_u64: +** whilelo p0\.b, xzr, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_0r_b8_u64, uint64_t, + p0 = svwhilelt_b8_u64 (0, x1), + p0 = svwhilelt_b8 ((uint64_t) 0, x1)) + +/* +** whilelt_5r_b8_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.b, \1, x1 +** ret +*/ +TEST_COMPARE_S (whilelt_5r_b8_u64, uint64_t, + p0 = svwhilelt_b8_u64 (5, x1), + p0 = svwhilelt_b8 ((uint64_t) 5, x1)) + +/* +** whilelt_r5_b8_u64: +** mov (x[0-9]+), #?5 +** whilelo p0\.b, x0, \1 +** ret +*/ +TEST_COMPARE_S (whilelt_r5_b8_u64, uint64_t, + p0 = svwhilelt_b8_u64 (x0, 5), + p0 = svwhilelt_b8 (x0, (uint64_t) 5)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b16.c new file mode 100644 index 00000000000..269260eb40c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_b16_tied1: +** zip1 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (zip1_b16_tied1, + p0 = svzip1_b16 (p0, p1), + p0 = svzip1_b16 (p0, p1)) + +/* +** zip1_b16_tied2: +** zip1 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (zip1_b16_tied2, + p0 = svzip1_b16 (p1, p0), + p0 = svzip1_b16 (p1, p0)) + +/* +** zip1_b16_untied: +** zip1 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (zip1_b16_untied, + p0 = svzip1_b16 (p1, p2), + p0 = svzip1_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b32.c new file mode 100644 index 00000000000..027609a7d8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_b32_tied1: +** zip1 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (zip1_b32_tied1, + p0 = svzip1_b32 (p0, p1), + p0 = svzip1_b32 (p0, p1)) + +/* +** zip1_b32_tied2: +** zip1 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (zip1_b32_tied2, + p0 = svzip1_b32 (p1, p0), + p0 = svzip1_b32 (p1, p0)) + +/* +** zip1_b32_untied: +** zip1 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (zip1_b32_untied, + p0 = svzip1_b32 (p1, p2), + p0 = svzip1_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b64.c new file mode 100644 index 00000000000..8add16d8e6d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_b64_tied1: +** zip1 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (zip1_b64_tied1, + p0 = svzip1_b64 (p0, p1), + p0 = svzip1_b64 (p0, p1)) + +/* +** zip1_b64_tied2: +** zip1 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (zip1_b64_tied2, + p0 = svzip1_b64 (p1, p0), + p0 = svzip1_b64 (p1, p0)) + +/* +** zip1_b64_untied: +** zip1 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (zip1_b64_untied, + p0 = svzip1_b64 (p1, p2), + p0 = svzip1_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b8.c new file mode 100644 index 00000000000..8648298acb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_b8_tied1: +** zip1 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (zip1_b8_tied1, + p0 = svzip1_b8 (p0, p1), + p0 = svzip1_b8 (p0, p1)) + +/* +** zip1_b8_tied2: +** zip1 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (zip1_b8_tied2, + p0 = svzip1_b8 (p1, p0), + p0 = svzip1_b8 (p1, p0)) + +/* +** zip1_b8_untied: +** zip1 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (zip1_b8_untied, + p0 = svzip1_b8 (p1, p2), + p0 = svzip1_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f16.c new file mode 100644 index 00000000000..1c6ce4e7d1b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_f16_tied1: +** zip1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_f16_tied1, svfloat16_t, + z0 = svzip1_f16 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_f16_tied2: +** zip1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_f16_tied2, svfloat16_t, + z0 = svzip1_f16 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_f16_untied: +** zip1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_f16_untied, svfloat16_t, + z0 = svzip1_f16 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f32.c new file mode 100644 index 00000000000..288ceff3f29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_f32_tied1: +** zip1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_f32_tied1, svfloat32_t, + z0 = svzip1_f32 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_f32_tied2: +** zip1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_f32_tied2, svfloat32_t, + z0 = svzip1_f32 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_f32_untied: +** zip1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_f32_untied, svfloat32_t, + z0 = svzip1_f32 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f64.c new file mode 100644 index 00000000000..5abbea1cd3b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_f64_tied1: +** zip1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_f64_tied1, svfloat64_t, + z0 = svzip1_f64 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_f64_tied2: +** zip1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_f64_tied2, svfloat64_t, + z0 = svzip1_f64 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_f64_untied: +** zip1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_f64_untied, svfloat64_t, + z0 = svzip1_f64 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s16.c new file mode 100644 index 00000000000..8ecd20142f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_s16_tied1: +** zip1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_s16_tied1, svint16_t, + z0 = svzip1_s16 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_s16_tied2: +** zip1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_s16_tied2, svint16_t, + z0 = svzip1_s16 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_s16_untied: +** zip1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_s16_untied, svint16_t, + z0 = svzip1_s16 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s32.c new file mode 100644 index 00000000000..c523885ea29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_s32_tied1: +** zip1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_s32_tied1, svint32_t, + z0 = svzip1_s32 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_s32_tied2: +** zip1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_s32_tied2, svint32_t, + z0 = svzip1_s32 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_s32_untied: +** zip1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_s32_untied, svint32_t, + z0 = svzip1_s32 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s64.c new file mode 100644 index 00000000000..d1dca7ee98e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_s64_tied1: +** zip1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_s64_tied1, svint64_t, + z0 = svzip1_s64 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_s64_tied2: +** zip1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_s64_tied2, svint64_t, + z0 = svzip1_s64 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_s64_untied: +** zip1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_s64_untied, svint64_t, + z0 = svzip1_s64 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s8.c new file mode 100644 index 00000000000..1600ab58643 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_s8_tied1: +** zip1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_s8_tied1, svint8_t, + z0 = svzip1_s8 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_s8_tied2: +** zip1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_s8_tied2, svint8_t, + z0 = svzip1_s8 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_s8_untied: +** zip1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_s8_untied, svint8_t, + z0 = svzip1_s8 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u16.c new file mode 100644 index 00000000000..3773ed22fec --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_u16_tied1: +** zip1 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_u16_tied1, svuint16_t, + z0 = svzip1_u16 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_u16_tied2: +** zip1 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_u16_tied2, svuint16_t, + z0 = svzip1_u16 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_u16_untied: +** zip1 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip1_u16_untied, svuint16_t, + z0 = svzip1_u16 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u32.c new file mode 100644 index 00000000000..e67c121e56f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_u32_tied1: +** zip1 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_u32_tied1, svuint32_t, + z0 = svzip1_u32 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_u32_tied2: +** zip1 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_u32_tied2, svuint32_t, + z0 = svzip1_u32 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_u32_untied: +** zip1 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip1_u32_untied, svuint32_t, + z0 = svzip1_u32 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u64.c new file mode 100644 index 00000000000..bb6380a6a46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_u64_tied1: +** zip1 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_u64_tied1, svuint64_t, + z0 = svzip1_u64 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_u64_tied2: +** zip1 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_u64_tied2, svuint64_t, + z0 = svzip1_u64 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_u64_untied: +** zip1 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip1_u64_untied, svuint64_t, + z0 = svzip1_u64 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u8.c new file mode 100644 index 00000000000..01d89d4fe46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip1_u8_tied1: +** zip1 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_u8_tied1, svuint8_t, + z0 = svzip1_u8 (z0, z1), + z0 = svzip1 (z0, z1)) + +/* +** zip1_u8_tied2: +** zip1 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_u8_tied2, svuint8_t, + z0 = svzip1_u8 (z1, z0), + z0 = svzip1 (z1, z0)) + +/* +** zip1_u8_untied: +** zip1 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (zip1_u8_untied, svuint8_t, + z0 = svzip1_u8 (z1, z2), + z0 = svzip1 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b16.c new file mode 100644 index 00000000000..5624c9815a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_b16_tied1: +** zip2 p0\.h, p0\.h, p1\.h +** ret +*/ +TEST_UNIFORM_P (zip2_b16_tied1, + p0 = svzip2_b16 (p0, p1), + p0 = svzip2_b16 (p0, p1)) + +/* +** zip2_b16_tied2: +** zip2 p0\.h, p1\.h, p0\.h +** ret +*/ +TEST_UNIFORM_P (zip2_b16_tied2, + p0 = svzip2_b16 (p1, p0), + p0 = svzip2_b16 (p1, p0)) + +/* +** zip2_b16_untied: +** zip2 p0\.h, p1\.h, p2\.h +** ret +*/ +TEST_UNIFORM_P (zip2_b16_untied, + p0 = svzip2_b16 (p1, p2), + p0 = svzip2_b16 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b32.c new file mode 100644 index 00000000000..b73d5b4902c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_b32_tied1: +** zip2 p0\.s, p0\.s, p1\.s +** ret +*/ +TEST_UNIFORM_P (zip2_b32_tied1, + p0 = svzip2_b32 (p0, p1), + p0 = svzip2_b32 (p0, p1)) + +/* +** zip2_b32_tied2: +** zip2 p0\.s, p1\.s, p0\.s +** ret +*/ +TEST_UNIFORM_P (zip2_b32_tied2, + p0 = svzip2_b32 (p1, p0), + p0 = svzip2_b32 (p1, p0)) + +/* +** zip2_b32_untied: +** zip2 p0\.s, p1\.s, p2\.s +** ret +*/ +TEST_UNIFORM_P (zip2_b32_untied, + p0 = svzip2_b32 (p1, p2), + p0 = svzip2_b32 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b64.c new file mode 100644 index 00000000000..9ebf050b858 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_b64_tied1: +** zip2 p0\.d, p0\.d, p1\.d +** ret +*/ +TEST_UNIFORM_P (zip2_b64_tied1, + p0 = svzip2_b64 (p0, p1), + p0 = svzip2_b64 (p0, p1)) + +/* +** zip2_b64_tied2: +** zip2 p0\.d, p1\.d, p0\.d +** ret +*/ +TEST_UNIFORM_P (zip2_b64_tied2, + p0 = svzip2_b64 (p1, p0), + p0 = svzip2_b64 (p1, p0)) + +/* +** zip2_b64_untied: +** zip2 p0\.d, p1\.d, p2\.d +** ret +*/ +TEST_UNIFORM_P (zip2_b64_untied, + p0 = svzip2_b64 (p1, p2), + p0 = svzip2_b64 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b8.c new file mode 100644 index 00000000000..223a22f99e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_b8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_b8_tied1: +** zip2 p0\.b, p0\.b, p1\.b +** ret +*/ +TEST_UNIFORM_P (zip2_b8_tied1, + p0 = svzip2_b8 (p0, p1), + p0 = svzip2_b8 (p0, p1)) + +/* +** zip2_b8_tied2: +** zip2 p0\.b, p1\.b, p0\.b +** ret +*/ +TEST_UNIFORM_P (zip2_b8_tied2, + p0 = svzip2_b8 (p1, p0), + p0 = svzip2_b8 (p1, p0)) + +/* +** zip2_b8_untied: +** zip2 p0\.b, p1\.b, p2\.b +** ret +*/ +TEST_UNIFORM_P (zip2_b8_untied, + p0 = svzip2_b8 (p1, p2), + p0 = svzip2_b8 (p1, p2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f16.c new file mode 100644 index 00000000000..73d4272bcb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_f16_tied1: +** zip2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_f16_tied1, svfloat16_t, + z0 = svzip2_f16 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_f16_tied2: +** zip2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_f16_tied2, svfloat16_t, + z0 = svzip2_f16 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_f16_untied: +** zip2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_f16_untied, svfloat16_t, + z0 = svzip2_f16 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f32.c new file mode 100644 index 00000000000..2ad8ff81d6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_f32_tied1: +** zip2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_f32_tied1, svfloat32_t, + z0 = svzip2_f32 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_f32_tied2: +** zip2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_f32_tied2, svfloat32_t, + z0 = svzip2_f32 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_f32_untied: +** zip2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_f32_untied, svfloat32_t, + z0 = svzip2_f32 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f64.c new file mode 100644 index 00000000000..de5c2646fe4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_f64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_f64_tied1: +** zip2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_f64_tied1, svfloat64_t, + z0 = svzip2_f64 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_f64_tied2: +** zip2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_f64_tied2, svfloat64_t, + z0 = svzip2_f64 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_f64_untied: +** zip2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_f64_untied, svfloat64_t, + z0 = svzip2_f64 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s16.c new file mode 100644 index 00000000000..fc366c99138 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_s16_tied1: +** zip2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_s16_tied1, svint16_t, + z0 = svzip2_s16 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_s16_tied2: +** zip2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_s16_tied2, svint16_t, + z0 = svzip2_s16 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_s16_untied: +** zip2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_s16_untied, svint16_t, + z0 = svzip2_s16 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s32.c new file mode 100644 index 00000000000..e56934d264c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_s32_tied1: +** zip2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_s32_tied1, svint32_t, + z0 = svzip2_s32 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_s32_tied2: +** zip2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_s32_tied2, svint32_t, + z0 = svzip2_s32 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_s32_untied: +** zip2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_s32_untied, svint32_t, + z0 = svzip2_s32 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s64.c new file mode 100644 index 00000000000..cefc73b7236 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_s64_tied1: +** zip2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_s64_tied1, svint64_t, + z0 = svzip2_s64 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_s64_tied2: +** zip2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_s64_tied2, svint64_t, + z0 = svzip2_s64 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_s64_untied: +** zip2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_s64_untied, svint64_t, + z0 = svzip2_s64 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s8.c new file mode 100644 index 00000000000..452bbce26e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_s8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_s8_tied1: +** zip2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_s8_tied1, svint8_t, + z0 = svzip2_s8 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_s8_tied2: +** zip2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_s8_tied2, svint8_t, + z0 = svzip2_s8 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_s8_untied: +** zip2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_s8_untied, svint8_t, + z0 = svzip2_s8 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u16.c new file mode 100644 index 00000000000..9a20b4ed1d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u16.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_u16_tied1: +** zip2 z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_u16_tied1, svuint16_t, + z0 = svzip2_u16 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_u16_tied2: +** zip2 z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_u16_tied2, svuint16_t, + z0 = svzip2_u16 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_u16_untied: +** zip2 z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (zip2_u16_untied, svuint16_t, + z0 = svzip2_u16 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u32.c new file mode 100644 index 00000000000..70626c66e4c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u32.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_u32_tied1: +** zip2 z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_u32_tied1, svuint32_t, + z0 = svzip2_u32 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_u32_tied2: +** zip2 z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_u32_tied2, svuint32_t, + z0 = svzip2_u32 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_u32_untied: +** zip2 z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (zip2_u32_untied, svuint32_t, + z0 = svzip2_u32 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u64.c new file mode 100644 index 00000000000..43a43ff7cae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u64.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_u64_tied1: +** zip2 z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_u64_tied1, svuint64_t, + z0 = svzip2_u64 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_u64_tied2: +** zip2 z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_u64_tied2, svuint64_t, + z0 = svzip2_u64 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_u64_untied: +** zip2 z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (zip2_u64_untied, svuint64_t, + z0 = svzip2_u64 (z1, z2), + z0 = svzip2 (z1, z2)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u8.c new file mode 100644 index 00000000000..015f1844bbf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2_u8.c @@ -0,0 +1,30 @@ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sve_acle.h" + +/* +** zip2_u8_tied1: +** zip2 z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_u8_tied1, svuint8_t, + z0 = svzip2_u8 (z0, z1), + z0 = svzip2 (z0, z1)) + +/* +** zip2_u8_tied2: +** zip2 z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_u8_tied2, svuint8_t, + z0 = svzip2_u8 (z1, z0), + z0 = svzip2 (z1, z0)) + +/* +** zip2_u8_untied: +** zip2 z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (zip2_u8_untied, svuint8_t, + z0 = svzip2_u8 (z1, z2), + z0 = svzip2 (z1, z2)) -- 2.30.2