From bcb7f5cb0411558cb5faf10e2fb21ed0e6430fe2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 23 Jan 2022 11:04:25 +0000 Subject: [PATCH] add debug output of whether stall occurs on dcache --- src/soc/experiment/dcache.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index ee6cc5ca..910d123a 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -691,6 +691,9 @@ class DCache(Elaboratable): self.m_out = DCacheToMMUType("m_out") self.stall_out = Signal() + self.any_stall_out = Signal() + self.dreq_when_stall = Signal() + self.mreq_when_stall = Signal() # standard naming (wired to non-standard for compatibility) self.bus = Interface(addr_width=32, @@ -1686,8 +1689,8 @@ class DCache(Elaboratable): def elaborate(self, platform): m = Module() - comb = m.d.comb - d_in = self.d_in + comb, sync = m.d.comb, m.d.sync + m_in, d_in = self.m_in, self.d_in # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs cache_tags = CacheTagArray() @@ -1763,6 +1766,14 @@ class DCache(Elaboratable): comb += r0_stall.eq(r0_full & (r1.full | d_in.hold)) comb += r0_valid.eq(r0_full & ~r1.full & ~d_in.hold) comb += self.stall_out.eq(r0_stall) + # debugging: detect if any stall ever requested, which is fine, + # but if a request comes in when stall requested, that's bad. + with m.If(r0_stall): + sync += self.any_stall_out.eq(1) + with m.If(d_in.valid): + sync += self.dreq_when_stall.eq(1) + with m.If(m_in.valid): + sync += self.mreq_when_stall.eq(1) # deal with litex not doing wishbone pipeline mode # XXX in wrong way. FIFOs are needed in the SRAM test -- 2.30.2