From bce69d6cca1ff031fe371c4432bbf54826f9e440 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Sep 2020 12:25:37 +0100
Subject: [PATCH] attempt GPIO bi-directional

---
 src/soc/litex/florent/libresoc/ls180.py | 31 +++++++------------------
 src/soc/litex/florent/ls180soc.py       | 11 ++++-----
 2 files changed, 12 insertions(+), 30 deletions(-)

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 17b87725..68512277 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -109,29 +109,14 @@ _io = [
     ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
 ]
 
-if False:
-    pinbank1 = []
-    pinbank2 = []
-    for i in range(8):
-        pinbank1.append("X%d" % i)
-        pinbank2.append("Y%d" % i)
-    pins = ' '.join(pinbank1 + pinbank2)
-
-    # 16 GPIOs
-    _io.append( ("gpio", 16, Pins(pins), IOStandard("LVCMOS33")) )
-
-pinsin = []
-pinsout = []
-for i in range(8):
-    pinsin.append("X%d" % i)
-    pinsout.append("Y%d" % i)
-pinsin = ' '.join(pinsin)
-pinsout = ' '.join(pinsout)
-
-# GPIO in: 8 pins
-_io.append( ("gpio_in", 8, Pins(pinsin), IOStandard("LVCMOS33")) )
-# GPIO out: 8 pins
-_io.append( ("gpio_out", 8, Pins(pinsout), IOStandard("LVCMOS33")) )
+pins = []
+n_gpio = 12
+for i in range(n_gpio):
+    pins.append("X%d" % i)
+pins = ' '.join(pins)
+
+# 12 GPIOs
+_io.append( ("gpio", n_gpio, Pins(pins), IOStandard("LVCMOS33")) )
 
 # EINT: 3 pins
 _io.append( ("eint", 3, Pins("E0 E1 E2"), IOStandard("LVCMOS33")) )
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 72b23a66..4e7fc353 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -20,7 +20,7 @@ from litedram import modules as litedram_modules
 from litedram.phy.model import SDRAMPHYModel
 from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
 
-from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut#, GPIOTristate
+from litex.soc.cores.gpio import GPIOTristate
 from litex.soc.cores.spi import SPIMaster
 from litex.soc.cores.pwm import PWM
 from litex.soc.cores.bitbang import I2CMaster
@@ -170,12 +170,9 @@ class LibreSoCSim(SoCCore):
             self.add_constant("MEMTEST_ADDR_DEBUG", 1)
             self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
-        # GPIOs
-        #platform.add_extension([("gpio_in", 0, Pins(8))])
-        self.submodules.gpio_in = GPIOIn(platform.request("gpio_in"))
-        self.add_csr("gpio_in")
-        self.submodules.gpio_out = GPIOIn(platform.request("gpio_out"))
-        self.add_csr("gpio_out")
+        # GPIOs (bi-directional)
+        self.submodules.gpio = GPIOTristate(platform.request("gpio"))
+        self.add_csr("gpio")
 
         if False:
             self.submodules.gpio = GPIOTristate(platform.request("gpio"))
-- 
2.30.2