From bd14b1bcaa088e9a8385dd10cfbd4cc144db3ef3 Mon Sep 17 00:00:00 2001 From: Ciro Santilli Date: Fri, 5 Jun 2020 11:06:13 +0100 Subject: [PATCH] arch-arm: mark ID_AA64ISAR1_EL1.JSCVT implemented The feature was implemented at: I1b24839daef775bbb1eb9da5f32c4bb3843e0b28 Change-Id: I0c0f55e55a1ca3ca6bf40206a989ef0bb353ee84 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30934 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/ArmISA.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index f701f7d15..b2513f7cf 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012-2013, 2015-2019 ARM Limited +# Copyright (c) 2012-2013, 2015-2020 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -101,8 +101,8 @@ class ArmISA(BaseISA): id_aa64isar0_el1 = Param.UInt64(0x0000000000000000, "AArch64 Instruction Set Attribute Register 0") - # GPI = 0x0 | GPA = 0x1| API=0x0 | APA=0x1 | FCMA - id_aa64isar1_el1 = Param.UInt64(0x0000000001010010, + # GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1 + id_aa64isar1_el1 = Param.UInt64(0x0000000001011010, "AArch64 Instruction Set Attribute Register 1") # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA -- 2.30.2