From bd18a316e1495f501911d89c8b373382d1f8c8c2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Christian=20K=C3=B6nig?= Date: Wed, 18 Jul 2012 10:03:34 +0200 Subject: [PATCH] radeonsi: move infeered fb/rs state to new handling MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König --- .../drivers/radeonsi/evergreen_hw_context.c | 5 -- .../drivers/radeonsi/evergreen_state.c | 50 ---------------- src/gallium/drivers/radeonsi/radeonsi_pipe.h | 2 - src/gallium/drivers/radeonsi/si_state.c | 59 ++++++++++++++++--- src/gallium/drivers/radeonsi/si_state.h | 1 + 5 files changed, 52 insertions(+), 65 deletions(-) diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c b/src/gallium/drivers/radeonsi/evergreen_hw_context.c index 9d3187ba836..07fa74f7e1c 100644 --- a/src/gallium/drivers/radeonsi/evergreen_hw_context.c +++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c @@ -160,11 +160,6 @@ static const struct r600_reg si_context_reg_list[] = { {R_028AC8_DB_PRELOAD_CONTROL, 0}, {R_028B54_VGT_SHADER_STAGES_EN, 0}, {R_028B70_DB_ALPHA_TO_MASK, 0}, - {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0}, - {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0}, - {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0}, - {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0}, - {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0}, {R_028B94_VGT_STRMOUT_CONFIG, 0}, {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0}, {R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0}, diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c b/src/gallium/drivers/radeonsi/evergreen_state.c index a34f4329509..f1e7ee6fcfd 100644 --- a/src/gallium/drivers/radeonsi/evergreen_state.c +++ b/src/gallium/drivers/radeonsi/evergreen_state.c @@ -1206,56 +1206,6 @@ void si_init_config(struct r600_context *rctx) r600_context_pipe_state_set(rctx, rstate); } -void cayman_polygon_offset_update(struct r600_context *rctx) -{ - struct r600_pipe_state state; - - state.id = R600_PIPE_STATE_POLYGON_OFFSET; - state.nregs = 0; - if (rctx->queued.named.rasterizer && rctx->framebuffer.zsbuf) { - float offset_units = rctx->queued.named.rasterizer->offset_units; - unsigned offset_db_fmt_cntl = 0, depth; - - switch (rctx->framebuffer.zsbuf->texture->format) { - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - depth = -24; - offset_units *= 2.0f; - break; - case PIPE_FORMAT_Z32_FLOAT: - case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - depth = -23; - offset_units *= 1.0f; - offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); - break; - case PIPE_FORMAT_Z16_UNORM: - depth = -16; - offset_units *= 4.0f; - break; - default: - return; - } - /* FIXME some of those reg can be computed with cso */ - offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); - r600_pipe_state_add_reg(&state, - R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, - fui(rctx->queued.named.rasterizer->offset_scale), NULL, 0); - r600_pipe_state_add_reg(&state, - R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, - fui(offset_units), NULL, 0); - r600_pipe_state_add_reg(&state, - R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, - fui(rctx->queued.named.rasterizer->offset_scale), NULL, 0); - r600_pipe_state_add_reg(&state, - R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, - fui(offset_units), NULL, 0); - r600_pipe_state_add_reg(&state, - R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, - offset_db_fmt_cntl, NULL, 0); - r600_context_pipe_state_set(rctx, &state); - } -} - void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader) { struct r600_context *rctx = (struct r600_context *)ctx; diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h index 2a3004e0ff9..880912794d8 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h @@ -85,7 +85,6 @@ enum r600_pipe_state_id { R600_PIPE_STATE_CONSTANT, R600_PIPE_STATE_SAMPLER, R600_PIPE_STATE_RESOURCE, - R600_PIPE_STATE_POLYGON_OFFSET, R600_PIPE_NSTATES }; @@ -324,7 +323,6 @@ void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader); void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader); void si_update_spi_map(struct r600_context *rctx); void *cayman_create_db_flush_dsa(struct r600_context *rctx); -void cayman_polygon_offset_update(struct r600_context *rctx); uint32_t si_translate_vertexformat(struct pipe_screen *screen, enum pipe_format format, const struct util_format_description *desc, diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 149182e5265..ac1d3ff8e02 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -270,6 +270,55 @@ static void si_set_viewport_state(struct pipe_context *ctx, si_pm4_set_state(rctx, viewport, viewport); } +/* + * inferred state between framebuffer and rasterizer + */ +static void si_update_fb_rs_state(struct r600_context *rctx) +{ + struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; + struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); + unsigned offset_db_fmt_cntl = 0, depth; + float offset_units; + + if (!rs || !rctx->framebuffer.zsbuf) { + FREE(pm4); + return; + } + + offset_units = rctx->queued.named.rasterizer->offset_units; + switch (rctx->framebuffer.zsbuf->texture->format) { + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + depth = -24; + offset_units *= 2.0f; + break; + case PIPE_FORMAT_Z32_FLOAT: + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: + depth = -23; + offset_units *= 1.0f; + offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); + break; + case PIPE_FORMAT_Z16_UNORM: + depth = -16; + offset_units *= 4.0f; + break; + default: + return; + } + + /* FIXME some of those reg can be computed with cso */ + offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); + si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, + fui(rctx->queued.named.rasterizer->offset_scale)); + si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); + si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, + fui(rctx->queued.named.rasterizer->offset_scale)); + si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); + si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); + + si_pm4_set_state(rctx, fb_rs, pm4); +} + /* * Rasterizer */ @@ -407,10 +456,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; si_pm4_bind_state(rctx, rasterizer, rs); - - if (rctx->chip_class >= CAYMAN) { - cayman_polygon_offset_update(rctx); - } + si_update_fb_rs_state(rctx); } static void si_delete_rs_state(struct pipe_context *ctx, void *state) @@ -1069,10 +1115,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); si_pm4_set_state(rctx, framebuffer, pm4); - - if (state->zsbuf) { - cayman_polygon_offset_update(rctx); - } + si_update_fb_rs_state(rctx); } void si_init_state_functions(struct r600_context *rctx) diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index ff88d8305ca..68b54f8cee2 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -61,6 +61,7 @@ union si_state { struct si_state_viewport *viewport; struct si_pm4_state *framebuffer; struct si_state_rasterizer *rasterizer; + struct si_pm4_state *fb_rs; } named; struct si_pm4_state *array[0]; }; -- 2.30.2