From bd18d160991d69df57c50b580290ce0afbdbe56c Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 30 May 2022 08:13:42 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index b2276fdff..53fab3333 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -161,12 +161,12 @@ Mode bits. SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch Conditional: -| 4 | 5 | 6 | 7 | 19 | 20 | 21 | 22 23 | description | -| - | - | - | - | -- | -- | --- |---------|----------------- | -|ALL|SNZ| / | / | 0 | 0 | / | LRu sz | normal mode | -|ALL|SNZ| / |VSb| 0 | 1 | VLI | LRu sz | VLSET mode | -|ALL|SNZ|CTi| / | 1 | 0 | / | LRu sz | CTR-test mode | -|ALL|SNZ|CTi|VSb| 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode | +| 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 | 21 | 22 23 | description | +| - | - | - | - | -- | -- | -- | -- | --- |--------|----------------- | +|ALL|SNZ| / | / | | | 0 | 0 | / | LRu sz | normal mode | +|ALL|SNZ| / |VSb| | | 0 | 1 | VLI | LRu sz | VLSET mode | +|ALL|SNZ|CTi| / | | | 1 | 0 | / | LRu sz | CTR-test mode | +|ALL|SNZ|CTi|VSb| | | 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode | Brief description of fields: -- 2.30.2