From bd1a25959205a6bfb14acfa8c986ea4cdb1f90f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 15 Mar 2020 22:32:30 +0000 Subject: [PATCH] Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility --- 99/d0add69373ecb3355c2fd71f72b94ae39da7e1 | 82 +++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 99/d0add69373ecb3355c2fd71f72b94ae39da7e1 diff --git a/99/d0add69373ecb3355c2fd71f72b94ae39da7e1 b/99/d0add69373ecb3355c2fd71f72b94ae39da7e1 new file mode 100644 index 0000000..ba9a124 --- /dev/null +++ b/99/d0add69373ecb3355c2fd71f72b94ae39da7e1 @@ -0,0 +1,82 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Sun, 15 Mar 2020 22:33:05 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jDboe-0003T2-Eo; Sun, 15 Mar 2020 22:33:04 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jDbod-0003Sw-2r + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 22:33:03 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:In-Reply-To:References:MIME-Version; + bh=od6yAVh4SSplbczTmxhJeq8V/+Q2wH0AQk+NLm4h+p8=; + b=WXCfX5MRmPlIxavDb428nePic+d671uPF5+UD0yI4rBR6QYNqLVgwAdPhu0fPcuwhzu12sNapYGGFcUy6HIFXGAEEVbKp+iEdKJAvTserzaqhDlbk/ZgNYzI7Peb+cPCunUfEiwpPhM8zAK8etgJ/bcl8cT7+dxzyXEWTAfaTUU=; +Received: from mail-lf1-f44.google.com ([209.85.167.44]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jDboc-0008FP-Ms + for libre-riscv-dev@lists.libre-riscv.org; Sun, 15 Mar 2020 22:33:02 +0000 +Received: by mail-lf1-f44.google.com with SMTP id f3so2124821lfc.1 + for ; + Sun, 15 Mar 2020 15:32:47 -0700 (PDT) +X-Gm-Message-State: ANhLgQ0b9imLHtaS1uUnxG6I99ZfHy+G6cgJqYMqiApVbSgyu7AVibTx + aVtsY0sPxvZSjHIbhSYqVHUnUu7lIkuf97ZR0Fg= +X-Google-Smtp-Source: ADFU+vva33U8ly6Z2eHT35iguvjTOjrpdjwZXYlttt8/Z3seaLqbkM4rJ4uOYDZF15/BcexAdU0PuJiZJ7eBqOO6fU8= +X-Received: by 2002:a19:4cc4:: with SMTP id z187mr14691141lfa.49.1584311561730; + Sun, 15 Mar 2020 15:32:41 -0700 (PDT) +MIME-Version: 1.0 +References: <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu> + + <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> + + + + <1BB9EA49-275B-4365-963E-9FC21D574BB7@gatech.edu> + <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu> + + <75CA4609-370F-455E-A88D-50E3766D45D7@gatech.edu> + + <884F8FEE-60FF-4580-A2E7-8AAA40A6DB6B@gatech.edu> + + <8C348DCE-274B-476B-8F61-C1BB5F1C3EC1@gatech.edu> + + + +In-Reply-To: +From: Luke Kenneth Casson Leighton +Date: Sun, 15 Mar 2020 22:32:30 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture + feasibility +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gU3VuLCBNYXIgMTUsIDIwMjAgYXQgMTA6MjMgUE0gQWRhbSBWYW4gWW1lcmVuIDxhZGFtQHZh +bnkuY2E+IHdyb3RlOgoKPiBUZWNobmljYWxseSB0aGV5J2xsIGhhdmUgYW4gZWFzeSB0aW1lIHN1 +aW5nIHlvdS4KCnNvLi4uIGhvdyB3b3VsZCB0aGF0IGdvPyAgd2hhdCBkbyB5b3UgdGhpbmsgdGhl +IGhlYWRsaW5lIG5ld3Mgd291bGQKYmU/ICBhbmQgd2hhdCB3b3VsZCB0aGUgRUZGLCBGU0YgYW5k +IHRoZSBTRkxDJ3MgcmVzcG9uc2UgYmUgaWYgd2UKYXNrZWQgdGhlbSBmb3IgaGVscD8gIGhhdmUg +YSBndWVzcy4uLiA6KQoKbC4KCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f +X19fX19fX19fCmxpYnJlLXJpc2N2LWRldiBtYWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxp +c3RzLmxpYnJlLXJpc2N2Lm9yZwpodHRwOi8vbGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4v +bGlzdGluZm8vbGlicmUtcmlzY3YtZGV2Cg== -- 2.30.2