From bd1feb28273e8d7047304e5a2a02ca3d71de5533 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 24 Feb 2016 01:13:22 +0100 Subject: [PATCH] gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadata MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/r300/r300_texture.c | 4 ++-- src/gallium/drivers/radeon/r600_texture.c | 4 ++-- src/gallium/drivers/radeon/radeon_winsys.h | 8 ++++---- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 12 ++++++------ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 12 ++++++------ 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 3db7f372c68..57456c6d867 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -1064,7 +1064,7 @@ r300_texture_create_object(struct r300_screen *rscreen, tiling.microtile = tex->tex.microtile; tiling.macrotile = tex->tex.macrotile[0]; tiling.stride = tex->tex.stride_in_bytes[0]; - rws->buffer_set_tiling(tex->buf, &tiling); + rws->buffer_set_metadata(tex->buf, &tiling); return tex; @@ -1120,7 +1120,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, if (!buffer) return NULL; - rws->buffer_get_tiling(buffer, &tiling); + rws->buffer_get_metadata(buffer, &tiling); /* Enforce a microtiled zbuffer. */ if (util_format_is_depth_or_stencil(base->format) && diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index b9f5c61a3c3..4f187881334 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -253,7 +253,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, metadata.stride = surface->level[0].pitch_bytes; metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; - rscreen->ws->buffer_set_tiling(resource->buf, &metadata); + rscreen->ws->buffer_set_metadata(resource->buf, &metadata); return rscreen->ws->buffer_get_handle(resource->buf, surface->level[0].pitch_bytes, whandle); @@ -901,7 +901,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen if (!buf) return NULL; - rscreen->ws->buffer_get_tiling(buf, &metadata); + rscreen->ws->buffer_get_metadata(buf, &metadata); surface.bankw = metadata.bankw; surface.bankh = metadata.bankh; diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index a885df98d5c..566322c60ab 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -475,8 +475,8 @@ struct radeon_winsys { * \param buf A winsys buffer object to get the flags from. * \param md Metadata */ - void (*buffer_get_tiling)(struct pb_buffer *buf, - struct radeon_bo_metadata *md); + void (*buffer_get_metadata)(struct pb_buffer *buf, + struct radeon_bo_metadata *md); /** * Set buffer metadata. @@ -485,8 +485,8 @@ struct radeon_winsys { * \param buf A winsys buffer object to set the flags for. * \param md Metadata */ - void (*buffer_set_tiling)(struct pb_buffer *buf, - struct radeon_bo_metadata *md); + void (*buffer_set_metadata)(struct pb_buffer *buf, + struct radeon_bo_metadata *md); /** * Get a winsys buffer from a winsys handle. The internal structure diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 6a79e388311..10ac2b25c6b 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -390,8 +390,8 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split) } } -static void amdgpu_bo_get_tiling(struct pb_buffer *_buf, - struct radeon_bo_metadata *md) +static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf, + struct radeon_bo_metadata *md) { struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_info info = {0}; @@ -419,8 +419,8 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf, md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ } -static void amdgpu_bo_set_tiling(struct pb_buffer *_buf, - struct radeon_bo_metadata *md) +static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf, + struct radeon_bo_metadata *md) { struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_metadata metadata = {0}; @@ -702,8 +702,8 @@ static uint64_t amdgpu_bo_get_va(struct pb_buffer *buf) void amdgpu_bo_init_functions(struct amdgpu_winsys *ws) { - ws->base.buffer_set_tiling = amdgpu_bo_set_tiling; - ws->base.buffer_get_tiling = amdgpu_bo_get_tiling; + ws->base.buffer_set_metadata = amdgpu_buffer_set_metadata; + ws->base.buffer_get_metadata = amdgpu_buffer_get_metadata; ws->base.buffer_map = amdgpu_bo_map; ws->base.buffer_unmap = amdgpu_bo_unmap; ws->base.buffer_wait = amdgpu_bo_wait; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index cd769f7ade9..978df52447e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -636,8 +636,8 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split) } } -static void radeon_bo_get_tiling(struct pb_buffer *_buf, - struct radeon_bo_metadata *md) +static void radeon_bo_get_metadata(struct pb_buffer *_buf, + struct radeon_bo_metadata *md) { struct radeon_bo *bo = radeon_bo(_buf); struct drm_radeon_gem_set_tiling args; @@ -670,8 +670,8 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf, md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); } -static void radeon_bo_set_tiling(struct pb_buffer *_buf, - struct radeon_bo_metadata *md) +static void radeon_bo_set_metadata(struct pb_buffer *_buf, + struct radeon_bo_metadata *md) { struct radeon_bo *bo = radeon_bo(_buf); struct drm_radeon_gem_set_tiling args; @@ -1040,8 +1040,8 @@ static uint64_t radeon_winsys_bo_va(struct pb_buffer *buf) void radeon_drm_bo_init_functions(struct radeon_drm_winsys *ws) { - ws->base.buffer_set_tiling = radeon_bo_set_tiling; - ws->base.buffer_get_tiling = radeon_bo_get_tiling; + ws->base.buffer_set_metadata = radeon_bo_set_metadata; + ws->base.buffer_get_metadata = radeon_bo_get_metadata; ws->base.buffer_map = radeon_bo_map; ws->base.buffer_unmap = radeon_bo_unmap; ws->base.buffer_wait = radeon_bo_wait; -- 2.30.2