From bd5ed0977b57fca3b4d661edbcee3e89a7dd0a18 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Feb 2015 12:51:43 +0100 Subject: [PATCH] platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms) --- mibuild/platforms/apf27.py | 2 ++ mibuild/platforms/apf51.py | 2 ++ mibuild/platforms/de0nano.py | 2 ++ mibuild/platforms/kc705.py | 2 ++ mibuild/platforms/lx9_microboard.py | 2 ++ mibuild/platforms/m1.py | 2 ++ mibuild/platforms/mixxeo.py | 2 ++ mibuild/platforms/ml605.py | 2 ++ mibuild/platforms/papilio_pro.py | 2 ++ mibuild/platforms/rhino.py | 2 ++ mibuild/platforms/usrp_b100.py | 2 ++ mibuild/platforms/zedboard.py | 2 ++ mibuild/platforms/ztex_115d.py | 2 ++ 13 files changed, 26 insertions(+) diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py index 048b857b..3490c1c4 100644 --- a/mibuild/platforms/apf27.py +++ b/mibuild/platforms/apf27.py @@ -142,6 +142,8 @@ _connectors = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk0" + default_clk_period = 10 def __init__(self): XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios, lambda p: SimpleCRG(p, "clk0", None), _connectors) diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py index e15eb27a..2f7f92d6 100644 --- a/mibuild/platforms/apf51.py +++ b/mibuild/platforms/apf51.py @@ -169,6 +169,8 @@ _connectors = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk3" + default_clk_period = 10.526 def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios, lambda p: SimpleCRG(p, "clk3", None), _connectors) diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index d0c99046..4cab4b9c 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -92,6 +92,8 @@ _io = [ ] class Platform(AlteraQuartusPlatform): + default_clk_name = "clk50" + default_clk_period = 20 def __init__(self): AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io, lambda p: SimpleCRG(p, "clk50", None)) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 1deab34a..528a187d 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -348,6 +348,8 @@ def Platform(*args, toolchain="vivado", **kwargs): raise ValueError class RealPlatform(xilinx_platform): + default_clk_name = "clk156" + default_clk_period = 6.4 bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")): diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index a46d6319..8dbf01e8 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -103,6 +103,8 @@ _io = [ class Platform(XilinxISEPlatform): + default_clk_name = "clk_y3" + default_clk_period = 10 bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" ise_commands = """ promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 37b12cf0..cc1b619f 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -119,6 +119,8 @@ _io = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk50" + default_clk_period = 20 def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: SimpleCRG(p, "clk50", None)) diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index d09f546a..df9eac85 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -155,6 +155,8 @@ _io = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk50" + default_clk_period = 20 def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: SimpleCRG(p, "clk50", None)) diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py index f8236800..3b24ac21 100644 --- a/mibuild/platforms/ml605.py +++ b/mibuild/platforms/ml605.py @@ -52,6 +52,8 @@ _io = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk200" + default_clk_period = 5 def __init__(self): XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io, lambda p: CRG_DS(p, "clk200", "user_btn")) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index 82315552..0ccd8dd1 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -50,6 +50,8 @@ _connectors = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk32" + default_clk_period = 31.25 def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, lambda p: SimpleCRG(p, "clk32", None), _connectors) diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index f1af075e..9446305b 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -134,6 +134,8 @@ _io = [ ] class Platform(XilinxISEPlatform): + default_clk_name = "clk100" + default_clk_period = 10 def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io, lambda p: CRG_DS(p, "clk100", "gpio")) diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py index 1fb30080..8c826c4f 100644 --- a/mibuild/platforms/usrp_b100.py +++ b/mibuild/platforms/usrp_b100.py @@ -114,6 +114,8 @@ _io = [ class Platform(XilinxISEPlatform): + default_clk_name = "clk64" + default_clk_period = 15.625 bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" def __init__(self): XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io, diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index 2a3e91c6..5604a1f9 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -138,6 +138,8 @@ _io = [ class Platform(XilinxISEPlatform): + default_clk_name = "clk100" + default_clk_period = 10 def __init__(self): XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io, lambda p: SimpleCRG(p, "clk100", None)) diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index 970b1e7d..8513f96c 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -83,6 +83,8 @@ _io = [ class Platform(XilinxISEPlatform): def __init__(self): + default_clk_name = "clk_if" + default_clk_period = 20 XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io, lambda p: SimpleCRG(p, "clk_if", "rst")) self.add_platform_command(""" -- 2.30.2