From bd67eb2d784822e299d3162a015467ac8fba8ed4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 12:02:58 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 7f55cc2a3..12d2f28f7 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -212,13 +212,16 @@ FP Registers: | Value | Mnemonic | Description | |-------|----------------|------------------------------------| | 00 | DEFAULT | default behaviour for FP operation | -| 01 | `ELWIDTH=bf16` (rsvd) | Reserved for [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) | +| 01 | `ELWIDTH=bf16` | Reserved for `bf16` | | 10 | `ELWIDTH=f16` | 16-bit IEEE 754 Half floating-point | | 11 | `ELWIDTH=f32` | 32-bit IEEE 754 Single floating-point | +Note: [`bf16`](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) +is reserved for a future implementation of SV + CR Registers: -TODO +TODO, important, particularly for crops, mfcr and mtcr, what elwidth even means. instead it may be possible to use the bits as extra indices (EXTRA6) to access the full 64 CRs. TBD, several ideas ## SUBVL Encoding -- 2.30.2