From bd6dc53d6573de42d1d4441df140708f39b50cdf Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Tue, 26 Sep 2023 12:00:30 +0100 Subject: [PATCH] Added english language description, spaces and brackets for lq instruction --- openpower/isa/fixedload.mdwn | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 5ef607cd..649fa04c 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -619,6 +619,28 @@ Pseudo-code: EA <- b + EXTS(DQ || 0b0000) RTp <- MEM(EA, 16) +Description + + Let the effective address (EA) be the sum (RA|0)+ + (DQ||0b0000). The quadword in storage addressed by + EA is loaded into register pair RTp. + + If RTp is odd or RTp=RA, the instruction form is invalid. + If RTp=RA, an attempt to execute this instruction will + invoke the system illegal instruction error handler. (The + RTp=RA case includes the case of RTp=RA=0.) + + The quadword in storage addressed by EA is loaded + into an even-odd pair of GPRs as follows. In + Big-Endian mode, the even-numbered GPR is loaded + with the doubleword from storage addressed by EA + and the odd-numbered GPR is loaded with the double- + word addressed by EA+8. In Little-Endian mode, the + even-numbered GPR is loaded with the byte-reversed + doubleword from storage addressed by EA+8 and the + odd-numbered GPR is loaded with the byte-reversed + doubleword addressed by EA. + Special Registers Altered: None -- 2.30.2