From bd757fe5177e000680d16cd08f48d91072cfa22e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 27 Mar 2022 13:21:25 +0100 Subject: [PATCH] add link to Winbond HyperRAM model --- hyperram_model/README.txt | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hyperram_model/README.txt b/hyperram_model/README.txt index f2cf555..0718cbc 100644 --- a/hyperram_model/README.txt +++ b/hyperram_model/README.txt @@ -1,12 +1,18 @@ 1) download the Cypress HyperRAM Model http://www.cypress.com/verilog/s27kl0641-verilog -2) install icarus verilog -3) run ./runhyperramsim.sh +2) download the Winbond HyperRAM Model + https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip +3) install icarus verilog +4) run ./runhyperramsim.sh Cypress HyperRAM Model files are Copyright (C) 2015 Spansion, LLC. (no explicit license found, but they are available publicly for download) +Winbond HyperRAM Model files are +Copyright C 2019 Winbond Electronics Corp. All rights reserved. +(no explicit license found, but they are available publicly for download) + hbc_*.v files from https://github.com/gtjennings1/HyperBUS are Copyright 2017 Gnarly Grey LLC and have been released under this license by Gnarly Grey: -- 2.30.2