From bd7aac6caaece9a14841ae103c67bca423be3337 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 9 Sep 2022 19:08:56 -0700 Subject: [PATCH] move ffadds to not conflict with fptrans -- makes space for min/max/fmod/remainder ops --- openpower/isatables/minor_59.csv | 2 +- src/openpower/decoder/power_decoder2.py | 2 +- src/openpower/sv/trans/svp64.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index cdb66e40..2e7d13cc 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -18,7 +18,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -1000001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,2-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg +1111100000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,2-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg -----11011,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg 1001001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatan2s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1000001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatan2pis,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 157093c6..8cd7db70 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1037,7 +1037,7 @@ class PowerDecodeSubset(Elaboratable): '-----00101', # ffmadds '-----00110', # ffnmsubs '-----00111', # ffnmadds - '1000001100', # ffadds + '1111100000', # ffadds '-----11011', # fdmadds )) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 7b146fb4..7a7dad01 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1391,7 +1391,7 @@ class SVP64Asm: opcode |= int(v30b_newfields[0]) << (32-11) # FRT opcode |= int(v30b_newfields[1]) << (32-16) # FRA opcode |= int(v30b_newfields[2]) << (32-21) # FRB - opcode |= 0b1000001100 << (32-31) # bits 21-30 + opcode |= 0b1111100000 << (32-31) # bits 21-30 if rc: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode -- 2.30.2