From bd8a4100477a8026baa0f104f6685dde4f47f42c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 1 May 2020 20:12:02 +0200 Subject: [PATCH] cpu/minerva: add pythondata and use it to compile the sources. --- litex/soc/cores/cpu/minerva/core.py | 5 +++-- litex_setup.py | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index a4b63e62..b703f2f1 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -7,6 +7,7 @@ import subprocess from migen import * +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -98,8 +99,8 @@ class Minerva(CPU): cli_params.append("--with-dcache") if with_muldiv: cli_params.append("--with-muldiv") - os.system("git clone http://github.com/lambdaconcept/minerva") # FIXME: create pythondata. - if subprocess.call(["python3", os.path.join("minerva", "cli.py"), *cli_params, "generate"], + sdir = get_data_mod("cpu", "minerva").data_location + if subprocess.call(["python3", os.path.join(sdir, "cli.py"), *cli_params, "generate"], stdout=open(verilog_filename, "w")): raise OSError("Unable to elaborate Minerva CPU, please check your nMigen/Yosys install") diff --git a/litex_setup.py b/litex_setup.py index b0ef1f13..f6d6b393 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -46,6 +46,7 @@ repos = [ ("pythondata-cpu-serv", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos) -- 2.30.2