From bd8c9614da06899f81fd6d64834db56e4411a728 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 15 Aug 2019 11:45:53 +0100
Subject: [PATCH] dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER)

For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER)
Bits [63:32] and bits [31:0] are accessible separately.

Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/dev/arm/gic_v3_its.cc | 45 +++++++++++++++++++++++++++++++++++----
 src/dev/arm/gic_v3_its.hh |  4 ++++
 2 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/src/dev/arm/gic_v3_its.cc b/src/dev/arm/gic_v3_its.cc
index 26c123c03..de2683c24 100644
--- a/src/dev/arm/gic_v3_its.cc
+++ b/src/dev/arm/gic_v3_its.cc
@@ -826,14 +826,26 @@ Gicv3Its::read(PacketPtr pkt)
         value = gitsCbaser;
         break;
 
+      case GITS_CBASER + 4:
+        value = gitsCbaser.high;
+        break;
+
       case GITS_CWRITER:
         value = gitsCwriter;
         break;
 
+      case GITS_CWRITER + 4:
+        value = gitsCwriter.high;
+        break;
+
       case GITS_CREADR:
         value = gitsCreadr;
         break;
 
+      case GITS_CREADR + 4:
+        value = gitsCreadr.high;
+        break;
+
       case GITS_PIDR2:
         value = gic->getDistributor()->gicdPidr2;
         break;
@@ -879,16 +891,41 @@ Gicv3Its::write(PacketPtr pkt)
         panic("GITS_TYPER is Read Only\n");
 
       case GITS_CBASER:
-        assert(pkt->getSize() == sizeof(uint64_t));
-        gitsCbaser = pkt->getLE<uint64_t>();
+        if (pkt->getSize() == sizeof(uint32_t)) {
+            gitsCbaser.low = pkt->getLE<uint32_t>();
+        } else {
+            assert(pkt->getSize() == sizeof(uint64_t));
+            gitsCbaser = pkt->getLE<uint64_t>();
+        }
+
+        gitsCreadr = 0; // Cleared when CBASER gets written
+
+        checkCommandQueue();
+        break;
+
+      case GITS_CBASER + 4:
+        assert(pkt->getSize() == sizeof(uint32_t));
+        gitsCbaser.high = pkt->getLE<uint32_t>();
+
         gitsCreadr = 0; // Cleared when CBASER gets written
 
         checkCommandQueue();
         break;
 
       case GITS_CWRITER:
-        assert(pkt->getSize() == sizeof(uint64_t));
-        gitsCwriter = pkt->getLE<uint64_t>();
+        if (pkt->getSize() == sizeof(uint32_t)) {
+            gitsCwriter.low = pkt->getLE<uint32_t>();
+        } else {
+            assert(pkt->getSize() == sizeof(uint64_t));
+            gitsCwriter = pkt->getLE<uint64_t>();
+        }
+
+        checkCommandQueue();
+        break;
+
+      case GITS_CWRITER + 4:
+        assert(pkt->getSize() == sizeof(uint32_t));
+        gitsCwriter.high = pkt->getLE<uint32_t>();
 
         checkCommandQueue();
         break;
diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index e09f712be..dae18d516 100644
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -149,12 +149,16 @@ class Gicv3Its : public BasicPioDevice
 
     // Command read/write, (CREADR, CWRITER)
     BitUnion64(CRDWR)
+        Bitfield<63, 32> high;
+        Bitfield<31, 0> low;
         Bitfield<19, 5> offset;
         Bitfield<0> retry;
         Bitfield<0> stalled;
     EndBitUnion(CRDWR)
 
     BitUnion64(CBASER)
+        Bitfield<63, 32> high;
+        Bitfield<31, 0> low;
         Bitfield<63> valid;
         Bitfield<61, 59> innerCache;
         Bitfield<55, 53> outerCache;
-- 
2.30.2