From bdb70ff77dc04c559e65ad704c8885d885a4fd08 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 May 2020 15:06:03 +0100 Subject: [PATCH] mention that the 4x4 crossbar is a major data bottleneck --- 3d_gpu/architecture/regfile.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn index b71d52fa9..b59ebad67 100644 --- a/3d_gpu/architecture/regfile.mdwn +++ b/3d_gpu/architecture/regfile.mdwn @@ -45,6 +45,10 @@ busy. Below is the connectivity diagram: Notes: +* There is only **one** 4x4 crossbar (or, one for reads, one for writes?) + and thus only **one** inter-Quadrant 32-bit-wide data path (total + bandwidth 4x32 bits). These to be shared by **five** groups of + operand ports at each of the Quadrant Global Cyclic Buffers. * The **only** way for register results and operands to cross over between quadrants of the regfile is that 4x4 crossbar. Data transfer bandwidth being limited, the placement of an operation adversely affects its -- 2.30.2