From bdc47b205ac3c9624f3e82d21ff88e9a5b383030 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 18 Mar 2015 12:08:25 +0100 Subject: [PATCH] Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)" This breaks simulations, and we will try to use the "reg name = value" syntax instead. This reverts commit e946f6e4538277308e374cd1f0b1b9a31f66dc5a. --- migen/fhdl/verilog.py | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 7f97fa0d..de36556f 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -279,19 +279,11 @@ def _printinit(f, ios, ns): - ios \ - list_targets(f) \ - list_special_ios(f, False, True, True) - wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \ - - ios \ - - list_targets(f) \ - - list_special_ios(f, False, True, True) if signals: + r += "initial begin\n" for s in sorted(signals, key=lambda x: x.huid): - if s in wires: - r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n" - r += "always @(*) begin\n" - for s in sorted(signals, key=lambda x: x.huid): - if s not in wires: - r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n" - r += "end\n" + r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n" + r += "end\n\n" return r def convert(f, ios=None, name="top", -- 2.30.2