From bdde97f5fd3bacebba0e7adc2ec941f18852121d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 16 Jan 2012 18:42:55 +0100 Subject: [PATCH] New naming system beginning to work --- examples/simple_gpio.py | 2 +- migen/actorlib/dma_wishbone.py | 3 +++ migen/fhdl/namer.py | 14 ++++++++++---- migen/fhdl/structure.py | 2 +- migen/fhdl/verilog.py | 4 ++-- 5 files changed, 17 insertions(+), 8 deletions(-) diff --git a/examples/simple_gpio.py b/examples/simple_gpio.py index a6253d39..e0d1c6b8 100644 --- a/examples/simple_gpio.py +++ b/examples/simple_gpio.py @@ -20,6 +20,6 @@ inf = Fragment(incomb, insync) bank = csrgen.Bank([oreg, ireg]) f = bank.get_fragment() + inf i = bank.interface -ofield.dev_r.name = "gpio_out" +ofield.dev_r.name_override = "gpio_out" v = verilog.convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in}) print(v) diff --git a/migen/actorlib/dma_wishbone.py b/migen/actorlib/dma_wishbone.py index ac6704f0..4a6d4b1e 100644 --- a/migen/actorlib/dma_wishbone.py +++ b/migen/actorlib/dma_wishbone.py @@ -81,3 +81,6 @@ class Reader(Actor): controller = fsm.get_fragment() return address_generator + output_buffer + controller + +class Writer(Actor): + pass # TODO diff --git a/migen/fhdl/namer.py b/migen/fhdl/namer.py index cdd2a992..324b77d3 100644 --- a/migen/fhdl/namer.py +++ b/migen/fhdl/namer.py @@ -67,7 +67,7 @@ def build_tree(signals): def name_backtrace(root, backtrace): parts = [] - for step in backtrace: + for step in backtrace[:-1]: n = obj_name(step[0]) found = list(filter(lambda x: x.name == n, root.children)) node = found[0] @@ -78,13 +78,19 @@ def name_backtrace(root, backtrace): parts.append(node.name) if node.include_varname and step[1] is not None: parts.append(step[1]) + root = node + last = backtrace[-1] + if last[1] is not None: + parts.append(last[1]) + else: + parts.append(obj_name(last[0])) return "_".join(parts) def _include_divergence(root, bt1, bt2): for step1, step2 in zip(bt1, bt2): n1, n2 = obj_name(step1[0]), obj_name(step2[0]) - node1 = list(filter(lambda x: x.name == n1, root.children)) - node2 = list(filter(lambda x: x.name == n2, root.children)) + node1 = list(filter(lambda x: x.name == n1, root.children))[0] + node2 = list(filter(lambda x: x.name == n2, root.children))[0] if node1 != node2: node1.include_context = True node2.include_context = True @@ -101,7 +107,7 @@ def _include_divergence(root, bt1, bt2): def resolve_conflicts(root, signals): for s1, s2 in combinations(signals, 2): - if name_backtrace(root, s1) == name_backtrace(root, s2): + if name_backtrace(root, s1.backtrace) == name_backtrace(root, s2.backtrace): _include_divergence(root, s1.backtrace, s2.backtrace) def build_tree_res(signals): diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index 3dabbc6b..3b4033f8 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -145,7 +145,7 @@ class Signal(Value): return id(self) def __repr__(self): - return "" + return "" # statements diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 1842b20a..2d10d4f0 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -131,7 +131,7 @@ def _printcomb(f, ns): # to run the combinatorial process once at the beginning. syn_off = "// synthesis translate off\n" syn_on = "// synthesis translate on\n" - dummy_s = Signal() + dummy_s = Signal(name_override="dummy_s") r += syn_off r += "reg " + _printsig(ns, dummy_s) + ";\n" r += "initial " + ns.get_name(dummy_s) + " <= 1'b0;\n" @@ -143,7 +143,7 @@ def _printcomb(f, ns): if len(g[1]) == 1 and isinstance(g[1][0], _Assign): r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0]) else: - dummy_d = Signal() + dummy_d = Signal(name_override="dummy_d") r += "\n" + syn_off r += "reg " + _printsig(ns, dummy_d) + ";\n" r += syn_on -- 2.30.2