From bdea4152e3ffee02336078732144000e93ddd16b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 6 Jul 2017 18:32:08 +0200 Subject: [PATCH] soc/core/uart: add UartStub to enable fast simulation with cpu --- litex/soc/cores/uart.py | 20 ++++++++++++++++++++ litex/soc/integration/soc_core.py | 9 ++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 2edcf5c7..a32b6e5b 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -185,6 +185,26 @@ class UART(Module, AutoCSR): ] +class UARTStub(Module, AutoCSR): + def __init__(self): + self._rxtx = CSR(8) + self._txfull = CSRStatus() + self._rxempty = CSRStatus() + + self.submodules.ev = EventManager() + self.ev.tx = EventSourceProcess() + self.ev.rx = EventSourceProcess() + self.ev.finalize() + + # # # + + self.comb += [ + self._txfull.status.eq(0), + self.ev.tx.trigger.eq(~(self._rxtx.re & self._rxtx.r)), + self._rxempty.status.eq(1) + ] + + class UARTWishboneBridge(WishboneStreamingBridge): def __init__(self, pads, clk_freq, baudrate=115200): self.submodules.phy = RS232PHY(pads, clk_freq, baudrate) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 5959bd60..f3131784 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -41,7 +41,7 @@ class SoCCore(Module): integrated_main_ram_size=0, shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, - with_uart=True, uart_baudrate=115200, + with_uart=True, uart_baudrate=115200, uart_stub=False, ident="", with_timer=True): self.config = dict() @@ -107,8 +107,11 @@ class SoCCore(Module): self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) if with_uart: - self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate) - self.submodules.uart = uart.UART(self.uart_phy) + if uart_stub: + self.submodules.uart = uart.UARTStub() + else: + self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate) + self.submodules.uart = uart.UART(self.uart_phy) if ident: self.submodules.identifier = identifier.Identifier(ident) -- 2.30.2