From be1984326f91e54f5c6ab3378038600f9f042679 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 11 Sep 2021 16:26:39 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index bc52f0af7..86d1589eb 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -116,6 +116,10 @@ unaffected by their SVP64 variants in every conceivable way.
 
 # Format and fields
 
+With element-width overrides being meaningless for Condition
+Register Fields, bits 4 thru 7 of SVP64 RM may be used for additional
+Mode bits.
+
 SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
 Conditional:
 
-- 
2.30.2