From be19a68be8f59b70c359e8a958a4ec9246b4cba8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Apr 2021 15:43:16 +0100 Subject: [PATCH] add VCD output --- small_jtag_test/main.cpp | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/small_jtag_test/main.cpp b/small_jtag_test/main.cpp index 7859f64..987b742 100644 --- a/small_jtag_test/main.cpp +++ b/small_jtag_test/main.cpp @@ -12,8 +12,16 @@ #include #include +#include + #include "add.cpp" +#define VCD + +#ifdef VCD +#include +#endif + using namespace std; extern "C" { @@ -150,17 +158,44 @@ int read_openocd_jtagremote(cxxrtl_design::p_add &top, int sock) int main() { cxxrtl_design::p_add top; + int steps = 0; + +#ifdef VCD + // Load the debug items of the top down the whole design hierarchy + cxxrtl::debug_items all_debug_items; + top.debug_info(all_debug_items); + + // set up vcdwriter with 1ns resu + cxxrtl::vcd_writer vcd; + vcd.timescale(1, "us"); +#endif int listenfd = setup_socket(); int sock = -1; +#ifdef VCD + //vcd.add_without_memories(all_debug_items); + vcd.add(all_debug_items); + std::ofstream waves("waves.vcd"); +#endif + top.step(); +#ifdef VCD + vcd.sample(0); +#endif while (true) { top.p_clk.set(false); top.step(); +#ifdef VCD + vcd.sample(steps*2 + 0); +#endif top.p_clk.set(true); top.step(); +#ifdef VCD + vcd.sample(steps*2 + 1); +#endif + steps++; // if no current connection see if there is one if (sock == -1) { @@ -177,6 +212,9 @@ int main() cout << "f " << f << endl; */ + + waves << vcd.buffer; + vcd.buffer.clear(); } } -- 2.30.2