From be280bed5e60063a4c324564e721cdbf484abf88 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 12 Jul 2019 09:52:40 +0200 Subject: [PATCH] soc_zynq: use zynq fabric reset as sys reset --- litex/soc/integration/soc_zynq.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py index f8b1784f..a5451b25 100644 --- a/litex/soc/integration/soc_zynq.py +++ b/litex/soc/integration/soc_zynq.py @@ -32,6 +32,7 @@ class SoCZynq(SoCCore): SoCCore.__init__(self, platform, clk_freq, cpu_type=None, shadow_base=0x00000000, **kwargs) # PS7 (Minimal) ---------------------------------------------------------------------------- + fclk_reset0_n = Signal() ps7_ddram_pads = platform.request("ps7_ddram") self.ps7_params = dict( # clk/rst @@ -70,9 +71,11 @@ class SoCZynq(SoCCore): # usb0 i_USB0_VBUS_PWRFAULT=0, - # fabric clk + # fabric clk/rst o_FCLK_CLK0=ClockSignal("sys"), + o_FCLK_RESET0_N=fclk_reset0_n ) + self.comb += ResetSignal("sys").eq(~fclk_reset0_n) platform.add_ip(os.path.join("ip", ps7_name + ".xci")) # GP0 ------------------------------------------------------------------------------------------ -- 2.30.2