From be344b80cdf4fb5939e6a14b5f4d484481978071 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 9 May 2022 19:17:54 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 65b6ff27b..3f84bcba0 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -45,7 +45,13 @@ the underlying 150 mhz bitcells), but these efforts are dwarfed by the two nearly three orders of magnitude increase in CPU horsepower over the same timeframe. Seymour Cray, from his amazing in-depth knowledge, predicted that the mismatch -would become a serious limitation, over two decades ago. Some systems +would become a serious limitation, over two decades ago. + +The latency gap between that bitcell speed and the CPU speed can do nothing to help Random Access (unpredictable reads/writes). Cacheing helps only so +much, but not with some types of workloads (FFTs are one of the worst) +even though +they are fully deterministic. +Some systems at the time of writing are now approaching a *Gigabyte* of L4 Cache, by way of compensation, and as we know from experience even that will be considered inadequate in future. -- 2.30.2