From be3a1d33b8585e652febbb3608997036808dd3c8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Apr 2022 18:02:47 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index fb74a6526..f9a52c814 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -69,7 +69,8 @@ OPF ISA WG): |19 |RT |M |mask |BFA | 0 0 |XO[0:4]|0 mode |Rc|crrweird | |19 |RA |M |mask |BF | 0 1 |XO[0:4]|0 mode |/ |mtcrweird | |19 |BT |M |mask |BFA | 1 0 |XO[0:4]|0 mode |/ |crweirder | -|19 |BF //|M |mask |BFA | 1 1 |XO[0:4]|0 mode |/ |crweird | +|19 |BF //|M |mask |BFA | 1 1 |XO[0:4]|0 mode |0 |crweird | +|19 |BF //|M |mask |BFA | 1 1 |XO[0:4]|0 mode |1 |mcrfm | **crrweird** @@ -121,7 +122,7 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper **crweird** -bit 19=1, bit 20=0 +bit 19=1, bit 20=0, Rc=0 crweird: BF, BFA, M, mask.mode @@ -145,6 +146,29 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type oper 3-bit Data-dependent and 3-bit Predicate-result capability (BF is 3 bits) +**mcrfm** - Move CR Field, masked. + +bit 19=1, bit 20=0, Rc=1 + + mcrfm: BF, BFA, M, mask.mode + + result = mask & CR{BFA} + if M: + result |= CR{BF} & ~mask + else: + result ^= mode + CR{BF} = result + +Note that when M=1 this operation is a Read-Modify-Write on the CR Field +BF. Masked-out bits of the 4-bit CR Field BF will not be changed when +M=1. Correspondingly when M=0 this operation is an overwrite: no read +of BF is required because the masked-out bits of the BF CR Field are +set to zero. + +When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has +3-bit Data-dependent and 3-bit Predicate-result capability +(BF is 3 bits) + **crweirder** bit 19=1, bit 20=1 -- 2.30.2