From be4ae2e4365b53b73ca099ee092a9386e08f58bf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Mar 2021 20:09:34 +0100 Subject: [PATCH] use PRTBL SPR in RADIXMMU --- src/soc/decoder/isa/radixmmu.py | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py index accb78db..aeb7e97f 100644 --- a/src/soc/decoder/isa/radixmmu.py +++ b/src/soc/decoder/isa/radixmmu.py @@ -451,10 +451,8 @@ class RADIX: print("last 8 bits ----------") print - prtbl = SelectableInt(0x1000000,64) #FIXME do not hardcode - # get address of root entry - shift = selectconcat(SelectableInt(0,1),prtbl[58:63]) # TODO verify + shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr) print("starting with prtable, addr_next",addr_next) @@ -754,11 +752,14 @@ class TestRadixMMU(unittest.TestCase): testaddr = 0x1000 expected = 0x1000 + # starting prtbl + prtbl = 0x1000000 + # set up dummy minimal ISACaller spr = {'DSISR': SelectableInt(0, 64), 'DAR': SelectableInt(0, 64), 'PIDR': SelectableInt(0, 64), - 'PRTBL': SelectableInt(0, 64) + 'PRTBL': SelectableInt(prtbl, 64) } # set problem state == 0 (other unit tests, set to 1) msr = SelectableInt(0, 64) @@ -811,11 +812,14 @@ class TestRadixMMU(unittest.TestCase): testaddr = 0x1101 expected = 0x5001101 + # starting prtbl + prtbl = 0x1000000 + # set up dummy minimal ISACaller spr = {'DSISR': SelectableInt(0, 64), 'DAR': SelectableInt(0, 64), 'PIDR': SelectableInt(0, 64), - 'PRTBL': SelectableInt(0, 64) + 'PRTBL': SelectableInt(prtbl, 64) } # set problem state == 0 (other unit tests, set to 1) msr = SelectableInt(0, 64) -- 2.30.2