From be5b74c3e28e0738620f68d9574c2f2f26e98a37 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 4 May 2020 18:27:23 +0100 Subject: [PATCH] add links to bugreport and to memory/cache wiki page --- src/soc/experiment/l0_cache.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 27e2af66..22168267 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -8,6 +8,11 @@ test infrastructure, and, just as with minerva's memory arrangement, a dynamic runtime config *selects* alternative memory arrangements rather than *replaces and discards* this code. +Links: + +* https://bugs.libre-soc.org/show_bug.cgi?id=216 +* https://libre-soc.org/3d_gpu/architecture/memory_and_cache/ + """ from nmigen.compat.sim import run_simulation -- 2.30.2