From be8d26fcf524b0b73d4980afd72228dc310cbec3 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 15 May 2020 16:12:16 -0400 Subject: [PATCH] Implement op_bcreg --- src/soc/branch/main_stage.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py index 7d21be6a..b2cbc37a 100644 --- a/src/soc/branch/main_stage.py +++ b/src/soc/branch/main_stage.py @@ -100,7 +100,9 @@ class BranchMainStage(PipeModBase): comb += br_imm_addr.eq(br_ext(bd)) comb += br_taken.eq(bc_taken) #### branch conditional reg #### - # TODOwith m.Case(InternalOp.OP_BCREG): + with m.Case(InternalOp.OP_BCREG): + comb += br_imm_addr.eq(self.i.spr) + comb += br_taken.eq(bc_taken) ###### output next instruction address ##### -- 2.30.2