From be8eb5ff84168bdb5d91e50d258864be5c447d97 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Fri, 6 Jul 2018 18:22:32 +0800 Subject: [PATCH] vexriscv: debug: fix reading DATA register The REFRESH register accepts an 8-bit address and determines which register to refresh. Since there are only two addresses currently in use, this register can be either 0x00 or 0x04. A refactor replaced the compare with one that checked for any 0 bits. Since both 0x00 and 0x04 have 0 bits, this check always evaluated as true, causing the logic to always refresh the CORE register. Replace this check with an explicit check for 0x00. Signed-off-by: Sean Cross --- litex/soc/cores/cpu/vexriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 26ad64f7..a2476c74 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -95,7 +95,7 @@ class VexRiscv(Module, AutoCSR): # A write to the REFRESH register indicates which register # (DATA or CORE) we want to update from the CPU. ).Elif(debug_refresh.re, - If(~debug_refresh.storage, + If(debug_refresh.storage == 0, refreshing_data.eq(0), debug_bus_cmd_payload_address.eq(0) ).Else( -- 2.30.2