From be8eba062516c9767cb9e1b0c90ddc5f4700a8bf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 1 Feb 2017 02:00:05 +0100 Subject: [PATCH] radeonsi/gfx9: disable the 2-bit format fetch fix MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ae5aac0e465..b120e9a6836 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3342,6 +3342,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count, const struct pipe_vertex_element *elements) { + struct si_screen *sscreen = (struct si_screen*)ctx->screen; struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); bool used[SI_NUM_VERTEX_BUFFERS] = {}; int i; @@ -3381,9 +3382,12 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, v->format_size[i] = desc->block.bits / 8; /* The hardware always treats the 2-bit alpha channel as - * unsigned, so a shader workaround is needed. + * unsigned, so a shader workaround is needed. The affected + * chips are VI and older except Stoney (GFX8.1). */ - if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) { + if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 && + sscreen->b.chip_class <= VI && + sscreen->b.family != CHIP_STONEY) { if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) { v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM; } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) { -- 2.30.2