From be9ab669de4bf99e9475596681dbdfc8c5ba708f Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 21:07:31 +0100
Subject: [PATCH] scalar vector architectures

---
 svp64-primer/summary.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 2dd482882..0b613e0c3 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -98,7 +98,7 @@ the number of instructions increase:
 	Multi-issue decoding
 \end{itemize}
 
-\subsection{Vector Architectures}
+\subsection{Scalable Vector Architectures}
 An older alternative exists to utilise data parallelism - vector
 architectures. Vector CPUs collect operands from the main memory, and
 store them in large, sequential vector registers.\par
-- 
2.30.2