From be9b242d95f3ec5f044b7455fa9f32e2e8c55118 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 26 Jul 2013 04:39:25 -0700 Subject: [PATCH] Rip out Hwacha for now --- hwacha/README | 2 + hwacha/disasm.cc | 72 +++++++++++++++++++++ {riscv => hwacha}/insns/fmovn.h | 0 {riscv => hwacha}/insns/fmovz.h | 0 {riscv => hwacha}/insns/movn.h | 0 {riscv => hwacha}/insns/movz.h | 0 {riscv => hwacha}/insns/stop.h | 0 {riscv => hwacha}/insns/utidx.h | 0 {riscv => hwacha}/insns/venqcmd.h | 0 {riscv => hwacha}/insns/venqcnt.h | 0 {riscv => hwacha}/insns/venqimm1.h | 0 {riscv => hwacha}/insns/venqimm2.h | 0 {riscv => hwacha}/insns/vf.h | 0 {riscv => hwacha}/insns/vfld.h | 0 {riscv => hwacha}/insns/vflsegd.h | 0 {riscv => hwacha}/insns/vflsegstd.h | 0 {riscv => hwacha}/insns/vflsegstw.h | 0 {riscv => hwacha}/insns/vflsegw.h | 0 {riscv => hwacha}/insns/vflstd.h | 0 {riscv => hwacha}/insns/vflstw.h | 0 {riscv => hwacha}/insns/vflw.h | 0 {riscv => hwacha}/insns/vfmst.h | 0 {riscv => hwacha}/insns/vfmsv.h | 0 {riscv => hwacha}/insns/vfmts.h | 0 {riscv => hwacha}/insns/vfmvv.h | 0 {riscv => hwacha}/insns/vfsd.h | 0 {riscv => hwacha}/insns/vfssegd.h | 0 {riscv => hwacha}/insns/vfssegstd.h | 0 {riscv => hwacha}/insns/vfssegstw.h | 0 {riscv => hwacha}/insns/vfssegw.h | 0 {riscv => hwacha}/insns/vfsstd.h | 0 {riscv => hwacha}/insns/vfsstw.h | 0 {riscv => hwacha}/insns/vfsw.h | 0 {riscv => hwacha}/insns/vlb.h | 0 {riscv => hwacha}/insns/vlbu.h | 0 {riscv => hwacha}/insns/vld.h | 0 {riscv => hwacha}/insns/vlh.h | 0 {riscv => hwacha}/insns/vlhu.h | 0 {riscv => hwacha}/insns/vlsegb.h | 0 {riscv => hwacha}/insns/vlsegbu.h | 0 {riscv => hwacha}/insns/vlsegd.h | 0 {riscv => hwacha}/insns/vlsegh.h | 0 {riscv => hwacha}/insns/vlseghu.h | 0 {riscv => hwacha}/insns/vlsegstb.h | 0 {riscv => hwacha}/insns/vlsegstbu.h | 0 {riscv => hwacha}/insns/vlsegstd.h | 0 {riscv => hwacha}/insns/vlsegsth.h | 0 {riscv => hwacha}/insns/vlsegsthu.h | 0 {riscv => hwacha}/insns/vlsegstw.h | 0 {riscv => hwacha}/insns/vlsegstwu.h | 0 {riscv => hwacha}/insns/vlsegw.h | 0 {riscv => hwacha}/insns/vlsegwu.h | 0 {riscv => hwacha}/insns/vlstb.h | 0 {riscv => hwacha}/insns/vlstbu.h | 0 {riscv => hwacha}/insns/vlstd.h | 0 {riscv => hwacha}/insns/vlsth.h | 0 {riscv => hwacha}/insns/vlsthu.h | 0 {riscv => hwacha}/insns/vlstw.h | 0 {riscv => hwacha}/insns/vlstwu.h | 0 {riscv => hwacha}/insns/vlw.h | 0 {riscv => hwacha}/insns/vlwu.h | 0 {riscv => hwacha}/insns/vmst.h | 0 {riscv => hwacha}/insns/vmsv.h | 0 {riscv => hwacha}/insns/vmts.h | 0 {riscv => hwacha}/insns/vmvv.h | 0 {riscv => hwacha}/insns/vsb.h | 0 {riscv => hwacha}/insns/vsd.h | 0 {riscv => hwacha}/insns/vsetvl.h | 0 {riscv => hwacha}/insns/vsh.h | 0 {riscv => hwacha}/insns/vssegb.h | 0 {riscv => hwacha}/insns/vssegd.h | 0 {riscv => hwacha}/insns/vssegh.h | 0 {riscv => hwacha}/insns/vssegstb.h | 0 {riscv => hwacha}/insns/vssegstd.h | 0 {riscv => hwacha}/insns/vssegsth.h | 0 {riscv => hwacha}/insns/vssegstw.h | 0 {riscv => hwacha}/insns/vssegw.h | 0 {riscv => hwacha}/insns/vsstb.h | 0 {riscv => hwacha}/insns/vsstd.h | 0 {riscv => hwacha}/insns/vssth.h | 0 {riscv => hwacha}/insns/vsstw.h | 0 {riscv => hwacha}/insns/vsw.h | 0 {riscv => hwacha}/insns/vtcfg.h | 0 {riscv => hwacha}/insns/vtcfgivl.h | 0 {riscv => hwacha}/insns/vvcfg.h | 0 {riscv => hwacha}/insns/vvcfgivl.h | 0 {riscv => hwacha}/insns/vxcptevac.h | 0 {riscv => hwacha}/insns/vxcpthold.h | 0 {riscv => hwacha}/insns/vxcptkill.h | 0 {riscv => hwacha}/insns/vxcptrestore.h | 0 {riscv => hwacha}/insns/vxcptsave.h | 0 {riscv => hwacha}/insns/vxcptwait.h | 0 riscv/disasm.cc | 70 -------------------- riscv/opcodes.h | 89 -------------------------- riscv/processor.cc | 8 --- 95 files changed, 74 insertions(+), 167 deletions(-) create mode 100644 hwacha/README create mode 100644 hwacha/disasm.cc rename {riscv => hwacha}/insns/fmovn.h (100%) rename {riscv => hwacha}/insns/fmovz.h (100%) rename {riscv => hwacha}/insns/movn.h (100%) rename {riscv => hwacha}/insns/movz.h (100%) rename {riscv => hwacha}/insns/stop.h (100%) rename {riscv => hwacha}/insns/utidx.h (100%) rename {riscv => hwacha}/insns/venqcmd.h (100%) rename {riscv => hwacha}/insns/venqcnt.h (100%) rename {riscv => hwacha}/insns/venqimm1.h (100%) rename {riscv => hwacha}/insns/venqimm2.h (100%) rename {riscv => hwacha}/insns/vf.h (100%) rename {riscv => hwacha}/insns/vfld.h (100%) rename {riscv => hwacha}/insns/vflsegd.h (100%) rename {riscv => hwacha}/insns/vflsegstd.h (100%) rename {riscv => hwacha}/insns/vflsegstw.h (100%) rename {riscv => hwacha}/insns/vflsegw.h (100%) rename {riscv => hwacha}/insns/vflstd.h (100%) rename {riscv => hwacha}/insns/vflstw.h (100%) rename {riscv => hwacha}/insns/vflw.h (100%) rename {riscv => hwacha}/insns/vfmst.h (100%) rename {riscv => hwacha}/insns/vfmsv.h (100%) rename {riscv => hwacha}/insns/vfmts.h (100%) rename {riscv => hwacha}/insns/vfmvv.h (100%) rename {riscv => hwacha}/insns/vfsd.h (100%) rename {riscv => hwacha}/insns/vfssegd.h (100%) rename {riscv => hwacha}/insns/vfssegstd.h (100%) rename {riscv => hwacha}/insns/vfssegstw.h (100%) rename {riscv => hwacha}/insns/vfssegw.h (100%) rename {riscv => hwacha}/insns/vfsstd.h (100%) rename {riscv => hwacha}/insns/vfsstw.h (100%) rename {riscv => hwacha}/insns/vfsw.h (100%) rename {riscv => hwacha}/insns/vlb.h (100%) rename {riscv => hwacha}/insns/vlbu.h (100%) rename {riscv => hwacha}/insns/vld.h (100%) rename {riscv => hwacha}/insns/vlh.h (100%) rename {riscv => hwacha}/insns/vlhu.h (100%) rename {riscv => hwacha}/insns/vlsegb.h (100%) rename {riscv => hwacha}/insns/vlsegbu.h (100%) rename {riscv => hwacha}/insns/vlsegd.h (100%) rename {riscv => hwacha}/insns/vlsegh.h (100%) rename {riscv => hwacha}/insns/vlseghu.h (100%) rename {riscv => hwacha}/insns/vlsegstb.h (100%) rename {riscv => hwacha}/insns/vlsegstbu.h (100%) rename {riscv => hwacha}/insns/vlsegstd.h (100%) rename {riscv => hwacha}/insns/vlsegsth.h (100%) rename {riscv => hwacha}/insns/vlsegsthu.h (100%) rename {riscv => hwacha}/insns/vlsegstw.h (100%) rename {riscv => hwacha}/insns/vlsegstwu.h (100%) rename {riscv => hwacha}/insns/vlsegw.h (100%) rename {riscv => hwacha}/insns/vlsegwu.h (100%) rename {riscv => hwacha}/insns/vlstb.h (100%) rename {riscv => hwacha}/insns/vlstbu.h (100%) rename {riscv => hwacha}/insns/vlstd.h (100%) rename {riscv => hwacha}/insns/vlsth.h (100%) rename {riscv => hwacha}/insns/vlsthu.h (100%) rename {riscv => hwacha}/insns/vlstw.h (100%) rename {riscv => hwacha}/insns/vlstwu.h (100%) rename {riscv => hwacha}/insns/vlw.h (100%) rename {riscv => hwacha}/insns/vlwu.h (100%) rename {riscv => hwacha}/insns/vmst.h (100%) rename {riscv => hwacha}/insns/vmsv.h (100%) rename {riscv => hwacha}/insns/vmts.h (100%) rename {riscv => hwacha}/insns/vmvv.h (100%) rename {riscv => hwacha}/insns/vsb.h (100%) rename {riscv => hwacha}/insns/vsd.h (100%) rename {riscv => hwacha}/insns/vsetvl.h (100%) rename {riscv => hwacha}/insns/vsh.h (100%) rename {riscv => hwacha}/insns/vssegb.h (100%) rename {riscv => hwacha}/insns/vssegd.h (100%) rename {riscv => hwacha}/insns/vssegh.h (100%) rename {riscv => hwacha}/insns/vssegstb.h (100%) rename {riscv => hwacha}/insns/vssegstd.h (100%) rename {riscv => hwacha}/insns/vssegsth.h (100%) rename {riscv => hwacha}/insns/vssegstw.h (100%) rename {riscv => hwacha}/insns/vssegw.h (100%) rename {riscv => hwacha}/insns/vsstb.h (100%) rename {riscv => hwacha}/insns/vsstd.h (100%) rename {riscv => hwacha}/insns/vssth.h (100%) rename {riscv => hwacha}/insns/vsstw.h (100%) rename {riscv => hwacha}/insns/vsw.h (100%) rename {riscv => hwacha}/insns/vtcfg.h (100%) rename {riscv => hwacha}/insns/vtcfgivl.h (100%) rename {riscv => hwacha}/insns/vvcfg.h (100%) rename {riscv => hwacha}/insns/vvcfgivl.h (100%) rename {riscv => hwacha}/insns/vxcptevac.h (100%) rename {riscv => hwacha}/insns/vxcpthold.h (100%) rename {riscv => hwacha}/insns/vxcptkill.h (100%) rename {riscv => hwacha}/insns/vxcptrestore.h (100%) rename {riscv => hwacha}/insns/vxcptsave.h (100%) rename {riscv => hwacha}/insns/vxcptwait.h (100%) diff --git a/hwacha/README b/hwacha/README new file mode 100644 index 0000000..be5a97c --- /dev/null +++ b/hwacha/README @@ -0,0 +1,2 @@ +This directory contains work in progress on Hwacha, a data-parallel +accelerator. It is not currently usable. diff --git a/hwacha/disasm.cc b/hwacha/disasm.cc new file mode 100644 index 0000000..086ec6c --- /dev/null +++ b/hwacha/disasm.cc @@ -0,0 +1,72 @@ +hwacha_disassembler::hwacha_disassembler() +{ + #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg) + #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg) + #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg) + #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg) + #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg) + #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg) + + DEFINE_RS1(vxcptsave); + DEFINE_RS1(vxcptrestore); + DEFINE_NOARG(vxcptkill); + + DEFINE_RS1(vxcptevac); + DEFINE_NOARG(vxcpthold); + DEFINE_RS1_RS2(venqcmd); + DEFINE_RS1_RS2(venqimm1); + DEFINE_RS1_RS2(venqimm2); + DEFINE_RS1_RS2(venqcnt); + + DEFINE_VEC_XMEM(vld); + DEFINE_VEC_XMEM(vlw); + DEFINE_VEC_XMEM(vlwu); + DEFINE_VEC_XMEM(vlh); + DEFINE_VEC_XMEM(vlhu); + DEFINE_VEC_XMEM(vlb); + DEFINE_VEC_XMEM(vlbu); + DEFINE_VEC_FMEM(vfld); + DEFINE_VEC_FMEM(vflw); + DEFINE_VEC_XMEMST(vlstd); + DEFINE_VEC_XMEMST(vlstw); + DEFINE_VEC_XMEMST(vlstwu); + DEFINE_VEC_XMEMST(vlsth); + DEFINE_VEC_XMEMST(vlsthu); + DEFINE_VEC_XMEMST(vlstb); + DEFINE_VEC_XMEMST(vlstbu); + DEFINE_VEC_FMEMST(vflstd); + DEFINE_VEC_FMEMST(vflstw); + + DEFINE_VEC_XMEM(vsd); + DEFINE_VEC_XMEM(vsw); + DEFINE_VEC_XMEM(vsh); + DEFINE_VEC_XMEM(vsb); + DEFINE_VEC_FMEM(vfsd); + DEFINE_VEC_FMEM(vfsw); + DEFINE_VEC_XMEMST(vsstd); + DEFINE_VEC_XMEMST(vsstw); + DEFINE_VEC_XMEMST(vssth); + DEFINE_VEC_XMEMST(vsstb); + DEFINE_VEC_FMEMST(vfsstd); + DEFINE_VEC_FMEMST(vfsstw); + + DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg); + DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg); + DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg); + DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg); + DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg); + DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg); + DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg); + DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg); + + DEFINE_RS1_RS2(vvcfg); + DEFINE_RS1_RS2(vtcfg); + + DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); + DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); + DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg); + DISASM_INSN("vf", vf, 0, xrs1_reg, imm); + + DEFINE_NOARG(fence_v_l); + DEFINE_NOARG(fence_v_g); +} diff --git a/riscv/insns/fmovn.h b/hwacha/insns/fmovn.h similarity index 100% rename from riscv/insns/fmovn.h rename to hwacha/insns/fmovn.h diff --git a/riscv/insns/fmovz.h b/hwacha/insns/fmovz.h similarity index 100% rename from riscv/insns/fmovz.h rename to hwacha/insns/fmovz.h diff --git a/riscv/insns/movn.h b/hwacha/insns/movn.h similarity index 100% rename from riscv/insns/movn.h rename to hwacha/insns/movn.h diff --git a/riscv/insns/movz.h b/hwacha/insns/movz.h similarity index 100% rename from riscv/insns/movz.h rename to hwacha/insns/movz.h diff --git a/riscv/insns/stop.h b/hwacha/insns/stop.h similarity index 100% rename from riscv/insns/stop.h rename to hwacha/insns/stop.h diff --git a/riscv/insns/utidx.h b/hwacha/insns/utidx.h similarity index 100% rename from riscv/insns/utidx.h rename to hwacha/insns/utidx.h diff --git a/riscv/insns/venqcmd.h b/hwacha/insns/venqcmd.h similarity index 100% rename from riscv/insns/venqcmd.h rename to hwacha/insns/venqcmd.h diff --git a/riscv/insns/venqcnt.h b/hwacha/insns/venqcnt.h similarity index 100% rename from riscv/insns/venqcnt.h rename to hwacha/insns/venqcnt.h diff --git a/riscv/insns/venqimm1.h b/hwacha/insns/venqimm1.h similarity index 100% rename from riscv/insns/venqimm1.h rename to hwacha/insns/venqimm1.h diff --git a/riscv/insns/venqimm2.h b/hwacha/insns/venqimm2.h similarity index 100% rename from riscv/insns/venqimm2.h rename to hwacha/insns/venqimm2.h diff --git a/riscv/insns/vf.h b/hwacha/insns/vf.h similarity index 100% rename from riscv/insns/vf.h rename to hwacha/insns/vf.h diff --git a/riscv/insns/vfld.h b/hwacha/insns/vfld.h similarity index 100% rename from riscv/insns/vfld.h rename to hwacha/insns/vfld.h diff --git a/riscv/insns/vflsegd.h b/hwacha/insns/vflsegd.h similarity index 100% rename from riscv/insns/vflsegd.h rename to hwacha/insns/vflsegd.h diff --git a/riscv/insns/vflsegstd.h b/hwacha/insns/vflsegstd.h similarity index 100% rename from riscv/insns/vflsegstd.h rename to hwacha/insns/vflsegstd.h diff --git a/riscv/insns/vflsegstw.h b/hwacha/insns/vflsegstw.h similarity index 100% rename from riscv/insns/vflsegstw.h rename to hwacha/insns/vflsegstw.h diff --git a/riscv/insns/vflsegw.h b/hwacha/insns/vflsegw.h similarity index 100% rename from riscv/insns/vflsegw.h rename to hwacha/insns/vflsegw.h diff --git a/riscv/insns/vflstd.h b/hwacha/insns/vflstd.h similarity index 100% rename from riscv/insns/vflstd.h rename to hwacha/insns/vflstd.h diff --git a/riscv/insns/vflstw.h b/hwacha/insns/vflstw.h similarity index 100% rename from riscv/insns/vflstw.h rename to hwacha/insns/vflstw.h diff --git a/riscv/insns/vflw.h b/hwacha/insns/vflw.h similarity index 100% rename from riscv/insns/vflw.h rename to hwacha/insns/vflw.h diff --git a/riscv/insns/vfmst.h b/hwacha/insns/vfmst.h similarity index 100% rename from riscv/insns/vfmst.h rename to hwacha/insns/vfmst.h diff --git a/riscv/insns/vfmsv.h b/hwacha/insns/vfmsv.h similarity index 100% rename from riscv/insns/vfmsv.h rename to hwacha/insns/vfmsv.h diff --git a/riscv/insns/vfmts.h b/hwacha/insns/vfmts.h similarity index 100% rename from riscv/insns/vfmts.h rename to hwacha/insns/vfmts.h diff --git a/riscv/insns/vfmvv.h b/hwacha/insns/vfmvv.h similarity index 100% rename from riscv/insns/vfmvv.h rename to hwacha/insns/vfmvv.h diff --git a/riscv/insns/vfsd.h b/hwacha/insns/vfsd.h similarity index 100% rename from riscv/insns/vfsd.h rename to hwacha/insns/vfsd.h diff --git a/riscv/insns/vfssegd.h b/hwacha/insns/vfssegd.h similarity index 100% rename from riscv/insns/vfssegd.h rename to hwacha/insns/vfssegd.h diff --git a/riscv/insns/vfssegstd.h b/hwacha/insns/vfssegstd.h similarity index 100% rename from riscv/insns/vfssegstd.h rename to hwacha/insns/vfssegstd.h diff --git a/riscv/insns/vfssegstw.h b/hwacha/insns/vfssegstw.h similarity index 100% rename from riscv/insns/vfssegstw.h rename to hwacha/insns/vfssegstw.h diff --git a/riscv/insns/vfssegw.h b/hwacha/insns/vfssegw.h similarity index 100% rename from riscv/insns/vfssegw.h rename to hwacha/insns/vfssegw.h diff --git a/riscv/insns/vfsstd.h b/hwacha/insns/vfsstd.h similarity index 100% rename from riscv/insns/vfsstd.h rename to hwacha/insns/vfsstd.h diff --git a/riscv/insns/vfsstw.h b/hwacha/insns/vfsstw.h similarity index 100% rename from riscv/insns/vfsstw.h rename to hwacha/insns/vfsstw.h diff --git a/riscv/insns/vfsw.h b/hwacha/insns/vfsw.h similarity index 100% rename from riscv/insns/vfsw.h rename to hwacha/insns/vfsw.h diff --git a/riscv/insns/vlb.h b/hwacha/insns/vlb.h similarity index 100% rename from riscv/insns/vlb.h rename to hwacha/insns/vlb.h diff --git a/riscv/insns/vlbu.h b/hwacha/insns/vlbu.h similarity index 100% rename from riscv/insns/vlbu.h rename to hwacha/insns/vlbu.h diff --git a/riscv/insns/vld.h b/hwacha/insns/vld.h similarity index 100% rename from riscv/insns/vld.h rename to hwacha/insns/vld.h diff --git a/riscv/insns/vlh.h b/hwacha/insns/vlh.h similarity index 100% rename from riscv/insns/vlh.h rename to hwacha/insns/vlh.h diff --git a/riscv/insns/vlhu.h b/hwacha/insns/vlhu.h similarity index 100% rename from riscv/insns/vlhu.h rename to hwacha/insns/vlhu.h diff --git a/riscv/insns/vlsegb.h b/hwacha/insns/vlsegb.h similarity index 100% rename from riscv/insns/vlsegb.h rename to hwacha/insns/vlsegb.h diff --git a/riscv/insns/vlsegbu.h b/hwacha/insns/vlsegbu.h similarity index 100% rename from riscv/insns/vlsegbu.h rename to hwacha/insns/vlsegbu.h diff --git a/riscv/insns/vlsegd.h b/hwacha/insns/vlsegd.h similarity index 100% rename from riscv/insns/vlsegd.h rename to hwacha/insns/vlsegd.h diff --git a/riscv/insns/vlsegh.h b/hwacha/insns/vlsegh.h similarity index 100% rename from riscv/insns/vlsegh.h rename to hwacha/insns/vlsegh.h diff --git a/riscv/insns/vlseghu.h b/hwacha/insns/vlseghu.h similarity index 100% rename from riscv/insns/vlseghu.h rename to hwacha/insns/vlseghu.h diff --git a/riscv/insns/vlsegstb.h b/hwacha/insns/vlsegstb.h similarity index 100% rename from riscv/insns/vlsegstb.h rename to hwacha/insns/vlsegstb.h diff --git a/riscv/insns/vlsegstbu.h b/hwacha/insns/vlsegstbu.h similarity index 100% rename from riscv/insns/vlsegstbu.h rename to hwacha/insns/vlsegstbu.h diff --git a/riscv/insns/vlsegstd.h b/hwacha/insns/vlsegstd.h similarity index 100% rename from riscv/insns/vlsegstd.h rename to hwacha/insns/vlsegstd.h diff --git a/riscv/insns/vlsegsth.h b/hwacha/insns/vlsegsth.h similarity index 100% rename from riscv/insns/vlsegsth.h rename to hwacha/insns/vlsegsth.h diff --git a/riscv/insns/vlsegsthu.h b/hwacha/insns/vlsegsthu.h similarity index 100% rename from riscv/insns/vlsegsthu.h rename to hwacha/insns/vlsegsthu.h diff --git a/riscv/insns/vlsegstw.h b/hwacha/insns/vlsegstw.h similarity index 100% rename from riscv/insns/vlsegstw.h rename to hwacha/insns/vlsegstw.h diff --git a/riscv/insns/vlsegstwu.h b/hwacha/insns/vlsegstwu.h similarity index 100% rename from riscv/insns/vlsegstwu.h rename to hwacha/insns/vlsegstwu.h diff --git a/riscv/insns/vlsegw.h b/hwacha/insns/vlsegw.h similarity index 100% rename from riscv/insns/vlsegw.h rename to hwacha/insns/vlsegw.h diff --git a/riscv/insns/vlsegwu.h b/hwacha/insns/vlsegwu.h similarity index 100% rename from riscv/insns/vlsegwu.h rename to hwacha/insns/vlsegwu.h diff --git a/riscv/insns/vlstb.h b/hwacha/insns/vlstb.h similarity index 100% rename from riscv/insns/vlstb.h rename to hwacha/insns/vlstb.h diff --git a/riscv/insns/vlstbu.h b/hwacha/insns/vlstbu.h similarity index 100% rename from riscv/insns/vlstbu.h rename to hwacha/insns/vlstbu.h diff --git a/riscv/insns/vlstd.h b/hwacha/insns/vlstd.h similarity index 100% rename from riscv/insns/vlstd.h rename to hwacha/insns/vlstd.h diff --git a/riscv/insns/vlsth.h b/hwacha/insns/vlsth.h similarity index 100% rename from riscv/insns/vlsth.h rename to hwacha/insns/vlsth.h diff --git a/riscv/insns/vlsthu.h b/hwacha/insns/vlsthu.h similarity index 100% rename from riscv/insns/vlsthu.h rename to hwacha/insns/vlsthu.h diff --git a/riscv/insns/vlstw.h b/hwacha/insns/vlstw.h similarity index 100% rename from riscv/insns/vlstw.h rename to hwacha/insns/vlstw.h diff --git a/riscv/insns/vlstwu.h b/hwacha/insns/vlstwu.h similarity index 100% rename from riscv/insns/vlstwu.h rename to hwacha/insns/vlstwu.h diff --git a/riscv/insns/vlw.h b/hwacha/insns/vlw.h similarity index 100% rename from riscv/insns/vlw.h rename to hwacha/insns/vlw.h diff --git a/riscv/insns/vlwu.h b/hwacha/insns/vlwu.h similarity index 100% rename from riscv/insns/vlwu.h rename to hwacha/insns/vlwu.h diff --git a/riscv/insns/vmst.h b/hwacha/insns/vmst.h similarity index 100% rename from riscv/insns/vmst.h rename to hwacha/insns/vmst.h diff --git a/riscv/insns/vmsv.h b/hwacha/insns/vmsv.h similarity index 100% rename from riscv/insns/vmsv.h rename to hwacha/insns/vmsv.h diff --git a/riscv/insns/vmts.h b/hwacha/insns/vmts.h similarity index 100% rename from riscv/insns/vmts.h rename to hwacha/insns/vmts.h diff --git a/riscv/insns/vmvv.h b/hwacha/insns/vmvv.h similarity index 100% rename from riscv/insns/vmvv.h rename to hwacha/insns/vmvv.h diff --git a/riscv/insns/vsb.h b/hwacha/insns/vsb.h similarity index 100% rename from riscv/insns/vsb.h rename to hwacha/insns/vsb.h diff --git a/riscv/insns/vsd.h b/hwacha/insns/vsd.h similarity index 100% rename from riscv/insns/vsd.h rename to hwacha/insns/vsd.h diff --git a/riscv/insns/vsetvl.h b/hwacha/insns/vsetvl.h similarity index 100% rename from riscv/insns/vsetvl.h rename to hwacha/insns/vsetvl.h diff --git a/riscv/insns/vsh.h b/hwacha/insns/vsh.h similarity index 100% rename from riscv/insns/vsh.h rename to hwacha/insns/vsh.h diff --git a/riscv/insns/vssegb.h b/hwacha/insns/vssegb.h similarity index 100% rename from riscv/insns/vssegb.h rename to hwacha/insns/vssegb.h diff --git a/riscv/insns/vssegd.h b/hwacha/insns/vssegd.h similarity index 100% rename from riscv/insns/vssegd.h rename to hwacha/insns/vssegd.h diff --git a/riscv/insns/vssegh.h b/hwacha/insns/vssegh.h similarity index 100% rename from riscv/insns/vssegh.h rename to hwacha/insns/vssegh.h diff --git a/riscv/insns/vssegstb.h b/hwacha/insns/vssegstb.h similarity index 100% rename from riscv/insns/vssegstb.h rename to hwacha/insns/vssegstb.h diff --git a/riscv/insns/vssegstd.h b/hwacha/insns/vssegstd.h similarity index 100% rename from riscv/insns/vssegstd.h rename to hwacha/insns/vssegstd.h diff --git a/riscv/insns/vssegsth.h b/hwacha/insns/vssegsth.h similarity index 100% rename from riscv/insns/vssegsth.h rename to hwacha/insns/vssegsth.h diff --git a/riscv/insns/vssegstw.h b/hwacha/insns/vssegstw.h similarity index 100% rename from riscv/insns/vssegstw.h rename to hwacha/insns/vssegstw.h diff --git a/riscv/insns/vssegw.h b/hwacha/insns/vssegw.h similarity index 100% rename from riscv/insns/vssegw.h rename to hwacha/insns/vssegw.h diff --git a/riscv/insns/vsstb.h b/hwacha/insns/vsstb.h similarity index 100% rename from riscv/insns/vsstb.h rename to hwacha/insns/vsstb.h diff --git a/riscv/insns/vsstd.h b/hwacha/insns/vsstd.h similarity index 100% rename from riscv/insns/vsstd.h rename to hwacha/insns/vsstd.h diff --git a/riscv/insns/vssth.h b/hwacha/insns/vssth.h similarity index 100% rename from riscv/insns/vssth.h rename to hwacha/insns/vssth.h diff --git a/riscv/insns/vsstw.h b/hwacha/insns/vsstw.h similarity index 100% rename from riscv/insns/vsstw.h rename to hwacha/insns/vsstw.h diff --git a/riscv/insns/vsw.h b/hwacha/insns/vsw.h similarity index 100% rename from riscv/insns/vsw.h rename to hwacha/insns/vsw.h diff --git a/riscv/insns/vtcfg.h b/hwacha/insns/vtcfg.h similarity index 100% rename from riscv/insns/vtcfg.h rename to hwacha/insns/vtcfg.h diff --git a/riscv/insns/vtcfgivl.h b/hwacha/insns/vtcfgivl.h similarity index 100% rename from riscv/insns/vtcfgivl.h rename to hwacha/insns/vtcfgivl.h diff --git a/riscv/insns/vvcfg.h b/hwacha/insns/vvcfg.h similarity index 100% rename from riscv/insns/vvcfg.h rename to hwacha/insns/vvcfg.h diff --git a/riscv/insns/vvcfgivl.h b/hwacha/insns/vvcfgivl.h similarity index 100% rename from riscv/insns/vvcfgivl.h rename to hwacha/insns/vvcfgivl.h diff --git a/riscv/insns/vxcptevac.h b/hwacha/insns/vxcptevac.h similarity index 100% rename from riscv/insns/vxcptevac.h rename to hwacha/insns/vxcptevac.h diff --git a/riscv/insns/vxcpthold.h b/hwacha/insns/vxcpthold.h similarity index 100% rename from riscv/insns/vxcpthold.h rename to hwacha/insns/vxcpthold.h diff --git a/riscv/insns/vxcptkill.h b/hwacha/insns/vxcptkill.h similarity index 100% rename from riscv/insns/vxcptkill.h rename to hwacha/insns/vxcptkill.h diff --git a/riscv/insns/vxcptrestore.h b/hwacha/insns/vxcptrestore.h similarity index 100% rename from riscv/insns/vxcptrestore.h rename to hwacha/insns/vxcptrestore.h diff --git a/riscv/insns/vxcptsave.h b/hwacha/insns/vxcptsave.h similarity index 100% rename from riscv/insns/vxcptsave.h rename to hwacha/insns/vxcptsave.h diff --git a/riscv/insns/vxcptwait.h b/hwacha/insns/vxcptwait.h similarity index 100% rename from riscv/insns/vxcptwait.h rename to hwacha/insns/vxcptwait.h diff --git a/riscv/disasm.cc b/riscv/disasm.cc index 57f43d7..86b70e0 100644 --- a/riscv/disasm.cc +++ b/riscv/disasm.cc @@ -438,13 +438,6 @@ disassembler::disassembler() #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, xrd_reg, frs1_reg) #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, frd_reg, xrs1_reg) - #define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg) - #define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg) - #define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg) - #define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg) - #define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg) - #define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg) - DEFINE_XLOAD(lb) DEFINE_XLOAD(lbu) DEFINE_XLOAD(lh) @@ -571,17 +564,6 @@ disassembler::disassembler() add_insn(new disasm_insn_t("clearpcr", match_clearpcr, mask_clearpcr, xrd_reg, pcr_reg, imm)); DEFINE_NOARG(eret) - DEFINE_RS1(vxcptsave); - DEFINE_RS1(vxcptrestore); - DEFINE_NOARG(vxcptkill); - - DEFINE_RS1(vxcptevac); - DEFINE_NOARG(vxcpthold); - DEFINE_RS1_RS2(venqcmd); - DEFINE_RS1_RS2(venqimm1); - DEFINE_RS1_RS2(venqimm2); - DEFINE_RS1_RS2(venqcnt); - DEFINE_FRTYPE(fadd_s); DEFINE_FRTYPE(fsub_s); DEFINE_FRTYPE(fmul_s); @@ -646,58 +628,6 @@ disassembler::disassembler() add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr, xrd_reg, xrs1_reg)); DEFINE_DTYPE(mffsr); - DEFINE_VEC_XMEM(vld); - DEFINE_VEC_XMEM(vlw); - DEFINE_VEC_XMEM(vlwu); - DEFINE_VEC_XMEM(vlh); - DEFINE_VEC_XMEM(vlhu); - DEFINE_VEC_XMEM(vlb); - DEFINE_VEC_XMEM(vlbu); - DEFINE_VEC_FMEM(vfld); - DEFINE_VEC_FMEM(vflw); - DEFINE_VEC_XMEMST(vlstd); - DEFINE_VEC_XMEMST(vlstw); - DEFINE_VEC_XMEMST(vlstwu); - DEFINE_VEC_XMEMST(vlsth); - DEFINE_VEC_XMEMST(vlsthu); - DEFINE_VEC_XMEMST(vlstb); - DEFINE_VEC_XMEMST(vlstbu); - DEFINE_VEC_FMEMST(vflstd); - DEFINE_VEC_FMEMST(vflstw); - - DEFINE_VEC_XMEM(vsd); - DEFINE_VEC_XMEM(vsw); - DEFINE_VEC_XMEM(vsh); - DEFINE_VEC_XMEM(vsb); - DEFINE_VEC_FMEM(vfsd); - DEFINE_VEC_FMEM(vfsw); - DEFINE_VEC_XMEMST(vsstd); - DEFINE_VEC_XMEMST(vsstw); - DEFINE_VEC_XMEMST(vssth); - DEFINE_VEC_XMEMST(vsstb); - DEFINE_VEC_FMEMST(vfsstd); - DEFINE_VEC_FMEMST(vfsstw); - - DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg); - DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg); - DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg); - DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg); - DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg); - DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg); - DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg); - DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg); - - DEFINE_RS1_RS2(vvcfg); - DEFINE_RS1_RS2(vtcfg); - - DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); - DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg); - DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg); - DISASM_INSN("vf", vf, 0, xrs1_reg, imm); - - DEFINE_NOARG(fence_v_l); - DEFINE_NOARG(fence_v_g); - // provide a default disassembly for all instructions as a fallback #define DECLARE_INSN(code, match, mask) \ add_insn(new disasm_insn_t(#code " (args unknown)", match, mask)); diff --git a/riscv/opcodes.h b/riscv/opcodes.h index f18aebd..34e10c1 100644 --- a/riscv/opcodes.h +++ b/riscv/opcodes.h @@ -1,17 +1,10 @@ -DECLARE_INSN(movn, 0x6f7, 0x1ffff) -DECLARE_INSN(vfsstw, 0x150f, 0x1ffff) DECLARE_INSN(remuw, 0x7bb, 0x1ffff) DECLARE_INSN(fmin_d, 0x180d3, 0x1ffff) DECLARE_INSN(lr_w, 0x1012b, 0x3fffff) -DECLARE_INSN(vlsthu, 0x128b, 0x1ffff) DECLARE_INSN(bltu, 0x363, 0x3ff) -DECLARE_INSN(vlsegstwu, 0xb0b, 0xfff) -DECLARE_INSN(vvcfg, 0x473, 0xf801ffff) -DECLARE_INSN(movz, 0x2f7, 0x1ffff) DECLARE_INSN(fmin_s, 0x18053, 0x1ffff) DECLARE_INSN(slliw, 0x9b, 0x3f83ff) DECLARE_INSN(lb, 0x3, 0x3ff) -DECLARE_INSN(vlwu, 0x30b, 0x3fffff) DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff) DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff) DECLARE_INSN(lh, 0x83, 0x3ff) @@ -24,53 +17,32 @@ DECLARE_INSN(fmax_d, 0x190d3, 0x1ffff) DECLARE_INSN(bne, 0xe3, 0x3ff) DECLARE_INSN(rdcycle, 0x277, 0x7ffffff) DECLARE_INSN(fcvt_s_d, 0x11053, 0x3ff1ff) -DECLARE_INSN(vlh, 0x8b, 0x3fffff) DECLARE_INSN(bgeu, 0x3e3, 0x3ff) -DECLARE_INSN(vflstd, 0x158b, 0x1ffff) DECLARE_INSN(fadd_d, 0xd3, 0x1f1ff) DECLARE_INSN(sltiu, 0x193, 0x3ff) DECLARE_INSN(mtpcr, 0x1fb, 0x1ffff) -DECLARE_INSN(vlb, 0xb, 0x3fffff) -DECLARE_INSN(stop, 0x177, 0xffffffff) -DECLARE_INSN(vld, 0x18b, 0x3fffff) DECLARE_INSN(break, 0xf7, 0xffffffff) DECLARE_INSN(fcvt_s_w, 0xe053, 0x3ff1ff) -DECLARE_INSN(vflstw, 0x150b, 0x1ffff) DECLARE_INSN(mul, 0x433, 0x1ffff) -DECLARE_INSN(vxcptevac, 0x237b, 0xf83fffff) -DECLARE_INSN(vlw, 0x10b, 0x3fffff) -DECLARE_INSN(vssegstw, 0x90f, 0xfff) DECLARE_INSN(amominu_d, 0x19ab, 0x1ffff) DECLARE_INSN(mftx_d, 0x1c0d3, 0x3fffff) DECLARE_INSN(srli, 0x293, 0x3f03ff) DECLARE_INSN(amominu_w, 0x192b, 0x1ffff) DECLARE_INSN(divuw, 0x6bb, 0x1ffff) DECLARE_INSN(mulw, 0x43b, 0x1ffff) -DECLARE_INSN(vssegstd, 0x98f, 0xfff) DECLARE_INSN(srlw, 0x2bb, 0x1ffff) -DECLARE_INSN(vssegstb, 0x80f, 0xfff) -DECLARE_INSN(utidx, 0x1f7, 0x7ffffff) DECLARE_INSN(div, 0x633, 0x1ffff) -DECLARE_INSN(vtcfg, 0xc73, 0xf801ffff) DECLARE_INSN(mftx_s, 0x1c053, 0x3fffff) -DECLARE_INSN(vssegsth, 0x88f, 0xfff) -DECLARE_INSN(vvcfgivl, 0xf3, 0x3ff) DECLARE_INSN(j, 0x67, 0x7f) DECLARE_INSN(fence, 0x12f, 0x3ff) -DECLARE_INSN(vsw, 0x10f, 0x3fffff) DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff) -DECLARE_INSN(vfssegstd, 0xd8f, 0xfff) DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff) DECLARE_INSN(fle_s, 0x17053, 0x1ffff) DECLARE_INSN(fence_v_l, 0x22f, 0x3ff) -DECLARE_INSN(vsb, 0xf, 0x3fffff) DECLARE_INSN(mffsr, 0x1d053, 0x7ffffff) DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff) -DECLARE_INSN(vlstbu, 0x120b, 0x1ffff) -DECLARE_INSN(vsetvl, 0x2f3, 0x3fffff) DECLARE_INSN(fle_d, 0x170d3, 0x1ffff) DECLARE_INSN(fence_i, 0xaf, 0x3ff) -DECLARE_INSN(vlsegbu, 0x220b, 0x1ffff) DECLARE_INSN(fnmsub_d, 0xcb, 0x1ff) DECLARE_INSN(addw, 0x3b, 0x1ffff) DECLARE_INSN(sll, 0xb3, 0x1ffff) @@ -78,21 +50,15 @@ DECLARE_INSN(xor, 0x233, 0x1ffff) DECLARE_INSN(sub, 0x10033, 0x1ffff) DECLARE_INSN(eret, 0x27b, 0xffffffff) DECLARE_INSN(blt, 0x263, 0x3ff) -DECLARE_INSN(vsstw, 0x110f, 0x1ffff) DECLARE_INSN(mtfsr, 0x1f053, 0x3fffff) -DECLARE_INSN(vssth, 0x108f, 0x1ffff) DECLARE_INSN(sc_w, 0x1052b, 0x1ffff) DECLARE_INSN(rem, 0x733, 0x1ffff) DECLARE_INSN(srliw, 0x29b, 0x3f83ff) DECLARE_INSN(lui, 0x37, 0x7f) -DECLARE_INSN(vsstb, 0x100f, 0x1ffff) DECLARE_INSN(fcvt_s_lu, 0xd053, 0x3ff1ff) -DECLARE_INSN(vsstd, 0x118f, 0x1ffff) DECLARE_INSN(addi, 0x13, 0x3ff) -DECLARE_INSN(vfmst, 0x1173, 0x1ffff) DECLARE_INSN(mulh, 0x4b3, 0x1ffff) DECLARE_INSN(fmul_s, 0x2053, 0x1f1ff) -DECLARE_INSN(vlsegsthu, 0xa8b, 0xfff) DECLARE_INSN(srai, 0x10293, 0x3f03ff) DECLARE_INSN(amoand_d, 0x9ab, 0x1ffff) DECLARE_INSN(flt_d, 0x160d3, 0x1ffff) @@ -107,45 +73,29 @@ DECLARE_INSN(feq_s, 0x15053, 0x1ffff) DECLARE_INSN(fsgnjx_d, 0x70d3, 0x1ffff) DECLARE_INSN(sra, 0x102b3, 0x1ffff) DECLARE_INSN(bge, 0x2e3, 0x3ff) -DECLARE_INSN(venqimm2, 0x337b, 0xf801ffff) DECLARE_INSN(sraiw, 0x1029b, 0x3f83ff) -DECLARE_INSN(vssegd, 0x218f, 0x1ffff) DECLARE_INSN(srl, 0x2b3, 0x1ffff) -DECLARE_INSN(venqcmd, 0x2b7b, 0xf801ffff) DECLARE_INSN(fsub_d, 0x10d3, 0x1f1ff) -DECLARE_INSN(vfmts, 0x1973, 0x1ffff) -DECLARE_INSN(venqimm1, 0x2f7b, 0xf801ffff) DECLARE_INSN(fsgnjx_s, 0x7053, 0x1ffff) -DECLARE_INSN(vfmsv, 0x973, 0x3fffff) DECLARE_INSN(feq_d, 0x150d3, 0x1ffff) DECLARE_INSN(fcvt_d_wu, 0xf0d3, 0x3ff1ff) -DECLARE_INSN(vxcptrestore, 0x77b, 0xf83fffff) -DECLARE_INSN(vmts, 0x1873, 0x1ffff) DECLARE_INSN(or, 0x333, 0x1ffff) DECLARE_INSN(rdinstret, 0xa77, 0x7ffffff) DECLARE_INSN(fcvt_wu_d, 0xb0d3, 0x3ff1ff) DECLARE_INSN(subw, 0x1003b, 0x1ffff) DECLARE_INSN(fmax_s, 0x19053, 0x1ffff) DECLARE_INSN(amomaxu_d, 0x1dab, 0x1ffff) -DECLARE_INSN(vlstw, 0x110b, 0x1ffff) -DECLARE_INSN(vlsth, 0x108b, 0x1ffff) DECLARE_INSN(xori, 0x213, 0x3ff) DECLARE_INSN(fdiv_d, 0x30d3, 0x1f1ff) DECLARE_INSN(amomaxu_w, 0x1d2b, 0x1ffff) DECLARE_INSN(fcvt_wu_s, 0xb053, 0x3ff1ff) -DECLARE_INSN(vlstb, 0x100b, 0x1ffff) -DECLARE_INSN(vlstd, 0x118b, 0x1ffff) DECLARE_INSN(rdtime, 0x677, 0x7ffffff) DECLARE_INSN(andi, 0x393, 0x3ff) DECLARE_INSN(clearpcr, 0x7b, 0x3ff) -DECLARE_INSN(venqcnt, 0x377b, 0xf801ffff) DECLARE_INSN(fsgnjn_d, 0x60d3, 0x1ffff) DECLARE_INSN(fnmadd_s, 0x4f, 0x1ff) DECLARE_INSN(jal, 0x6f, 0x7f) DECLARE_INSN(lwu, 0x303, 0x3ff) -DECLARE_INSN(vlsegstbu, 0xa0b, 0xfff) -DECLARE_INSN(vlhu, 0x28b, 0x3fffff) -DECLARE_INSN(vfsstd, 0x158f, 0x1ffff) DECLARE_INSN(fnmadd_d, 0xcf, 0x1ff) DECLARE_INSN(amoadd_d, 0x1ab, 0x1ffff) DECLARE_INSN(lr_d, 0x101ab, 0x3fffff) @@ -156,9 +106,6 @@ DECLARE_INSN(fcvt_d_lu, 0xd0d3, 0x3ff1ff) DECLARE_INSN(amomax_d, 0x15ab, 0x1ffff) DECLARE_INSN(fsd, 0x1a7, 0x3ff) DECLARE_INSN(fcvt_w_d, 0xa0d3, 0x3ff1ff) -DECLARE_INSN(fmovz, 0xaf7, 0x1ffff) -DECLARE_INSN(vmvv, 0x73, 0x3fffff) -DECLARE_INSN(vfssegstw, 0xd0f, 0xfff) DECLARE_INSN(slt, 0x133, 0x1ffff) DECLARE_INSN(mxtf_d, 0x1e0d3, 0x3fffff) DECLARE_INSN(sllw, 0xbb, 0x1ffff) @@ -169,80 +116,44 @@ DECLARE_INSN(flw, 0x107, 0x3ff) DECLARE_INSN(remw, 0x73b, 0x1ffff) DECLARE_INSN(sltu, 0x1b3, 0x1ffff) DECLARE_INSN(slli, 0x93, 0x3f03ff) -DECLARE_INSN(vssegw, 0x210f, 0x1ffff) DECLARE_INSN(amoor_w, 0xd2b, 0x1ffff) -DECLARE_INSN(vsd, 0x18f, 0x3fffff) DECLARE_INSN(beq, 0x63, 0x3ff) DECLARE_INSN(fld, 0x187, 0x3ff) DECLARE_INSN(mxtf_s, 0x1e053, 0x3fffff) DECLARE_INSN(fsub_s, 0x1053, 0x1f1ff) DECLARE_INSN(and, 0x3b3, 0x1ffff) -DECLARE_INSN(vtcfgivl, 0x1f3, 0x3ff) DECLARE_INSN(lbu, 0x203, 0x3ff) -DECLARE_INSN(vf, 0x3f3, 0xf80003ff) -DECLARE_INSN(vlsegstw, 0x90b, 0xfff) DECLARE_INSN(syscall, 0x77, 0xffffffff) DECLARE_INSN(fsgnj_s, 0x5053, 0x1ffff) -DECLARE_INSN(vfmvv, 0x173, 0x3fffff) -DECLARE_INSN(vlstwu, 0x130b, 0x1ffff) -DECLARE_INSN(vsh, 0x8f, 0x3fffff) -DECLARE_INSN(vlsegstb, 0x80b, 0xfff) -DECLARE_INSN(vxcptsave, 0x37b, 0xf83fffff) -DECLARE_INSN(vlsegstd, 0x98b, 0xfff) -DECLARE_INSN(vflsegd, 0x258b, 0x1ffff) -DECLARE_INSN(vflsegw, 0x250b, 0x1ffff) -DECLARE_INSN(vlsegsth, 0x88b, 0xfff) DECLARE_INSN(amomax_w, 0x152b, 0x1ffff) DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff) -DECLARE_INSN(vflsegstw, 0xd0b, 0xfff) DECLARE_INSN(mulhu, 0x5b3, 0x1ffff) DECLARE_INSN(fence_v_g, 0x2af, 0x3ff) -DECLARE_INSN(vmsv, 0x873, 0x3fffff) -DECLARE_INSN(vmst, 0x1073, 0x1ffff) DECLARE_INSN(setpcr, 0xfb, 0x3ff) DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff) -DECLARE_INSN(vxcpthold, 0x277b, 0xffffffff) DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff) -DECLARE_INSN(vflsegstd, 0xd8b, 0xfff) DECLARE_INSN(auipc, 0x17, 0x7f) DECLARE_INSN(fcvt_lu_d, 0x90d3, 0x3ff1ff) -DECLARE_INSN(vfld, 0x58b, 0x3fffff) DECLARE_INSN(sc_d, 0x105ab, 0x1ffff) DECLARE_INSN(fmadd_s, 0x43, 0x1ff) -DECLARE_INSN(fmovn, 0xef7, 0x1ffff) -DECLARE_INSN(vssegh, 0x208f, 0x1ffff) DECLARE_INSN(fsqrt_s, 0x4053, 0x3ff1ff) -DECLARE_INSN(vxcptkill, 0xb7b, 0xffffffff) DECLARE_INSN(amomin_w, 0x112b, 0x1ffff) DECLARE_INSN(fsgnjn_s, 0x6053, 0x1ffff) -DECLARE_INSN(vlsegwu, 0x230b, 0x1ffff) -DECLARE_INSN(vfsw, 0x50f, 0x3fffff) DECLARE_INSN(amoswap_d, 0x5ab, 0x1ffff) DECLARE_INSN(fsqrt_d, 0x40d3, 0x3ff1ff) -DECLARE_INSN(vflw, 0x50b, 0x3fffff) DECLARE_INSN(fmadd_d, 0xc3, 0x1ff) DECLARE_INSN(divw, 0x63b, 0x1ffff) DECLARE_INSN(amomin_d, 0x11ab, 0x1ffff) DECLARE_INSN(divu, 0x6b3, 0x1ffff) DECLARE_INSN(amoswap_w, 0x52b, 0x1ffff) -DECLARE_INSN(vfsd, 0x58f, 0x3fffff) DECLARE_INSN(jalr, 0x6b, 0x3ff) DECLARE_INSN(fadd_s, 0x53, 0x1f1ff) -DECLARE_INSN(vlsegb, 0x200b, 0x1ffff) DECLARE_INSN(fcvt_l_d, 0x80d3, 0x3ff1ff) -DECLARE_INSN(vlsegd, 0x218b, 0x1ffff) -DECLARE_INSN(vlsegh, 0x208b, 0x1ffff) DECLARE_INSN(sw, 0x123, 0x3ff) DECLARE_INSN(fmsub_s, 0x47, 0x1ff) -DECLARE_INSN(vfssegw, 0x250f, 0x1ffff) DECLARE_INSN(lhu, 0x283, 0x3ff) DECLARE_INSN(sh, 0xa3, 0x3ff) -DECLARE_INSN(vlsegw, 0x210b, 0x1ffff) DECLARE_INSN(fsw, 0x127, 0x3ff) -DECLARE_INSN(vlbu, 0x20b, 0x3fffff) DECLARE_INSN(sb, 0x23, 0x3ff) DECLARE_INSN(fmsub_d, 0xc7, 0x1ff) -DECLARE_INSN(vlseghu, 0x228b, 0x1ffff) -DECLARE_INSN(vssegb, 0x200f, 0x1ffff) -DECLARE_INSN(vfssegd, 0x258f, 0x1ffff) DECLARE_INSN(sd, 0x1a3, 0x3ff) diff --git a/riscv/processor.cc b/riscv/processor.cc index 3bd4a19..42182bd 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -261,10 +261,6 @@ void processor_t::set_pcr(int which, reg_t val) case PCR_K1: pcr_k1 = val; break; - case PCR_VECBANK: - vecbanks = val & 0xff; - vecbanks_count = __builtin_popcountll(vecbanks); - break; case PCR_TOHOST: if (tohost == 0) tohost = val; @@ -304,10 +300,6 @@ reg_t processor_t::get_pcr(int which) return pcr_k0; case PCR_K1: return pcr_k1; - case PCR_VECBANK: - return vecbanks; - case PCR_VECCFG: - return nfpr_use << 18 | nxpr_use << 12 | vl; case PCR_TOHOST: return tohost; case PCR_FROMHOST: -- 2.30.2