From bebcb2dcf74fc60850b099d810938f7078445cb4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 14 Nov 2021 10:27:24 +0000 Subject: [PATCH] --- docs/pinmux.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn index 12b813857..d51b49b90 100644 --- a/docs/pinmux.mdwn +++ b/docs/pinmux.mdwn @@ -2,7 +2,11 @@ Managing IO on an ASIC is nowhere near as simple as on an FPGA. An FPGA has built-in IO Pads, the wires terminate inside an -existing silicon block which has been tested for you. +existing silicon block which has been tested for you. In an +ASIC, a bi-directional IO Pad requires three wires (in, out, +out-enable) to be routed right the way from the ASIC, all +the way to the IO PAD, where only then does a wire bond connect +it to a single pin. Designing an ASIC, there is no guarantee that the IO pad is working when manufactured. Worse, the peripheral could be -- 2.30.2