From bed3d976b7a4fd111f3e291f1bd896cf441b3479 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Thu, 26 Apr 2018 08:31:14 +0200 Subject: [PATCH] x86: fix indentation in build_modrm_byte() The VEX3SOURCES code was (originally) written with just space indentation, which is not in line with general coding style as well as the style later in the function. --- gas/ChangeLog | 4 +++ gas/config/tc-i386.c | 78 ++++++++++++++++++++++---------------------- 2 files changed, 43 insertions(+), 39 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index f9a0aa91bb7..c1109a79e76 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2018-04-26 Jan Beulich + + * config/tc-i386.c (build_modrm_byte): Use tabs for indentation. + 2018-04-26 Jan Beulich * config/tc-i386.c (build_modrm_byte): Move and fold diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 0fff4a1c201..42186ffe9d7 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6577,15 +6577,15 @@ build_modrm_byte (void) nds = dest - 1; /* There are 2 kinds of instructions: - 1. 5 operands: 4 register operands or 3 register operands - plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and - VexW0 or VexW1. The destination must be either XMM, YMM or + 1. 5 operands: 4 register operands or 3 register operands + plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and + VexW0 or VexW1. The destination must be either XMM, YMM or ZMM register. - 2. 4 operands: 4 register operands or 3 register operands + 2. 4 operands: 4 register operands or 3 register operands plus 1 memory operand, with VexXDS. */ gas_assert ((i.reg_operands == 4 - || (i.reg_operands == 3 && i.mem_operands == 1)) - && i.tm.opcode_modifier.vexvvvv == VEXXDS + || (i.reg_operands == 3 && i.mem_operands == 1)) + && i.tm.opcode_modifier.vexvvvv == VEXXDS && i.tm.opcode_modifier.vexw && i.tm.operand_types[dest].bitfield.regsimd); @@ -6603,46 +6603,46 @@ build_modrm_byte (void) } if (i.imm_operands == 0) - { - /* When there is no immediate operand, generate an 8bit - immediate operand to encode the first operand. */ - exp = &im_expressions[i.imm_operands++]; - i.op[i.operands].imms = exp; - i.types[i.operands] = imm8; - i.operands++; - - gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); - exp->X_op = O_constant; - exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; + { + /* When there is no immediate operand, generate an 8bit + immediate operand to encode the first operand. */ + exp = &im_expressions[i.imm_operands++]; + i.op[i.operands].imms = exp; + i.types[i.operands] = imm8; + i.operands++; + + gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); + exp->X_op = O_constant; + exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); } else - { - unsigned int imm_slot; + { + unsigned int imm_slot; gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); - if (i.tm.opcode_modifier.immext) - { - /* When ImmExt is set, the immediate byte is the last - operand. */ - imm_slot = i.operands - 1; - source--; - reg_slot--; - } - else - { - imm_slot = 0; - - /* Turn on Imm8 so that output_imm will generate it. */ - i.types[imm_slot].bitfield.imm8 = 1; - } - - gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); - i.op[imm_slot].imms->X_add_number - |= register_number (i.op[reg_slot].regs) << 4; + if (i.tm.opcode_modifier.immext) + { + /* When ImmExt is set, the immediate byte is the last + operand. */ + imm_slot = i.operands - 1; + source--; + reg_slot--; + } + else + { + imm_slot = 0; + + /* Turn on Imm8 so that output_imm will generate it. */ + i.types[imm_slot].bitfield.imm8 = 1; + } + + gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); + i.op[imm_slot].imms->X_add_number + |= register_number (i.op[reg_slot].regs) << 4; gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); - } + } gas_assert (i.tm.operand_types[nds].bitfield.regsimd); i.vex.register_specifier = i.op[nds].regs; -- 2.30.2