From bf10172d3dbdf1dbe8a9d33abd566fa5ca2b8eca Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 11 Sep 2020 16:25:11 +0100 Subject: [PATCH] missing comb += --- src/soc/experiment/dcache.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 44aff9e4..28579a5e 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -318,7 +318,7 @@ class RegStage1(RecordObject): # Cache hit state self.hit_way = Signal(WAY_BITS) self.hit_load_valid = Signal() - self.hit_index = Signal(NUM_LINES) + self.hit_index = Signal(INDEX_BITS) self.cache_hit = Signal() # TLB hit state @@ -852,7 +852,7 @@ class DCache(Elaboratable): # The way to replace on a miss with m.If(r1.write_tag): - replace_way.eq(plru_victim[r1.store_index]) + comb += replace_way.eq(plru_victim[r1.store_index]) with m.Else(): comb += replace_way.eq(r1.store_way) -- 2.30.2