From bf1b98b95813b0ef89f5857c3ab05c9ad79f8f34 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 25 May 2020 20:20:59 +1000 Subject: [PATCH] litedram: Add support for booting without BRAM This adds an option to disable the main BRAM and instead copy a payload stashed along with the init code in the secondary BRAM into DRAM and boot from there Signed-off-by: Benjamin Herrenschmidt --- core_dram_tb.vhdl | 137 +-- fpga/top-arty.vhdl | 34 +- fpga/top-nexys-video.vhdl | 31 +- include/microwatt_soc.h | 2 + litedram/extras/fusesoc-add-files.py | 3 +- litedram/extras/wrapper-mw-init.vhdl | 7 + litedram/gen-src/dram-init-mem.vhdl | 125 ++- litedram/gen-src/sdram_init/main.c | 22 +- litedram/generated/arty/litedram-initmem.vhdl | 69 +- litedram/generated/arty/litedram_core.init | 777 ++++++++++-------- litedram/generated/arty/litedram_core.v | 2 +- .../nexys-video/litedram-initmem.vhdl | 125 ++- .../generated/nexys-video/litedram_core.init | 777 ++++++++++-------- .../generated/nexys-video/litedram_core.v | 2 +- litedram/generated/sim/litedram-initmem.vhdl | 126 ++- litedram/generated/sim/litedram_core.init | 720 ++++++++-------- litedram/generated/sim/litedram_core.v | 2 +- microwatt.core | 11 +- soc.vhdl | 47 +- syscon.vhdl | 41 +- utils.vhdl | 6 +- 21 files changed, 1774 insertions(+), 1292 deletions(-) diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl index 835c1e2..8f91746 100644 --- a/core_dram_tb.vhdl +++ b/core_dram_tb.vhdl @@ -7,33 +7,52 @@ use work.common.all; use work.wishbone_types.all; entity core_dram_tb is + generic ( + MEMORY_SIZE : natural := (384*1024); + MAIN_RAM_FILE : string := "main_ram.bin"; + DRAM_INIT_FILE : string := ""; + DRAM_INIT_SIZE : natural := 16#c000# + ); end core_dram_tb; architecture behave of core_dram_tb is - signal clk, rst: std_logic; - signal system_clk, soc_rst : std_ulogic; - - -- testbench signals - constant clk_period : time := 10 ns; - - -- Sim DRAM - signal wb_dram_in : wishbone_master_out; - signal wb_dram_out : wishbone_slave_out; - signal wb_dram_ctrl_in : wb_io_master_out; - signal wb_dram_ctrl_out : wb_io_slave_out; - signal wb_dram_is_csr : std_ulogic; - signal wb_dram_is_init : std_ulogic; - signal core_alt_reset : std_ulogic; + signal clk, rst: std_logic; + signal system_clk, soc_rst : std_ulogic; + + -- testbench signals + constant clk_period : time := 10 ns; + + -- Sim DRAM + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + signal wb_dram_ctrl_in : wb_io_master_out; + signal wb_dram_ctrl_out : wb_io_slave_out; + signal wb_dram_is_csr : std_ulogic; + signal wb_dram_is_init : std_ulogic; + signal core_alt_reset : std_ulogic; + + -- ROM size + function get_rom_size return natural is + begin + if MEMORY_SIZE = 0 then + return DRAM_INIT_SIZE; + else + return 0; + end if; + end function; + + constant ROM_SIZE : natural := get_rom_size; begin soc0: entity work.soc generic map( SIM => true, - MEMORY_SIZE => (384*1024), - RAM_INIT_FILE => "main_ram.bin", + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => MAIN_RAM_FILE, RESET_LOW => false, HAS_DRAM => true, DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => ROM_SIZE, CLK_FREQ => 100000000 ) port map( @@ -50,48 +69,50 @@ begin alt_reset => core_alt_reset ); - dram: entity work.litedram_wrapper - generic map( - DRAM_ABITS => 24, - DRAM_ALINES => 1 - ) - port map( - clk_in => clk, - rst => rst, - system_clk => system_clk, - system_reset => soc_rst, - core_alt_reset => core_alt_reset, - pll_locked => open, - - wb_in => wb_dram_in, - wb_out => wb_dram_out, - wb_ctrl_in => wb_dram_ctrl_in, - wb_ctrl_out => wb_dram_ctrl_out, - wb_ctrl_is_csr => wb_dram_is_csr, - wb_ctrl_is_init => wb_dram_is_init, - - serial_tx => open, - serial_rx => '1', - - init_done => open, - init_error => open, - - ddram_a => open, - ddram_ba => open, - ddram_ras_n => open, - ddram_cas_n => open, - ddram_we_n => open, - ddram_cs_n => open, - ddram_dm => open, - ddram_dq => open, - ddram_dqs_p => open, - ddram_dqs_n => open, - ddram_clk_p => open, - ddram_clk_n => open, - ddram_cke => open, - ddram_odt => open, - ddram_reset_n => open - ); + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 1, + PAYLOAD_FILE => DRAM_INIT_FILE, + PAYLOAD_SIZE => ROM_SIZE + ) + port map( + clk_in => clk, + rst => rst, + system_clk => system_clk, + system_reset => soc_rst, + core_alt_reset => core_alt_reset, + pll_locked => open, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_dram_ctrl_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_dram_is_csr, + wb_ctrl_is_init => wb_dram_is_init, + + serial_tx => open, + serial_rx => '1', + + init_done => open, + init_error => open, + + ddram_a => open, + ddram_ba => open, + ddram_ras_n => open, + ddram_cas_n => open, + ddram_we_n => open, + ddram_cs_n => open, + ddram_dm => open, + ddram_dq => open, + ddram_dqs_p => open, + ddram_dqs_n => open, + ddram_clk_p => open, + ddram_clk_n => open, + ddram_cke => open, + ddram_odt => open, + ddram_reset_n => open + ); clk_process: process begin diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index e3782ed..c8c2ed8 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -10,11 +10,12 @@ use work.wishbone_types.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 16384; + MEMORY_SIZE : integer := 16384; RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_FREQUENCY : positive := 100000000; USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false ); port( @@ -85,6 +86,28 @@ architecture behaviour of toplevel is -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise signal pwm_counter : std_ulogic_vector(8 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; begin uart_pmod_rts_n <= '0'; @@ -92,13 +115,14 @@ begin -- Main SoC soc0: entity work.soc generic map( - MEMORY_SIZE => MEMORY_SIZE, + MEMORY_SIZE => BRAM_SIZE, RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( @@ -159,7 +183,7 @@ begin ); ddram_clk_dummy <= '0'; - end generate; + end generate; has_dram: if USE_LITEDRAM generate signal dram_init_done : std_ulogic; @@ -189,7 +213,9 @@ begin dram: entity work.litedram_wrapper generic map( DRAM_ABITS => 24, - DRAM_ALINES => 14 + DRAM_ALINES => 14, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE ) port map( clk_in => ext_clk, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 9acbee1..42e6c11 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -10,11 +10,12 @@ use work.wishbone_types.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 16384; + MEMORY_SIZE : integer := 16384; RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_FREQUENCY : positive := 100000000; USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false ); port( @@ -70,18 +71,40 @@ architecture behaviour of toplevel is -- Control/status signal core_alt_reset : std_ulogic; + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; begin -- Main SoC soc0: entity work.soc generic map( - MEMORY_SIZE => MEMORY_SIZE, + MEMORY_SIZE => BRAM_SIZE, RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 512 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( @@ -171,7 +194,9 @@ begin dram: entity work.litedram_wrapper generic map( DRAM_ABITS => 25, - DRAM_ALINES => 15 + DRAM_ALINES => 15, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE ) port map( clk_in => ext_clk, diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index 443a8ae..866ccb4 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -23,6 +23,7 @@ #define SYS_REG_INFO 0x08 #define SYS_REG_INFO_HAS_UART (1ull << 0) #define SYS_REG_INFO_HAS_DRAM (1ull << 1) +#define SYS_REG_INFO_HAS_BRAM (1ull << 2) #define SYS_REG_BRAMINFO 0x10 #define SYS_REG_DRAMINFO 0x18 #define SYS_REG_CLKINFO 0x20 @@ -30,6 +31,7 @@ #define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) #define SYS_REG_CTRL_CORE_RESET (1ull << 1) #define SYS_REG_CTRL_SOC_RESET (1ull << 2) +#define SYS_REG_DRAMINITINFO 0x30 /* * Register definitions for the potato UART diff --git a/litedram/extras/fusesoc-add-files.py b/litedram/extras/fusesoc-add-files.py index efc2233..32681d6 100644 --- a/litedram/extras/fusesoc-add-files.py +++ b/litedram/extras/fusesoc-add-files.py @@ -6,7 +6,8 @@ import pathlib class LiteDRAMGenerator(Generator): def run(self): - board = self.config.get('board') + board = self.config.get('board') + payload = self.config.get('payload') # Collect a bunch of directory path script_dir = os.path.dirname(sys.argv[0]) diff --git a/litedram/extras/wrapper-mw-init.vhdl b/litedram/extras/wrapper-mw-init.vhdl index be4da1e..47f0a6f 100644 --- a/litedram/extras/wrapper-mw-init.vhdl +++ b/litedram/extras/wrapper-mw-init.vhdl @@ -10,6 +10,9 @@ entity litedram_wrapper is generic ( DRAM_ABITS : positive; DRAM_ALINES : positive; + -- Pseudo-ROM payload + PAYLOAD_SIZE : natural; + PAYLOAD_FILE : string; -- Debug LITEDRAM_TRACE : boolean := false ); @@ -144,6 +147,10 @@ begin -- Init code BRAM memory slave init_ram_0: entity work.dram_init_mem + generic map( + EXTRA_PAYLOAD_FILE => PAYLOAD_FILE, + EXTRA_PAYLOAD_SIZE => PAYLOAD_SIZE + ) port map( clk => system_clk, wb_in => wb_init_in, diff --git a/litedram/gen-src/dram-init-mem.vhdl b/litedram/gen-src/dram-init-mem.vhdl index f83d732..13bd0ce 100644 --- a/litedram/gen-src/dram-init-mem.vhdl +++ b/litedram/gen-src/dram-init-mem.vhdl @@ -5,66 +5,117 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index fd43970..68eda15 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -54,12 +54,18 @@ void main(void) printf("UART "); if (ftr & SYS_REG_INFO_HAS_DRAM) printf("DRAM "); + if (ftr & SYS_REG_INFO_HAS_BRAM) + printf("BRAM "); printf("\n"); - val = readq(SYSCON_BASE + SYS_REG_BRAMINFO); - printf(" BRAM: %lld KB\n", val / 1024); + if (ftr & SYS_REG_INFO_HAS_BRAM) { + val = readq(SYSCON_BASE + SYS_REG_BRAMINFO); + printf(" BRAM: %lld KB\n", val / 1024); + } if (ftr & SYS_REG_INFO_HAS_DRAM) { val = readq(SYSCON_BASE + SYS_REG_DRAMINFO); printf(" DRAM: %lld MB\n", val / (1024 * 1024)); + val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO); + printf(" DRAM INIT: %lld KB\n", val / 1024); } val = readq(SYSCON_BASE + SYS_REG_CLKINFO); printf(" CLK: %lld MHz\n", val / 1000000); @@ -70,5 +76,15 @@ void main(void) MIGEN_GIT_SHA1, LITEX_GIT_SHA1); sdrinit(); } - printf("Booting from BRAM...\n"); + if (ftr & SYS_REG_INFO_HAS_BRAM) + printf("Booting from BRAM...\n"); + else { + void *s = (void *)(DRAM_INIT_BASE + 0x4000); + void *d = (void *)DRAM_BASE; + int sz = (0x10000 - 0x4000); + printf("Copying payload to DRAM...\n"); + memcpy(d, s, sz); + printf("Booting from DRAM...\n"); + flush_cpu_icache(); + } } diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl index f83d732..717e4b6 100644 --- a/litedram/generated/arty/litedram-initmem.vhdl +++ b/litedram/generated/arty/litedram-initmem.vhdl @@ -5,8 +5,13 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; wb_in : in wb_io_master_out; @@ -16,11 +21,30 @@ end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is file ram_file : text open read_mode is name; @@ -28,6 +52,11 @@ architecture rtl of dram_init_mem is variable temp_ram : ram_t := (others => (others => '0')); variable ram_line : line; begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; for i in 0 to (INIT_RAM_SIZE/8)-1 loop exit when endfile(ram_file); readline(ram_file, ram_line); @@ -35,25 +64,45 @@ architecture rtl of dram_init_mem is temp_ram(i*2) := temp_word(31 downto 0); temp_ram(i*2+1) := temp_word(63 downto 32); end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin if rising_edge(clk) then - wb_out.ack <= '0'; + oack <= '0'; if (wb_in.cyc and wb_in.stb) = '1' then adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); + obuf <= init_ram(adr); else for i in 0 to 3 loop if wb_in.sel(i) = '1' then @@ -62,8 +111,10 @@ begin end if; end loop; end if; - wb_out.ack <= '1'; + oack <= '1'; end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; end if; end process; diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 3c81a1a..bbad64d 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421f000782107c6 3d80000060213f00 798c07c6618c0000 -618c108c658cf000 +618c10a4658cf000 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +3842a1003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,61 +519,83 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800161df94101c8 +48001739f94101c8 7c7e1b7860000000 -480011a17fe3fb78 +480012517fe3fb78 3821017060000000 -48001bdc7fc3f378 +48001cf87fc3f378 0100000000000000 4e80002000000280 0000000000000000 +7c0007ac00000000 +4e8000204c00012c +0000000000000000 3c4c000100000000 -7c0802a638429e74 -7d908026fbe1fff8 -f801001091810008 -480010adf821ff91 +7c0802a63842a05c +7d800026fbe1fff8 +91810008f8010010 +48001145f821ff91 3c62ffff60000000 -4bffff4d38637d60 +4bffff3538637c78 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+392300012fa30000 +409e00087d4af850 +2c29000139200001 +3929ffffe8c10060 +7ce8305041820010 +419d00207faa3840 +7f65db78e8810060 +7c9e20507fa3eb78 +4bfff9cd7c84f850 +38e000204bfffdd4 +e8e1006098e60000 +f8e1006038e70001 +2b87006c4bffffb4 +409efdb03b200008 +4bfffda87cd83378 +3b2000022b870068 +7cd83378409efd9c +4bfffd903b200001 +4bfffd883b200008 +3b0100413a600020 +993e00004bfffc60 +e92100607d455378 +f921006039290001 +000000004bfffb24 +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1431,6 +1466,7 @@ e8010010ebc1fff0 0000000000000000 0000002054524155 000000204d415244 +000000204d415242 2020202020202020 203a4d4152422020 0a424b20646c6c25 @@ -1439,6 +1475,10 @@ e8010010ebc1fff0 203a4d4152442020 0a424d20646c6c25 0000000000000000 +4152442020202020 +203a54494e49204d +0a424b20646c6c25 +0000000000000000 2020202020202020 203a4b4c43202020 7a484d20646c6c25 @@ -1455,6 +1495,13 @@ e8010010ebc1fff0 20676e69746f6f42 415242206d6f7266 0000000a2e2e2e4d +20676e6979706f43 +2064616f6c796170 +2e4d415244206f74 +00000000000a2e2e +20676e69746f6f42 +415244206d6f7266 +0000000a2e2e2e4d 20747365746d654d 6c69616620737562 252f6425203a6465 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 6cb2c1e..48af9e2 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:16 +// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:38 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/nexys-video/litedram-initmem.vhdl b/litedram/generated/nexys-video/litedram-initmem.vhdl index f83d732..13bd0ce 100644 --- a/litedram/generated/nexys-video/litedram-initmem.vhdl +++ b/litedram/generated/nexys-video/litedram-initmem.vhdl @@ -5,66 +5,117 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 3c81a1a..bbad64d 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421f000782107c6 3d80000060213f00 798c07c6618c0000 -618c108c658cf000 +618c10a4658cf000 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +3842a1003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,61 +519,83 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800161df94101c8 +48001739f94101c8 7c7e1b7860000000 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7c0004ac79290020 @@ -631,11 +653,11 @@ f801001091810008 9864000099240001 000000004e800020 0000000000000000 -38429b383c4c0001 -480017ed7c0802a6 +38429c883c4c0001 +480018597c0802a6 7c7e1b78f821ff21 -38637f403c62ffff -600000004bfffc21 +38637eb83c62ffff +600000004bfffb71 390100603ca08020 3940000460a50003 7d1d43783920002a @@ -686,7 +708,7 @@ f801001091810008 793500203ee2ffff 7d2907b47ed607b4 3b0100703be00000 -7f3db2143af77f68 +7f3db2143af77ee0 7f5d4a147ebdaa14 3860000f4bfffd75 4bfffca93b800000 @@ -727,8 +749,8 @@ f801001091810008 4bffffcc3b400000 7fbfe2142f9f0020 409e006c7fbd0e70 -38637f503c62ffff -600000004bfff939 +38637ec83c62ffff +600000004bfff889 3be000007fc3f378 7f9fe8004bfffb8d 3d40c010419c0070 @@ -739,45 +761,45 @@ f801001091810008 7d20572a7c0004ac 4bfffaed3860000b 4bfffb213860000f -480014e4382100e0 +48001550382100e0 3c62ffff7cbfe050 7ca501947ca50e70 -38637f587fa4eb78 -4bfff8bd7ca507b4 +38637ed07fa4eb78 +4bfff80d7ca507b4 4bffff8460000000 3bff00017fc3f378 7fff07b44bfffb59 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a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 2364067..e42fa0d 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:18 +// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:40 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl index 614f19b..e9a379c 100644 --- a/litedram/generated/sim/litedram-initmem.vhdl +++ b/litedram/generated/sim/litedram-initmem.vhdl @@ -5,66 +5,118 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + file payload_file : text open read_mode is EXTRA_PAYLOAD_FILE; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + procedure init_load_payload(ram: inout ram_t; filename: string) is + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 11e61fa..8cd34d7 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -7,7 +7,7 @@ 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93dd000093dc0000 -4bfffd9993c90000 +4bfffce993c90000 813f000060000000 7d29f278815c0000 7d2900347f8af000 @@ -622,7 +644,7 @@ f821ff713f804000 93dd000093dc0000 3d20400093c90000 93c900006129000c -600000004bfffcfd +600000004bfffc4d 7f89f000813c0000 3bff0001419e000c 813d00007fff07b4 @@ -638,7 +660,7 @@ f821ff713f804000 3bff0001419e0028 3c62ffff7fff07b4 7fe4fb7838a00100 -4bfffc0538637ef0 +4bfffb5538637f70 4800000c60000000 409effe02fbf0000 3ce0802039000004 @@ -648,7 +670,7 @@ f821ff713f804000 7d2900d0792907e0 7d293838394a0004 912afffc7d294278 -4bfffc294200ffe4 +4bfffb794200ffe4 3900000460000000 7d0903a63ce08020 3d40400060e70003 @@ -662,7 +684,7 @@ f821ff713f804000 2fbe00004200ffd4 3c62ffff419e001c 7fc4f37838a00004 -4bfffb4538637f18 +4bfffa9538637f98 3d20400060000000 6129000839400000 914900003ba00000 @@ -672,7 +694,7 @@ f821ff713f804000 9149000061290010 394000033d204000 9149000061290014 -600000004bfffb6d +600000004bfffabd 3940000039200004 3d2a10007d2903a6 8129000879291764 @@ -682,12 +704,12 @@ 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6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1124,6 +1160,7 @@ ebe1fff8e8010010 0000000000000000 0000002054524155 000000204d415244 +000000204d415242 2020202020202020 203a4d4152422020 0a424b20646c6c25 @@ -1132,6 +1169,10 @@ ebe1fff8e8010010 203a4d4152442020 0a424d20646c6c25 0000000000000000 +4152442020202020 +203a54494e49204d +0a424b20646c6c25 +0000000000000000 2020202020202020 203a4b4c43202020 7a484d20646c6c25 @@ -1148,6 +1189,13 @@ ebe1fff8e8010010 20676e69746f6f42 415242206d6f7266 0000000a2e2e2e4d +20676e6979706f43 +2064616f6c796170 +2e4d415244206f74 +00000000000a2e2e +20676e69746f6f42 +415244206d6f7266 +0000000a2e2e2e4d 20747365746d654d 6c69616620737562 252f6425203a6465 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index 10f9ecb..b92a59c 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-22 17:57:20 +// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:42 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/microwatt.core b/microwatt.core index 9cc51ee..8dc5a12 100644 --- a/microwatt.core +++ b/microwatt.core @@ -130,6 +130,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_nexys_video] tools: vivado: {part : xc7a200tsbg484-1} @@ -156,6 +157,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_arty] tools: vivado: {part : xc7a35ticsg324-1L} @@ -182,6 +184,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_arty] tools: vivado: {part : xc7a100ticsg324-1L} @@ -219,7 +222,7 @@ generate: parameters: memory_size: datatype : int - description : On-chip memory size (bytes) + description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload paramtype : generic default : 16384 @@ -256,3 +259,9 @@ parameters: description : Use liteDRAM paramtype : generic default : false + + no_bram: + datatype : bool + description : No internal block RAM (only DRAM and init code carrying payload) + paramtype : generic + default : false diff --git a/soc.vhdl b/soc.vhdl index 7aef68a..62d6ac4 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -26,14 +26,15 @@ use work.wishbone_types.all; entity soc is generic ( - MEMORY_SIZE : positive; - RAM_INIT_FILE : string; - RESET_LOW : boolean; - CLK_FREQ : positive; - SIM : boolean; + MEMORY_SIZE : natural; + RAM_INIT_FILE : string; + RESET_LOW : boolean; + CLK_FREQ : positive; + SIM : boolean; DISABLE_FLATTEN_CORE : boolean := false; - HAS_DRAM : boolean := false; - DRAM_SIZE : integer := 0 + HAS_DRAM : boolean := false; + DRAM_SIZE : integer := 0; + DRAM_INIT_SIZE : integer := 0 ); port( rst : in std_ulogic; @@ -105,7 +106,6 @@ architecture behaviour of soc is -- Main memory signals: signal wb_bram_in : wishbone_master_out; signal wb_bram_out : wishbone_slave_out; - constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE)))); -- DMI debug bus signals signal dmi_addr : std_ulogic_vector(7 downto 0); @@ -466,6 +466,7 @@ begin HAS_DRAM => HAS_DRAM, BRAM_SIZE => MEMORY_SIZE, DRAM_SIZE => DRAM_SIZE, + DRAM_INIT_SIZE => DRAM_INIT_SIZE, CLK_FREQ => CLK_FREQ ) port map( @@ -516,17 +517,25 @@ begin ); -- BRAM Memory slave - bram0: entity work.wishbone_bram_wrapper - generic map( - MEMORY_SIZE => MEMORY_SIZE, - RAM_INIT_FILE => RAM_INIT_FILE - ) - port map( - clk => system_clk, - rst => rst_bram, - wishbone_in => wb_bram_in, - wishbone_out => wb_bram_out - ); + bram: if MEMORY_SIZE /= 0 generate + bram0: entity work.wishbone_bram_wrapper + generic map( + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE + ) + port map( + clk => system_clk, + rst => rst_bram, + wishbone_in => wb_bram_in, + wishbone_out => wb_bram_out + ); + end generate; + + no_bram: if MEMORY_SIZE = 0 generate + wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb; + wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF"; + wb_bram_out.stall <= wb_bram_in.cyc and not wb_bram_out.ack; + end generate; -- DMI(debug bus) <-> JTAG bridge dtm: entity work.dmi_dtm diff --git a/syscon.vhdl b/syscon.vhdl index a9dd1cc..79d9531 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -8,12 +8,13 @@ use work.wishbone_types.all; entity syscon is generic ( - SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001"; - CLK_FREQ : integer; - HAS_UART : boolean; - HAS_DRAM : boolean; - BRAM_SIZE : integer; - DRAM_SIZE : integer + SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001"; + CLK_FREQ : integer; + HAS_UART : boolean; + HAS_DRAM : boolean; + BRAM_SIZE : integer; + DRAM_SIZE : integer; + DRAM_INIT_SIZE : integer ); port ( clk : in std_ulogic; @@ -36,12 +37,13 @@ architecture behaviour of syscon is constant SYS_REG_BITS : positive := 3; -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg) - constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000"; - constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001"; - constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010"; - constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011"; - constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100"; - constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101"; + constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000"; + constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001"; + constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010"; + constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011"; + constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100"; + constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101"; + constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "110"; -- Muxed reg read signal signal reg_out : std_ulogic_vector(63 downto 0); @@ -49,6 +51,7 @@ architecture behaviour of syscon is -- INFO register bits constant SYS_REG_INFO_HAS_UART : integer := 0; constant SYS_REG_INFO_HAS_DRAM : integer := 1; + constant SYS_REG_INFO_HAS_BRAM : integer := 2; -- BRAMINFO contains the BRAM size in the bottom 52 bits -- DRAMINFO contains the DRAM size if any in the bottom 52 bits @@ -69,14 +72,16 @@ architecture behaviour of syscon is signal reg_info : std_ulogic_vector(63 downto 0); signal reg_braminfo : std_ulogic_vector(63 downto 0); signal reg_draminfo : std_ulogic_vector(63 downto 0); + signal reg_dramiinfo : std_ulogic_vector(63 downto 0); signal reg_clkinfo : std_ulogic_vector(63 downto 0); signal info_has_dram : std_ulogic; + signal info_has_bram : std_ulogic; signal info_has_uart : std_ulogic; signal info_clk : std_ulogic_vector(39 downto 0); begin -- Generated output signals - dram_at_0 <= reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); + dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); @@ -87,13 +92,17 @@ begin -- Info register is hard wired info_has_uart <= '1' when HAS_UART else '0'; info_has_dram <= '1' when HAS_DRAM else '0'; + info_has_bram <= '1' when BRAM_SIZE /= 0 else '0'; info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); reg_info <= (0 => info_has_uart, 1 => info_has_dram, + 2 => info_has_bram, others => '0'); reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM else (others => '0'); + reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM + else (others => '0'); reg_clkinfo <= (39 downto 0 => info_clk, others => '0'); @@ -107,6 +116,7 @@ begin reg_info when SYS_REG_INFO, reg_braminfo when SYS_REG_BRAMINFO, reg_draminfo when SYS_REG_DRAMINFO, + reg_dramiinfo when SYS_REG_DRAMINITINFO, reg_clkinfo when SYS_REG_CLKINFO, reg_ctrl_out when SYS_REG_CTRL, (others => '0') when others; @@ -136,6 +146,11 @@ begin if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0'; end if; + + -- If BRAM doesn't exist, force DRAM at 0 + if BRAM_SIZE = 0 then + reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1'; + end if; end if; end if; end process; diff --git a/utils.vhdl b/utils.vhdl index 4ccc3b5..14a6838 100644 --- a/utils.vhdl +++ b/utils.vhdl @@ -7,7 +7,7 @@ package utils is function log2(i : natural) return integer; function log2ceil(i : natural) return integer; function ispow2(i : integer) return boolean; - + function round_up(i : integer; s : integer) return integer; end utils; package body utils is @@ -43,5 +43,9 @@ package body utils is end if; end function; + function round_up(i : integer; s : integer) return integer is + begin + return ((i + (s - 1)) / s) * s; + end function; end utils; -- 2.30.2