From bf1d0c68e55859885b356d58ae7f4dac1a7b2b8d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Jul 2018 10:48:37 +0100
Subject: [PATCH] convert mux to interface style same as gpio

---
 src/bsv/bsv_lib/gpio_instance.bsv | 16 +++++++++++++++
 src/bsv/bsv_lib/mux.bsv           | 33 +++++++++++--------------------
 2 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/src/bsv/bsv_lib/gpio_instance.bsv b/src/bsv/bsv_lib/gpio_instance.bsv
index a6dc260..8705704 100644
--- a/src/bsv/bsv_lib/gpio_instance.bsv
+++ b/src/bsv/bsv_lib/gpio_instance.bsv
@@ -22,6 +22,7 @@ package gpio_instance;
 	import Semi_FIFOF        :: *;
 	import AXI4_Lite_Types   :: *;
 	import gpio   :: *;
+	import mux   :: *;
 	/*============================ */
       `include "instance_defines.bsv"
 
@@ -32,6 +33,12 @@ package gpio_instance;
     interface GPIO_config#(15) bankB_config;
 		interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) bankB_slave;
 	endinterface
+	interface MUX_real;
+    interface MUX_config#(32) muxbankA_config;
+		interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) muxbankA_slave;
+    interface MUX_config#(15) muxbankB_config;
+		interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) muxbankB_slave;
+	endinterface
   (*synthesize*)
   module mkgpio_real(GPIO_real);
     GPIO#(32) mygpioA <- mkgpio();
@@ -41,5 +48,14 @@ package gpio_instance;
     interface bankA_slave=mygpioA.axi_slave;
     interface bankB_slave=mygpioB.axi_slave;
   endmodule
+  (*synthesize*)
+  module mkmux_real(MUX_real);
+    MUX#(32)  mymuxA <- mkmux();
+    MUX#(15)  mymuxB <- mkmux();
+    interface muxbankA_config=mymuxA.mux_config;
+    interface muxbankB_config=mymuxB.mux_config;
+    interface muxbankA_slave=mymuxA.axi_slave;
+    interface muxbankB_slave=mymuxB.axi_slave;
+  endmodule
 endpackage
 
diff --git a/src/bsv/bsv_lib/mux.bsv b/src/bsv/bsv_lib/mux.bsv
index bb9a281..0be0742 100644
--- a/src/bsv/bsv_lib/mux.bsv
+++ b/src/bsv/bsv_lib/mux.bsv
@@ -22,23 +22,23 @@ package mux;
 	import Semi_FIFOF        :: *;
 	import AXI4_Lite_Types   :: *;
 	/*============================ */
-  `define ADDR 32
-  `define DATA 64
-  `define USER 0
-  `define IONum 32
-  `define GPIO_MUX
+    `include "instance_defines.bsv"
 
-	interface MUX#(numeric type ionum);
+    interface MUX_config#(numeric type ionum);
 		(*always_ready,always_enabled*)
 		method Vector#(ionum,Bit#(2))   mux;
-		interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USER) axi_slave;
+    endinterface
+
+	interface MUX#(numeric type ionum);
+        interface MUX_config#(ionum) mux_config;
+            interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
 	endinterface
 
 //	(*synthesize*)
 	module mkmux(MUX#(ionum_));
 	  Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg 				<-replicateM(mkConfigReg(0));
 		
-		AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USER)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
+		AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
     let ionum=valueOf(ionum_);
 		rule rl_wr_respond;
 			// Get the wr request
@@ -61,7 +61,7 @@ package mux;
 		rule rl_rd_respond;
 			let ar<- pop_o(s_xactor.o_rd_addr);
 			Bit#(32) temp=0;
-			AXI4_Lite_Rd_Data#(`DATA,`USER) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
+			AXI4_Lite_Rd_Data#(`DATA,`USERSPACE) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
 		  if(ar.araddr[5:0]=='h2c)begin
 		  	for(Integer i=0;i<min(ionum, 16);i=i+1) begin
           temp[i*2+ 1:i*2]=muxer_reg[i];
@@ -80,26 +80,15 @@ package mux;
 		endrule
 
 		interface axi_slave= s_xactor.axi_side;
+    interface mux_config=interface MUX_config
 		method Vector#(ionum,Bit#(2))   mux;
 			Vector#(ionum,Bit#(2)) temp;
 			for(Integer i=0;i<ionum;i=i+1)
 				temp[i]=pack(muxer_reg[i]);
 			return temp;
 		endmethod
+    endinterface;
 	endmodule
 
-
-  // instantiation template
-	interface MUX_real;
-		(*always_ready,always_enabled*)
-		method Vector#(32,Bit#(2))   mux;
-		interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USER) axi_slave;
-	endinterface
-  (*synthesize*)
-  module mkmux_real(MUX_real);
-    MUX#(32) mymux <-mkmux();
-    method mux=mymux.mux;
-    interface axi_slave=mymux.axi_slave;
-  endmodule
 endpackage
 
-- 
2.30.2