From bf41ae9a1ace70834f502b0cf4da123874c3345e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 23 May 2020 18:40:49 +0100 Subject: [PATCH] add notes on FunctionUnit API --- src/soc/experiment/compalu_multi.py | 3 +- src/soc/fu/compunits.py | 63 +++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 src/soc/fu/compunits.py diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 89e4c6ee..3e41739c 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -153,6 +153,7 @@ class CompUnitRecord(RecordObject): return self._rwid return get_regspec_bitwidth(self._rwid, 0, i) + class MultiCompUnit(Elaboratable): def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1): """MultiCompUnit @@ -203,14 +204,12 @@ class MultiCompUnit(Elaboratable): if isinstance(self.rwid, int): # old - testing - API (rwid is int) return self.alu.out[i] # regspec-based API: look up variable through regspec according to row number - print ("get out", dir(self.alu.n.data_o)) return getattr(self.alu.n.data_o, self.rwid[1][i][1]) def get_in(self, i): if isinstance(self.rwid, int): # old - testing - API (rwid is int) return self.alu.i[i] # regspec-based API: look up variable through regspec according to row number - print ("get in", dir(self.alu.p.data_i)) return getattr(self.alu.p.data_i, self.rwid[0][i][1]) def get_op(self): diff --git a/src/soc/fu/compunits.py b/src/soc/fu/compunits.py new file mode 100644 index 00000000..68d42d88 --- /dev/null +++ b/src/soc/fu/compunits.py @@ -0,0 +1,63 @@ +""" +* see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs + +""" + +from nmigen.cli import rtlil +from soc.experiment.compalu_multi import MultiCompUnit + +from soc.fu.alu.pipeline import ALUBasePipe +from soc.fu.alu.pipe_data import ALUPipeSpec + +from soc.fu.cr.pipeline import CRBasePipe +from soc.fu.cr.pipe_data import CRPipeSpec + + +class FunctionUnitBaseSingle(MultiCompUnit): + """FunctionUnitBaseSingle + + main "glue" class that brings everything together. + ONLY use this class for single-stage pipelines. + + * :speckls: - the specification. contains regspec and op subset info, + and contains common "stuff" like the pipeline ctx, + what type of nmutil pipeline base is to be used (etc) + * :pipekls: - the type of pipeline. actually connects things together + + note that it is through MultiCompUnit.get_in/out that we *actually* + connect up the association between regspec variable names (defined + in the pipe_data). + """ + def __init__(self, speckls, pipekls): + pspec = speckls(id_wid=2) # spec (NNNPipeSpec instance) + opsubset = pspec.opsubsetkls # get the operand subset class + regspec = pspec.regspec # get the regspec + alu = pipekls(pspec) # create actual NNNBasePipe + super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit + + +###################################################################### +###### actual Function Units: these are "single" stage pipelines ##### + +class ALUFunctionUnit(FunctionUnitBaseSingle): + def __init__(self): super().__init__(ALUPipeSpec, ALUBasePipe) + +class CRFunctionUnit(FunctionUnitBaseSingle): + def __init__(self): super().__init__(CRPipeSpec, CRBasePipe) + +##################################################################### +###### actual Function Units: these are "multi" stage pipelines ##### + +# TODO: ReservationStations-based. + + +def tst_single_fus_il(): + for (name, kls) in (('alu', ALUFunctionUnit), + ('cr', CRFunctionUnit)): + fu = kls() + vl = rtlil.convert(fu, ports=fu.ports()) + with open("fu_%s.il" % name, "w") as f: + f.write(vl) + +if __name__ == '__main__': + tst_single_fus_il() -- 2.30.2