From bf60f3593452f6ab6340c7a8737cc74f223f2a62 Mon Sep 17 00:00:00 2001
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Fri, 17 Sep 2010 11:13:26 +0800
Subject: [PATCH] i965: disasm quarter and write enable instruction control on
 sandybridge

---
 src/mesa/drivers/dri/i965/brw_disasm.c | 70 ++++++++++++++++++++++----
 1 file changed, 61 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index f74a236834b..90520824f60 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -164,6 +164,11 @@ char *accwr[2] = {
     [1] = "AccWrEnable"
 };
 
+char *wectrl[2] = {
+    [0] = "WEnormal",
+    [1] = "WEpredicted"
+};
+
 char *exec_size[8] = {
     [0] = "1",
     [1] = "2",
@@ -651,6 +656,7 @@ static int src_da16 (FILE *file,
 	err |= control (file, "channel select", chan_sel, swz_z, NULL);
 	err |= control (file, "channel select", chan_sel, swz_w, NULL);
     }
+    err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
     return err;
 }
 
@@ -804,6 +810,44 @@ static int src1 (FILE *file, struct brw_instruction *inst)
     }
 }
 
+int esize[6] = {
+	[0] = 1,
+	[1] = 2,
+	[2] = 4,
+	[3] = 8,
+	[4] = 16,
+	[5] = 32,
+};
+
+static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
+{
+    int qtr_ctl = inst->header.compression_control;
+    int exec_size = esize[inst->header.execution_size];
+
+    if (exec_size == 8) {
+	switch (qtr_ctl) {
+	case 0:
+	    string (file, " 1Q");
+	    break;
+	case 1:
+	    string (file, " 2Q");
+	    break;
+	case 2:
+	    string (file, " 3Q");
+	    break;
+	case 3:
+	    string (file, " 4Q");
+	    break;
+	}
+    } else if (exec_size == 16){
+	if (qtr_ctl < 2)
+	    string (file, " 1H");
+	else
+	    string (file, " 2H");
+    }
+    return 0;
+}
+
 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 {
     int	err = 0;
@@ -998,18 +1042,26 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	string (file, "{");
 	space = 1;
 	err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
-	err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
+	if (gen >= 6)
+	    err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
+	else
+	    err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
 	err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
 
-	if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
-	    opcode[inst->header.opcode].ndst > 0 &&
-	    inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
-	    inst->bits1.da1.dest_reg_nr & (1 << 7)) {
-	   format (file, " compr4");
-	} else {
-	   err |= control (file, "compression control", compr_ctrl,
-			   inst->header.compression_control, &space);
+	if (gen >= 6)
+	    err |= qtr_ctrl (file, inst);
+	else {
+	    if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
+		opcode[inst->header.opcode].ndst > 0 &&
+		inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
+		inst->bits1.da1.dest_reg_nr & (1 << 7)) {
+		format (file, " compr4");
+	    } else {
+		err |= control (file, "compression control", compr_ctrl,
+				inst->header.compression_control, &space);
+	    }
 	}
+
 	err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
 	if (gen >= 6)
 	    err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
-- 
2.30.2