From bf6407079bfc221cbac559dcddd10c6f69037982 Mon Sep 17 00:00:00 2001
From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon, 19 Oct 2015 18:46:29 -0700
Subject: [PATCH] i965: Split process_nir into two haves; pre- and post-

---
 src/mesa/drivers/dri/i965/brw_nir.c | 39 ++++++++++++++++++-----------
 src/mesa/drivers/dri/i965/brw_nir.h | 11 +++++---
 src/vulkan/anv_compiler.cpp         |  8 +++---
 3 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c
index dc497770914..9a33188cb5c 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -200,7 +200,14 @@ brw_create_nir(struct brw_context *brw,
    }
    nir_validate_shader(nir);
 
-   brw_process_nir(nir, brw->intelScreen->devinfo, shader_prog, stage, is_scalar);
+   brw_preprocess_nir(nir, brw->intelScreen->devinfo, is_scalar);
+
+   if (shader_prog) {
+      nir_lower_samplers(nir, shader_prog);
+      nir_validate_shader(nir);
+   }
+
+   brw_postprocess_nir(nir, brw->intelScreen->devinfo, is_scalar);
 
    static GLuint msg_id = 0;
    _mesa_gl_debug(&brw->ctx, &msg_id,
@@ -208,23 +215,21 @@ brw_create_nir(struct brw_context *brw,
                   MESA_DEBUG_TYPE_OTHER,
                   MESA_DEBUG_SEVERITY_NOTIFICATION,
                   "%s NIR shader:\n",
-                  _mesa_shader_stage_to_abbrev(stage));
+                  _mesa_shader_stage_to_abbrev(nir->stage));
 
    return nir;
 }
 
 void
-brw_process_nir(nir_shader *nir,
-                const struct brw_device_info *devinfo,
-                const struct gl_shader_program *shader_prog,
-                gl_shader_stage stage, bool is_scalar)
+brw_preprocess_nir(nir_shader *nir,
+                   const struct brw_device_info *devinfo,
+                   bool is_scalar)
 {
-   bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
    static const nir_lower_tex_options tex_options = {
       .lower_txp = ~0,
    };
 
-   if (stage == MESA_SHADER_GEOMETRY) {
+   if (nir->stage == MESA_SHADER_GEOMETRY) {
       nir_lower_gs_intrinsics(nir);
       nir_validate_shader(nir);
    }
@@ -249,6 +254,15 @@ brw_process_nir(nir_shader *nir,
 
    /* Get rid of split copies */
    nir_optimize(nir, is_scalar);
+}
+
+void
+brw_postprocess_nir(nir_shader *nir,
+                    const struct brw_device_info *devinfo,
+                    bool is_scalar)
+{
+   bool debug_enabled =
+      (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
 
    brw_nir_lower_inputs(nir, is_scalar);
    brw_nir_lower_outputs(nir, is_scalar);
@@ -261,11 +275,6 @@ brw_process_nir(nir_shader *nir,
    nir_remove_dead_variables(nir);
    nir_validate_shader(nir);
 
-   if (shader_prog) {
-      nir_lower_samplers(nir, shader_prog);
-      nir_validate_shader(nir);
-   }
-
    nir_lower_system_values(nir);
    nir_validate_shader(nir);
 
@@ -301,7 +310,7 @@ brw_process_nir(nir_shader *nir,
       }
 
       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
-              _mesa_shader_stage_to_string(stage));
+              _mesa_shader_stage_to_string(nir->stage));
       nir_print_shader(nir, stderr);
    }
 
@@ -328,7 +337,7 @@ brw_process_nir(nir_shader *nir,
 
    if (unlikely(debug_enabled)) {
       fprintf(stderr, "NIR (final form) for %s shader:\n",
-              _mesa_shader_stage_to_string(stage));
+              _mesa_shader_stage_to_string(nir->stage));
       nir_print_shader(nir, stderr);
    }
 }
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h b/src/mesa/drivers/dri/i965/brw_nir.h
index 19e55527545..a6d6768795a 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -86,10 +86,13 @@ enum brw_reg_type brw_type_for_nir_type(nir_alu_type type);
 enum glsl_base_type brw_glsl_base_type_for_nir_type(nir_alu_type type);
 
 void
-brw_process_nir(nir_shader *nir,
-                const struct brw_device_info *devinfo,
-                const struct gl_shader_program *shader_prog,
-                gl_shader_stage stage, bool is_scalar);
+brw_preprocess_nir(nir_shader *nir,
+                   const struct brw_device_info *devinfo,
+                   bool is_scalar);
+void
+brw_postprocess_nir(nir_shader *nir,
+                    const struct brw_device_info *devinfo,
+                    bool is_scalar);
 
 void brw_nir_setup_glsl_uniforms(nir_shader *shader,
                                  struct gl_shader_program *shader_prog,
diff --git a/src/vulkan/anv_compiler.cpp b/src/vulkan/anv_compiler.cpp
index 14d3fad23e7..5d74f0f131e 100644
--- a/src/vulkan/anv_compiler.cpp
+++ b/src/vulkan/anv_compiler.cpp
@@ -729,11 +729,13 @@ anv_compile_shader_spirv(struct anv_compiler *compiler,
    }
    nir_validate_shader(mesa_shader->Program->nir);
 
+   brw_preprocess_nir(mesa_shader->Program->nir,
+                      compiler->screen->devinfo, is_scalar);
+
    setup_nir_io(mesa_shader, mesa_shader->Program->nir);
 
-   brw_process_nir(mesa_shader->Program->nir,
-                   compiler->screen->devinfo,
-                   NULL, mesa_shader->Stage, is_scalar);
+   brw_postprocess_nir(mesa_shader->Program->nir,
+                       compiler->screen->devinfo, is_scalar);
 
    mesa_shader->num_uniform_components =
       mesa_shader->Program->nir->num_uniforms;
-- 
2.30.2