From bf755067514a42003af435ec2bf8fa820187f7e7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 28 Mar 2022 23:32:24 +0100 Subject: [PATCH] links and qualification of SVP64 types in cr_int_predication ops --- openpower/sv/cr_int_predication.mdwn | 41 ++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 073de068c..722c6a0c3 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -108,13 +108,15 @@ Note that `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is def Instruction format: - | 0-5 | 6-10 | 11 | 12-15 | 16-18 | 19-20 | 21-25 | 26-30 | 31 | name | - | --- | ---- | -- | ----- | ----- | ----- | ----- | ----- | -- | ---- | - | 19 | RT | | mask | BB | | XO[0:4] | XO[5:9] | / | | - | 19 | RT | 0 | mask | BB | 0 M | XO[0:4] | 0 mode | Rc | crrweird | - | 19 | RA | 1 | mask | BT | 0 / | XO[0:4] | 0 mode | / | mtcrweird | - | 19 | BT // | 0 | mask | BB | 1 / | XO[0:4] | 0 mode | / | crweird | - | 19 | BFT | 1 | mask | BB | 1 M | XO[0:4] | 0 mode | / | crweirder | +|0-5|6-10 |11|12-15|16-18|19-20|21-25 |26-30 |31|name | +|---|---- |--|-----|-----|-----|----- |----- |--|---- | +|19 |RT | |mask |BB | |XO[0:4]|XO[5:9]|/ | | +|19 |RT |0 |mask |BB | 0 M |XO[0:4]|0 mode |Rc|crrweird | +|19 |RA |1 |mask |BT | 0 / |XO[0:4]|0 mode |/ |mtcrweird | +|19 |BT //|0 |mask |BB | 1 / |XO[0:4]|0 mode |/ |crweird | +|19 |BFT |1 |mask |BB | 1 M |XO[0:4]|0 mode |/ |crweirder | + +**crrweird** mode is encoded in XO and is 4 bits @@ -130,7 +132,12 @@ bit 11=0, bit 19=0 result = n0|n1|n2|n3 if M else n0&n1&n2&n3 RT[63] = result # MSB0 numbering, 63 is LSB If Rc: - CR1 = analyse(RT) + CR0 = analyse(RT) + +This is a [[openpower/sv/normal]] SVP64 type operation and as +such can use Rc=1 and RC1 Data-dependent Mode capability + +**mtcrweird** bit 11=1, bit 19=0 @@ -144,6 +151,12 @@ bit 11=1, bit 19=0 n3 = mask[3] & (mode[3] == lsb) CR{BT} = n0 || n1 || n2 || n3 +This is a [[openpower/sv/cr_int]] SVP64 type operation that has +3-bit Data-dependent and 3-bit Predicate-result capability +(BT is 3 bits) + +**crweird** + bit 11=0, bit 19=1 crweird: BT, BB, mask.mode @@ -155,6 +168,12 @@ bit 11=0, bit 19=1 n3 = mask[3] & (mode[3] == creg[3]) CR{BT} = n0 || n1 || n2 || n3 +This is a [[openpower/sv/cr_int]] SVP64 type operation that has +3-bit Data-dependent and 3-bit Predicate-result capability +(BT is 3 bits) + +**crweirder** + bit 11=1, bit 19=1 crweirder: BFT, BB, mask.mode @@ -169,7 +188,11 @@ bit 11=1, bit 19=1 result = n0|n1|n2|n3 if M else n0&n1&n2&n3 CR{BF}[bit] = result -Pseudo-op: +This is a [[openpower/sv/cr_int]] SVP64 type operation that has +5-bit Data-dependent and 5-bit Predicate-result capability +(BFT is 5 bits) + +**Example Pseudo-ops:** mtcri BB, mode mtcrweird r0, BB, 0b1111.~mode mtcrset BB, mask mtcrweird r0, BB, mask.0b0000 -- 2.30.2