From bfaa026c90d2c5150335cd4496e288005490ecda Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 15 Sep 2020 10:23:30 +0100 Subject: [PATCH] mmu uses RB, go with it --- src/soc/fu/mmu/pipe_data.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py index 5affde65..4116a781 100644 --- a/src/soc/fu/mmu/pipe_data.py +++ b/src/soc/fu/mmu/pipe_data.py @@ -2,9 +2,8 @@ Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE. -Note: RB is *redirected* (in the decoder CSV files) to the field that -happens, here, to be named "ra"! yes wonderfully confusing. similar -thing goes on with shift_rot. +Interestingly none of the MMU instructions use RA, they all use RB. +go with it... Links: * https://bugs.libre-soc.org/show_bug.cgi?id=491 @@ -17,14 +16,14 @@ from soc.fu.alu.pipe_data import CommonPipeSpec class MMUInputData(IntegerData): - regspec = [('INT', 'ra', '0:63'), # RA + regspec = [('INT', 'rb', '0:63'), # RB ('SPR', 'spr1', '0:63'), # MMU (slow) ('FAST', 'fast1', '0:63'), # MMU (fast: LR, CTR etc) ] def __init__(self, pspec): super().__init__(pspec, False) # convenience - self.a = self.ra + self.b = self.rb class MMUOutputData(IntegerData): -- 2.30.2