From bfabf12685561ff17101b97faac9d26a8c3c5688 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Apr 2019 17:55:30 +0100 Subject: [PATCH] convert fdiv to set op based on get_op return results --- src/add/nmigen_div_experiment.py | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py index abbcf95f..ff0e54cb 100644 --- a/src/add/nmigen_div_experiment.py +++ b/src/add/nmigen_div_experiment.py @@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat from nmigen.cli import main, verilog from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState -from fpcommon.getop import FPGetOp +from singlepipe import eq class Div: def __init__(self, width): @@ -61,31 +61,24 @@ class FPDIV(FPBase): m.submodules.z = z m.submodules.of = of + m.d.comb += a.v.eq(self.in_a.v) + m.d.comb += b.v.eq(self.in_b.v) + with m.FSM() as fsm: # ****** # gets operand a - geta = FPGetOp("get_a", "get_b", self.in_a, self.width) - geta.setup(m, self.in_a) - with m.State("get_a"): - geta.action(m) - with m.If(geta.out_decode): - m.d.sync += a.decode(self.in_a.v) - #self.get_op(m, self.in_a, a, "get_b") + res = self.get_op(m, self.in_a, a, "get_b") + m.d.sync += eq([a, self.in_a.ack], res) # ****** # gets operand b - getb = FPGetOp("get_b", "special_cases", self.in_b, self.width) - getb.setup(m, self.in_b) - with m.State("get_b"): - getb.action(m) - with m.If(getb.out_decode): - m.d.sync += b.decode(self.in_b.v) - #self.get_op(m, self.in_b, b, "special_cases") + res = self.get_op(m, self.in_b, b, "special_cases") + m.d.sync += eq([b, self.in_b.ack], res) # ****** # special cases: NaNs, infs, zeros, denormalised -- 2.30.2