From bfb2b902464b1c493e4bfa1f3c2da065a964ac85 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Fri, 19 Oct 2018 16:16:41 -0400 Subject: [PATCH] radeonsi: Disable clear_state with radeon kernel driver MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Sonny Jiang Tested-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_pipe.c | 6 ++++-- src/gallium/drivers/radeonsi/si_state.c | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 46cf37567f9..7bc34498cf4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -993,8 +993,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; + * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. + * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class >= CIK && + sscreen->info.drm_major == 3; sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 176ec749148..36dce381539 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->info.chip_class == SI); + /* SI, radeon kernel disabled CLEAR_STATE. */ + assert(has_clear_state || sscreen->info.chip_class == SI || + sscreen->info.drm_major != 3); if (!pm4) return; -- 2.30.2